CN105914150A - 薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置 - Google Patents
薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置 Download PDFInfo
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- CN105914150A CN105914150A CN201610282800.6A CN201610282800A CN105914150A CN 105914150 A CN105914150 A CN 105914150A CN 201610282800 A CN201610282800 A CN 201610282800A CN 105914150 A CN105914150 A CN 105914150A
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- film transistor
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Classifications
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- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- G—PHYSICS
- G02—OPTICS
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Abstract
本发明的实施例提供一种薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置,涉及显示技术领域,可采用溶液法制备高迁移率的金属氧化物薄膜晶体管。该薄膜晶体管的制备方法,包括在衬底上制备形成栅极、栅绝缘层、有源层、源极和漏极;通过溶液法制备形成所述有源层,所述有源层的材料为氧化锆铟半导体材料。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置。
背景技术
近年来,随着显示器尺寸的不断增大,以及驱动电路频率的不断提高,现有的非晶硅薄膜晶体管的迁移率已难以满足需求。由于金属氧化物薄膜晶体管的迁移率高、均一性好,受到了广泛的关注。
目前应用较为成熟的金属氧化物薄膜晶体管为采用铟镓锌氧化物(Indium Gallium Zinc Oxide,简称IGZO)作为有源层的金属氧化物薄膜晶体管。但工业化的金属氧化物薄膜晶体管主要采用物理气相沉积(Physical Vapor Deposition,PVD)的方法进行制备,这需要昂贵的真空设备,成本较高。此外,材料的利用率极低也大大增加了生产成本。
相比较而言,溶液法可以实现旋涂、滴涂、打印以及卷对卷等工艺,易于操作且材料的利用率较高,成本更低,具有更广阔的应用潜景。然而由于溶液法不可避免地会引入相对较多的杂质,导致金属氧化物薄膜晶体管的迁移率比较低。例如:对于采用IGZO制成的金属氧化物薄膜晶体管,当采用溶液法制备有源层时,其迁移率不足1cm2/Vs。
发明内容
本发明的实施例提供一种薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置,可采用溶液法制备高迁移率的金属氧化物薄膜晶体管。
为达到上述目的,本发明的实施例采用如下技术方案:
第一方面,提供一种薄膜晶体管的制备方法,包括在衬底上制备形成栅极、栅绝缘层、有源层、源极和漏极;通过溶液法制备形成所述有源层,所述有源层的材料为氧化锆铟半导体材料。
优选的,所述氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比介于0.1-20%之间。
优选的,通过溶液法制备形成所述有源层,包括:通过喷墨打印的方法制备形成所述有源层。
进一步优选的,喷墨打印采用的溶液为In(NO3)3·xH2O和ZrOCl2·xH2O溶于乙二醇单甲醚和乙二醇的混合溶液。
基于上述,优选的,在形成所述有源层之后,形成所述源极与所述漏极之前,所述方法还包括:形成刻蚀阻挡层。
可选的,所述衬底为硬质衬底或柔性衬底。
第二方面,提供一种阵列基板的制备方法,包括形成薄膜晶体管和与所述薄膜晶体管的漏极电联接的第一电极;其中,通过第一方面的制备方法形成所述薄膜晶体管。
可选的,所述第一电极为阳极;所述制备方法还包括:形成阴极以及位于所述阳极和所述阴极之间的有机材料功能层;或者,所述第一电极为像素电极。
第三方面,提供一种薄膜晶体管,包括衬底、设置在所述衬底上的栅极、栅绝缘层、有源层、源极和漏极;所述有源层的材料为氧化锆铟半导体材料。
优选的,所述氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比介于0.1%至20%之间。
可选的,所述衬底为硬质衬底或柔性衬底。
第四方面,提供一种阵列基板,包括第三方面所述的薄膜晶体管,还包括与所述薄膜晶体管的漏极电联接的第一电极。
第五方面,提供一种显示面板,包括第四方面所述的阵列基板。
第六方面,提供一种显示装置,包括第五方面所述的显示面板。
本发明的实施例提供一种薄膜晶体管及制备方法、阵列基板及制备方法、显示面板、显示装置,由于采用氧化锆铟作为有源层的材料,而在氧化锆铟里锆有抑制氧空位的作用,故能提高稳定性,同时,由于氧化锆铟中不含锌,故可减少对水氧的敏感性,此外,锆还能取代铟产生施主能级,故可保持载流子浓度,因此能够避免在薄膜制备过程中由于采用溶液法引入的杂质造成的载流子浓度急剧下降而导致迁移率低的问题,本发明可制备得到高迁移率的薄膜晶体管。其中,由于有源层采用溶液法制备,因此本发明实施例提供的金属氧化物薄膜晶体管还具有制备成本低的特点。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种薄膜晶体管的结构示意图一;
图2为本发明实施例提供的一种薄膜晶体管的结构示意图二;
图3为本发明实施例提供的一种薄膜晶体管的结构示意图三;
图4(a)为本发明实施例提供的一种薄膜晶体管的结构示意图四;
图4(b)为本发明实施例提供的一种薄膜晶体管的结构示意图五;
图5(a)为本发明实施例提供的一种制备薄膜晶体管的流程示意图一;
图5(b)为本发明实施例提供的一种制备薄膜晶体管的流程示意图二;
图6为本发明实施例提供的一种制备薄膜晶体管的转移特性曲线一;
图7为本发明实施例提供的一种制备薄膜晶体管的转移特性曲线二;
图8为本发明实施例提供的一种阵列基板的结构示意图一;
图9为本发明实施例提供的一种阵列基板的结构示意图二;
图10为本发明实施例提供的一种阵列基板的结构示意图三;
图11为本发明实施例提供的一种阵列基板的结构示意图四。
附图标记:
10-衬底;11-栅极;12-栅绝缘层;13-有源层;14-源极;15-漏极;16-刻蚀阻挡层;17-缓冲层;18-像素电极;19-公共电极;20-阳极;21-阴极;22-有机材料功能层。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供一种薄膜晶体管的制备方法,如图1和图2所示,包括在衬底10上制备形成栅极11、栅绝缘层12、有源层13、源极14和漏极15;其中,通过溶液法制备形成所述有源层13,所述有源层13的材料为氧化锆铟半导体材料。
溶液法包括旋涂、滴涂、印刷等,印刷可包括喷墨打印,转印。
本发明实施例中,栅极11可以由单层或两层及以上薄膜构成。当由单层薄膜构成时,其材料可以是导电材料,例如金属、合金、导电金属氧化物、掺杂硅、导电聚合物等。当由两层及以上薄膜构成时,可由以上材料的任意组合构成的两层以上的薄膜叠加而成。栅极11的厚度可以在100nm~2000nm之间。
栅绝缘层12可以由单层或两层及以上薄膜构成。当由单层薄膜构成时,其材料例如可以是二氧化硅、氮化硅、氮氧化硅、氧化铝、氧化铝合金、氧化镱、氧化钛、氧化铪、氧化钽、氧化锆、聚合物绝缘材料、光刻胶等。当由两层及以上薄膜构成时,可由以上材料的任意组合构成的两层以上的薄膜叠加而成。栅绝缘层12的厚度可以在50nm~500nm之间。
源极14和漏极15可以由单层或两层及以上薄膜构成。当由单层薄膜构成时,其材料可以是导电材料,例如金属、合金、导电金属氧化物、掺杂硅、导电聚合物等。当由两层及以上薄膜构成时,可由以上材料的任意组合构成的两层以上的薄膜叠加而成。源极14和漏极15的厚度可以在100nm~2000nm之间。
有源层的厚度可以在10nm~100nm之间。
需要说明的是,本发明实施例中,薄膜晶体管可以是底栅型,也可是顶栅型,还可以为双栅型。根据薄膜晶体管的类型的不同,形成栅极11、源极14和漏极15的顺序也不相同。
本发明实施例提供了一种薄膜晶体管的制备方法,由于采用氧化锆铟作为有源层13的材料,而在氧化锆铟里锆有抑制氧空位的作用,故能提高稳定性,同时,由于氧化锆铟中不含锌,故可减少对水氧的敏感性,此外,锆还能取代铟产生施主能级,故可保持载流子浓度,因此能够避免在薄膜制备过程中由于采用溶液法引入的杂质而造成的载流子浓度急剧下降而导致迁移率低的问题,本发明可制备得到高迁移率的薄膜晶体管。其中,由于有源层13采用溶液法制备,因此本发明实施例提供的薄膜晶体管还具有制备成本低的特点。
优选的,氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比[Zr/(In+Zr)]介于0.1%至20%之间,以1%~16%更佳。
这样,可保证氧化锆铟的半导体性能更佳。
考虑到喷墨打印的材料利用率以及成膜质量较高,可以直接图案化,而且可以实现大尺寸化,因此,优选通过喷墨打印的方法制备形成有源层13。
此处,喷墨打印的材料需溶解在溶剂中形成溶液才可以打印,后续通过蒸发工艺蒸发掉溶液中的溶剂,形成有源层13。
其中,蒸发工艺可在150℃~300℃的温度下进行,持续时间可控制在0.5h~3h。
优选的,喷墨打印采用的溶液为In(NO3)3·xH2O(硝酸铟)和ZrOCl2·xH2O(氯氧化锆)溶于乙二醇单甲醚和乙二醇的混合溶液。
优选的,如图3所示,在形成有源层13之后,形成源极14与漏极15之前,所述方法还包括形成刻蚀阻挡层16。
其中,刻蚀阻挡层16的厚度可以为50~200nm。
本发明实施例中,形成刻蚀阻挡层16,一方面,可进一步避免氧化锆铟暴露在空气中与氧气或水反应,另一方面,可避免在后续形成源极14与漏极15的工艺中对有源层13的影响。
优选的,如图4(a)和图4(b)所示,所述制备方法还包括:在衬底10表面形成缓冲层17。这样,可避免由于衬底10的杂质进入有源层13或者由于衬底本省不平坦而导致后续成膜质量较差,从而可保证薄膜晶体管的性能。
其中,缓冲层17的厚度可以为100nm~300nm。
下面提供两个具体实施例以详细描述上述的薄膜晶体管的制备过程,并且以实验数据对薄膜晶体管的性能进行说明。
实施例一,提供一种如图4(b)所示的薄膜晶体管的制备方法,如图5(a)所示,包括如下步骤:
S10、在衬底10上,采用PECVD(Plasma Enhanced Chemical VaporDeposition,等离子体增强化学气相沉积)法沉积SiO2(二氧化硅)的缓冲层17,厚度为200nm。
其中,衬底10可以为无碱玻璃。
S11、在S10的基础上,采用PVD法依次沉积Mo(钼)/Al(铝)/Mo三层金属薄膜,厚度分别为25nm/100nm/25nm,通过光刻工艺处理,形成栅极11。
S12、在S11的基础上,采用PECVD法依次沉积SiNx(氮化硅)和SiO2,厚度分别为300nm和30nm,形成栅绝缘层12。
S13、在S12的基础上,采用喷墨打印法制备氧化锆铟半导体材料的有源层13,厚度为20nm。
其中,喷墨打印采用的溶液为In(NO3)3·xH2O和ZrOCl2·xH2O溶于乙二醇单甲醚和乙二醇的混合溶液。
氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比[Zr/(In+Zr)]可以为1%、6%、11%、16%。
S14、在S13的基础上,在180℃在空气中加热2小时。
S15、在S14的基础上,采用真空蒸发法制备300nm的源极14和漏极15,源极14和漏极15的材料为Al。
或者,也可采用印刷的方法形成源极14和漏极15。
如图6所示,为对S10-S15所制得的金属氧化物薄膜晶体管在空气中测试的转移特性曲线,即,漏极电流与栅极电压之间的关系。其中,测试条件为源极电压(VS)为0V,漏极电压(VD)恒定为20V,栅极电压(VG)先从-20V到20V正扫、再从20V到-20V回扫,测试的漏极电流(ID)。由此可知,通过溶液法制备的氧化锆铟作为有源层的薄膜晶体管具备很好的性能,迁移率得到大幅度提升,漏电流也较低。
下表为S10-S15所制得的金属氧化物薄膜晶体管的参数。可以看出,Zr含量较小的时候,Zr取代In造成的电子富余占据主导地位,此时,迁移率较高,关态电流较大。当Zr含量达到11%时,关态电流显著减小,虽然迁移率也在减小,但仍能满足迁移率要求,而且正扫和回扫之间的磁滞效应也减小,说明这时Zr抑制氧空位的作用开始占据主导。
Zr/(In+Zr) | 1% | 6% | 11% | 16% |
迁移率(cm2/Vs) | 19.6 | 25.3 | 11.2 | 7.1 |
磁滞效应(V) | 1.0 | 1.2 | 0.4 | 0.4 |
关态电流(A) | 1×10-9 | 1×10-8 | 5×10-10 | 1×10-11 |
实施例二,提供一种如图1所示的薄膜晶体管的制备方法,如图5(b)所示,包括如下步骤:
S20、在衬底10上,采用PVD法沉积Al(铝)金属薄膜,厚度为300nm,通过光刻工艺处理,形成栅极11。
其中,衬底10可以为PEN(聚萘二甲酸乙二醇酯)柔性衬底。
S21、在S20的基础上,采用阳极氧化法制备氧化铝的栅绝缘层12,厚度为200nm。
S22、在S21的基础上,采用喷墨打印法制备氧化锆铟半导体材料的有源层13,厚度为20nm。
其中,喷墨打印采用的溶液为In(NO3)3·xH2O和ZrOCl2·xH2O溶于乙二醇单甲醚和乙二醇的混合溶液。
氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比[Zr/(In+Zr)]可以为12%。
S23、在S22的基础上,在150℃在空气中加热2小时。
S24、在S23的基础上,采用溅射方法制备ITO(氧化铟锡)金属薄膜,厚度为500nm,通过剥离(lift-off)的图形化方法,形成源极14和漏极15。
如图7所示,为对S20-S24所制得的金属氧化物薄膜晶体管在空气中测试的转移特性曲线,即,漏极电流与栅极电压之间的关系。其中,测试条件为源极电压(VS)为0V,漏极电压(VD)恒定为20V,栅极电压(VG)先从-20V到20V正扫、再从20V到-20V回扫,测试的漏极电流(ID)。由此可知,通过溶液法制备的氧化锆铟作为有源层的薄膜晶体管具备很好的性能,迁移率得到大幅度提升,漏电流也较低。
所制备的薄膜晶体管的迁移率为9.8cm2/Vs,满足薄膜晶体管迁移率大于5cm2/Vs的要求,说明本发明实施例制备的金属氧化物薄膜晶体管即使在退火温度低的情况下也具有迁移率高的特点,因而可与柔性衬底兼容。
即,本发明实施例的薄膜晶体管的衬底10可以为硬质衬底,也可以为柔性衬底。硬质衬底例如为玻璃、硅片、金属箔片、石英等。柔性衬底,其材料例如可以为PEN、PET(聚对苯二甲酸乙二酯)、PI(聚酰亚胺)、PC(聚碳酸酯)、PEI(聚醚酰亚胺)等。
本发明实施例还提供一种阵列基板的制备方法,可通过上述方法形成所述薄膜晶体管,此外还形成第一电极。
其中,所述阵列基板可以用于LCD(Liquid Crystal Display,液晶显示器),基于此,如图8所示,第一电极可以为像素电极18。
在此基础上,所述阵列基板的制备方法还包括:形成公共电极19。在此情况下,对于IPS(In-Plane Switch,共平面切换)型阵列基板而言,如图9所示,像素电极18和公共电极19同层间隔设置,且均为条状电极;对于ADS(Advanced-super Dimensional Switching,高级超维场转换)型阵列基板而言,如图10所示,像素电极18和公共电极19不同层设置,其中在上的电极为条状电极,在下的电极为板状电极。
当然,所述阵列基板还可以用于AMOLED(Active Matrix/OrganicLight Emitting Diode,有源矩阵有机电致发光二极管)显示器。基于此,如图11所示,第一电极可以为阳极20,在此基础上,所述阵列基板的制备方法还包括:形成阴极21以及位于阳极20和阴极21之间的有机材料功能层22。
其中,对于所述有机材料功能层22,其可以至少包括发光层,进一步的还可以包括电子传输层和空穴传输层,在此基础上,为了能够提高电子和空穴注入发光层的效率,所述有机材料功能层22还可以包括形成在阴极21与电子传输层之间的电子注入层,以及形成在阳极20与空穴传输层之间的空穴注入层。
具体的根据阳极20和阴极21的材料的不同,可以分为单面发光型OLED阵列基板和双面发光型OLED阵列基板;即:当阳极20和阴极21中其中一个电极的材料为不透明材料时,OLED阵列基板为单面发光型;当阳极20和阴极21的材料均为透明材料时,OLED阵列基板为双面发光型。
对于单面发光型OLED阵列基板,根据阳极20和阴极21的材料的不同,又可以分为上发光型和下发光型。具体的,当阳极20靠近衬底设置,阴极21远离衬底设置,且阳极20的材料为透明导电材料,阴极21的材料为不透明导电材料时,由于光从阳极20、再经衬底一侧出射,因此,可以称为下发光型;当阳极20的材料为不透明导电材料,阴极21的材料为透明导电材料时,由于光从阴极21一侧出射,因此,可以称为上发光型。当然,也可以将上述两种阳极20和阴极21的相对位置进行替换,在此再赘述。
本发明实施例还提供一种薄膜晶体管,如图1和图2所示,包括衬底10、设置在衬底10上的栅极11、栅绝缘层12、有源层13、源极14和漏极15;有源层12的材料为氧化锆铟半导体材料。
本发明实施例中,栅极11可以由单层或两层及以上薄膜构成。当由单层薄膜构成时,其材料可以是导电材料,例如金属、合金、导电金属氧化物、掺杂硅、导电聚合物等。当由两层及以上薄膜构成时,可由以上材料的任意组合构成的两层以上的薄膜叠加而成。栅极11的厚度可以在100nm~2000nm之间。
栅绝缘层12可以由单层或两层及以上薄膜构成。当由单层薄膜构成时,其材料例如可以是二氧化硅、氮化硅、氮氧化硅、氧化铝、氧化铝合金、氧化镱、氧化钛、氧化铪、氧化钽、氧化锆、聚合物绝缘材料、光刻胶等。当由两层及以上薄膜构成时,可由以上材料的任意组合构成的两层以上的薄膜叠加而成。栅绝缘层12的厚度可以在50nm~500nm之间。
源极14和漏极15可以由单层或两层及以上薄膜构成。当由单层薄膜构成时,其材料可以是导电材料,例如金属、合金、导电金属氧化物、掺杂硅、导电聚合物等。当由两层及以上薄膜构成时,可由以上材料的任意组合构成的两层以上的薄膜叠加而成。源极14和漏极15的厚度可以在100nm~2000nm之间。
有源层的厚度可以在10nm~100nm之间。
需要说明的是,本发明实施例中,薄膜晶体管可以是底栅型,也可是顶栅型,还可以为双栅型。根据薄膜晶体管的类型的不同,形成栅极11、源极14和漏极15的顺序也不相同。
本发明实施例提供了一种薄膜晶体管的制备方法,由于采用氧化锆铟作为有源层13的材料,而在氧化锆铟里锆有抑制氧空位的作用,故能提高稳定性,同时,由于氧化锆铟中不含锌,故可减少对水氧的敏感性,此外,锆还能取代铟产生施主能级,故可保持载流子浓度,因此能够避免在薄膜制备过程中由于采用溶液法引入的杂质而造成的载流子浓度急剧下降而导致迁移率低的问题,本发明可制备得到高迁移率的薄膜晶体管。其中,由于有源层13采用溶液法制备,因此本发明实施例提供的金属氧化物薄膜晶体管还具有制备成本低的特点。
优选的,氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比[Zr/(In+Zr)]介于0.1%至20%之间,以1%~16%更佳。
这样,可保证氧化锆铟的半导体性能更佳。
优选的,如图3所示,所述薄膜晶体管还包括设置在有源层13和源极14与漏极15之间的刻蚀阻挡层16。
其中,刻蚀阻挡层16的厚度可以为50~200nm。
本发明实施例中,形成刻蚀阻挡层16,一方面,可进一步避免氧化锆铟暴露在空气中与氧气或水反应,另一方面,可避免在后续形成源极14与漏极15的工艺中对有源层13的影响。
优选的,如图4(a)和图4(b)所示,所述薄膜晶体管还包括设置在衬底10表面的缓冲层17。这样,可避免由于衬底10的杂质进入有源层13或者由于衬底本省不平坦而导致后续成膜质量较差,从而可保证薄膜晶体管的性能。
其中,缓冲层17的厚度可以为100nm~300nm。
基于上述,衬底10可以为硬质衬底,也可以为柔性衬底。硬质衬底例如为玻璃、硅片、金属箔片、石英等。柔性衬底,其材料例如可以为PEN、PET、PI、PC、PEI等。
本发明实施例还提供一种阵列基板,包括上述的薄膜晶体管,还包括与所述薄膜晶体管的漏极电联接的第一电极。
其中,所述阵列基板可以用于LCD,基于此,如图8所示,第一电极可以为像素电极18。
在此基础上,如图9和图10所示,所述阵列基板的制备方法还包括公共电极19。
当然,所述阵列基板还可以用于AMOLED显示器。基于此,如图11所示,第一电极可以为阳极20,在此基础上,所述阵列基板的还包括:阴极21以及位于阳极20和阴极21之间的有机材料功能层22。
本发明实施例还提供一种显示面板,包括上述的阵列基板。
当第一电极为像素电极18时,该显示面板还包括对盒基板。
当第一电极为阳极20时,该显示面板还包括封装基板。
本发明实施例还提供一种显示装置,包括上述的显示面板。
该显示装置可以为LCD,也可以为OLED显示装置。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (14)
1.一种薄膜晶体管的制备方法,包括在衬底上制备形成栅极、栅绝缘层、有源层、源极和漏极;其特征在于,通过溶液法制备形成所述有源层,所述有源层的材料为氧化锆铟半导体材料。
2.根据权利要求1所述的制备方法,其特征在于,所述氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比介于0.1-20%之间。
3.根据权利要求1所述的制备方法,其特征在于,通过溶液法制备形成所述有源层,包括:通过喷墨打印的方法制备形成所述有源层。
4.根据权利要求3所述的制备方法,其特征在于,喷墨打印采用的溶液为In(NO3)3·xH2O和ZrOCl2·xH2O溶于乙二醇单甲醚和乙二醇的混合溶液。
5.根据权利要求1-4任一项所述的制备方法,其特征在于,在形成所述有源层之后,形成所述源极与所述漏极之前,所述方法还包括:形成刻蚀阻挡层。
6.根据权利要求1-4任一项所述的制备方法,其特征在于,所述衬底为硬质衬底或柔性衬底。
7.一种阵列基板的制备方法,包括形成薄膜晶体管和与所述薄膜晶体管的漏极电联接的第一电极;其特征在于,通过权利要求1-6任一项所述的制备方法形成所述薄膜晶体管。
8.根据权利要求7所述的制备方法,其特征在于,所述第一电极为阳极;所述制备方法还包括:形成阴极以及位于所述阳极和所述阴极之间的有机材料功能层;或者,
所述第一电极为像素电极。
9.一种薄膜晶体管,包括衬底、设置在所述衬底上的栅极、栅绝缘层、有源层、源极和漏极;其特征在于,所述有源层的材料为氧化锆铟半导体材料。
10.根据权利要求9所述的薄膜晶体管,其特征在于,所述氧化锆铟半导体材料中锆原子数与锆铟原子总数的百分比介于0.1%至20%之间。
11.根据权利要求9所述的薄膜晶体管,其特征在于,所述衬底为硬质衬底或柔性衬底。
12.一种阵列基板,其特征在于,包括权利要求9-11任一项所述的薄膜晶体管,还包括与所述薄膜晶体管的漏极电联接的第一电极。
13.一种显示面板,其特征在于,包括权利要求12所述的阵列基板。
14.一种显示装置,其特征在于,包括权利要求13所述的显示面板。
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CN113555398A (zh) * | 2021-07-16 | 2021-10-26 | 京东方科技集团股份有限公司 | 显示模组的背板及其制备方法、显示面板、显示装置 |
CN113555398B (zh) * | 2021-07-16 | 2024-05-24 | 京东方科技集团股份有限公司 | 显示模组的背板及其制备方法、显示面板、显示装置 |
WO2023184600A1 (zh) * | 2022-03-30 | 2023-10-05 | 广州华星光电半导体显示技术有限公司 | 阵列基板及其制备方法、显示面板 |
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WO2017186094A1 (zh) | 2017-11-02 |
US20180138037A1 (en) | 2018-05-17 |
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