WO2017185823A1 - 阵列基板及其制作方法、显示面板和显示装置 - Google Patents

阵列基板及其制作方法、显示面板和显示装置 Download PDF

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Publication number
WO2017185823A1
WO2017185823A1 PCT/CN2017/070286 CN2017070286W WO2017185823A1 WO 2017185823 A1 WO2017185823 A1 WO 2017185823A1 CN 2017070286 W CN2017070286 W CN 2017070286W WO 2017185823 A1 WO2017185823 A1 WO 2017185823A1
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Prior art keywords
layer
array substrate
conductive material
material layer
gate insulating
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English (en)
French (fr)
Inventor
宋博韬
杨成绍
黄寅虎
刘宁
马骏
万云海
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/535,391 priority Critical patent/US10546882B2/en
Publication of WO2017185823A1 publication Critical patent/WO2017185823A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure generally relates to the field of display technology, and more particularly to an array substrate, a display panel including the array substrate, and a display device, and a method of fabricating the array substrate.
  • a metal such as aluminum or copper is usually used to form a metal pattern, such as a signal line, a source and a drain, etc., and a metal insulating layer such as a gate insulating layer, an etch barrier layer, a passivation layer, or the like is formed on the metal pattern.
  • the layer is then dry etched at a position corresponding to the metal pattern of each layer on the metal pattern by using a gas such as oxygen to form a connection hole exposing the metal pattern to electrically connect the metal pattern from the outside.
  • a dry etching gas such as oxygen may react with a metal material of a metal pattern, resulting in a drum pattern-like defect in the metal pattern.
  • bulge-like defects may cause a series of problems such as pad erosion, bonding failure, and the like.
  • this bulge-like defect is difficult to improve by changing the conditions of dry etching, and thus will seriously affect the final product quality and reduce the yield of the final product.
  • An object of the present disclosure is to provide an array substrate, a display panel including the array substrate, and a display device, and a method of fabricating the array substrate capable of at least partially alleviating or eliminating one of the above-mentioned problems in the prior art Or multiple.
  • an array substrate which may include a substrate substrate, a metal layer disposed over the substrate substrate, a conductive material layer disposed over the metal layer, and a conductive material disposed A connection hole above the layer that exposes a layer of conductive material.
  • the conductive material layer is protected during etching of a layer such as a gate insulating layer or a passivation layer over a metal layer by arranging a conductive material layer over the metal layer to form a connection hole.
  • the metal layer is unaffected by the etching, thereby reducing or even avoiding the generation of bulge-like defects in the metal layer, thereby improving the quality and yield of the final product.
  • the layer of conductive material may be in the same layer as the display drive electrode layer of the array substrate.
  • a metal layer is first formed, and then the same layer is formed to form a display driving electrode layer and a conductive material layer, thereby not increasing In the case of the number of layers of the array substrate and the thickness, the metal material in the metal layer is prevented from having a bulge-like defect when etching the connection hole, thereby improving the quality of the final product.
  • the array substrate includes a thin film transistor
  • the metal layer may include at least one of a source and a drain of the thin film transistor.
  • the source and/or drain may be protected during etching of the layers above the source and/or drain to form the connection holes. Quality degradation can occur due to etching effects.
  • the metal layer can include signal lines of the array substrate.
  • the signal line can include a data line.
  • the array substrate of the display device generally includes a plurality of mutually parallel gate lines and a plurality of mutually parallel data lines, the mutually intersecting gate lines and data lines defining a plurality of pixel units, and thin film transistors are disposed at intersections of the gate lines and the data lines
  • the TFT can control whether the pixel unit corresponding to the thin film transistor displays a screen or not by controlling the on and off of the thin film transistor, and can further control the display device to display an image.
  • the array substrate may further include a gate insulating layer disposed between the data line and the substrate substrate and a passivation layer disposed over the conductive material layer, the connection hole being disposed in the passivation layer .
  • the array substrate may be a bottom gate type array substrate in which the gate metal layer is located under the source and drain metal layers.
  • the connection holes are used to electrically connect the data lines through the conductive material layer.
  • the array substrate may further include a gate insulating layer and a passivation layer sequentially disposed over the conductive material layer, the connection holes being disposed in the gate insulating layer and the passivation layer.
  • the array substrate may be a top gate type array substrate in which the gate metal layer is located above the source and drain metal layers.
  • the connection holes are used to pass the logarithm of the conductive material layer Electrical connection is made according to the line.
  • the layer of conductive material may be in the same layer as the pixel electrode layer of the array substrate.
  • a data line is first formed, and then a pixel electrode layer and a conductive material layer are formed in the same layer, so that the array substrate is not added.
  • the metal material in the data line is prevented from having a bulge-like defect when etching the connection hole, thereby improving the quality of the final product.
  • the signal line may include a common electrode line
  • the array substrate may further include a gate insulating layer and a passivation layer sequentially disposed over the conductive material layer, the connection hole being disposed on the gate insulating layer and In the passivation layer.
  • the array substrate may be a bottom gate type array substrate in which the gate metal layer is located under the source and drain metal layers.
  • the connection holes are for electrically connecting the common electrode lines through the conductive material layer.
  • the layer of conductive material may be in the same layer as the common electrode layer of the array substrate.
  • a common electrode line is first formed, and then a common electrode layer and a conductive material layer are formed in the same layer, thereby not increasing In the case of the number of layers of the array substrate and the thickness, the metal material in the common electrode line is prevented from having a bulge-like defect when etching the connection hole, thereby improving the quality of the final product.
  • the layer of electrically conductive material can be made of a conductive oxide.
  • the conductive oxide may include one or more of indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), indium-doped zinc oxide (IZO), or indium-doped cadmium oxide.
  • ITO indium tin oxide
  • AZO aluminum-doped zinc oxide
  • IZO indium-doped zinc oxide
  • indium-doped cadmium oxide indium tin oxide or tin-doped indium oxide is the currently known and most widely used transparent conductive oxide, which is widely used due to its ease of deposition as a film.
  • the metal layer can be made of copper and/or aluminum.
  • a display panel comprising the array substrate of any of the above embodiments.
  • a display device comprising the above display panel.
  • the conductive layer protects the metal layer from etching, thereby reducing or even avoiding the generation of bulge-like defects in the metal layer, thereby improving the quality and yield of the final product.
  • a method of fabricating an array substrate may include forming a metal layer over a substrate substrate; forming a conductive material layer over the metal layer; and forming an exposed layer over the conductive material layer a connection hole of the conductive material layer.
  • the layer of conductive material protects the metal layer from etching, thereby reducing or even avoiding the generation of bulge-like defects in the metal layer, thereby improving the quality and yield of the final product.
  • the conductive material layer and the display drive electrode layer of the array substrate can be simultaneously formed during one patterning process.
  • the array substrate may include a thin film transistor, and the metal layer includes at least one of a source and a drain of the thin film transistor.
  • the metal layer can include signal lines of the array substrate.
  • the signal line includes a data line.
  • the method of fabricating the array substrate may further include forming a gate insulating layer on the base substrate before forming the conductive material layer; and forming a passivation layer over the conductive material layer, wherein the connection hole Formed in the passivation layer.
  • the array substrate thus formed may be a bottom gate type array substrate in which a gate metal layer is located under the source and drain metal layers. The connection holes are used to electrically connect the data lines through the conductive material layer.
  • the method of fabricating the array substrate may further include sequentially forming a gate insulating layer and a passivation layer over the conductive material layer, wherein the connection holes are formed in the gate insulating layer and the passivation layer .
  • the array substrate thus formed may be a top gate type array substrate in which a gate metal layer is located above the source and drain metal layers.
  • the connection holes are used to electrically connect the data lines through the layer of conductive material.
  • the conductive material layer and the pixel electrode layer of the array substrate can be simultaneously formed during one patterning process.
  • the signal line includes a common electrode line
  • the fabricating method may further include sequentially forming a gate insulating layer and a passivation layer over the conductive material layer, wherein the connection hole is insulated at the gate Formed in the layer and the passivation layer.
  • the array substrate thus formed may be a bottom gate type array substrate in which a gate metal layer is located under the source and drain metal layers.
  • the connection holes are for electrically connecting the common electrode lines through the conductive material layer.
  • the conductive material layer and the common electrode layer of the array substrate can be simultaneously formed during one patterning process.
  • FIG. 1 is a cross-sectional view of a portion of an array substrate in accordance with some embodiments of the present disclosure
  • FIG. 2 is a cross-sectional view of a portion of an array substrate in accordance with some embodiments of the present disclosure
  • FIG. 3 is a cross-sectional view of a portion of an array substrate in accordance with some embodiments of the present disclosure
  • FIG. 4 is a cross-sectional view of a portion of an array substrate in accordance with some embodiments of the present disclosure
  • FIG. 5 is a cross-sectional view of a portion of an array substrate in accordance with some embodiments of the present disclosure
  • FIG. 6 illustrates a flow chart of a method of fabricating an array substrate, in accordance with some embodiments of the present disclosure
  • FIG. 7a-7d are schematic views illustrating the steps of the method of fabricating the array substrate shown in Fig. 6.
  • FIG. 1 illustrates a cross-sectional view of a portion of an array substrate in accordance with an embodiment of the present disclosure.
  • the array substrate includes a substrate substrate 101, a metal layer 102 disposed above the substrate substrate, a conductive material layer 103 disposed over the metal layer 102, and other layers 105 disposed on the conductive material layer 103 ( There may be a plurality of sub-layers), and a connection hole 106 disposed above the conductive material layer 103 exposing the conductive material layer 103.
  • the conductive material layer 103 is protected during the process of etching the other layers 105 over the metal layer 102 to form the connection holes 106 by arranging the conductive material layer 103 over the metal layer 102.
  • the metal layer 102 is unaffected by etching, thereby reducing or even avoiding the generation of bulge-like defects in the metal layer 102, thereby improving the quality and yield of the final product.
  • the conductive material layer 103 may be in the same layer as the display driving electrode layer (not shown in FIG. 1) of the array substrate.
  • a metal layer is first formed, and then the same layer is formed to form a display driving electrode layer and a conductive material layer, thereby not increasing In the case of the number of layers of the array substrate and the thickness, the metal material in the metal layer is prevented from having a bulge-like defect when etching the connection hole, thereby improving the quality of the final product.
  • the metal layer 102 may include signal lines of the array substrate.
  • the signal line can include a data line.
  • 2 illustrates a cross-sectional view of a portion of a bottom gate type array substrate in accordance with one embodiment of the present disclosure.
  • the array substrate includes a substrate substrate 201, a data line 202 disposed above the substrate substrate 201, a conductive material layer 203 disposed over the data line 202, and a data line 202 and a substrate substrate 201.
  • the connection holes 206 are for electrically connecting the data lines 202 through the conductive material layer 203.
  • the conductive material layer is formed during the process of forming the connection hole 206 by etching the passivation layer 205 over the data line 202 by arranging the conductive material layer 203 over the data line 202.
  • 203 protects the data line 202 from etching, thereby reducing or even avoiding the generation of bulge-like defects in the data line 202, thereby improving the final production. Product quality and yield.
  • FIG. 3 illustrates a cross-sectional view of a portion of a top gate type array substrate in accordance with another embodiment of the present disclosure.
  • the array substrate includes a base substrate 301, a data line 302 disposed above the base substrate 301, a conductive material layer 303 disposed over the data line 302, and a gate sequentially disposed over the conductive material layer 303.
  • the connection holes 306 are for electrically connecting the data lines 302 through the conductive material layer 303.
  • the process of etching the gate insulating layer 307 and the passivation layer 305 over the data line 302 to form the connection hole 306 by arranging the conductive material layer 303 over the data line 302 is performed.
  • the conductive material layer 303 protects the data lines 302 from etching, thereby reducing or even avoiding the generation of bulge-like defects in the data lines 302, thereby improving final product quality and yield.
  • the conductive material layer 203 and/or the conductive material layer 303 may be in the same layer as the pixel electrode layer (not shown in the drawing) of the array substrate.
  • a data line is first formed, and then a pixel electrode layer and a conductive material layer are formed in the same layer, so that the array substrate is not added.
  • the metal material in the data line is prevented from having a bulge-like defect when etching the connection hole, thereby improving the quality of the final product.
  • the array substrate includes a substrate substrate 401, a common electrode line 402 disposed above the base substrate 401, a conductive material layer 403 disposed over the common electrode line 402, and sequentially disposed over the conductive material layer 403.
  • the connection holes 406 are for electrically connecting the common electrode lines 402 through the conductive material layer 403.
  • the gate insulating layer 407 and the passivation layer 405 over the common electrode line 402 are etched to form the connection hole 406 by arranging the conductive material layer 403 over the common electrode line 402. During this process, the conductive material layer 403 protects the common electrode line 402 from etching, thereby reducing or even avoiding the generation of bulge-like defects in the common electrode line 402, thereby improving final product quality and yield.
  • the conductive material layer 403 can be combined with the array substrate
  • the common electrode layer (not shown in Figure 4) is in the same layer.
  • a common electrode line is first formed, and then a common electrode layer and a conductive material layer are formed in the same layer, thereby not increasing
  • the metal material in the common electrode line is prevented from having a bulge-like defect when etching the connection hole, thereby improving the quality of the final product.
  • the array substrate shown in FIG. 1 may include a thin film transistor, and the metal layer 102 may include at least one of a source and a drain of the thin film transistor.
  • FIG. 5 illustrates a cross-sectional view of a portion of an array substrate in accordance with an embodiment of the present disclosure. As shown in FIG. 5, the array substrate includes a substrate substrate 501, a source and drain 502 disposed over the substrate substrate 501, an active region 508 disposed between the source and drain electrodes 502, and a source and drain electrode 502 disposed above the source and drain electrodes 502.
  • connection hole 506 is for electrically connecting the source and drain electrodes 502 through the conductive material layer 503.
  • etching may be performed on the gate insulating layer 507 over the source and/or drain 502 by forming a conductive material layer 503 on the source and/or drain 502 of the thin film transistor.
  • the protection source and/or the drain 502 does not cause quality degradation due to etching effects.
  • the layer of electrically conductive material is made of a conductive oxide.
  • the conductive oxide may include one or more of indium tin oxide, aluminum-doped zinc oxide, indium-doped zinc oxide, or indium-doped cadmium oxide.
  • one or more of metal layer 102, data lines 202, 302, common electrode line 402, and source drain 502 may be made of copper and/or aluminum.
  • FIG. 6 illustrates a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure
  • FIGS. 7a-7d schematically illustrate the steps of the fabrication method.
  • a metal layer 702 is formed over the base substrate 701.
  • the metal layer 702 can be fabricated by processes such as sputtering, evaporation, photolithography, and lift-off.
  • a conductive material layer 703 is formed over the metal layer 702 as shown in FIG. 7b.
  • the conductive material layer 703 can be fabricated by spin coating, photolithography, lift-off, or the like.
  • step S603 as shown in FIG. 7c, another layer 705 is formed over the conductive material layer 703, which may include a plurality of sub-layers such as the above-mentioned gate insulating layer, passivation layer, and the like.
  • step S604 as shown in FIG. 7d, the other layer 705 over the metal layer 702 is etched by dry etching to form a connection hole 706 exposing the conductive material layer 703.
  • the layer of conductive material protects the metal layer from etching, thereby reducing or even avoiding the generation of bulge-like defects in the metal layer, thereby improving the quality and yield of the final product.
  • a conductive material layer and a display driving electrode layer of the array substrate are simultaneously formed during one patterning process.
  • the metal layer includes a data line
  • the method of fabricating the array substrate may further include forming a gate insulating layer on the substrate substrate before forming the conductive material layer; and forming a passivation layer over the conductive material layer, wherein The connection holes are formed in the passivation layer.
  • the array substrate thus formed may be a bottom gate type array substrate in which a gate metal layer is located under the source and drain metal layers. The connection holes are used to electrically connect the data lines through the conductive material layer.
  • the method for fabricating the array substrate further includes: sequentially forming a gate insulating layer and a passivation layer over the conductive material layer, wherein the connection holes are formed in the gate insulating layer and the passivation layer.
  • the array substrate thus formed may be a top gate type array substrate in which a gate metal layer is located above the source and drain metal layers.
  • the connection holes are used to electrically connect the data lines through the layer of conductive material.
  • the conductive material layer and the pixel electrode layer of the array substrate are simultaneously formed in one patterning process.
  • the metal layer comprises a common electrode line
  • the method for fabricating the array substrate further comprises: sequentially forming a gate insulating layer and a passivation layer over the conductive material layer, wherein the connection hole is in the gate insulating layer and passivated Formed in the layer.
  • the array substrate thus formed may be a bottom gate type array substrate in which a gate metal layer is located under the source and drain metal layers.
  • the connection holes are for electrically connecting the common electrode lines through the conductive material layer.
  • a conductive material layer and a common electrode layer of the array substrate are simultaneously formed in one patterning process.
  • the present disclosure also provides a display panel and a display device comprising the array substrate of any of the above embodiments.

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Abstract

一种阵列基板、包括阵列基板的显示面板和显示装置，以及阵列基板的制作方法。所述阵列基板包括衬底基板（101、201、301、401、501、701）、布置在衬底基板（101、201、301、401、501、701）上方的金属层（102、202、302、402、502、702）、布置在金属层（102、202、302、402、502、702）之上的导电材料层（103、203、303、403、503、703），以及布置在导电材料层（103、203、303、403、503、703）上方的、暴露出导电材料层（103、203、303、403、503、703）的连接孔（106、206、306、406、506、706）。

Description

阵列基板及其制作方法、显示面板和显示装置
相关申请
本申请要求享有2016年4月29日提交的中国专利申请No.201610276100.6的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开一般地涉及显示技术领域，并且更特别地涉及一种阵列基板、包括阵列基板的显示面板和显示装置，以及阵列基板的制作方法。
背景技术
在制作显示装置的阵列基板时，通常采用铝或铜等金属来制作金属图形，例如信号线、源漏极等，并且在金属图形上制作诸如栅极绝缘层、蚀刻阻挡层、钝化层等层，而后采用氧气等气体在金属图形上的各层的与金属图形对应的位置处进行干法蚀刻，以形成暴露出金属图形的连接孔，以便从外部对金属图形进行电连接。然而，在干法蚀刻条件下，诸如氧气之类的干法蚀刻气体可能与金属图形的金属材料产生反应，导致金属图形产生鼓包状缺陷。在后续的工艺中发现，该鼓包状缺陷可能会引起例如焊盘侵蚀、键合失败等一系列问题。不幸的是，该鼓包状缺陷难以通过更改干法蚀刻的条件来改善，因而将严重影响最终的产品质量，降低最终产品的产率。
鉴于上文，在本领域中存在对提供一种改进的显示装置阵列基板的需要。
发明内容
本公开的一个目的是提供一种阵列基板、包括阵列基板的显示面板和显示装置，以及阵列基板的制作方法，其能够至少部分地缓解或消除以上提到的现有技术中的问题中的一个或多个。
根据本公开的第一方面，提供了一种阵列基板，该阵列基板可以包括衬底基板、布置在衬底基板上方的金属层、布置在金属层之上的导电材料层，以及布置在导电材料层上方的、暴露出导电材料层的连接孔。
在上述阵列基板中，通过在金属层上方布置导电材料层，在对金属层上方的诸如栅极绝缘层、钝化层之类的层进行蚀刻以形成连接孔的过程中，该导电材料层保护金属层不受蚀刻影响，从而减少或甚至避免金属层中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
在一些实施例中，所述导电材料层可以与阵列基板的显示驱动电极层同层。
相比于现有技术中首先形成显示驱动电极层，而后形成金属层的制造过程，在该实施例中，首先形成金属层，而后同层形成显示驱动电极层和导电材料层，从而在不增加阵列基板层数以及厚度的情况下，避免金属层中的金属材料在蚀刻连接孔时出现鼓包状缺陷，从而改善最终产品品质。
在一些实施例中，所述阵列基板包括薄膜晶体管，并且所述金属层可以包括薄膜晶体管的源极和漏极中的至少一个。
通过在薄膜晶体管的源极和/或漏极上形成导电材料层，可以在源极和/或漏极上方的各层进行蚀刻以形成连接孔的过程中，保护源极和/或漏极不会因为蚀刻影响而产生质量降级。
在一些实施例中，所述金属层可以包括阵列基板的信号线。
在一些实施例中，所述信号线可以包括数据线。
显示装置的阵列基板通常包括多条相互平行的栅线和多条相互平行的数据线，相互交叉的栅线和数据线限定多个像素单元，在栅线和数据线的交叉处设置有薄膜晶体管TFT，通过控制薄膜晶体管的导通与断开，可以控制与该薄膜晶体管对应的像素单元显示画面与否，进而可以控制显示装置显示图像。
在一些实施例中，所述阵列基板还可以包括布置在数据线与衬底基板之间的栅极绝缘层以及布置在导电材料层上方的钝化层，所述连接孔布置在钝化层中。在这样的情况下，阵列基板可以是底栅型阵列基板，其中栅金属层位于源漏金属层下方。连接孔用于通过导电材料层对数据线进行电连接。
在一些实施例中，所述阵列基板还可以包括依次布置在导电材料层上方的栅极绝缘层和钝化层，所述连接孔布置在栅极绝缘层和钝化层中。在这样的情况下，阵列基板可以是顶栅型阵列基板，其中栅金属层位于源漏金属层上方。同样地，连接孔用于通过导电材料层对数 据线进行电连接。
在一些实施例中，所述导电材料层可以与阵列基板的像素电极层同层。
相比于现有技术中首先形成像素电极层，而后形成数据线的制造过程，在该实施例中，首先形成数据线，而后同层形成像素电极层和导电材料层，从而在不增加阵列基板层数以及厚度的情况下，避免数据线中的金属材料在蚀刻连接孔时出现鼓包状缺陷，从而改善最终产品品质。
在一些实施例中，所述信号线可以包括公共电极线，并且阵列基板还可以包括依次布置在导电材料层上方的栅极绝缘层和钝化层，所述连接孔布置在栅极绝缘层和钝化层中。在这样的情况下，阵列基板可以是底栅型阵列基板，其中栅金属层位于源漏金属层下方。连接孔用于通过导电材料层对公共电极线进行电连接。
在一些实施例中，所述导电材料层可以与阵列基板的公共电极层同层。
相比于现有技术中首先形成公共电极层，而后形成公共电极线的制造过程，在该实施例中，首先形成公共电极线，而后同层形成公共电极层和导电材料层，从而在不增加阵列基板层数以及厚度的情况下，避免公共电极线中的金属材料在蚀刻连接孔时出现鼓包状缺陷，从而改善最终产品品质。
在一些实施例中，所述导电材料层可以由导电氧化物制成。例如，导电氧化物可以包括铟锡氧化物(ITO)、铝掺杂的氧化锌(AZO)、铟掺杂的氧化锌(IZO)或铟掺杂的氧化镉中的一个或多个。其中，氧化铟锡或锡掺杂的氧化铟是目前已知最佳的且最广泛使用的透明导电氧化物，其由于可以沉积为薄膜的简易性而得到广泛的使用。
在一些实施例中，所述金属层可以由铜和/或铝制成。
出于成本和导电性的权衡，在传统半导体制造工艺中主要采用铝作为金属互连材料，但是随着晶体管尺寸越来越小，采用铝线制造的器件开始在可靠性方面出现问题。选用电阻率较小的金属作为互连材料，并选用介电常数较小的介电材料是降低信号延时、提高时钟频率的两个主要方向。由于铜的电阻率仅为1.67μΩ-cm，远小于铝的2.66μΩ-cm，同时能减少互连层的厚度，通过降低电容达到了减少信号延 时的效果。因此，如果配合采用低K介电材料，可以降低信号线之间的耦合电容，信号的转换速度也随之加快，即进一步降低了信号的延时，铜互连工艺由此应运而生。如今，铜互连技术已成为90nm及以下产品的标准工艺。
根据本公开的第二方面，提供了一种显示面板，包括以上任一实施例所述的阵列基板。
根据本公开的第三方面，提供了一种显示装置，包括上述显示面板。
在上述显示面板和显示装置中，通过在金属层上方布置导电材料层，在对金属层上方的诸如栅极绝缘层、钝化层之类的层进行蚀刻以形成连接孔的过程中，该导电材料层保护金属层不受蚀刻影响，从而减少或甚至避免金属层中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
根据本公开的第四方面，提供了一种阵列基板的制作方法，该方法可以包括在衬底基板上方形成金属层；在金属层之上形成导电材料层；以及在导电材料层上方形成暴露出导电材料层的连接孔。
在上述阵列基板的制作方法中，通过在金属层上方形成导电材料层，在对金属层上方的诸如栅极绝缘层、钝化层之类的层进行蚀刻以形成连接孔的后续过程中，该导电材料层保护金属层不受蚀刻影响，从而减少或甚至避免金属层中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
在一些实施例中，可以在一个图案化工艺过程中同时形成导电材料层和阵列基板的显示驱动电极层。
在一些实施例中，阵列基板可以包括薄膜晶体管，并且所述金属层包括薄膜晶体管的源极和漏极中的至少一个。
在一些实施例中，金属层可以包括阵列基板的信号线。例如，信号线包括数据线。
在一些实施例中，所述阵列基板的制作方法还可以包括在形成导电材料层之前在衬底基板上形成栅极绝缘层；以及在导电材料层上方形成钝化层，其中，所述连接孔在钝化层中形成。如此形成的阵列基板可以是底栅型阵列基板，其中栅金属层位于源漏金属层下方。连接孔用于通过导电材料层对数据线进行电连接。
在一些实施例中，所述阵列基板的制作方法还可以包括：在导电材料层上方依次形成栅极绝缘层和钝化层，其中，所述连接孔在栅极绝缘层和钝化层中形成。如此形成的阵列基板可以是顶栅型阵列基板，其中栅金属层位于源漏金属层上方。同样地，连接孔用于通过导电材料层对数据线进行电连接。
在一些实施例中，可以在一个图案化工艺过程中同时形成导电材料层与阵列基板的像素电极层。
在一些实施例中，所述信号线包括公共电极线，并且所述制作方法还可以包括：在导电材料层上方依次形成栅极绝缘层和钝化层，其中，所述连接孔在栅极绝缘层和钝化层中形成。如此形成的阵列基板可以是底栅型阵列基板，其中栅金属层位于源漏金属层下方。连接孔用于通过导电材料层对公共电极线进行电连接。
在一些实施例中，可以在一个图案化工艺过程中同时形成导电材料层与阵列基板的公共电极层。
应当指出的是，本公开的第二、第三和第四方面具有与本公开的第一方面类似或相同的示例实现和益处，在此不再赘述。
本公开的这些和其它方面将从以下描述的实施例显而易见并且将参照以下描述的实施例加以阐述。
附图说明
图1是根据本公开的一些实施例的阵列基板的部分的横截面视图；
图2是根据本公开的一些实施例的阵列基板的部分的横截面视图；
图3是根据本公开的一些实施例的阵列基板的部分的横截面视图；
图4是根据本公开的一些实施例的阵列基板的部分的横截面视图；
图5是根据本公开的一些实施例的阵列基板的部分的横截面视图；
图6图示了根据本公开的一些实施例的制作阵列基板的方法的流程图；以及
图7a-7d是图示了图6所示的阵列基板制作方法的各步骤的示意图。
具体实施方式
以下将结合附图详细描述本公开的示例性实施例。附图是示意性的，并未按比例绘制，且只是为了说明本公开的实施例而并不意图限 制本公开的保护范围。在附图中，相同的附图标记表示相同或相似的部分。为了使本公开的技术方案更加清楚，本领域熟知的工艺步骤及器件结构在此省略。
图1图示了根据本公开的一个实施例的阵列基板的部分的横截面视图。如图1所示，阵列基板包括衬底基板101、布置在衬底基板上方的金属层102、布置在金属层102之上的导电材料层103、布置在导电材料层103上的其它层105(可能包括多个子层)，以及布置在导电材料层103上方的、暴露出导电材料层103的连接孔106。
在如图1所示的阵列基板中，通过在金属层102上方布置导电材料层103，在对金属层102上方的其它层105进行蚀刻以形成连接孔106的过程中，该导电材料层103保护金属层102不受蚀刻影响，从而减少或甚至避免金属层102中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
在如图1所示的阵列基板中，导电材料层103可以与阵列基板的显示驱动电极层(在图1中未示出)同层。
相比于现有技术中首先形成显示驱动电极层，而后形成金属层的制造过程，在该实施例中，首先形成金属层，而后同层形成显示驱动电极层和导电材料层，从而在不增加阵列基板层数以及厚度的情况下，避免金属层中的金属材料在蚀刻连接孔时出现鼓包状缺陷，从而改善最终产品品质。
金属层102可以包括阵列基板的信号线。例如，信号线可以包括数据线。图2图示了根据本公开的一个实施例的底栅型阵列基板的部分的横截面视图。如图2所示，阵列基板包括衬底基板201、布置在衬底基板201上方的数据线202、布置在数据线202之上的导电材料层203、布置在数据线202与衬底基板201之间的栅极绝缘层207、布置在导电材料层203上方的钝化层205，以及形成在钝化层205中的、暴露出导电材料层203的连接孔206。连接孔206用于通过导电材料层203对数据线202进行电连接。
在如图2所示的阵列基板中，通过在数据线202之上布置导电材料层203，在对数据线202上方的钝化层205进行蚀刻以形成连接孔206的过程中，该导电材料层203保护数据线202不受蚀刻影响，从而减少或甚至避免数据线202中的鼓包状缺陷的产生，从而提高最终产 品品质和产率。
本公开的发明概念还可以应用于顶栅型阵列基板中。图3图示了根据本公开的另一实施例的顶栅型阵列基板的部分的横截面视图。如图3所示，阵列基板包括衬底基板301、布置在衬底基板301上方的数据线302、布置在数据线302之上的导电材料层303、依次布置在导电材料层303上方的栅极绝缘层307和钝化层305，以及形成在栅极绝缘层307和钝化层305中的、暴露出导电材料层303的连接孔306。连接孔306用于通过导电材料层303对数据线302进行电连接。
在如图2所示的阵列基板中，通过在数据线302之上布置导电材料层303，在对数据线302上方的栅极绝缘层307和钝化层305进行蚀刻以形成连接孔306的过程中，该导电材料层303保护数据线302不受蚀刻影响，从而减少或甚至避免数据线302中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
在如图2和图3所示的阵列基板中，导电材料层203和/或导电材料层303可以与阵列基板的像素电极层(在图中未示出)同层。相比于现有技术中首先形成像素电极层，而后形成数据线的制造过程，在该实施例中，首先形成数据线，而后同层形成像素电极层和导电材料层，从而在不增加阵列基板层数以及厚度的情况下，避免数据线中的金属材料在蚀刻连接孔时出现鼓包状缺陷，从而改善最终产品品质。
图4是根据本公开的又一实施例的底栅型阵列基板的部分的横截面视图。如图4所示，阵列基板包括衬底基板401、布置在衬底基板401上方的公共电极线402、布置在公共电极线402之上的导电材料层403、依次布置在导电材料层403上方的栅极绝缘层407和钝化层405，以及形成在栅极绝缘层407和钝化层405中的、暴露出导电材料层403的连接孔406。连接孔406用于通过导电材料层403对公共电极线402进行电连接。
在如图4所示的阵列基板中，通过在公共电极线402上方布置导电材料层403，在对公共电极线402上方的栅极绝缘层407和钝化层405进行蚀刻以形成连接孔406的过程中，该导电材料层403保护公共电极线402不受蚀刻影响，从而减少或甚至避免公共电极线402中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
在如图4所示的阵列基板中，导电材料层403可以与阵列基板的 公共电极层(在图4中未示出)同层。相比于现有技术中首先形成公共电极层，而后形成公共电极线的制造过程，在该实施例中，首先形成公共电极线，而后同层形成公共电极层和导电材料层，从而在不增加阵列基板层数以及厚度的情况下，避免公共电极线中的金属材料在蚀刻连接孔时出现鼓包状缺陷，从而改善最终产品品质。
图1中所示的阵列基板可以包括薄膜晶体管，并且金属层102可以包括薄膜晶体管的源极和漏极中的至少一个。图5图示了根据本公开的一个实施例的阵列基板的部分的横截面视图。如图5所示，阵列基板包括衬底基板501、布置在衬底基板501上方的源漏极502、布置在源漏极502之间的有源区508、布置在源漏极502之上的导电材料层503、布置在导电材料层503上方的栅极绝缘层507、布置在栅极绝缘层507中的、暴露出导电材料层503的连接孔506，以及布置在栅极绝缘层507上方的栅极504。连接孔506用于通过导电材料层503对源漏极502进行电连接。
在如图5所示的阵列基板中，通过在薄膜晶体管的源极和/或漏极502上形成导电材料层503，可以在源极和/或漏极502上方的栅极绝缘层507进行蚀刻以形成连接孔506的过程中，保护源极和/或漏极502不会因为蚀刻影响而产生质量降级。
在上述实施例中的一个或多个中，导电材料层由导电氧化物制成。例如，导电氧化物可以包括铟锡氧化物、铝掺杂的氧化锌、铟掺杂的氧化锌或铟掺杂的氧化镉中的一个或多个。另外，金属层102、数据线202，302、公共电极线402和源漏极502中的一个或多个可以由铜和/或铝制成。
图6图示了根据本公开的实施例的阵列基板的制作方法的流程图，并且图7a-7d示意性地图示了该制作方法的各步骤。
在步骤S601中，如图7a中所示，在衬底基板701上方形成金属层702。金属层702可以通过溅射、蒸镀、光刻、剥离等工艺制作。
在步骤S602中，如图7b中所示，在金属层702之上形成导电材料层703。导电材料层703可以通过旋涂、光刻、剥离等工艺制作。
在步骤S603中，如图7c中所示，在导电材料层703上方形成其它层705，所述其它层705可以包括多个子层，诸如以上提到的栅极绝缘层、钝化层等。
在步骤S604中，如图7d中所示，采用干法蚀刻的方法对金属层702上方的其它层705进行蚀刻以形成暴露出导电材料层703的连接孔706。
在上述阵列基板的制作方法中，通过在金属层上方形成导电材料层，在对金属层上方的诸如栅极绝缘层、钝化层之类的层进行蚀刻以形成连接孔的后续过程中，该导电材料层保护金属层不受蚀刻影响，从而减少或甚至避免金属层中的鼓包状缺陷的产生，从而提高最终产品品质和产率。
可选地，在一个图案化工艺过程中同时形成导电材料层和阵列基板的显示驱动电极层。
可选地，金属层包括数据线，并且阵列基板的制作方法还可以包括在形成导电材料层之前在衬底基板上形成栅极绝缘层；以及在导电材料层上方形成钝化层，其中，所述连接孔在钝化层中形成。如此形成的阵列基板可以是底栅型阵列基板，其中栅金属层位于源漏金属层下方。连接孔用于通过导电材料层对数据线进行电连接。
可选地，阵列基板的制作方法还可以包括：在导电材料层上方依次形成栅极绝缘层和钝化层，其中，所述连接孔在栅极绝缘层和钝化层中形成。如此形成的阵列基板可以是顶栅型阵列基板，其中栅金属层位于源漏金属层上方。同样地，连接孔用于通过导电材料层对数据线进行电连接。
可选地，在一个图案化工艺过程中同时形成导电材料层与阵列基板的像素电极层。
可选地，金属层包括公共电极线，并且阵列基板的制作方法还包括：在导电材料层上方依次形成栅极绝缘层和钝化层，其中，所述连接孔在栅极绝缘层和钝化层中形成。如此形成的阵列基板可以是底栅型阵列基板，其中栅金属层位于源漏金属层下方。连接孔用于通过导电材料层对公共电极线进行电连接。
可选地，在一个图案化工艺过程中同时形成导电材料层与阵列基板的公共电极层。
本公开还提供了一种显示面板和显示装置，其包括上述任一实施例所述的阵列基板。
本公开的概念可以广泛应用于任何具有显示功能的系统，包括台 式计算机、膝上型计算机、移动电话、平板电脑等。另外，尽管上文已经详细描述了几个实施例，但是其它修改是可能的。例如，以上描述的流程图不要求所描述的特定次序或顺序的次序来实现合期望的结果。可以提供其它步骤，或者可以从所描述的流中除去步骤，并且其它组件可以添加到所描述的系统或者从所描述的系统移除。其它实施例可以在本公开的范围内。本领域技术人员鉴于本公开的教导，可以实现众多变型和修改而不脱离于本公开的精神和范围。

Claims (25)

  1. 一种阵列基板，包括衬底基板、布置在衬底基板上方的金属层、布置在金属层之上的导电材料层，以及布置在导电材料层上方的、暴露出导电材料层的连接孔。
  2. 根据权利要求1所述的阵列基板，其中，所述导电材料层与阵列基板的显示驱动电极层同层。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括薄膜晶体管，并且所述金属层包括薄膜晶体管的源极和漏极中的至少一个。
  4. 根据权利要求1所述的阵列基板，其中，所述金属层包括阵列基板的信号线。
  5. 根据权利要求4所述的阵列基板，其中，所述信号线包括数据线。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括布置在数据线与衬底基板之间的栅极绝缘层以及布置在导电材料层上方的钝化层，所述连接孔布置在钝化层中。
  7. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括依次布置在导电材料层上方的栅极绝缘层和钝化层，所述连接孔布置在栅极绝缘层和钝化层中。
  8. 根据权利要求5-7中任一项所述的阵列基板，其中，所述导电材料层与阵列基板的像素电极层同层。
  9. 根据权利要求4所述的阵列基板，其中，所述信号线包括公共电极线，并且所述阵列基板还包括依次布置在导电材料层上方的栅极绝缘层和钝化层，所述连接孔布置在栅极绝缘层和钝化层中。
  10. 根据权利要求3或9所述的阵列基板，其中，所述导电材料层与阵列基板的公共电极层同层。
  11. 根据权利要求1所述的阵列基板，其中，所述导电材料层由导电氧化物制成。
  12. 根据权利要求11所述的阵列基板，其中，所述导电氧化物包括铟锡氧化物、铝掺杂的氧化锌、铟掺杂的氧化锌或铟掺杂的氧化镉中的一个或多个。
  13. 根据权利要求1所述的阵列基板，其中，所述金属层由铜和/或铝制成。
  14. 一种显示面板，包括权利要求1-13中任一项所述的阵列基板。
  15. 一种显示装置，包括权利要求14所述的显示面板。
  16. 一种阵列基板的制作方法，包括：
    在衬底基板上方形成金属层；
    在金属层之上形成导电材料层；以及
    在导电材料层上方形成暴露出导电材料层的连接孔。
  17. 根据权利要求16所述的制作方法，其中，在一个图案化工艺过程中同时形成导电材料层和阵列基板的显示驱动电极层。
  18. 根据权利要求16所述的制作方法，其中，所述阵列基板包括薄膜晶体管，并且所述金属层包括薄膜晶体管的源极和漏极中的至少一个。
  19. 根据权利要求16所述的制作方法，其中，所述金属层包括阵列基板的信号线。
  20. 根据权利要求19所述的制作方法，其中，所述信号线包括数据线。
  21. 根据权利要求20所述的制作方法，还包括：
    在形成导电材料层之前在衬底基板上形成栅极绝缘层；以及
    在导电材料层上方形成钝化层，
    其中，
    所述连接孔在钝化层中形成。
  22. 根据权利要求20所述的制作方法，还包括：
    在导电材料层上方依次形成栅极绝缘层和钝化层，
    其中，
    所述连接孔在栅极绝缘层和钝化层中形成。
  23. 根据权利要求20-22中任一项所述的制作方法，其中，在一个图案化工艺过程中同时形成导电材料层与阵列基板的像素电极层。
  24. 根据权利要求19所述的制作方法，其中，所述信号线包括公共电极线，并且所述制作方法还包括：
    在导电材料层上方依次形成栅极绝缘层和钝化层，
    其中，
    所述连接孔在栅极绝缘层和钝化层中形成。
  25. 根据权利要求18或24所述的阵列基板，其中，在一个图案化工艺过程中同时形成导电材料层与阵列基板的公共电极层。
PCT/CN2017/070286 2016-04-29 2017-01-05 阵列基板及其制作方法、显示面板和显示装置 Ceased WO2017185823A1 (zh)

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