WO2017181464A1 - Tft阵列基板及其制作方法 - Google Patents

Tft阵列基板及其制作方法 Download PDF

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Publication number
WO2017181464A1
WO2017181464A1 PCT/CN2016/082411 CN2016082411W WO2017181464A1 WO 2017181464 A1 WO2017181464 A1 WO 2017181464A1 CN 2016082411 W CN2016082411 W CN 2016082411W WO 2017181464 A1 WO2017181464 A1 WO 2017181464A1
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Prior art keywords
protective layer
data line
passivation protective
layer
drain
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French (fr)
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宋文庆
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/115,687 priority Critical patent/US20180182779A1/en
Publication of WO2017181464A1 publication Critical patent/WO2017181464A1/zh
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Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a TFT array substrate and a method of fabricating the same.
  • Liquid crystal display is one of the most widely used flat panel displays.
  • the liquid crystal display panel is a core component of liquid crystal displays.
  • the liquid crystal display panel usually consists of a color filter (CF) substrate, a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • the TFT array substrate is provided with TFTs arranged in an array for driving the rotation of the liquid crystal to control the display of each pixel
  • the CF substrate is provided with a color filter layer for forming each pixel. color.
  • the working principle of the liquid crystal display panel is to control the rotation of the liquid crystal molecules of the liquid crystal layer by applying a driving voltage on the TFT array substrate and the CF substrate, and refract the light of the backlight module to generate a picture.
  • the technology development of liquid crystal displays is becoming more and more mature.
  • the main development direction is to reduce the power consumption of liquid crystal display panels.
  • FIG. 1 is a schematic structural diagram of a conventional TFT array substrate, including: a substrate substrate 100', a gate electrode 200' disposed on the substrate substrate 100', and a gate electrode disposed on the gate electrode 200'.
  • the insulating layer 300 ′, the active layer 400 ′ disposed on the gate insulating layer 300 ′ and corresponding to the gate 200 ′, disposed on the gate insulating layer 300 ′ and the active layer 400 ′ and the active layer 400 respectively a source 500' and a drain 600' which are in contact with each other, and a data line 700' disposed on the gate insulating layer 300' in the same layer as the source 500' and the drain 600', covering the gate An insulating layer 300', a source 500', a drain 600', a passivation protective layer 800' with the data line 700', and a pixel electrode 900' disposed on the passivation protective layer 800', wherein the pixel electrode 900' passes The via 810' penetrating the passiva
  • the capacitance Cgd is inversely proportional to the pitch of the data line 700' and the gate 200', and the pitch of the data line 700' and the gate 200' can be increased by increasing the thickness of the gate insulating layer 300', thereby reducing the parasitic capacitance Cgd, however,
  • the source 500', the drain 600', and the data line 700' of the TFT are located on the same layer, and are disposed on the gate insulating layer 300'.
  • the parasitic capacitance Cgd is controlled.
  • the position of the source 500' and the drain 600' is changed to avoid the TFT characteristics. Therefore, the conventional TFT array substrate shown in FIG. 1 cannot flexibly adjust the parasitic capacitance Cgd.
  • the object of the present invention is to provide a TFT array substrate, which can flexibly adjust the spacing between the data line and the gate, reduce the parasitic capacitance between the data line and the gate, and reduce the data line under the premise of ensuring the characteristics of the TFT. Power consumption.
  • Another object of the present invention is to provide a method for fabricating a TFT array substrate, which can ensure TFT characteristics, reduce parasitic capacitance between data lines and gates, and reduce power consumption of data lines.
  • the present invention first provides a TFT array substrate, comprising: a substrate substrate, a TFT disposed on the substrate, a first passivation protective layer covering the TFT, and the first Passivating a data line on the protective layer, a second passivation protective layer covering the first passivation protective layer and the data line, and a pixel electrode disposed on the second passivation protective layer;
  • the TFT includes: a gate disposed on the substrate, a gate insulating layer covering the gate and the substrate, an active layer disposed on the gate insulating layer above the gate, And a source and a drain respectively contacting the two ends of the active layer on the gate insulating layer;
  • a first via hole penetrating through the first passivation protection layer is disposed above the drain; the data line is in contact with the drain through the first via hole.
  • the materials of the source, the drain, and the data line are the same metal material.
  • the material of the source, the drain, and the data line is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the substrate is a glass substrate; the material of the pixel electrode is ITO; the material of the gate insulating layer, the first passivation protective layer, and the second passivation protective layer is silicon nitride, silicon oxide, or a combination of the two.
  • a second via hole penetrating the first passivation protective layer and the second passivation protective layer is disposed above the source, and the pixel electrode is in contact with the source through the second via.
  • the invention also provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing and patterning a first metal layer on the substrate to form a gate;
  • Step 2 depositing a gate insulating layer on the gate and the substrate;
  • Step 3 forming an active layer on the gate insulating layer above the gate
  • Step 4 depositing and patterning a second metal layer on the gate insulating layer and the active layer for a first time to form a source and a drain respectively contacting the two ends of the active layer, thereby completing the fabrication of the TFT;
  • Step 5 depositing a first passivation protective layer on the source, the drain, and the gate insulating layer, and patterning the first passivation protective layer to form a through-first layer over the drain Passivating the first via of the protective layer;
  • Step 6 Depositing and patterning a second metal layer a second time on the first passivation protective layer to form a data line, and the data line is in contact with the drain through the first via hole;
  • Step 7 depositing a second passivation protective layer on the first passivation protective layer and the data line, and performing a patterning process, forming a through passivation protective layer and a first blunt on the source electrode a second via of the protective layer;
  • Step 8 Depositing and patterning a transparent conductive film on the second passivation protective layer to form a pixel electrode, and the pixel electrode is in contact with the source through the second via.
  • the material of the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the base substrate is a glass substrate; the transparent conductive film is an ITO film; the gate insulating layer, the first passivation protective layer, and the second passivation protective layer are made of silicon nitride, silicon oxide, or a combination of the two.
  • the present invention also provides a TFT array substrate, comprising: a base substrate, a TFT disposed on the base substrate, a first passivation protective layer covering the TFT, and disposed on the first passivation protective layer a data line, a second passivation protective layer covering the first passivation protective layer and the data line, and a pixel electrode disposed on the second passivation protective layer;
  • the TFT includes: a gate disposed on the substrate, a gate insulating layer covering the gate and the substrate, an active layer disposed on the gate insulating layer above the gate, And a source and a drain respectively contacting the two ends of the active layer on the gate insulating layer;
  • the materials of the source, the drain, and the data line are the same metal material
  • the substrate is a glass substrate; the material of the pixel electrode is ITO; the material of the gate insulating layer, the first passivation protective layer, and the second passivation protective layer is silicon nitride or silicon oxide. Or a combination of the two.
  • the TFT array substrate provided by the present invention has a source and a drain of a TFT disposed on a gate insulating layer, and a data line disposed on a first passivation protective layer covering a source and a drain of the TFT.
  • a source and a drain of a TFT disposed on a gate insulating layer
  • a data line disposed on a first passivation protective layer covering a source and a drain of the TFT.
  • the thickness of the first passivation protective layer is adjusted to flexibly adjust the spacing between the data line and the gate. Compared with the prior art, the spacing between the data line and the gate is increased, and the data line and the gate are reduced. The parasitic capacitance between them reduces the power consumption of the data line.
  • the method for fabricating a TFT array substrate provided by the present invention firstly forms a source and a drain of a TFT on a gate insulating layer, and then forms a data line on a first passivation protective layer covering a source and a drain of the TFT.
  • the TFT characteristics can be ensured, and the parasitic capacitance between the data line and the gate can be reduced, and the power consumption of the data line can be reduced.
  • 1 is a schematic structural view of a conventional TFT array substrate
  • FIG. 2 is a schematic structural view of a TFT array substrate of the present invention.
  • FIG. 3 is a flow chart showing a method of fabricating a TFT array substrate of the present invention.
  • FIG. 4 is a schematic view showing the first step of the method for fabricating the TFT array substrate of the present invention.
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT array substrate of the present invention
  • FIG. 6 is a schematic diagram of step 3 of a method for fabricating a TFT array substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating a TFT array substrate of the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating a TFT array substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 6 of a method of fabricating a TFT array substrate of the present invention.
  • step 7 of a method for fabricating a TFT array substrate of the present invention is a schematic diagram of step 7 of a method for fabricating a TFT array substrate of the present invention.
  • Figure 11 is a schematic view showing the step 8 of the method of fabricating the TFT array substrate of the present invention.
  • the present invention first provides a TFT array substrate, comprising: a substrate substrate 100, a TFT 200 disposed on the substrate substrate 100, a first passivation protective layer 300 covering the TFT 200, and a setting a data line 400 on the first passivation protection layer 300, a second passivation protection layer 500 covering the first passivation protection layer 300 and the data line 400, and a second passivation protection layer A pixel electrode 600 on 500.
  • the TFT 200 includes a gate 210 disposed on the base substrate 100 and covering the gate
  • the gate insulating layer 220 of the base substrate 100, the active layer 230 disposed on the gate insulating layer 220 over the gate 210, and the gate insulating layer 220 are respectively respectively in contact with A source 240 and a drain 250 are provided at both ends of the source layer 230.
  • a first via 310 penetrating through the first passivation protection layer 300 is disposed above the drain 250, and the data line 400 is in contact with the drain 250 through the first via 310.
  • a second via hole 350 penetrating the first passivation protective layer 300 and the second passivation protective layer 500 is disposed above the source 240, and the pixel electrode 600 is in contact with the source 240 through the second via 350 .
  • the base substrate 100 is a transparent substrate, preferably a glass substrate.
  • the source 240, the drain 250, and the data line 400 are made of the same metal material, and the metal material is preferably one of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu). Or a variety of stack combinations.
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the gate insulating layer 220, the first passivation protective layer 300, and the second passivation protective layer 500 may be silicon nitride (SiNx), silicon oxide (SiOx), or a combination of both.
  • the pixel electrode 600 is a transparent electrode, and the material is preferably Indium Tin Oxides (ITO).
  • ITO Indium Tin Oxides
  • the data line 400 and the gate 210 can be regarded as two oppositely disposed metal electrode plates with a parasitic capacitance Cgd therebetween.
  • Cgd parasitic capacitance
  • ⁇ 0 is the vacuum dielectric constant
  • ⁇ r is the relative dielectric constant of the material
  • s is the facing area of the data line 400 and the gate 210
  • d is the spacing between the data line 400 and the gate 210.
  • the data line 400 is disposed on the first passivation protection covering the source 240 and the drain 250 of the TFT 200.
  • the layer 300 that is, the data line 400 and the source 240 and the drain 250 of the TFT 200 are located at different layers, and the spacing between the data line 400 and the gate 210 is the thickness and gate of the first passivation protection layer 300.
  • the sum of the thicknesses of the pole insulating layers 220 increases the thickness of the first passivation protective layer 300 by the spacing between the data lines 400 and the gate electrodes 210 compared to the conventional TFT array substrate.
  • the parasitic capacitance Cgd is inversely proportional to the interval between the data line 400 and the gate 210, and the pitch between the data line 400 and the gate 210 is increased to reduce the parasitic capacitance Cgd, which can effectively reduce the data line.
  • the power consumption of the TFT array substrate further reduces the power consumption of the TFT array substrate.
  • the TFT array substrate of the present invention can flexibly adjust the spacing between the data line 400 and the gate 210 by adjusting the thickness of the first passivation protection layer 300.
  • the parasitic capacitance Cgd is flexibly adjusted, for example, by increasing the thickness of the first passivation protective layer 300 to increase the pitch between the data line 400 and the gate 210, and reducing the parasitic capacitance Cgd. It is worth noting that due to the relationship between the data line 400 and the gate 210 The reason why the pitch is increased is that the layer in which the data line 400 is located is raised to the first passivation protective layer 300, the thickness of the gate insulating layer 220 is not affected, and the positions of the source 240 and the drain 250 of the TFT 200 are not The characteristics of the TFT 200 can be kept stable.
  • the present invention further provides a method for fabricating a TFT array substrate, comprising the following steps:
  • Step 1 As shown in FIG. 4, a substrate substrate 100 is provided on which a first metal layer is deposited and patterned to form a gate electrode 210.
  • the base substrate 100 is a transparent substrate, preferably a glass substrate.
  • This step 1 uses a first mask to pattern the first metal layer by an etching process.
  • Step 2 As shown in FIG. 5, a gate insulating layer 220 is deposited on the gate 210 and the base substrate 100.
  • the material of the gate insulating layer 220 is silicon nitride, silicon oxide, or a combination of the two.
  • Step 3 As shown in FIG. 6, an active layer 230 is formed on the gate insulating layer 220 over the gate electrode 210.
  • the detailed process of forming the active layer 230 in the step 3 is: first depositing an amorphous silicon layer, then performing crystallization treatment to obtain a polysilicon layer, followed by ion doping, and finally patterning by an etching process using a second mask. Processing, the source layer 230 is obtained.
  • Step 4 depositing and patterning a second metal layer on the gate insulating layer 220 and the active layer 230 for a first time to form a source 240 respectively contacting both ends of the active layer 230 and The drain 250 is completed, and the fabrication of the TFT 200 is completed.
  • the material of the second metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • step 4 the second metal layer is subjected to a first patterning process by an etching process using a third mask to obtain a source 240 and a drain 250.
  • Step 5 depositing a first passivation protective layer 300 on the source 240, the drain 250, and the gate insulating layer 220, and patterning the first passivation protective layer 300 A first via 310 extending through the first passivation protection layer 300 is formed over the drain 250.
  • the material of the first passivation protective layer 300 is silicon nitride, silicon oxide, or a combination of the two.
  • This step 5 uses a fourth mask to pattern the first passivation protective layer 300 by an etching process.
  • Step 6 as shown in FIG. 9, a second metal layer is deposited and patterned on the first passivation protective layer 300 for a second time to form a data line 400, and the data line 400 passes through the first via 310. Contact with the drain 250.
  • the second metal layer described in the step 6 is the same as the material of the second metal layer in the above step 4, and is still a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • This step 6 uses a fifth mask to perform a second patterning process on the second metal layer by an etching process to obtain the data line 400.
  • Step 7 as shown in FIG. 10, depositing a second passivation protective layer 500 on the first passivation protective layer 300 and the data line 400, and performing a patterning process to form a through-passage over the source 240 The second passivation protective layer 500 and the second via 350 of the first passivation protective layer 300.
  • the material of the second passivation protective layer 500 is silicon nitride, silicon oxide, or a combination of the two.
  • This step 7 uses a sixth mask to pattern the second passivation protective layer 500 and the first passivation protective layer 300 by an etching process to form a second via 350.
  • Step 8 As shown in FIG. 11 , a transparent conductive film is deposited and patterned on the second passivation protective layer 500 to form a pixel electrode 600.
  • the pixel electrode 600 passes through the second via 350 and the source 240. contact.
  • the transparent conductive film is an ITO film.
  • This step 8 uses a seventh reticle to pattern the transparent conductive film by an etching process to form the pixel electrode 600.
  • the source 240 and the drain 250 of the TFT 200 are formed on the gate insulating layer 220, and the data line 400 is formed on the source 240 and the drain 250 of the TFT 200.
  • the first passivation protective layer 300 is such that the data line 400 and the source 240 and the drain 250 of the TFT 200 are located at different layers.
  • the data line 400 and the gate 210 can be regarded as two oppositely disposed metal electrode plates with a parasitic capacitance Cgd therebetween.
  • Cgd parasitic capacitance
  • ⁇ 0 is the vacuum dielectric constant
  • ⁇ r is the relative dielectric constant of the material
  • s is the facing area of the data line 400 and the gate 210
  • d is the spacing between the data line 400 and the gate 210.
  • the TFT array substrate produced by the method for fabricating the array substrate of the present invention has a data line 400 and a source 240 and a drain 250 of the TFT 200 in different layers, between the data line 400 and the gate 210.
  • the pitch is the sum of the thickness of the first passivation protective layer 300 and the thickness of the gate insulating layer 220. Compared with the conventional TFT array substrate, the spacing between the data line 400 and the gate 210 increases the first passivation. The thickness of the protective layer 300.
  • the parasitic capacitance Cgd is inversely proportional to the interval between the data line 400 and the gate 210, and the pitch between the data line 400 and the gate 210 is increased to reduce the parasitic capacitance Cgd, which can effectively reduce the data line.
  • 400 power consumption which in turn reduces the power consumption of the TFT array substrate; in addition, it can also be adjusted by adjusting the first passivation
  • the thickness of the layer 300 is used to flexibly adjust the spacing between the data line 400 and the gate 210, thereby flexibly adjusting the parasitic capacitance Cgd, such as increasing the thickness of the first passivation protection layer 300 to increase the data line 400 and the gate 210.
  • the spacing between them reduces the parasitic capacitance Cgd. It is to be noted that since the spacing between the data line 400 and the gate 210 is increased because the layer in which the data line 400 is located is raised to the first passivation protective layer 300, the thickness of the gate insulating layer 220 is not affected. The influence of the positions of the source 240 and the drain 250 of the TFT 200 is constant, and the characteristics of the TFT 200 can be kept stable.
  • the TFT array substrate of the present invention has a source and a drain of the TFT disposed on the gate insulating layer, and a data line disposed on the first passivation protective layer covering the source and the drain of the TFT.
  • the data line and the source and the drain of the TFT are located in different layers, and the spacing between the data line and the gate can be flexibly adjusted by adjusting the thickness of the first passivation protective layer, which is increased compared with the prior art.
  • the spacing between the data line and the gate reduces the parasitic capacitance between the data line and the gate, reduces the power consumption of the data line, and at the same time, the thickness of the gate insulating layer is not affected, and the source of the TFT is The position of the drain is constant, and the stability of the TFT characteristics can be maintained.
  • the source and the drain of the TFT are first formed on the gate insulating layer, and the data line is formed on the first passivation protective layer covering the source and the drain of the TFT. It can not only ensure the characteristics of the TFT, but also reduce the parasitic capacitance between the data line and the gate, and reduce the power consumption of the data line.

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Abstract

本发明提供一种TFT阵列基板及其制作方法。该TFT阵列基板将TFT(200)的源极(240)和漏极(250)设置在栅极绝缘层(220)上，将数据线(400)设置在覆盖TFT(200)的源极(240)和漏极(250)的第一钝化保护层(300)上，使得数据线(400)与TFT(200)的源极(240)和漏极(250)位于不同的层别，能够通过调整第一钝化保护层(300)的厚度来灵活调整数据线(400)与栅极(210)之间的间距，与现有技术相比，增大了数据线(400)与栅极(210)之间的间距，减小了数据线(400)与栅极(210)之间的寄生电容，降低了数据线(400)的功耗，同时，栅极绝缘层(220)的厚度不受影响，TFT(200)的源极(240)与漏极(250)的位置不变，能够维持TFT特性的稳定。

Description

TFT阵列基板及其制作方法 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种TFT阵列基板及其制作方法。
背景技术
液晶显示器(Liquid Crystal Display，LCD)是目前最广泛使用的平板显示器之一，液晶显示面板是液晶显示器的核心组成部分。
液晶显示面板通常是由一彩色滤光片(Color Filter，CF)基板、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其中TFT阵列基板上制备有呈阵列式排布的TFT，用于驱动液晶的旋转，控制每个像素的显示，而CF基板上设置有彩色滤光层，用于形成每个像素的色彩。液晶显示面板的工作原理是通过在TFT阵列基板与CF基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
目前，液晶显示器的技术发展日趋成熟，现阶段以降低液晶显示面板的功耗为主要发展方向。
请参阅图1，为一种现有的TFT阵列基板的结构示意图，包括：衬底基板100’、设置在衬底基板100’上的栅极200’、设置在栅极200’上的栅极绝缘层300’、设置在栅极绝缘层300’上且位置与栅极200’对应的有源层400’，设置在栅极绝缘层300’和有源层400’上分别与有源层400’两端接触的源极500’和漏极600’、设置在栅极绝缘层300’上与所述源极500’和漏极600’位于同一层的数据线700’、覆盖所述栅极绝缘层300’、源极500’、漏极600’、与数据线700’的钝化保护层800’、以及设置在钝化保护层800’上的像素电极900’，其中像素电极900’通过贯穿钝化保护层800’的过孔810’与源极500’接触。
该现有的TFT阵列基板的数据线700’与栅极200’之间会产生寄生电容Cgd，公式为：Cgd＝ε0εr s/d，其中，ε0为真空介电常数，εr为材料的相对介电常数，s为数据线700’与栅极200’的正对面积，d为数据线700’与栅极200’的间距，即栅极绝缘层300’的厚度。
为降低数据线700’的功耗，需要减少寄生电容Cgd的值。由于寄生电 容Cgd与数据线700’和栅极200’的间距成反比，可以通过增加栅极绝缘层300’的厚度使数据线700’和栅极200’的间距增加，进而减少寄生电容Cgd，但是，TFT的源极500’、漏极600’、及数据线700’位于同一层，均设置在栅极绝缘层300’上，在改变栅极绝缘层300’的厚度控制寄生电容Cgd的同时，不可避免地使得源极500’及漏极600’的位置改变，影响到TFT特性，因此，图1所示的现有TFT阵列基板不能灵活地调整寄生电容Cgd。
发明内容
本发明的目的在于提供一种TFT阵列基板，能够在保证TFT特性的前提下，灵活调整数据线与栅极之间的间距，减小数据线与栅极之间的寄生电容，降低数据线的功耗。
本发明的另一目的在于提供一种TFT阵列基板的制作方法，既能够保证TFT特性，又能够减小数据线与栅极之间的寄生电容，降低数据线的功耗。
为实现上述目的，本发明首先提供一种TFT阵列基板，包括：衬底基板、设置在所述衬底基板上的TFT、覆盖所述TFT的第一钝化保护层、设置在所述第一钝化保护层上的数据线、覆盖所述第一钝化保护层和数据线的第二钝化保护层、及设置在所述第二钝化保护层上的像素电极；
所述TFT包括：设置在衬底基板上的栅极、覆盖所述栅极与衬底基板的栅极绝缘层、于所述栅极上方设置在所述栅极绝缘层上的有源层、及设置在所述栅极绝缘层上分别接触有源层两端的源极和漏极；
在所述漏极上方设有贯穿第一钝化保护层第一过孔；所述数据线通过所述第一过孔与漏极接触。
所述源极、漏极、及数据线的材料为相同的金属材料。
所述源极、漏极、及数据线的材料同为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述衬底基板为玻璃基板；所述像素电极的材料为ITO；所述栅极绝缘层、第一钝化保护层、与第二钝化保护层的材料为氮化硅、氧化硅、或二者的组合。
在所述源极上方设有贯穿第一钝化保护层与第二钝化保护层的第二过孔，所述像素电极通过所述第二过孔与源极接触。
本发明还提供一种TFT阵列基板的制作方法，包括以下步骤：
步骤1、提供一衬底基板，在所述衬底基板上沉积并图案化第一金属层，形成栅极；
步骤2、在所述栅极与衬底基板上沉积栅极绝缘层；
步骤3、于所述栅极上方在所述栅极绝缘层上形成有源层；
步骤4、在所述栅极绝缘层与有源层上第一次沉积并图案化第二金属层，形成分别与有源层两端接触的源极和漏极，至此完成TFT的制作；
步骤5、在所述源极、漏极、与栅极绝缘层上沉积覆盖第一钝化保护层，并对第一钝化保护层进行图案化处理，在所述漏极上方形成贯穿第一钝化保护层的第一过孔；
步骤6、在所述第一钝化保护层上第二次沉积并图案化第二金属层，形成数据线，所述数据线通过所述第一过孔与漏极接触；
步骤7、在所述第一钝化保护层、与数据线上沉积覆盖第二钝化保护层，并进行图案化处理，在所述源极上方形成贯穿第二钝化保护层与第一钝化保护层的第二过孔；
步骤8、在所述第二钝化保护层上沉积并图案化透明导电薄膜，形成像素电极，所述像素电极通过所述第二过孔与源极接触。
所述第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述衬底基板为玻璃基板；所述透明导电薄膜为ITO薄膜；所述栅极绝缘层、第一钝化保护层、与第二钝化保护层的材料为氮化硅、氧化硅、或二者的组合。
本发明还提供一种TFT阵列基板，包括：衬底基板、设置在所述衬底基板上的TFT、覆盖所述TFT的第一钝化保护层、设置在所述第一钝化保护层上的数据线、覆盖所述第一钝化保护层和数据线的第二钝化保护层、及设置在所述第二钝化保护层上的像素电极；
所述TFT包括：设置在衬底基板上的栅极、覆盖所述栅极与衬底基板的栅极绝缘层、于所述栅极上方设置在所述栅极绝缘层上的有源层、及设置在所述栅极绝缘层上分别接触有源层两端的源极和漏极；
在所述漏极上方设有贯穿第一钝化保护层的第一过孔；所述数据线通过所述第一过孔与漏极接触；
其中，所述源极、漏极、及数据线的材料为相同的金属材料；
其中，所述衬底基板为玻璃基板；所述像素电极的材料为ITO；所述栅极绝缘层、第一钝化保护层、与第二钝化保护层的材料为氮化硅、氧化硅、或二者的组合。
本发明的有益效果：本发明提供的TFT阵列基板，将TFT的源极和漏极设置在栅极绝缘层上，将数据线设置在覆盖TFT的源极和漏极的第一钝化保护层上，使得数据线与TFT的源极和漏极位于不同的层别，能够通过 调整第一钝化保护层的厚度来灵活调整数据线与栅极之间的间距，与现有技术相比，增大了数据线与栅极之间的间距，减小了数据线与栅极之间的寄生电容，降低了数据线的功耗，同时，栅极绝缘层的厚度不受影响，TFT的源极与漏极的位置不变，能够维持TFT特性的稳定。本发明提供的TFT阵列基板的制作方法，先将TFT的源极和漏极制作在栅极绝缘层上，再将数据线制作在覆盖TFT的源极和漏极的第一钝化保护层上，既能够保证TFT特性，又能够减小数据线与栅极之间的寄生电容，降低数据线的功耗。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为一种现有的TFT阵列基板的结构示意图；
图2为本发明的TFT阵列基板的结构示意图；
图3为本发明的TFT阵列基板的制作方法的流程图；
图4为本发明的TFT阵列基板的制作方法的步骤1的示意图；
图5为本发明的TFT阵列基板的制作方法的步骤2的示意图；
图6为本发明的TFT阵列基板的制作方法的步骤3的示意图；
图7为本发明的TFT阵列基板的制作方法的步骤4的示意图；
图8为本发明的TFT阵列基板的制作方法的步骤5的示意图；
图9为本发明的TFT阵列基板的制作方法的步骤6的示意图；
图10为本发明的TFT阵列基板的制作方法的步骤7的示意图；
图11为本发明的TFT阵列基板的制作方法的步骤8的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种TFT阵列基板，包括：衬底基板100、设置在所述衬底基板100上的TFT 200、覆盖所述TFT 200的第一钝化保护层300、设置在所述第一钝化保护层300上的数据线400、覆盖所述第一钝化保护层300和数据线400的第二钝化保护层500、及设置在所述第二钝化保护层500上的像素电极600。
所述TFT 200包括：设置在衬底基板100上的栅极210、覆盖所述栅极 210与衬底基板100的栅极绝缘层220、于所述栅极210上方设置在所述栅极绝缘层220上的有源层230、及设置在所述栅极绝缘层220上分别接触有源层230两端的源极240和漏极250。
在所述漏极250上方设有贯穿第一钝化保护层300的第一过孔310，所述数据线400通过所述第一过孔310与漏极250接触。
在所述源极240上方设有贯穿第一钝化保护层300与第二钝化保护层500的第二过孔350，所述像素电极600通过所述第二过孔350与源极240接触。
具体地，所述衬底基板100为透明基板，优选玻璃基板。
所述源极240、漏极250、及数据线400使用相同的金属材料制作，所述金属材料优选为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
所述栅极绝缘层220、第一钝化保护层300、与第二钝化保护层500的材料可为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
所述像素电极600为透明电极，材料优选氧化铟锡(Indium Tin Oxides，ITO)。
进一步地，数据线400、与栅极210可以看作是两相对设置的金属电极板，二者之间存在寄生电容Cgd。由电容的计算公式知：
Cgd＝ε0εr s/d(1)
其中，ε0为真空介电常数，εr为材料的相对介电常数，s为数据线400与栅极210的正对面积，d为数据线400与栅极210之间的间距。
本发明的TFT阵列基板中，由于TFT 200的源极240和漏极250设置在栅极绝缘层220上，数据线400设置在覆盖TFT 200的源极240和漏极250的第一钝化保护层300上，即数据线400与TFT 200的源极240和漏极250位于不同的层别，所述数据线400与栅极210之间的间距为第一钝化保护层300的厚度与栅极绝缘层220的厚度之和，相较于传统的TFT阵列基板，所述数据线400与栅极210之间的间距增加了第一钝化保护层300的厚度。根据公式(1)可知寄生电容Cgd与数据线400和栅极210之间的间距成反比，数据线400与栅极210之间的间距增大使得寄生电容Cgd减小，能够有效地降低数据线400的功耗，进而降低TFT阵列基板的功耗；另外，本发明的TFT阵列基板能够通过调整第一钝化保护层300的厚度来灵活调整数据线400与栅极210之间的间距，进而灵活调整寄生电容Cgd，如通过增大第一钝化保护层300的厚度来增大数据线400与栅极210之间的间距，减小寄生电容Cgd。值得注意的是，由于数据线400与栅极210之间 的间距增大的原因是将数据线400所在的层别升至第一钝化保护层300上，栅极绝缘层220的厚度不受影响，TFT 200的源极240与漏极250的位置不变，能够使TFT 200的特性保持稳定。
请参阅图3，基于同一发明构思，本发明还提供一种TFT阵列基板的制作方法，包括以下步骤：
步骤1、如图4所示，提供一衬底基板100，在所述衬底基板100上沉积并图案化第一金属层，形成栅极210。
具体地，所述衬底基板100为透明基板，优选为玻璃基板。
该步骤1使用第一道光罩通过蚀刻工艺来图案化第一金属层。
步骤2、如图5所示，在所述栅极210与衬底基板100上沉积栅极绝缘层220。
具体地，所述栅极绝缘层220的材料为氮化硅、氧化硅、或二者的组合。
步骤3、如图6所示，于所述栅极210上方在所述栅极绝缘层220上形成有源层230。
具体地，该步骤3形成有源层230的详细过程为：首先沉积非晶硅层，然后进行晶化处理得到多晶硅层，接着进行离子掺杂，最后使用第二道光罩通过蚀刻工艺进行图案化处理，得到源层230。
步骤4、如图7所示，在所述栅极绝缘层220与有源层230上第一次沉积并图案化第二金属层，形成分别与有源层230两端接触的源极240和漏极250，至此完成TFT 200的制作。
具体地，所述第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
该步骤4使用第三道光罩通过蚀刻工艺来对第二金属层进行第一次图案化处理得到源极240和漏极250。
步骤5、如图8所示，在所述源极240、漏极250、与栅极绝缘层220上沉积覆盖第一钝化保护层300，并对第一钝化保护层300进行图案化处理，在所述漏极250上方形成贯穿第一钝化保护层300的第一过孔310。
具体地，所述第一钝化保护层300的材料为氮化硅、氧化硅、或二者的组合。
该步骤5使用第四道光罩通过蚀刻工艺来图案化第一钝化保护层300。
步骤6、如图9所示，在所述第一钝化保护层300上第二次沉积并图案化第二金属层，形成数据线400，所述数据线400通过所述第一过孔310与漏极250接触。
具体地，该步骤6中所述的第二金属层与上述步骤4中的第二金属层的材料相同，仍为钼、钛、铝、铜中的一种或多种的堆栈组合。
该步骤6使用第五道光罩通过蚀刻工艺来对第二金属层进行第二次图案化处理得到数据线400。
步骤7、如图10所示，在所述第一钝化保护层300、与数据线400上沉积覆盖第二钝化保护层500，并进行图案化处理，在所述源极240上方形成贯穿第二钝化保护层500与第一钝化保护层300的第二过孔350。
具体地，所述第二钝化保护层500的材料为氮化硅、氧化硅、或二者的组合。
该步骤7使用第六道光罩通过蚀刻工艺来图案化第二钝化保护层500与第一钝化保护层300，形成第二过孔350。
步骤8、如图11所示，在所述第二钝化保护层500上沉积并图案化透明导电薄膜，形成像素电极600，所述像素电极600通过所述第二过孔350与源极240接触。
具体地，所述透明导电薄膜为ITO薄膜。
该步骤8使用第七道光罩通过蚀刻工艺来图案化透明导电薄膜形成像素电极600。
本发明的TFT阵列基板的制作方法，先将TFT 200的源极240和漏极250制作在栅极绝缘层220上，再将数据线400制作在覆盖TFT 200的源极240和漏极250的第一钝化保护层300上，使得数据线400与TFT 200的源极240和漏极250位于不同的层别。
数据线400、与栅极210可以看作是两相对设置的金属电极板，二者之间存在寄生电容Cgd。由电容的计算公式知：
Cgd＝ε0εr s/d                (1)
其中，ε0为真空介电常数，εr为材料的相对介电常数，s为数据线400与栅极210的正对面积，d为数据线400与栅极210之间的间距。
通过本发明的阵列基板的制作方法制得的TFT阵列基板，由于其数据线400与TFT 200的源极240和漏极250位于不同的层别，所述数据线400与栅极210之间的间距为第一钝化保护层300的厚度与栅极绝缘层220的厚度之和，相较于传统的TFT阵列基板，所述数据线400与栅极210之间的间距增加了第一钝化保护层300的厚度。根据公式(1)可知寄生电容Cgd与数据线400和栅极210之间的间距成反比，数据线400与栅极210之间的间距增大使得寄生电容Cgd减小，能够有效地降低数据线400的功耗，进而降低TFT阵列基板的功耗；另外，还能够通过调整第一钝化保护 层300的厚度来灵活调整数据线400与栅极210之间的间距，进而灵活调整寄生电容Cgd，如通过增大第一钝化保护层300的厚度来增大数据线400与栅极210之间的间距，减小寄生电容Cgd。值得注意的是，由于数据线400与栅极210之间的间距增大的原因是将数据线400所在的层别升至第一钝化保护层300上，栅极绝缘层220的厚度不受影响，TFT 200的源极240与漏极250的位置不变，能够使TFT 200的特性保持稳定。
综上所述，本发明的TFT阵列基板，将TFT的源极和漏极设置在栅极绝缘层上，将数据线设置在覆盖TFT的源极和漏极的第一钝化保护层上，使得数据线与TFT的源极和漏极位于不同的层别，能够通过调整第一钝化保护层的厚度来灵活调整数据线与栅极之间的间距，与现有技术相比，增大了数据线与栅极之间的间距，减小了数据线与栅极之间的寄生电容，降低了数据线的功耗，同时，栅极绝缘层的厚度不受影响，TFT的源极与漏极的位置不变，能够维持TFT特性的稳定。本发明的TFT阵列基板的制作方法，先将TFT的源极和漏极制作在栅极绝缘层上，再将数据线制作在覆盖TFT的源极和漏极的第一钝化保护层上，既能够保证TFT特性，又能够减小数据线与栅极之间的寄生电容，降低数据线的功耗。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种TFT阵列基板，包括：衬底基板、设置在所述衬底基板上的TFT、覆盖所述TFT的第一钝化保护层、设置在所述第一钝化保护层上的数据线、覆盖所述第一钝化保护层和数据线的第二钝化保护层、及设置在所述第二钝化保护层上的像素电极；
    所述TFT包括：设置在衬底基板上的栅极、覆盖所述栅极与衬底基板的栅极绝缘层、于所述栅极上方设置在所述栅极绝缘层上的有源层、及设置在所述栅极绝缘层上分别接触有源层两端的源极和漏极；
    在所述漏极上方设有贯穿第一钝化保护层的第一过孔；所述数据线通过所述第一过孔与漏极接触。
  2. 如权利要求1所述的TFT阵列基板，其中，所述源极、漏极、及数据线的材料为相同的金属材料。
  3. 如权利要求2所述的TFT阵列基板，其中，所述源极、漏极、及数据线的材料同为钼、钛、铝、铜中的一种或多种的堆栈组合。
  4. 如权利要求1所述的TFT阵列基板，其中，所述衬底基板为玻璃基板；所述像素电极的材料为ITO；所述栅极绝缘层、第一钝化保护层、与第二钝化保护层的材料为氮化硅、氧化硅、或二者的组合。
  5. 如权利要求1所述的TFT阵列基板，其中，在所述源极上方设有贯穿第一钝化保护层与第二钝化保护层的第二过孔，所述像素电极通过所述第二过孔与源极接触。
  6. 一种TFT阵列基板的制作方法，包括以下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上沉积并图案化第一金属层，形成栅极；
    步骤2、在所述栅极与衬底基板上沉积栅极绝缘层；
    步骤3、于所述栅极上方在所述栅极绝缘层上形成有源层；
    步骤4、在所述栅极绝缘层与有源层上第一次沉积并图案化第二金属层，形成分别与有源层两端接触的源极和漏极，至此完成TFT的制作；
    步骤5、在所述源极、漏极、与栅极绝缘层上沉积覆盖第一钝化保护层，并对第一钝化保护层进行图案化处理，在所述漏极上方形成贯穿第一钝化保护层的第一过孔；
    步骤6、在所述第一钝化保护层上第二次沉积并图案化第二金属层，形成数据线，所述数据线通过所述第一过孔与漏极接触；
    步骤7、在所述第一钝化保护层、与数据线上沉积覆盖第二钝化保护层，并进行图案化处理，在所述源极上方形成贯穿第二钝化保护层与第一钝化保护层的第二过孔；
    步骤8、在所述第二钝化保护层上沉积并图案化透明导电薄膜，形成像素电极，所述像素电极通过所述第二过孔与源极接触。
  7. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述第二金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  8. 如权利要求6所述的TFT阵列基板的制作方法，其中，所述衬底基板为玻璃基板；所述透明导电薄膜为ITO薄膜；所述栅极绝缘层、第一钝化保护层、与第二钝化保护层的材料为氮化硅、氧化硅、或二者的组合。
  9. 一种TFT阵列基板，包括：衬底基板、设置在所述衬底基板上的TFT、覆盖所述TFT的第一钝化保护层、设置在所述第一钝化保护层上的数据线、覆盖所述第一钝化保护层和数据线的第二钝化保护层、及设置在所述第二钝化保护层上的像素电极；
    所述TFT包括：设置在衬底基板上的栅极、覆盖所述栅极与衬底基板的栅极绝缘层、于所述栅极上方设置在所述栅极绝缘层上的有源层、及设置在所述栅极绝缘层上分别接触有源层两端的源极和漏极；
    在所述漏极上方设有贯穿第一钝化保护层的第一过孔；所述数据线通过所述第一过孔与漏极接触；
    其中，所述源极、漏极、及数据线的材料为相同的金属材料；
    其中，所述衬底基板为玻璃基板；所述像素电极的材料为ITO；所述栅极绝缘层、第一钝化保护层、与第二钝化保护层的材料为氮化硅、氧化硅、或二者的组合。
  10. 如权利要求9所述的TFT阵列基板，其中，所述源极、漏极、及数据线的材料同为钼、钛、铝、铜中的一种或多种的堆栈组合。
  11. 如权利要求9所述的TFT阵列基板，其中，在所述源极上方设有贯穿第一钝化保护层与第二钝化保护层的第二过孔，所述像素电极通过所述第二过孔与源极接触。
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