WO2017166343A1 - 薄膜晶体管阵列面板 - Google Patents

薄膜晶体管阵列面板 Download PDF

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WO2017166343A1
WO2017166343A1 PCT/CN2016/080028 CN2016080028W WO2017166343A1 WO 2017166343 A1 WO2017166343 A1 WO 2017166343A1 CN 2016080028 W CN2016080028 W CN 2016080028W WO 2017166343 A1 WO2017166343 A1 WO 2017166343A1
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Prior art keywords
thin film
film transistor
array panel
transistor array
layer
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French (fr)
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李珊
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/121,917 priority Critical patent/US10243082B2/en
Publication of WO2017166343A1 publication Critical patent/WO2017166343A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor array panel.
  • the thin film transistor generally adopts a back channel etch structure or an etch barrier structure.
  • the thin film transistor may cause back channel damage.
  • the problem when the source and the drain are etched on the semiconductor layer, whether the dry etching or the wet etching is used, the thin film transistor may cause back channel damage. The problem.
  • the semiconductor layer is susceptible to ion damage, resulting in carrier trap generation on the exposed channel surface and an increase in oxygen vacancy concentration, resulting in poor stability of the thin film transistor.
  • the semiconductor layer is sensitive to most of the acidic etching liquid, the semiconductor layer is easily corroded during the etching process, thereby also affecting the performance of the thin film transistor. .
  • An object of the present invention is to provide a thin film transistor array panel capable of effectively improving the etching resistance of a semiconductor layer in a thin film transistor, thereby effectively protecting a back channel in the thin film transistor to prevent the back channel Damage, thereby improving the stability of the thin film transistor.
  • a thin film transistor array panel comprising: a substrate; a scan line; a thin film transistor having a back channel etch structure, the thin film transistor comprising: a gate; a semiconductor layer, the semiconductor The semiconductor material in the layer is tin silicon oxide; a source; and a drain; wherein, in the back channel etch structure, the source and the drain are both disposed on the semiconductor layer, and The source and the drain are both in contact with the semiconductor layer; an insulating layer disposed between the gate and the semiconductor layer; a data line, the data line and the source a pole connection; an electrode layer, the electrode layer is connected to the drain; the scan line and/or the gate is a combination of a first metal layer, a second metal layer and a third metal layer; The metal corresponding to the first metal layer is molybdenum, the metal corresponding to the second metal layer is aluminum, and the metal corresponding to the third metal layer is molybdenum; the source and the drain correspond to Metal layer is a fourth metal layer, said The metal corresponding to
  • the semiconductor material is further doped with nitrogen, and the composition of the semiconductor material is SixSn(1-x)O(2-y)Nz, wherein 0.001 ⁇ x ⁇ 0.15, y>0, 0 ⁇ z ⁇ 0.01.
  • the nitrogen is mixed into the semiconductor material during the process of fabricating the target using the silicon dioxide material and the tin oxide material; and/or Nitrogen is introduced into the semiconductor material by passing a nitrogen-containing gas into the process of sputtering a target containing the silica material and the tin oxide material onto the insulating layer.
  • a thin film transistor array panel comprising: a substrate; a scan line; a thin film transistor having a back channel etch structure, the thin film transistor comprising: a gate; a semiconductor layer, the semiconductor The semiconductor material in the layer is tin silicon oxide; a source; and a drain; wherein, in the back channel etch structure, the source and the drain are both disposed on the semiconductor layer, and The source and the drain are both in contact with the semiconductor layer; an insulating layer disposed between the gate and the semiconductor layer; a data line, the data line and the source a pole connection; an electrode layer, the electrode layer being connected to the drain.
  • the semiconductor material is further doped with nitrogen, and the composition of the semiconductor material is SixSn(1-x)O(2-y)Nz, wherein 0.001 ⁇ x ⁇ 0.15, y>0, 0 ⁇ z ⁇ 0.01.
  • the nitrogen is mixed into the semiconductor material during the process of fabricating the target using the silicon dioxide material and the tin oxide material; and/or Nitrogen is introduced into the semiconductor material by passing a nitrogen-containing gas into the process of sputtering a target containing the silica material and the tin oxide material onto the insulating layer.
  • the semiconductor layer is formed by mixing a tin dioxide material and a silicon dioxide material in a third predetermined ratio to form a third target, and
  • the metal layer provided on the semiconductor layer is etched by using any one of sulfuric acid, hydrochloric acid, and a metal etching solution to form the source and the drain.
  • the etch rate of the semiconductor layer by any one of the sulfuric acid, the hydrochloric acid, and the metal etching solution is less than or equal to 10 nanometers/minute.
  • the semiconductor layer In the above thin film transistor array panel, in the process of etching a metal layer provided on the semiconductor layer with the metal etching solution to form the source and the drain, the semiconductor layer The etching rate etched by the metal etching solution is less than or equal to 5 nm/min.
  • the metal etching solution is a mixed solution of nitric acid, acetic acid and phosphoric acid, wherein the content of the nitric acid is 5%, the content of the acetic acid is 10%, and the content of the phosphoric acid is 70%.
  • the concentration of the sulfuric acid ranges from 70% to 96%, and the concentration of the hydrochloric acid ranges from 30% to 38%.
  • the semiconductor layer is used at a concentration of 0.5% to 51%
  • the hydrofluoric acid is etched for patterning.
  • the scan line and/or the gate electrode are a combination of a first metal layer, a second metal layer, and a third metal layer; the first metal layer corresponds to The metal is molybdenum, the metal corresponding to the second metal layer is aluminum, and the metal corresponding to the third metal layer is molybdenum.
  • the first metal layer has a thickness of 25 nm
  • the second metal layer has a thickness of 100 nm
  • the third metal layer has a thickness of 25 nm.
  • the metal layer corresponding to the source and the drain is a fourth metal layer, and the metal corresponding to the fourth metal layer is molybdenum.
  • the fourth metal layer has a thickness of 300 nm.
  • the thickness of the semiconductor layer ranges from 10 nm to 200 nm.
  • the present invention can effectively improve the etching resistance of the semiconductor layer in the thin film transistor, and thus can effectively protect the back channel in the thin film transistor to prevent the back channel damage, thereby making the film
  • the stability of the transistor is improved.
  • FIG. 1 is a schematic view of a first embodiment of a thin film transistor array panel of the present invention
  • FIG. 2 is an electron transfer characteristic curve of a thin film transistor in a first embodiment of the thin film transistor array panel of the present invention
  • FIG. 3 is an electron transfer characteristic curve of a thin film transistor in a second embodiment of the thin film transistor array panel of the present invention.
  • FIG. 4 is an electron transfer characteristic curve of a thin film transistor in a third embodiment of the thin film transistor array panel of the present invention.
  • the thin film transistor array panel of the present invention can be applied to a display panel, which can be a TFT-LCD (Thin Film) Transistor Liquid Crystal Display, OLED (Organic Light Emitting) Diode, organic light emitting diode display panel) and so on.
  • a display panel which can be a TFT-LCD (Thin Film) Transistor Liquid Crystal Display, OLED (Organic Light Emitting) Diode, organic light emitting diode display panel) and so on.
  • the thin film transistor array panel of the present invention may be an array panel used in the thin film transistor liquid crystal display panel, in which case the electrode layer 107 in the thin film transistor array panel may be a strip electrode, the thin film transistor
  • the array panel is configured to form the thin film transistor liquid crystal display panel with a liquid crystal layer and a color filter array panel.
  • the thin film transistor array panel of the present invention may also be an array panel used in the organic light emitting diode display panel, in which case the electrode layer 107 in the thin film transistor array panel may be a cathode layer, the thin film transistor The array panel is configured to form the organic light emitting diode display panel with an organic light emitting material layer and an anode layer.
  • FIG. 1 is a schematic view of a first embodiment of a thin film transistor array panel of the present invention.
  • the first embodiment of the thin film transistor array panel of the present invention includes a substrate 101, a scanning line, a thin film transistor, an insulating layer 103, a data line, and an electrode layer 107.
  • the thin film transistor has a back channel etch structure including a gate electrode 102, a semiconductor layer 104, a source electrode 105, and a drain electrode 106.
  • the semiconductor material in the semiconductor layer 104 is tin silicon oxide.
  • the source 105 and the drain 106 are both disposed on the semiconductor layer 104, and the source 105 and the drain 106 are both The semiconductor layers 104 are in contact.
  • the insulating layer 103 is disposed between the gate electrode 102 and the semiconductor layer 104.
  • the data line is connected to the source 105.
  • the electrode layer 107 is connected to the drain 106.
  • the semiconductor material is tin silicon oxide, that is, a part of silicon in silicon oxide is replaced by tin, since silicon and tin are both tetravalent, such substitution does not occur. In addition, excess electrons are generated, which can suppress the free carrier concentration. At the same time, since the electron orbital of silicon is relatively simple, a large number of energy level splitting defects are not generated, and the mobility can be improved. In addition, the etching rate of the semiconductor layer 104 in the acid can also be adjusted by silicon, and the more the silicon content, the slower the etching rate.
  • the semiconductor material is further doped with nitrogen, and the composition of the semiconductor material is SixSn(1-x)O(2-y)Nz, wherein 0.001 ⁇ x ⁇ 0.15,y >0,0 ⁇ z ⁇ 0.01. Specifically, y>0 and y ⁇ 2.
  • the nitrogen is mixed into the semiconductor material during the process of fabricating the target using the silica material and the tin dioxide material; and/or
  • the nitrogen is introduced into the semiconductor material by introducing a nitrogen-containing gas into a process of sputtering a target containing a silica material and a tin oxide material onto the insulating layer 103.
  • the role of nitrogen is to enhance the stability of the thin film transistor.
  • the thin film transistor has an electron mobility of 3.3 cm 2 /(V*S), that is, a higher electron mobility can be achieved, as shown in FIG. 2 .
  • the metal layer provided on the semiconductor layer 104 is etched by using any one of sulfuric acid, hydrochloric acid, and metal etching liquid to form the source electrode 105 and During the process of the drain 106, the etch rate of the semiconductor layer 104 by any one of the sulfuric acid, the hydrochloric acid, and the metal etching solution is less than or equal to 10 nanometers/minute.
  • the concentration of the sulfuric acid ranges from 70% to 96%, and the concentration of the hydrochloric acid ranges from 30% to 38%.
  • the semiconductor layer 104 is subjected to the metal during etching of the metal layer disposed on the semiconductor layer 104 by the metal etching solution to form the source 105 and the drain 106.
  • the etching rate of the etching solution is less than or equal to 5 nm/min.
  • the metal etching solution is a mixed solution of nitric acid, acetic acid and phosphoric acid, wherein the content of the nitric acid is 5%, the content of the acetic acid is 10%, and the content of the phosphoric acid is 70%.
  • the etching rate of the semiconductor layer 104 in the metal etching solution can be controlled by controlling the content of silicon in the semiconductor material, wherein the higher the silicon content, the higher the etching rate. Slowly, in the case of 0.001 ⁇ x ⁇ 0.15, the etching rate of the semiconductor layer 104 in the metal etching solution is in the range of 5 nm/min to 0.02 nm/min.
  • the semiconductor layer 104 is used at a concentration of 0.5% to 51%.
  • the hydrofluoric acid is etched for patterning.
  • the semiconductor layer 104 is etched using a concentration of 10% hydrofluoric acid for patterning.
  • the semiconductor layer 104 has a carrier concentration of less than 10 ⁇ 17/cm 3 .
  • the semiconductor layer 104 has a carrier concentration of less than 10 ⁇ 16/cm 3 .
  • the scan line and/or the gate electrode 102 are a combination of a first metal layer, a second metal layer, and a third metal layer, the first metal
  • the metal corresponding to the layer is molybdenum (Mo)
  • the metal corresponding to the second metal layer is aluminum (Al)
  • the metal corresponding to the third metal layer is molybdenum (Mo).
  • the first metal layer has a thickness of 25 nm
  • the second metal layer has a thickness of 100 nm
  • the third metal layer has a thickness of 25 nm.
  • the first metal layer, the second metal layer and the third metal layer are all formed by a physical vapor deposition process.
  • the metal layer corresponding to the source 105 and the drain 106 is a fourth metal layer, the metal corresponding to the fourth metal layer is molybdenum (Mo), and the fourth metal layer has a thickness of 300 nm.
  • the thickness of the semiconductor layer 104 ranges from 10 nanometers (nm) to 200 nanometers (nm).
  • the electron mobility of the thin film transistor is 7.6 cm 2 / (V * S), that is, a higher electron mobility can be achieved, as shown in FIG.
  • the third embodiment of the thin film transistor array panel of the present invention is similar to the first embodiment or the second embodiment described above, except that:
  • the semiconductor layer 104 is formed by mixing a tin dioxide material and a silicon dioxide material in a third predetermined ratio to form a third target, and sputtering the third target to the same
  • z 0 is the case where the semiconductor material is not doped with nitrogen.
  • the electron mobility of the thin film transistor is 2.6 cm ⁇ 2/(V*S), that is, a higher electron mobility can be achieved, as shown in FIG.
  • the etching resistance of the semiconductor layer 104 can be effectively improved, and thus the back channel in the thin film transistor can be effectively protected to prevent the back channel damage, thereby making the thin film transistor
  • the stability is improved.
  • the electron mobility of the semiconductor layer 104 can be effectively improved.

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  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管阵列面板。薄膜晶体管阵列面板中的薄膜晶体管具有背沟道刻蚀结构，半导体层（104）所对应的半导体材料是锡硅氧化物，在背沟道刻蚀结构中，源极（105）和漏极（106）均设置于半导体层（104）上，并且源极（105）和漏极（106）均与半导体层（104）相接触，能有效提高半导体层（104）的耐刻蚀性，能够有效保护薄膜晶体管中的背沟道。

Description

薄膜晶体管阵列面板 技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管阵列面板。
 背景技术
传统的显示面板一般都包括薄膜晶体管。所述薄膜晶体管一般采用背沟道刻蚀结构或刻蚀阻挡层结构。
在实践中，发明人发现现有技术至少存在以下问题：
在采用背沟道刻蚀结构的薄膜晶体管中，当在半导体层上刻蚀源极和漏极时，不论采用干法刻蚀还是湿法刻蚀，都会导致所述薄膜晶体管出现背沟道损伤的问题。
具体地，当采用干法刻蚀时，所述半导体层容易受到离子损伤，导致暴露的沟道表面有载流子陷阱生成以及氧空位浓度增加，从而导致所述薄膜晶体管的稳定性较差。
当采用湿法刻蚀时，因为所述半导体层对大部分酸性刻蚀液都比较敏感，因此所述半导体层很容易在刻蚀过程中被腐蚀，从而也将会影响所述薄膜晶体管的性能。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列面板，其能有效提高薄膜晶体管中的半导体层的耐刻蚀性，因此能够有效保护所述薄膜晶体管中的背沟道，以防止所述背沟道损伤，从而使得所述薄膜晶体管的稳定性得到提高。
 技术解决方案
一种薄膜晶体管阵列面板，所述薄膜晶体管阵列面板包括：基板；扫描线；薄膜晶体管，所述薄膜晶体管具有背沟道刻蚀结构，所述薄膜晶体管包括：栅极；半导体层，所述半导体层中的半导体材料是锡硅氧化物；源极；以及漏极；其中，在所述背沟道刻蚀结构中，所述源极和所述漏极均设置于所述半导体层上，并且所述源极和所述漏极均与所述半导体层相接触；绝缘层，所述绝缘层设置于所述栅极与所述半导体层之间；数据线，所述数据线与所述源极连接；电极层，所述电极层与所述漏极连接；所述扫描线和/或所述栅极是由第一金属层、第二金属层和第三金属层叠加组合而成的；所述第一金属层所对应的金属为钼，所述第二金属层所对应的金属为铝，所述第三金属层所对应的金属为钼；所述源极和所述漏极所对应的金属层为第四金属层，所述第四金属层所对应的金属为钼。
在上述薄膜晶体管阵列面板中，所述半导体材料还掺有氮，所述半导体材料的成分为SixSn（1-x）O（2-y）Nz，其中，0.001≤x≤0.15，y>0，0≤z≤0.01。
在上述薄膜晶体管阵列面板中，所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的；和/或所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层上的过程中通入含氮气体来掺入到所述半导体材料中的。
一种薄膜晶体管阵列面板，所述薄膜晶体管阵列面板包括：基板；扫描线；薄膜晶体管，所述薄膜晶体管具有背沟道刻蚀结构，所述薄膜晶体管包括：栅极；半导体层，所述半导体层中的半导体材料是锡硅氧化物；源极；以及漏极；其中，在所述背沟道刻蚀结构中，所述源极和所述漏极均设置于所述半导体层上，并且所述源极和所述漏极均与所述半导体层相接触；绝缘层，所述绝缘层设置于所述栅极与所述半导体层之间；数据线，所述数据线与所述源极连接；电极层，所述电极层与所述漏极连接。
在上述薄膜晶体管阵列面板中，所述半导体材料还掺有氮，所述半导体材料的成分为SixSn（1-x）O（2-y）Nz，其中，0.001≤x≤0.15，y>0，0≤z≤0.01。
在上述薄膜晶体管阵列面板中，所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的；和/或所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层上的过程中通入含氮气体来掺入到所述半导体材料中的。
在上述薄膜晶体管阵列面板中，10^（-15）≤z≤10^（-5）。
在上述薄膜晶体管阵列面板中，x=0.001；所述半导体层是通过将二氧化锡材料和二氧化硅材料按第一预设比例混合，以制作成第一靶材，并在将所述第一靶材溅射到所述绝缘层上的过程中向所述第一靶材通入氩气、氧气和氮气来形成的；其中，z=10^（-15）。
在上述薄膜晶体管阵列面板中，x=0.05；所述半导体层是通过将二氧化锡材料、二氧化硅材料和氮化硅材料按第二预设比例混合，以制作成第二靶材，并在将所述第二靶材溅射到所述绝缘层上的过程中向所述第二靶材通入氩气和氧气来形成的；其中，z=10^（-15）。
在上述薄膜晶体管阵列面板中，x=0.15；所述半导体层是通过将二氧化锡材料和二氧化硅材料按第三预设比例混合，以制作成第三靶材，并在将所述第三靶材溅射到所述绝缘层上的过程中向所述第三靶材通入氩气和氧气来形成的；其中，z=0。
在上述薄膜晶体管阵列面板中，在利用硫酸、盐酸、金属刻蚀液中的任意一种对设置于所述半导体层上的金属层进行刻蚀，以形成所述源极和所述漏极的过程中，所述半导体层受所述硫酸、所述盐酸、所述金属刻蚀液中的任意一种刻蚀的刻蚀速率小于或等于10纳米/分钟。
在上述薄膜晶体管阵列面板中，在利用所述金属刻蚀液对设置于所述半导体层上的金属层进行刻蚀，以形成所述源极和所述漏极的过程中，所述半导体层受所述金属刻蚀液刻蚀的刻蚀速率小于或等于5纳米/分钟。
在上述薄膜晶体管阵列面板中，所述金属刻蚀液为硝酸、乙酸和磷酸的混合液，其中，所述硝酸的含量为5%，所述乙酸的含量为10%，所述磷酸的含量为70%。
在上述薄膜晶体管阵列面板中，所述硫酸的浓度范围为70%至96%，所述盐酸的浓度范围为30%至38%。
在上述薄膜晶体管阵列面板中，所述半导体层是采用浓度为0.5%至51% 的氢氟酸来刻蚀，以进行图形化的。
在上述薄膜晶体管阵列面板中，所述扫描线和/或所述栅极是由第一金属层、第二金属层和第三金属层叠加组合而成的；所述第一金属层所对应的金属为钼，所述第二金属层所对应的金属为铝，所述第三金属层所对应的金属为钼。
在上述薄膜晶体管阵列面板中，所述第一金属层的厚度为25纳米，所述第二金属层的厚度为100纳米，所述第三金属层的厚度为25纳米。
在上述薄膜晶体管阵列面板中，所述源极和所述漏极所对应的金属层为第四金属层，所述第四金属层所对应的金属为钼。
在上述薄膜晶体管阵列面板中，所述第四金属层的厚度为300纳米。
在上述薄膜晶体管阵列面板中，所述半导体层的厚度范围处于10纳米至200纳米范围内。
 有益效果
相对现有技术，本发明能有效提高薄膜晶体管中的半导体层的耐刻蚀性，因此能够有效保护所述薄膜晶体管中的背沟道，以防止所述背沟道损伤，从而使得所述薄膜晶体管的稳定性得到提高。
 附图说明
图1为本发明的薄膜晶体管阵列面板的第一实施例的示意图；
图2是本发明的薄膜晶体管阵列面板的第一实施例中的薄膜晶体管的电子迁移特性曲线；
图3是本发明的薄膜晶体管阵列面板的第二实施例中的薄膜晶体管的电子迁移特性曲线；
图4是本发明的薄膜晶体管阵列面板的第三实施例中的薄膜晶体管的电子迁移特性曲线。
 本发明的最佳实施方式
本说明书所使用的词语“实施例”意指实例、示例或例证。此外，本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”，除非另外指定或从上下文可以清楚确定单数形式。
本发明的薄膜晶体管阵列面板可以应用于显示面板中，所述显示面板可以是TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）、OLED（Organic Light Emitting Diode，有机发光二极管显示面板）等。
本发明的薄膜晶体管阵列面板可以是用于所述薄膜晶体管液晶显示面板中的阵列面板，在这种情况下，所述薄膜晶体管阵列面板中的电极层107可以是条状电极，所述薄膜晶体管阵列面板用于与液晶层、彩色滤光片阵列面板组成所述薄膜晶体管液晶显示面板。
本发明的薄膜晶体管阵列面板也可以是用于所述有机发光二极管显示面板中的阵列面板，在这种情况下，所述薄膜晶体管阵列面板中的电极层107可以是阴极层，所述薄膜晶体管阵列面板用于与有机发光材料层、阳极层组成所述有机发光二极管显示面板。
参考图1，图1为本发明的薄膜晶体管阵列面板的第一实施例的示意图。
本发明的薄膜晶体管阵列面板的第一实施例包括基板101、扫描线、薄膜晶体管、绝缘层103、数据线、电极层107。
所述薄膜晶体管具有背沟道刻蚀结构，所述薄膜晶体管包括栅极102、半导体层104、源极105、漏极106。所述半导体层104中的半导体材料是锡硅氧化物。其中，在所述背沟道刻蚀结构中，所述源极105和所述漏极106均设置于所述半导体层104上，并且所述源极105和所述漏极106均与所述半导体层104相接触。
其中，所述绝缘层103设置于所述栅极102与所述半导体层104之间。所述数据线与所述源极105连接。所述电极层107与所述漏极106连接。
在本实施例的薄膜晶体管阵列面板中，由于所述半导体材料是锡硅氧化物，即，利用锡取代氧化硅中的部分硅，由于硅和锡都是四价的，所以这种取代不会另外产生多余电子，能抑制自由载流子浓度；同时由于硅的电子轨道比较简单，不会产生大量的能级分裂造成缺陷，能提高迁移率。此外，还能通过硅调节所述半导体层104在酸中的刻蚀速率，硅的含量越多，刻蚀速率越慢。
在本实施例的薄膜晶体管阵列面板中，所述半导体材料还掺有氮，所述半导体材料的成分为SixSn（1-x）O（2-y）Nz，其中，0.001≤x≤0.15，y>0，0≤z≤0.01。具体地，y>0，且y≤2。
所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的；和/或
所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层103上的过程中通入含氮气体来掺入到所述半导体材料中的。
其中，氮的作用是增强所述薄膜晶体管的稳定性。
在本实施例的薄膜晶体管阵列面板中，10^（-15）≤z≤10^（-5）。
在本实施例的薄膜晶体管阵列面板中，x=0.001；所述半导体层104是通过将二氧化锡材料和二氧化硅材料按第一预设比例混合，以制作成第一靶材，并在将所述第一靶材溅射到所述绝缘层103上的过程中向所述第一靶材通入氩气、氧气和氮气来形成的；其中，z=10^（-15）。在本实施例中，所述薄膜晶体管的电子迁移率为3.3cm^2/（V*S），即，可以实现较高的电子迁移率，如图2所示。
在本实施例的薄膜晶体管阵列面板中，在利用硫酸、盐酸、金属刻蚀液中的任意一种对设置于所述半导体层104上的金属层进行刻蚀，以形成所述源极105和所述漏极106的过程中，所述半导体层104受所述硫酸、所述盐酸、所述金属刻蚀液中的任意一种刻蚀的刻蚀速率小于或等于10纳米/分钟。
其中，所述硫酸的浓度范围为70%至96%，所述盐酸的浓度范围为30%至38%。
在利用所述金属刻蚀液对设置于所述半导体层104上的金属层进行刻蚀，以形成所述源极105和所述漏极106的过程中，所述半导体层104受所述金属刻蚀液刻蚀的刻蚀速率小于或等于5纳米/分钟。
其中，所述金属刻蚀液为硝酸、乙酸和磷酸的混合液，其中，所述硝酸的含量为5%，所述乙酸的含量为10%，所述磷酸的含量为70%。
在本实施例中，可通过控制所述半导体材料中的硅的含量来控制所述半导体层104在所述金属刻蚀液中的刻蚀速率，其中，硅的含量越高，刻蚀速率越慢，在0.001≤x≤0.15的情况下，所述半导体层104在所述金属刻蚀液中的刻蚀速率处于5纳米/分钟至0.02纳米/分钟的范围内。
在本实施例的薄膜晶体管阵列面板中，所述半导体层104是采用浓度为0.5%至51% 的氢氟酸来刻蚀，以进行图形化的。
优选地，所述半导体层104是采用浓度为10% 的氢氟酸来刻蚀的，以进行图形化的。
在本实施例的薄膜晶体管阵列面板中，所述半导体层104的载流子浓度小于10^17/立方厘米。
优选地，所述半导体层104的载流子浓度小于10^16/立方厘米。
在本实施例的薄膜晶体管阵列面板中，所述扫描线和/或所述栅极102是由第一金属层、第二金属层和第三金属层叠加组合而成的，所述第一金属层所对应的金属为钼（Mo），所述第二金属层所对应的金属为铝（Al），所述第三金属层所对应的金属为钼（Mo）。所述第一金属层的厚度为25纳米，所述第二金属层的厚度为100纳米，所述第三金属层的厚度为25纳米。所述第一金属层、所述第二金属层和所述第三金属层均是利用物理气相沉积制程形成的。
所述源极105和所述漏极106所对应的金属层为第四金属层，所述第四金属层所对应的金属为钼（Mo），所述第四金属层的厚度为300纳米。
在本实施例的薄膜晶体管阵列面板中，所述半导体层104的厚度范围处于10纳米（nm）至200纳米（nm）范围内。
本发明的薄膜晶体管阵列面板的第二实施例与上述第一实施例相似，不同之处在于：
x=0.05；所述半导体层104是通过将二氧化锡材料、二氧化硅材料和氮化硅材料按第二预设比例混合，以制作成第二靶材，并在将所述第二靶材溅射到所述绝缘层103上的过程中向所述第二靶材通入氩气和氧气来形成的；其中，z=10^（-15）。在本实施例中，所述薄膜晶体管的电子迁移率为7.6cm^2/（V*S），即，可以实现较高的电子迁移率，如图3所示。
本发明的薄膜晶体管阵列面板的第三实施例与上述第一实施例或第二实施例相似，不同之处在于：
x=0.15；所述半导体层104是通过将二氧化锡材料和二氧化硅材料按第三预设比例混合，以制作成第三靶材，并在将所述第三靶材溅射到所述绝缘层103上的过程中向所述第三靶材通入氩气和氧气来形成的；其中，z=0。z=0为所述半导体材料没有掺氮的情况。在本实施例中，所述薄膜晶体管的电子迁移率为2.6cm^2/（V*S），即，可以实现较高的电子迁移率，如图4所示。
通过上述技术方案，可以有效提高所述半导体层104的耐刻蚀性，因此能够有效保护所述薄膜晶体管中的所述背沟道，以防止所述背沟道损伤，从而使得所述薄膜晶体管的稳定性得到提高。
此外，通过上述技术方案，还可以有效提高所述半导体层104的电子迁移率。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：
    基板；
    扫描线；
    薄膜晶体管，所述薄膜晶体管具有背沟道刻蚀结构，所述薄膜晶体管包括：
    栅极；
    半导体层，所述半导体层中的半导体材料是锡硅氧化物；
    源极；以及
    漏极；
    其中，在所述背沟道刻蚀结构中，所述源极和所述漏极均设置于所述半导体层上，并且所述源极和所述漏极均与所述半导体层相接触；
    绝缘层，所述绝缘层设置于所述栅极与所述半导体层之间；
    数据线，所述数据线与所述源极连接；
    电极层，所述电极层与所述漏极连接；
    所述扫描线和/或所述栅极是由第一金属层、第二金属层和第三金属层叠加组合而成的；
    所述第一金属层所对应的金属为钼，所述第二金属层所对应的金属为铝，所述第三金属层所对应的金属为钼；
    所述源极和所述漏极所对应的金属层为第四金属层，所述第四金属层所对应的金属为钼。
  2. 根据权利要求1所述的薄膜晶体管阵列面板，其中，所述半导体材料还掺有氮，所述半导体材料的成分为SixSn（1-x）O（2-y）Nz，其中，0.001≤x≤0.15，y>0，0≤z≤0.01。
  3. 根据权利要求2所述的薄膜晶体管阵列面板，其中，所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的；和/或
    所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层上的过程中通入含氮气体来掺入到所述半导体材料中的。
  4. 一种薄膜晶体管阵列面板，其中，所述薄膜晶体管阵列面板包括：
    基板；
    扫描线；
    薄膜晶体管，所述薄膜晶体管具有背沟道刻蚀结构，所述薄膜晶体管包括：
    栅极；
    半导体层，所述半导体层中的半导体材料是锡硅氧化物；
    源极；以及
    漏极；
    其中，在所述背沟道刻蚀结构中，所述源极和所述漏极均设置于所述半导体层上，并且所述源极和所述漏极均与所述半导体层相接触；
    绝缘层，所述绝缘层设置于所述栅极与所述半导体层之间；
    数据线，所述数据线与所述源极连接；
    电极层，所述电极层与所述漏极连接。
  5. 根据权利要求4所述的薄膜晶体管阵列面板，其中，所述半导体材料还掺有氮，所述半导体材料的成分为SixSn（1-x）O（2-y）Nz，其中，0.001≤x≤0.15，y>0，0≤z≤0.01。
  6. 根据权利要求5所述的薄膜晶体管阵列面板，其中，所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的；和/或
    所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层上的过程中通入含氮气体来掺入到所述半导体材料中的。
  7. 根据权利要求6所述的薄膜晶体管阵列面板，其中，10^（-15）≤z≤10^（-5）。
  8. 根据权利要求7所述的薄膜晶体管阵列面板，其中，x=0.001；
    所述半导体层是通过将二氧化锡材料和二氧化硅材料按第一预设比例混合，以制作成第一靶材，并在将所述第一靶材溅射到所述绝缘层上的过程中向所述第一靶材通入氩气、氧气和氮气来形成的；
    其中，z=10^（-15）。
  9. 根据权利要求7所述的薄膜晶体管阵列面板，其中，x=0.05；
    所述半导体层是通过将二氧化锡材料、二氧化硅材料和氮化硅材料按第二预设比例混合，以制作成第二靶材，并在将所述第二靶材溅射到所述绝缘层上的过程中向所述第二靶材通入氩气和氧气来形成的；
    其中，z=10^（-15）。
  10. 根据权利要求6所述的薄膜晶体管阵列面板，其中，x=0.15；
    所述半导体层是通过将二氧化锡材料和二氧化硅材料按第三预设比例混合，以制作成第三靶材，并在将所述第三靶材溅射到所述绝缘层上的过程中向所述第三靶材通入氩气和氧气来形成的；
    其中，z=0。
  11. 根据权利要求4所述的薄膜晶体管阵列面板，其中，在利用硫酸、盐酸、金属刻蚀液中的任意一种对设置于所述半导体层上的金属层进行刻蚀，以形成所述源极和所述漏极的过程中，所述半导体层受所述硫酸、所述盐酸、所述金属刻蚀液中的任意一种刻蚀的刻蚀速率小于或等于10纳米/分钟。
  12. 根据权利要求11所述的薄膜晶体管阵列面板，其中，在利用所述金属刻蚀液对设置于所述半导体层上的金属层进行刻蚀，以形成所述源极和所述漏极的过程中，所述半导体层受所述金属刻蚀液刻蚀的刻蚀速率小于或等于5纳米/分钟。
  13. 根据权利要求11所述的薄膜晶体管阵列面板，其中，所述金属刻蚀液为硝酸、乙酸和磷酸的混合液，其中，所述硝酸的含量为5%，所述乙酸的含量为10%，所述磷酸的含量为70%。
  14. 根据权利要求11所述的薄膜晶体管阵列面板，其中，所述硫酸的浓度范围为70%至96%，所述盐酸的浓度范围为30%至38%。
  15. 根据权利要求4所述的薄膜晶体管阵列面板，其中，所述半导体层是采用浓度为0.5%至51% 的氢氟酸来刻蚀，以进行图形化的。
  16. 根据权利要求4所述的薄膜晶体管阵列面板，其中，所述扫描线和/或所述栅极是由第一金属层、第二金属层和第三金属层叠加组合而成的；
    所述第一金属层所对应的金属为钼，所述第二金属层所对应的金属为铝，所述第三金属层所对应的金属为钼。
  17. 根据权利要求16所述的薄膜晶体管阵列面板，其中，所述第一金属层的厚度为25纳米，所述第二金属层的厚度为100纳米，所述第三金属层的厚度为25纳米。
  18. 根据权利要求4所述的薄膜晶体管阵列面板，其中，所述源极和所述漏极所对应的金属层为第四金属层，所述第四金属层所对应的金属为钼。
  19. 根据权利要求18所述的薄膜晶体管阵列面板，其中，所述第四金属层的厚度为300纳米。
  20. 根据权利要求4所述的薄膜晶体管阵列面板，其中，所述半导体层的厚度范围处于10纳米至200纳米范围内。
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