CN105845695A - 薄膜晶体管阵列面板 - Google Patents

薄膜晶体管阵列面板 Download PDF

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CN105845695A
CN105845695A CN201610190504.3A CN201610190504A CN105845695A CN 105845695 A CN105845695 A CN 105845695A CN 201610190504 A CN201610190504 A CN 201610190504A CN 105845695 A CN105845695 A CN 105845695A
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film transistor
thin
semiconductor layer
display panel
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CN105845695B (zh
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李珊
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2016/080028 priority patent/WO2017166343A1/zh
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Abstract

本发明公开了一种薄膜晶体管阵列面板。所述薄膜晶体管阵列面板包括:基板;扫描线;薄膜晶体管,所述薄膜晶体管具有背沟道刻蚀结构,所述薄膜晶体管包括:栅极;半导体层,所述半导体层中的半导体材料是锡硅氧化物;源极;以及漏极;其中,在所述背沟道刻蚀结构中,所述源极和所述漏极均设置于所述半导体层上,并且所述源极和所述漏极均与所述半导体层相接触;绝缘层,所述绝缘层设置于所述栅极与所述半导体层之间;数据线,所述数据线与所述源极连接;电极层,所述电极层与所述漏极连接。本发明能有效提高薄膜晶体管中的半导体层的耐刻蚀性,能够有效保护所述薄膜晶体管中的背沟道,以防止所述背沟道损伤,从而提高所述薄膜晶体管的稳定性。

Description

薄膜晶体管阵列面板
【技术领域】
本发明涉及显示技术领域,特别涉及一种薄膜晶体管阵列面板。
【背景技术】
传统的显示面板一般都包括薄膜晶体管。所述薄膜晶体管一般采用背沟道刻蚀结构或刻蚀阻挡层结构。
在实践中,发明人发现现有技术至少存在以下问题:
在采用背沟道刻蚀结构的薄膜晶体管中,当在半导体层上刻蚀源极和漏极时,不论采用干法刻蚀还是湿法刻蚀,都会导致所述薄膜晶体管出现背沟道损伤的问题。
具体地,当采用干法刻蚀时,所述半导体层容易受到离子损伤,导致暴露的沟道表面有载流子陷阱生成以及氧空位浓度增加,从而导致所述薄膜晶体管的稳定性较差。
当采用湿法刻蚀时,因为所述半导体层对大部分酸性刻蚀液都比较敏感,因此所述半导体层很容易在刻蚀过程中被腐蚀,从而也将会影响所述薄膜晶体管的性能。
故,有必要提出一种新的技术方案,以解决上述技术问题。
【发明内容】
本发明的目的在于提供一种薄膜晶体管阵列面板,其能有效提高薄膜晶体管中的半导体层的耐刻蚀性,因此能够有效保护所述薄膜晶体管中的背沟道,以防止所述背沟道损伤,从而使得所述薄膜晶体管的稳定性得到提高。
为解决上述问题,本发明的技术方案如下:
一种薄膜晶体管阵列面板,所述薄膜晶体管阵列面板包括:基板;扫描线;薄膜晶体管,所述薄膜晶体管具有背沟道刻蚀结构,所述薄膜晶体管包括:栅极;半导体层,所述半导体层中的半导体材料是锡硅氧化物;源极;以及漏极;其中,在所述背沟道刻蚀结构中,所述源极和所述漏极均设置于所述半导体层上,并且所述源极和所述漏极均与所述半导体层相接触;绝缘层,所述绝缘层设置于所述栅极与所述半导体层之间;数据线,所述数据线与所述源极连接;电极层,所述电极层与所述漏极连接。
在上述薄膜晶体管阵列面板中,所述半导体材料还掺有氮,所述半导体材料的成分为SixSn(1-x)O(2-y)Nz,其中,0.001≤x≤0.15,y>0,0≤z≤0.01。
在上述薄膜晶体管阵列面板中,所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的;和/或所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层上的过程中通入含氮气体来掺入到所述半导体材料中的。
在上述薄膜晶体管阵列面板中,10^(-15)≤z≤10^(-5)。
在上述薄膜晶体管阵列面板中,x=0.001;所述半导体层是通过将二氧化锡材料和二氧化硅材料按第一预设比例混合,以制作成第一靶材,并在将所述第一靶材溅射到所述绝缘层上的过程中向所述第一靶材通入氩气、氧气和氮气来形成的;其中,z=10^(-15)。
在上述薄膜晶体管阵列面板中,x=0.05;所述半导体层是通过将二氧化锡材料、二氧化硅材料和氮化硅材料按第二预设比例混合,以制作成第二靶材,并在将所述第二靶材溅射到所述绝缘层上的过程中向所述第二靶材通入氩气和氧气来形成的;其中,z=10^(-15)。
在上述薄膜晶体管阵列面板中,x=0.15;所述半导体层是通过将二氧化锡材料和二氧化硅材料按第三预设比例混合,以制作成第三靶材,并在将所述第三靶材溅射到所述绝缘层上的过程中向所述第三靶材通入氩气和氧气来形成的;其中,z=0。
在上述薄膜晶体管阵列面板中,在利用硫酸、盐酸、金属刻蚀液中的任意一种对设置于所述半导体层上的金属层进行刻蚀,以形成所述源极和所述漏极的过程中,所述半导体层受所述硫酸、所述盐酸、所述金属刻蚀液中的任意一种刻蚀的刻蚀速率小于或等于10纳米/分钟。
在上述薄膜晶体管阵列面板中,所述金属刻蚀液为硝酸、乙酸和磷酸的混合液,其中,所述硝酸的含量为5%,所述乙酸的含量为10%,所述磷酸的含量为70%。
在上述薄膜晶体管阵列面板中,所述半导体层是采用浓度为0.5%至51%的氢氟酸来刻蚀,以进行图形化的。
相对现有技术,本发明能有效提高薄膜晶体管中的半导体层的耐刻蚀性,因此能够有效保护所述薄膜晶体管中的背沟道,以防止所述背沟道损伤,从而使得所述薄膜晶体管的稳定性得到提高。
为让本发明的上述内容能更明显易懂,下文特举优选实施例,并配合所附图式,作详细说明如下。
【附图说明】
图1为本发明的薄膜晶体管阵列面板的第一实施例的示意图;
图2是本发明的薄膜晶体管阵列面板的第一实施例中的薄膜晶体管的电子迁移特性曲线;
图3是本发明的薄膜晶体管阵列面板的第二实施例中的薄膜晶体管的电子迁移特性曲线;
图4是本发明的薄膜晶体管阵列面板的第三实施例中的薄膜晶体管的电子迁移特性曲线。
【具体实施方式】
本说明书所使用的词语“实施例”意指实例、示例或例证。此外,本说明书和所附权利要求中所使用的冠词“一”一般地可以被解释为“一个或多个”,除非另外指定或从上下文可以清楚确定单数形式。
本发明的薄膜晶体管阵列面板可以应用于显示面板中,所述显示面板可以是TFT-LCD(Thin Film Transistor Liquid CrystalDisplay,薄膜晶体管液晶显示面板)、OLED(Organic LightEmitting Diode,有机发光二极管显示面板)等。
本发明的薄膜晶体管阵列面板可以是用于所述薄膜晶体管液晶显示面板中的阵列面板,在这种情况下,所述薄膜晶体管阵列面板中的电极层107可以是条状电极,所述薄膜晶体管阵列面板用于与液晶层、彩色滤光片阵列面板组成所述薄膜晶体管液晶显示面板。
本发明的薄膜晶体管阵列面板也可以是用于所述有机发光二极管显示面板中的阵列面板,在这种情况下,所述薄膜晶体管阵列面板中的电极层107可以是阴极层,所述薄膜晶体管阵列面板用于与有机发光材料层、阳极层组成所述有机发光二极管显示面板。
参考图1,图1为本发明的薄膜晶体管阵列面板的第一实施例的示意图。
本发明的薄膜晶体管阵列面板的第一实施例包括基板101、扫描线、薄膜晶体管、绝缘层103、数据线、电极层107。
所述薄膜晶体管具有背沟道刻蚀结构,所述薄膜晶体管包括栅极102、半导体层104、源极105、漏极106。所述半导体层104中的半导体材料是锡硅氧化物。其中,在所述背沟道刻蚀结构中,所述源极105和所述漏极106均设置于所述半导体层104上,并且所述源极105和所述漏极106均与所述半导体层104相接触。
其中,所述绝缘层103设置于所述栅极102与所述半导体层104之间。所述数据线与所述源极105连接。所述电极层107与所述漏极106连接。
在本实施例的薄膜晶体管阵列面板中,由于所述半导体材料是锡硅氧化物,即,利用锡取代氧化硅中的部分硅,由于硅和锡都是四价的,所以这种取代不会另外产生多余电子,能抑制自由载流子浓度;同时由于硅的电子轨道比较简单,不会产生大量的能级分裂造成缺陷,能提高迁移率。此外,还能通过硅调节所述半导体层104在酸中的刻蚀速率,硅的含量越多,刻蚀速率越慢。
在本实施例的薄膜晶体管阵列面板中,所述半导体材料还掺有氮,所述半导体材料的成分为SixSn(1-x)O(2-y)Nz,其中,0.001≤x≤0.15,y>0,0≤z≤0.01。具体地,y>0,且y≤2。
所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的;和/或
所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层103上的过程中通入含氮气体来掺入到所述半导体材料中的。
其中,氮的作用是增强所述薄膜晶体管的稳定性。
在本实施例的薄膜晶体管阵列面板中,10^(-15)≤z≤10^(-5)。
在本实施例的薄膜晶体管阵列面板中,x=0.001;所述半导体层104是通过将二氧化锡材料和二氧化硅材料按第一预设比例混合,以制作成第一靶材,并在将所述第一靶材溅射到所述绝缘层103上的过程中向所述第一靶材通入氩气、氧气和氮气来形成的;其中,z=10^(-15)。在本实施例中,所述薄膜晶体管的电子迁移率为3.3cm^2/(V*S),即,可以实现较高的电子迁移率,如图2所示。
在本实施例的薄膜晶体管阵列面板中,在利用硫酸、盐酸、金属刻蚀液中的任意一种对设置于所述半导体层104上的金属层进行刻蚀,以形成所述源极105和所述漏极106的过程中,所述半导体层104受所述硫酸、所述盐酸、所述金属刻蚀液中的任意一种刻蚀的刻蚀速率小于或等于10纳米/分钟。
其中,所述硫酸的浓度范围为70%至96%,所述盐酸的浓度范围为30%至38%。
在利用所述金属刻蚀液对设置于所述半导体层104上的金属层进行刻蚀,以形成所述源极105和所述漏极106的过程中,所述半导体层104受所述金属刻蚀液刻蚀的刻蚀速率小于或等于5纳米/分钟。
其中,所述金属刻蚀液为硝酸、乙酸和磷酸的混合液,其中,所述硝酸的含量为5%,所述乙酸的含量为10%,所述磷酸的含量为70%。
在本实施例中,可通过控制所述半导体材料中的硅的含量来控制所述半导体层104在所述金属刻蚀液中的刻蚀速率,其中,硅的含量越高,刻蚀速率越慢,在0.001≤x≤0.15的情况下,所述半导体层104在所述金属刻蚀液中的刻蚀速率处于5纳米/分钟至0.02纳米/分钟的范围内。
在本实施例的薄膜晶体管阵列面板中,所述半导体层104是采用浓度为0.5%至51%的氢氟酸来刻蚀,以进行图形化的。
优选地,所述半导体层104是采用浓度为10%的氢氟酸来刻蚀的,以进行图形化的。
在本实施例的薄膜晶体管阵列面板中,所述半导体层104的载流子浓度小于10^17/立方厘米。
优选地,所述半导体层104的载流子浓度小于10^16/立方厘米。
在本实施例的薄膜晶体管阵列面板中,所述扫描线和/或所述栅极102是由第一金属层、第二金属层和第三金属层叠加组合而成的,所述第一金属层所对应的金属为钼(Mo),所述第二金属层所对应的金属为铝(Al),所述第三金属层所对应的金属为钼(Mo)。所述第一金属层的厚度为25纳米,所述第二金属层的厚度为100纳米,所述第三金属层的厚度为25纳米。所述第一金属层、所述第二金属层和所述第三金属层均是利用物理气相沉积制程形成的。
所述源极105和所述漏极106所对应的金属层为第四金属层,所述第四金属层所对应的金属为钼(Mo),所述第四金属层的厚度为300纳米。
在本实施例的薄膜晶体管阵列面板中,所述半导体层104的厚度范围处于10nm至200nm范围内。
本发明的薄膜晶体管阵列面板的第二实施例与上述第一实施例相似,不同之处在于:
x=0.05;所述半导体层104是通过将二氧化锡材料、二氧化硅材料和氮化硅材料按第二预设比例混合,以制作成第二靶材,并在将所述第二靶材溅射到所述绝缘层103上的过程中向所述第二靶材通入氩气和氧气来形成的;其中,z=10^(-15)。在本实施例中,所述薄膜晶体管的电子迁移率为7.6cm^2/(V*S),即,可以实现较高的电子迁移率,如图3所示。
本发明的薄膜晶体管阵列面板的第三实施例与上述第一实施例或第二实施例相似,不同之处在于:
x=0.15;所述半导体层104是通过将二氧化锡材料和二氧化硅材料按第三预设比例混合,以制作成第三靶材,并在将所述第三靶材溅射到所述绝缘层103上的过程中向所述第三靶材通入氩气和氧气来形成的;其中,z=0。z=0为所述半导体材料没有掺氮的情况。在本实施例中,所述薄膜晶体管的电子迁移率为2.6cm^2/(V*S),即,可以实现较高的电子迁移率,如图4所示。
通过上述技术方案,可以有效提高所述半导体层104的耐刻蚀性,因此能够有效保护所述薄膜晶体管中的所述背沟道,以防止所述背沟道损伤,从而使得所述薄膜晶体管的稳定性得到提高。
此外,通过上述技术方案,还可以有效提供所述半导体层104的电子迁移率。
尽管已经相对于一个或多个实现方式示出并描述了本发明,但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型,并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能,用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示),即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外,尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开,但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且,就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言,这样的术语旨在以与术语“包含”相似的方式包括。
综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种薄膜晶体管阵列面板,其特征在于,所述薄膜晶体管阵列面板包括:
基板;
扫描线;
薄膜晶体管,所述薄膜晶体管具有背沟道刻蚀结构,所述薄膜晶体管包括:
栅极;
半导体层,所述半导体层中的半导体材料是锡硅氧化物;
源极;以及
漏极;
其中,在所述背沟道刻蚀结构中,所述源极和所述漏极均设置于所述半导体层上,并且所述源极和所述漏极均与所述半导体层相接触;
绝缘层,所述绝缘层设置于所述栅极与所述半导体层之间;
数据线,所述数据线与所述源极连接;
电极层,所述电极层与所述漏极连接。
2.根据权利要求1所述的薄膜晶体管阵列面板,其特征在于,所述半导体材料还掺有氮,所述半导体材料的成分为SixSn(1-x)O(2-y)Nz,其中,0.001≤x≤0.15,y>0,0≤z≤0.01。
3.根据权利要求2所述的薄膜晶体管阵列面板,其特征在于,所述氮是在利用二氧化硅材料和二氧化锡材料制作靶材的过程中混合氮化硅材料来掺入到所述半导体材料中的;和/或
所述氮是在将含有二氧化硅材料和二氧化锡材料的靶材溅射到所述绝缘层上的过程中通入含氮气体来掺入到所述半导体材料中的。
4.根据权利要求3所述的薄膜晶体管阵列面板,其特征在于,10^(-15)≤z≤10^(-5)。
5.根据权利要求4所述的薄膜晶体管阵列面板,其特征在于,x=0.001;
所述半导体层是通过将二氧化锡材料和二氧化硅材料按第一预设比例混合,以制作成第一靶材,并在将所述第一靶材溅射到所述绝缘层上的过程中向所述第一靶材通入氩气、氧气和氮气来形成的;
其中,z=10^(-15)。
6.根据权利要求4所述的薄膜晶体管阵列面板,其特征在于,x=0.05;
所述半导体层是通过将二氧化锡材料、二氧化硅材料和氮化硅材料按第二预设比例混合,以制作成第二靶材,并在将所述第二靶材溅射到所述绝缘层上的过程中向所述第二靶材通入氩气和氧气来形成的;
其中,z=10^(-15)。
7.根据权利要求3所述的薄膜晶体管阵列面板,其特征在于,x=0.15;
所述半导体层是通过将二氧化锡材料和二氧化硅材料按第三预设比例混合,以制作成第三靶材,并在将所述第三靶材溅射到所述绝缘层上的过程中向所述第三靶材通入氩气和氧气来形成的;
其中,z=0。
8.根据权利要求1至7中任意一项所述的薄膜晶体管阵列面板,其特征在于,在利用硫酸、盐酸、金属刻蚀液中的任意一种对设置于所述半导体层上的金属层进行刻蚀,以形成所述源极和所述漏极的过程中,所述半导体层受所述硫酸、所述盐酸、所述金属刻蚀液中的任意一种刻蚀的刻蚀速率小于或等于10纳米/分钟。
9.根据权利要求8所述的薄膜晶体管阵列面板,其特征在于,所述金属刻蚀液为硝酸、乙酸和磷酸的混合液,其中,所述硝酸的含量为5%,所述乙酸的含量为10%,所述磷酸的含量为70%。
10.根据权利要求1所述的薄膜晶体管阵列面板,其特征在于,所述半导体层是采用浓度为0.5%至51%的氢氟酸来刻蚀,以进行图形化的。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107749423A (zh) * 2017-10-12 2018-03-02 华南理工大学 一种非晶氧化物柔性薄膜晶体管及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983606A (zh) * 2005-12-15 2007-06-20 Lg.菲利浦Lcd株式会社 薄膜晶体管阵列基板及其制造方法
US20130119324A1 (en) * 2010-07-30 2013-05-16 Samsung Display Co., Ltd. Oxide for semiconductor layer of thin-film transistor, sputtering target, and thin-film transistor
CN103311130A (zh) * 2013-05-14 2013-09-18 广州新视界光电科技有限公司 一种非晶金属氧化物薄膜晶体管及其制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010147870A (ja) * 2008-12-19 2010-07-01 Panasonic Electric Works Co Ltd Baw共振装置の製造方法
JP2012028481A (ja) * 2010-07-22 2012-02-09 Fujifilm Corp 電界効果型トランジスタ及びその製造方法
KR101934978B1 (ko) * 2011-08-04 2019-01-04 삼성디스플레이 주식회사 박막 트랜지스터 및 박막 트랜지스터 표시판
CN103236443B (zh) * 2013-05-14 2014-05-14 广州新视界光电科技有限公司 一种金属氧化物薄膜晶体管及其制备方法
CN103794652B (zh) * 2014-02-25 2017-04-12 华南理工大学 金属氧化物半导体薄膜晶体管及其制备方法
US10008609B2 (en) * 2015-03-17 2018-06-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, method for manufacturing the same, or display device including the same
CN105552114A (zh) * 2015-12-14 2016-05-04 华南理工大学 一种基于非晶氧化物半导体材料的薄膜晶体管及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1983606A (zh) * 2005-12-15 2007-06-20 Lg.菲利浦Lcd株式会社 薄膜晶体管阵列基板及其制造方法
US20130119324A1 (en) * 2010-07-30 2013-05-16 Samsung Display Co., Ltd. Oxide for semiconductor layer of thin-film transistor, sputtering target, and thin-film transistor
CN103311130A (zh) * 2013-05-14 2013-09-18 广州新视界光电科技有限公司 一种非晶金属氧化物薄膜晶体管及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107749423A (zh) * 2017-10-12 2018-03-02 华南理工大学 一种非晶氧化物柔性薄膜晶体管及其制备方法

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