WO2017161722A1 - 一种双栅线阵列基板、测试方法、显示面板和显示装置 - Google Patents

一种双栅线阵列基板、测试方法、显示面板和显示装置 Download PDF

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WO2017161722A1
WO2017161722A1 PCT/CN2016/087237 CN2016087237W WO2017161722A1 WO 2017161722 A1 WO2017161722 A1 WO 2017161722A1 CN 2016087237 W CN2016087237 W CN 2016087237W WO 2017161722 A1 WO2017161722 A1 WO 2017161722A1
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pixel
adjacent
lines
data
array substrate
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PCT/CN2016/087237
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English (en)
French (fr)
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任兴凤
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/534,526 priority Critical patent/US10283027B2/en
Publication of WO2017161722A1 publication Critical patent/WO2017161722A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/10—Dealing with defective pixels

Definitions

  • Embodiments of the present disclosure relate to the field of display, and more particularly to a dual gate line array substrate, a test method, a display panel, and a display device.
  • the display device can be classified into a cathode ray tube display CRT, a plasma display PDP, a liquid crystal display LCD, a light emitting diode LED display, an active light emitting diode OLED display, and the like, for example, depending on the materials of manufacture.
  • a cathode ray tube display CRT a plasma display PDP
  • a liquid crystal display LCD a light emitting diode LED display
  • an active light emitting diode OLED display and the like, for example, depending on the materials of manufacture.
  • flat panel displays such as LCDs and LED displays have gradually replaced conventional displays such as CRTs, and are widely used in various industries, becoming an indispensable component of most electronic devices.
  • an array substrate is a major component.
  • the pixel units are periodically arranged.
  • Each of the pixel units may include a thin film transistor (TFT) and a pixel electrode, and each pixel electrode is driven by a data line and a gate line connected to the TFT.
  • TFT thin film transistor
  • the data line is connected to the source of the thin film transistor
  • the gate line is connected to the gate of the thin film transistor
  • the pixel electrode is connected to the drain of the thin film transistor.
  • the single gate line array substrate may include N gate lines and M data lines, and is disposed at the intersection of the gate lines and the data lines. With pixel cells, different combinations of gate lines and data lines can drive different pixel cells.
  • a dual gate array substrate In order to reduce the cost of the product, a dual gate array substrate is provided.
  • the number of data lines can be substantially reduced by half compared to the single gate line array substrate described above, and the number of gate lines is substantially doubled. Due to the double grid line array substrate The reduction in the number of data lines and the cost of the drive circuit (IC) connecting the data lines are also reduced, thereby reducing the cost of the product.
  • the existing double gate line array substrate tends to cause a problem of low pixel detection rate, resulting in low product quality control, which in turn leads to an increase in related costs.
  • pixel defects caused by indium tin oxide (ITO) residues are a phenomenon encountered in the production of double grid line array substrates.
  • ITO indium tin oxide
  • pixel defects caused by the residual of the conductive material may not be detected in some cases. There is therefore a need for an improved dual gate line array substrate.
  • a dual gate line array substrate includes a plurality of sets of double gate lines, a plurality of data lines, and a plurality of pixel pairs disposed in a region defined by the plurality of sets of double gate lines and the plurality of data lines, wherein each set of the double gate lines includes Two gate lines for respectively transmitting the first scan signal and the second scan signal, wherein the relative orientations of the two gate lines are the same in each set of the double gate lines, and each of the pair of pixels includes two pixel units, a pair of double gate lines and two adjacent pairs of double gate lines and two adjacent pairs of data lines defining two adjacent pixel pairs, wherein two pixel units of each pixel pair are respectively connected to the phase The same data line of the two adjacent data lines, the adjacent two pixel units of the two pixel pairs are respectively connected to different data lines of the two adjacent data lines in the extending direction of the data line; One of the two pixel pairs adjacent in the direction in which the set of double gate lines extend,
  • each of the pixel units includes a pixel electrode and a thin film transistor; a gate of the thin film transistor is connected to the gate line, a source is connected to the data line, and a drain and the pixel electrode connection.
  • the pixel electrodes have different sizes and/or shapes.
  • the pixel electrodes are arranged in a strip structure or a triangular structure.
  • the thin film transistor is one of the following: an inorganic thin film transistor, or an organic thin film transistor.
  • the first scan signal and the second scan signal are different in timing.
  • the dual gate line array substrate further includes a common electrode.
  • a method of testing the above dual gate line array substrate wherein each gate line is sequentially numbered along the extending direction of the data line, the number starting from 1, Methods include:
  • the interrupt provides any data signal and scan signal, provides the same timing scan signal to the gate line numbered 2+3i, and performs steps (a) and (b) above;
  • the interrupt provides any data signal and scan signal, provides the same timing scan signal to the gate line numbered 3+3i, and performs steps (a) and (b) above.
  • a display panel that includes at least a dual gate line array substrate as described above.
  • a display device including at least a display panel as described above.
  • the double gate line array substrate disclosed above can be left in a conductive material (for example, ITO)
  • a conductive material for example, ITO
  • Figure 1 schematically illustrates a dual gate line array substrate
  • Figure 2 schematically illustrates the dual gate line array substrate of Figure 1 having a conductive material residue
  • FIG. 3 schematically illustrates a dual gate line array substrate in accordance with an example embodiment of the present disclosure
  • FIG. 4 schematically illustrates a dual gate line array substrate in accordance with another example embodiment of the present disclosure
  • FIG. 5 schematically illustrates a dual gate line array substrate in accordance with another example embodiment of the present disclosure
  • FIG. 6 schematically illustrates a flowchart of a test method of a dual gate line array substrate according to an example embodiment of the present disclosure
  • FIG. 7 schematically illustrates driving results of a pixel unit in which the double gate line array substrate of FIG. 3 is tested according to the test method of FIG.
  • FIG. 8 schematically illustrates driving results of a pixel unit in which the double gate line array substrate of FIG. 1 is tested according to the test method of FIG.
  • a gate line including "ge” in a reference numeral is defined as a gate line for transmitting a first scan signal, and a gate line including "go” in the reference numeral is defined as a second for transmission.
  • the gate line of the scan signal is defined to be different.
  • Data lines with different reference numerals are defined differently.
  • reference numerals of pixel electrodes may be used as reference numerals of pixel units including the pixel electrodes.
  • a pixel electrode may include a transparent conductive film such as an ITO film, an indium zinc oxide (IZO) film, a zinc gallium oxide (ZGO) film, an indium zinc oxide (IZGO) film, a zinc oxide (ZnO) film, AZO (zinc oxide aluminum) film, or other transparent conductive film that can be applied or developed in the future.
  • a transparent conductive film such as an ITO film, an indium zinc oxide (IZO) film, a zinc gallium oxide (ZGO) film, an indium zinc oxide (IZGO) film, a zinc oxide (ZnO) film, AZO (zinc oxide aluminum) film, or other transparent conductive film that can be applied or developed in the future.
  • FIG. 1 schematically shows the structure of a dual gate line array substrate 100.
  • a plurality of sets of double gate lines, a plurality of data lines, and a plurality of pixel pairs disposed in a region defined by the plurality of sets of double gate lines and the plurality of data lines are included.
  • each pixel unit includes a thin film transistor TFT and one pixel electrode connected to the TFT; pixel units in the double gate line array substrate 100 are arranged in a matrix; a horizontal solid line indicated by ge a gate line ge1 ⁇ 1, ge1 ⁇ 3, ge1 ⁇ 5, ge1 ⁇ 7 for transmitting the first scan signal, and a horizontal solid line marked as go indicates a gate line go1 ⁇ 2 for transmitting the second scan signal, go1 ⁇ 4, go1 ⁇ 6, go1 ⁇ 8; vertical solid lines indicate data lines d1 ⁇ 1, d1 ⁇ 2, d1 ⁇ 3, d1 ⁇ 4, d1 ⁇ 5; in the longitudinal direction, between two adjacent pixel units Two gate lines are defined as a set of double gate lines.
  • a set of double gate lines such as ge1 ⁇ 3, go1 ⁇ 4, are arranged between the pixel unit 1 and the pixel unit 2, and each set of double gate lines is included for transmission.
  • Two gate lines of the first scan signal and the second scan signal; every other two pixel units (such as the pixel unit 3 and the pixel unit 5) in the pixel unit of the same row in the dual gate line array substrate 100 are arranged with one data line, For example, d1 ⁇ 2; TFTs are respectively connected to adjacent data lines and gate lines, and images of the same column in the double gate line array substrate 100
  • the connection modes of the TFTs of the unit are basically the same.
  • the source and the gate of the TFT1-1 are connected to the data line d1 ⁇ 1 and the gate line ge1 ⁇ 3, respectively, and the source and gate of the TFT1 ⁇ 2 in the same column as the TFT1 ⁇ 1.
  • the gates of the TFTs of the adjacent pixel cells in the same row in the column substrate 100 are respectively connected to the gate lines transmitting different scanning signals.
  • the gate of the TFT1-1 is connected to the gate line ge1 ⁇ 3 transmitting the first scanning signal, adjacent to The gate of the TFT 1 - 3 is connected to the gate line go1 - 2 of the second scan signal.
  • a set of double gate lines (ge1 ⁇ 3, go1 ⁇ 4) and two adjacent sets of double gate lines ((ge1 ⁇ 1, go1 ⁇ 2) and (ge1 ⁇ 5, Go1 ⁇ 6)) and two adjacent data lines (d1 ⁇ 1 and d1 ⁇ 2) define two pixel pairs (pixel units 3, 4, 5, 6) in the region, and pixel unit 3 is (d1 ⁇ ) 1, go1 ⁇ 2) drive, pixel unit 4 is driven by (d1 ⁇ 1, go1 ⁇ 4); pixel unit 5 is driven by (d1 ⁇ 2, ge1 ⁇ 3), and pixel unit 6 is driven by (d1 ⁇ 2, ge1 ⁇ 5) )drive.
  • the gate line go1 ⁇ 2, go1 ⁇ 4 can transmit the second scan signal of the same timing, and therefore two pixel units (for example, the pixel unit 3 and the pixel unit 4) of the above two pixel pairs in the dual gate line array substrate 100
  • the drivers are the same.
  • ge1 - 3, ge1 - 5 can transmit the first scan signals of the same timing, the driving of the pixel unit 5 and the pixel unit 6 are the same.
  • FIG. 2 schematically shows a dual gate line array substrate 200 having a conductive material residue.
  • the structure of the double gate line array substrate 200 of FIG. 2 is substantially the same as that of the double gate line array substrate 100 shown in FIG. 1. Therefore, for the sake of brevity, the structure of the double gate line array substrate 200 will not be described in detail herein.
  • the dual gate line array substrate 200 is different from the dual gate line array substrate 100 between the pixel electrode 1 ′ and the pixel electrode 2 ′, between the pixel electrode 3 ′ and the pixel electrode 4 ′, and at the pixel electrode 4 ′.
  • a conductive material for example, ITO
  • a conductive material for example, ITO
  • a data signal is supplied to the data line d1-1' and a first scan signal is supplied to the gate line transmitting the first scan signal due to the pixel
  • the driving of the electrode 1' (d1 -1', ge1 - 3') is the same as the driving of the pixel electrode 2' (d1 - 1', ge1 - 5'), that is, the pixel electrode 1' and the pixel electrode 2' can simultaneously Is driven and obtains substantially the same voltage level, so in this case, regardless of whether there is a conductive material remaining between the pixel electrode 1' and the pixel electrode 2', the pixel is electrically The pole 1' and the pixel electrode 2' can be simultaneously driven and obtain substantially the same voltage level, and thus the conductive material residue 2 between the pixel electrode 1' and the pixel electrode 2' cannot be detected.
  • the data signal is supplied to the data line d1-1' and the second scan signal is supplied to the gate line transmitting the second scan signal, and the conductive material residue between the pixel electrode 3' and the pixel electrode 4' cannot be detected. .
  • the driving of the pixel electrode 3' (d1 - 1', go1 - 2') and the driving of the pixel electrode 5' (d1 - 2', ge1 - 5') are different, and the driving of the pixel electrode 5' (d1 - 2) ', ge1 ⁇ 5') and the driving of the pixel electrode 4' (d1 ⁇ 1', go1 ⁇ 4') are different, assuming that only one of the pixel electrodes is driven during a period of time, if adjacent to them The pixel electrodes are also driven, and it is possible to detect that there may be residual conductive material between them or they may be short-circuited.
  • the existing double gate line array is used.
  • the residual of the conductive material may cause a low pixel detection rate.
  • adjacent pixel cells having a conductive material remaining are detected as qualified.
  • other array testing methods may be present to detect the above-described conductive material residue, it may result in increased costs associated with array testing, such as time cost, production cost, and the like.
  • a dual gate line array substrate includes: a plurality of sets of double gate lines, a plurality of data lines, and a plurality of pixel pairs disposed in a region defined by the plurality of sets of double gate lines and the plurality of data lines, wherein each group
  • the double gate line includes two gate lines for respectively transmitting the first scan signal and the second scan signal, wherein the relative orientations of the two gate lines are the same in each set of double gate lines, and each pixel pair includes two pixel units,
  • a pair of double gate lines and two adjacent pairs of double gate lines and two adjacent pairs of data lines define two pixel pairs in each pixel pair, and two adjacent pixel units are respectively connected to two adjacent pixels
  • the same data line in the data line, the adjacent two pixel units of the two pixel pairs in the direction of the data line extension are respectively connected to different data lines of the adjacent two data lines; in the direction of
  • FIG. 3 schematically illustrates a dual gate line array substrate 300 in accordance with an embodiment of the present disclosure.
  • the dual gate line array substrate 300 includes a plurality of sets of double gate lines, a plurality of data lines, and a plurality of pixel pairs disposed in a region defined by the plurality of sets of double gate lines and the plurality of data lines, each set of double gate lines including And transmitting two gate lines of the first scan signal and the second scan signal, wherein the relative orientations of the two gate lines are the same in each set of the double gate lines, for example, the gate lines transmitting the first scan signal are transmitting the second scan signal Above the gate line, in other embodiments, the gate line transmitting the first scan signal is below the gate line transmitting the second scan signal.
  • Each pixel pair includes two pixel units.
  • each pixel unit includes a thin film transistor TFT and one pixel electrode connected to the TFT;
  • pixel units in the double gate line array substrate 300 are arranged in a matrix;
  • a horizontal solid line indicated by ge Grid lines ge3 ⁇ 1, ge3 ⁇ 3, ge3 ⁇ 5, ge3 ⁇ 7 for transmitting the first scan signal, and a horizontal solid line marked as go indicates the gate line go3 ⁇ 2 for transmitting the second scan signal, go3 ⁇ 4, go3 ⁇ 6, go3 ⁇ 8;
  • vertical solid lines indicate data lines d3 ⁇ 1, d3 ⁇ 2, d3 ⁇ 3, d3 ⁇ 4, d3 ⁇ 5; in the longitudinal direction, between two adjacent pixel units
  • the two gate lines are defined as a set of double gate lines.
  • a set of double gate lines such as ge3 ⁇ 3, go3 ⁇ 4, between each of the pixel unit 3 ⁇ 1 and the pixel unit 3 ⁇ 3, each set of double gate lines Include two gate lines for transmitting the first scan signal and the second scan signal; every second pixel unit of the same row of pixel units in the dual gate line array substrate 300 (such as pixel unit 3-1 and pixel unit 3 ⁇ 2)
  • a data line is arranged, for example, d3 ⁇ 2; any set of double gate lines and a pair of adjacent adjacent double gate lines and two adjacent data lines are defined
  • One pixel pair within a region includes two pixel units, one pixel pair as shown in block 304 of FIG.
  • any two sets of double gate lines and two adjacent pairs of double gate lines and two adjacent data lines are aligned in two pixels.
  • Two pixel units in each pixel pair are respectively connected to the same data line in the two adjacent data lines.
  • the pixel units 3 ⁇ 1 and 3 ⁇ 2 of one pixel pair are connected to the same data line d3 ⁇ 1, and the pixel unit 3 ⁇ 3 of the other pixel pair.
  • 3 ⁇ 4 are connected to the same data line d3 ⁇ 2.
  • adjacent two pixel units of the two pixel pairs in the data line extending direction respectively connect different data lines of the adjacent two data lines.
  • the pixel unit 3 ⁇ 1 in the extending direction of the data line d3 ⁇ 1, the pixel unit 3 ⁇ 1 is connected to the data line d3 ⁇ 1, and in the extending direction, the pixel unit 3 ⁇ 1 The adjacent pixel unit 3-3 is connected to a different data line d3-2.
  • a data line connected by two pixel units in one pixel pair and a data line connected to two pixel units in another pixel pair Different but adjacent.
  • the data line to which the pixel pair (pixel units 3 ⁇ 1 and 3 ⁇ 2) is connected is d3 ⁇ 1, and the pixel pair (pixel unit 3) ⁇ 1 and 3 ⁇ 2)
  • the adjacent pixel pairs (pixel units 3 ⁇ 5 and 3 ⁇ 6) are connected to the data line d3 ⁇ 2, and the data lines d3 ⁇ 1 and d3 ⁇ 2 are adjacent.
  • two pixel units adjacent in the extending direction of the data line are respectively connected to gate lines different from the transmission scanning signals adjacent thereto, and two pixel units adjacent to each other in the extending direction of the double gate lines are respectively connected to their respective Adjacent transmission scan signals have different gate lines.
  • two pixel units 3 ⁇ 1 and 3 ⁇ 3 adjacent in the extending direction of the data line d3 ⁇ 1 are respectively connected to gate lines ge3 ⁇ 3 and go3 different from their respective adjacent transmission scanning signals.
  • Two pixel cells adjacent in the direction in which any of the double gate lines extend are respectively connected to gate lines different from their respective adjacent transmission scan signals.
  • two pixel units 3-1 and 3-2 adjacent in the direction in which a set of double gate lines ge3 ⁇ 3 and go3 ⁇ 4 extend are respectively connected to their respective adjacent adjacent transmission scanning signals. Grid lines ge3 ⁇ 3 and go3 ⁇ 2.
  • the dual gate line array substrate 300 only the driving of two pixel units on one diagonal of four adjacent pixel units spanning two rows on one side of one data line is the same, and in FIG. 1 and
  • the dual gate line array substrate 100, 200 shown in FIG. 2 is in two pairs of pixels in a defined area of any two sets of double gate lines and two adjacent double gate lines and adjacent two data lines,
  • the driving of two adjacent pixel units in the extending direction of the data line is the same. That is, the number of adjacent pixel units driving the same in the double gate line array substrate 300 is reduced by 50% compared to the double gate line array substrate 100, 200. Therefore, array testing of the dual gate line array substrate 300 may be easier.
  • the test of the double gate line array substrate 300 will be described in detail.
  • each of the pixel units includes a pixel electrode and a thin film transistor; a gate of the thin film transistor is connected to the gate line, a source is connected to the data line, and a drain is connected to the pixel electrode.
  • the pixel unit 3-2 includes a pixel electrode 3-2 and a TFT3-2. The gate of the TFT3-2 is connected to the gate line go3-2, the source is connected to the data line d3-1, and the drain is connected. The pixel electrodes 3-2 are connected.
  • the first scan signal and the second scan signal have different timings.
  • one of the scan signals can be transmitted at the same time.
  • the pixel electrodes of the dual gate line array substrate may have different sizes and/or shapes.
  • FIG. 4 illustrates a dual gate line array substrate 400 having pixel electrodes of different sizes in accordance with an embodiment of the present disclosure.
  • the arrangement of the double gate line array substrate 400 and the double gate line array shown in FIG. 3 are different except that the size of the pixel electrode (for example, the pixel electrode 4-1 and the pixel electrode 4-2) is different.
  • the arrangement of the substrates 300 is substantially the same and will not be described in detail herein.
  • the size and/or shape of the pixel electrodes of the dual grid line array substrates 300 and 400 may correspond to a pentile arrangement.
  • the size and shape of the pixel electrodes of dual gate line array substrates 300 and 400 can be any size and shape that can be applied as well as any size and any shape developed in the future. Further, it is to be noted that the size and shape of the pixel electrodes of the double gate line array substrates 300 and 400 are merely examples.
  • the pixel electrodes may be arranged in a strip structure or a triangular structure.
  • the pixel electrodes of the double gate line array substrates 300 and 400 in FIG. 3-4 are arranged in a strip structure in which the pixel electrodes of each column are substantially aligned, and the pixel electrodes of each row are substantially aligned. .
  • the pixel electrodes of each row are substantially aligned, and the pixel electrodes of each column are not aligned.
  • FIG. 5 schematically shows a dual gate line array substrate 500 in which pixel electrodes are arranged in a triangular structure.
  • the arrangement of the double gate line array substrate 500 is substantially the same as that of the double gate line array substrates 300 and 400 shown in FIGS. 3 and 4 except that the pixel electrodes are arranged in a triangular structure, and will not be described in detail herein.
  • the pixel electrodes of the dual gate line array substrates 300, 400, and 500 may also be arranged in any other applicable structure or structure to be developed in the future, and the present disclosure is not limited thereto.
  • the dual gate line array substrates 300, 400, and 500 may further include a common electrode (V com ).
  • V com common electrode
  • a common electrode may be disposed on a dual gate line array substrate.
  • the structure of the common electrode may be a mesh structure or any other suitable structure known or developed in the future, and the present disclosure is not limited thereto.
  • the TFT may be one of the following: an inorganic thin film transistor, or an organic thin film transistor.
  • the inorganic thin film transistor may include an amorphous silicon thin film transistor, a polysilicon thin film transistor, or the like.
  • the TFT can be any thin film transistor that can be applied or developed in the future.
  • the TFT can also be transparent.
  • the dual gate line array substrates 300, 400, and 500 may be double gate line array substrates made of any known or future developed flexible material.
  • FIGS. 3-5 are merely examples of dual gate line array substrates in accordance with embodiments of the present disclosure.
  • the data lines and the gate lines are not necessarily straight lines, and may be any suitable shape and trace.
  • the shape and size of the pixel electrode are merely examples.
  • dual gate line array substrates 300, 400, and 500 can include any suitable number of pixel cells. Additionally, in some embodiments, other components may be present for the dual gate line array substrates 300, 400, and 500.
  • Embodiments of the present disclosure also disclose a method of testing a dual gate line array substrate according to an embodiment of the present disclosure, wherein each gate line is sequentially numbered along a data line extending direction, starting from 1. Note that in other embodiments, the numbering can begin with any suitable number.
  • FIG. 6 illustrates a flow chart of a method of testing a dual gate line array substrate in accordance with an embodiment of the present disclosure.
  • 7 illustrates the driving results of the pixel unit according to the test method of FIG. 6.
  • ge denotes a gate line numbered 1+3i
  • go denotes a gate line numbered 2+3i
  • gm denotes a number 3+3i
  • the gate line, i is a natural number
  • one of the adjacent data lines is represented by de
  • the other data line is represented by do.
  • a test method of a dual gate line array substrate will be described below with reference to FIGS. 6-7.
  • step 602 a scan signal of the same timing is supplied to the gate lines numbered 1+3i, i is a natural number, and step (a) is performed: a data signal is transmitted to one of the adjacent two data lines, if The driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, and then the driven pixel unit and any adjacent to the driven pixel unit are determined There may be a short circuit between one pixel unit.
  • step (a) a data signal is supplied to the data line de, and a scan signal of the same timing is supplied to the ge, so that the pixel unit connected to the data line de and the gate line ge is driven, for example, the second row and the third The pixel unit of the column.
  • a pixel unit If a pixel unit is driven, no one of the pixel units adjacent to it will be driven. Referring to FIG. 7, the pixel unit of the second row and the third column is driven, and the pixel unit adjacent thereto is not driven. Therefore, if the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, it can be determined that the driven pixel unit and any one of the pixels adjacent to the driven pixel unit can be determined. There may be a short circuit between the units. For example, optical inspection and/or electrical detection of the array substrate can be performed at this point to find pixel cells that may be shorted.
  • step (b) is performed: interrupting the transmission of the data signal to one of the adjacent two data lines, and transmitting the data signal to the other of the two adjacent data lines, if the driven pixel unit and If any one of the pixel units adjacent to the driven pixel unit is simultaneously driven, it is determined that there may be a short circuit between the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit.
  • the interrupt is supplied with the data signal to the data line de, and the data signal is supplied to the data line do while continuing to provide the same timing scan signal, thus being connected to the data line do and the gate line ge.
  • the pixel unit is driven, for example, the pixel unit of the second row and the fifth column.
  • a pixel unit If a pixel unit is driven, no one of the pixel units adjacent to it will be driven. Referring to FIG. 7, the pixel unit of the second row and the fifth column is driven, and the pixel unit adjacent thereto is not driven. Therefore, if the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, it can be determined that the driven pixel unit and any one of the pixels adjacent to the driven pixel unit can be determined. There may be a short circuit between the units. As described above, optical detection and/or electrical detection of the array substrate can be performed at this time to find a pixel unit in which a short circuit may exist.
  • step 604 the interrupt provides any data signals and scan signals, provides the same timing scan signal to the gate lines numbered 2+3i, and performs steps (a) and (b) above.
  • step (a) a data signal is supplied to the data line de, and a scan signal of the same timing is supplied to the go, so that the pixel unit connected to the data line de and the gate line go is driven, for example, the second row.
  • the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, it can be determined that the driven pixel unit and any one of the pixels adjacent to the driven pixel unit can be determined.
  • optical detection and/or electrical detection of the array substrate can be performed at this time to find a pixel unit in which a short circuit may exist.
  • the data signal is supplied to the data line do, and the scan signal of the same timing is supplied to the go, so that the pixel unit connected to the data line do and the gate line go is driven, for example, the pixel unit of the second row and the second column. .
  • a pixel unit If a pixel unit is driven, no one of the pixel units adjacent to it will be driven. Referring to FIG. 7, the pixel unit of the second row and the second column is driven, and the pixel unit adjacent thereto is not driven. Therefore, if the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, it can be determined that the driven pixel unit and any one of the pixels adjacent to the driven pixel unit can be determined. There may be a short circuit between the units. As described above, optical detection and/or electrical detection of the array substrate can be performed at this time to find a pixel unit in which a short circuit may exist.
  • step 606 the interrupt provides any data signals and scan signals, provides the same timing scan signal to the gate lines numbered 3+3i, and performs steps (a) and (b) above.
  • step (a) a data signal is supplied to the data line de, and a scanning signal of the same timing is supplied to gm, so that the pixel unit connected to the data line de and the gate line gm is driven, for example, the first row and the fifth.
  • the pixel unit of the column If a pixel unit is driven, no one of the pixel units adjacent to it will be driven. Referring to FIG. 7, the pixel unit of the 1st row and the 5th column is driven, and the pixel unit adjacent thereto is not driven.
  • the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, it can be determined that the driven pixel unit and any one of the pixels adjacent to the driven pixel unit can be determined.
  • optical detection and/or electrical detection of the array substrate can be performed at this time to find a pixel unit in which a short circuit may exist.
  • the data signal is supplied to the data line do, and the scanning signal of the same timing is supplied to the gm, so that the pixel unit connected to the data line do and the gate line gm is driven, for example, the pixel unit of the first row and the third column. .
  • any one of the pixel units adjacent thereto will not be driven.
  • the pixel unit of the 1st row and the 3rd column is driven, and the pixel unit adjacent thereto is not driven. Therefore, if the driven pixel unit and any one of the pixel units adjacent to the driven pixel unit are simultaneously driven, it can be determined that the driven pixel unit and any one of the pixels adjacent to the driven pixel unit can be determined. There may be a short circuit between the units. As described above, optical detection and/or electrical detection of the array substrate can be performed at this time to find a pixel unit in which a short circuit may exist.
  • FIG. 8 illustrates the driving results of a part of the pixel units in the dual gate line array substrate 100 by providing the same signals as described above.
  • the pixel unit 8-1 and the pixel unit 8-2 simultaneously obtain the same driving. Therefore, an array test of the dual gate line array substrate 100 may require a more complicated and/or time consuming method. Therefore, in contrast, the double grid line array substrate of the present disclosure has a simpler test method, higher efficiency, higher pixel detection rate, and lower cost.
  • a display panel including at least a dual gate line array substrate according to an embodiment of the present disclosure as described above.
  • the display panel may be a display panel of various types of LCDs, OLEDs, or the like, or a display panel developed in the future.
  • a display device including at least a display panel as described above.
  • the display device may be various types of display devices such as LCDs, OLEDs, or the like, including display panels as described above, or display devices developed in the future.

Abstract

公开了双栅线阵列基板，其中，任一组双栅线及与其相邻的两组双栅线和相邻的两条数据线限定区域内的两个像素对中，每个像素对中的像素单元分别连接相邻的两条数据线中相同的数据线，数据线延伸方向上两个像素对中的相邻的两个像素单元分别连接相邻的两条数据线中不同的数据线；任一组双栅线延伸方向上相邻的两个像素对中，一个像素对中的两个像素单元所连接的数据线与另一个像素对中的两个像素单元所连接的数据线不同但是相邻；数据线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线，任一组双栅线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线。该双栅线阵列基板可以提高像素检出率。

Description

一种双栅线阵列基板、测试方法、显示面板和显示装置
本申请要求于2016年3月24日递交的中国专利申请第201610173093.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示领域，更具体地涉及一种双栅线阵列基板、测试方法、显示面板和显示装置。
背景技术
一般而言，例如根据制造材料的不同，显示装置可以分为阴极射线管显示器CRT，等离子显示器PDP，液晶显示器LCD、发光二极管LED显示器、有源发光二极管OLED显示器等。目前，诸如LCD和LED显示器等的平板显示器已经逐步取代了例如CRT等的传统显示器，广泛地应用于各种行业，成为大多数电子设备必不可少的组成部件。
在诸如LCD和LED显示器等的显示器中，阵列(array)基板是一种主要组件。在阵列基板中，像素单元周期性地排列。每个像素单元可以包含薄膜晶体管(TFT)和像素电极，并且通过数据线和栅线与TFT连接来驱动每个像素电极。一般而言，数据线连接到薄膜晶体管的源极，栅线连接到薄膜晶体管的栅极，像素电极连接到薄膜晶体管的漏极。
在单栅线阵列基板中，假设阵列基板的结构是N*M个像素单元，则该单栅线阵列基板可以包括N个栅线和M个数据线，在栅线和数据线的相交处设置有像素单元，不同的栅线和数据线的组合可以驱动不同的像素单元。
为了降低产品的成本，提供了一种双栅线(dual gate)阵列基板。与上述单栅线阵列基板相比，在双栅线阵列基板中，数据线的数量基本上可以降低一半，而栅线的数量基本上增加了一倍。由于在双栅线阵列基板中 数据线的数量的减少，连接数据线的驱动电路(IC)的成本也相应减少，因此可以降低产品的成本。
然而，在对双栅线阵列基板进行阵列测试(Array Test)中，现有的双栅线阵列基板往往会导致像素检出率低的问题，导致产品品质控制低下，进而导致相关成本提高。例如，氧化铟锡(ITO)残留导致的像素不良是双栅线阵列基板生产过程中会遇到的一种现象。然而，在对现有技术的双栅线阵列基板进行阵列测试中，在一些情况下可能无法检出导电材料残留导致的像素不良。因此存在对改进的双栅线阵列基板的需求。
发明内容
根据本公开的一个方面，公开了一种双栅线阵列基板。所述双栅线阵列基板包括多组双栅线、多条数据线及设置于由多组双栅线及多条数据线限定区域的多个像素对，其中，每组所述双栅线包括分别用于传输第一扫描信号和第二扫描信号的两条栅线，在每组所述双栅线中两条栅线的相对方位相同，每个所述像素对包括两个像素单元，任一组双栅线及与其相邻的两组双栅线和相邻的两条数据线限定区域内的两个所述像素对中，每个像素对中的两个像素单元分别连接所述相邻的两条数据线中相同的数据线，在数据线延伸方向上所述两个像素对中的相邻的两个像素单元分别连接所述相邻的两条数据线中不同的数据线；在所述任一组双栅线延伸方向上相邻的两个所述像素对中，一个像素对中的两个像素单元所连接的数据线与另一个像素对中的两个像素单元所连接的数据线不同但是相邻；以及在数据线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线，在任一组双栅线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线。
根据本公开的实施例，每个所述像素单元包括像素电极及薄膜晶体管；所述薄膜晶体管的栅极与所述栅线连接，源极与所述数据线连接，漏极与所述像素电极连接。
根据本公开的实施例，所述像素电极具有不同的大小和/或形状。
根据本公开的实施例，所述像素电极被布置成条状结构或三角形结构。
根据本公开的实施例，所述薄膜晶体管为以下之一：无机薄膜晶体管，或有机薄膜晶体管。
根据本公开的实施例，所述第一扫描信号和第二扫描信号时序不同。
根据本公开的实施例，所述双栅线阵列基板还包括公共电极。
根据本公开的另一个方面，公开了一种对上述双栅线阵列基板进行测试的方法，其中，沿所述数据线延伸方向对每个栅线顺序编号，所述编号从1开始，所述方法包括：
向编号为1+3i的栅线提供相同时序的扫描信号，i为自然数，并执行以下步骤：
(a)向相邻两条数据线中的一条数据线传输数据信号，若被驱动的像素单元和与所述被驱动的像素单元相邻的任何一个像素单元同时被驱动，则判定所述被驱动的像素单元和所述与所述被驱动的像素单元相邻的任何一个像素单元之间可能存在短路；
(b)中断向所述相邻两条数据线中的所述一条数据线传输数据信号，向所述相邻两条数据线中的另一条数据线传输数据信号，若被驱动的像素单元和与所述被驱动的像素单元相邻的任何一个像素单元同时被驱动，则判定所述被驱动的像素单元和所述与所述被驱动的像素单元相邻的任何一个像素单元之间可能存在短路；
中断提供任何数据信号和扫描信号，向编号为2+3i的栅线提供相同时序的扫描信号，并执行上述步骤(a)和(b)；以及
中断提供任何数据信号和扫描信号，向编号为3+3i的栅线提供相同时序的扫描信号，并执行上述步骤(a)和(b)。
根据本公开的另一个方面，公开了一种显示面板，至少包括如上所述的双栅线阵列基板。
根据本公开的另一个方面，公开了一种显示装置，至少包括如上所述的显示面板。
上述公开的双栅线阵列基板，可以在导电材料(例如ITO)残留而导 致相邻像素单元短路或互通的情况下，提高像素检出率，提高产品品控，进而可以提高产品质量，节省成本。
附图说明
现在参照附图，附图仅是示例并且未必按比例绘制，其中：
图1示意性地说明了一种双栅线阵列基板；
图2示意性地说明了具有导电材料残留的图1的双栅线阵列基板；
图3示意性地说明了根据本公开的一个示例实施例的双栅线阵列基板；
图4示意性地说明了根据本公开的另一个示例实施例的双栅线阵列基板；以及
图5示意性地说明了根据本公开的另一个示例实施例的双栅线阵列基板；
图6示意性地说明了根据本公开的示例实施例的双栅线阵列基板的测试方法的流程图；以及
图7示意性说明了根据图6的测试方法对图3的双栅线阵列基板进行测试的像素单元的驱动结果。
图8示意性说明了根据图6的测试方法对图1的双栅线阵列基板进行测试的像素单元的驱动结果。
在附图中，为便于理解，已经使用相似的标记指代基本上具有相同或类似结构和/或相同或类似功能的元素。
具体实施方式
下面参照附图描述本公开的实施例。在下面的描述中，阐述了许多具体细节以便使所属技术领域的技术人员更全面地了解和实现本公开。但是，对所属技术领域的技术人员明显的是，本公开的实现可不具有这些具体细节中的一些具体细节。此外，应当理解的是，本公开并不局限于所介绍的特定实施例。相反，可以考虑用下面所述的特征和要素的任意组合来实施本公开，而无论它们是否涉及不同的实施例。因此，下面的方面、特征、 实施例和优点仅作说明之用，而不应看作是权利要求的要素或限定，除非在权利要求中明确提出。
如本文中使用的，附图标记中包含“ge”的栅线被定义为用于传输第一扫描信号的栅线，附图标记中包含“go”的栅线被定义为用于传输第二扫描信号的栅线。附图标记中包含“go”的栅线与附图标记中包含“ge”的栅线被定义为是不同的。而附图标记不同的数据线被定义是不同的。如本文中使用的，在附图中，像素电极的附图标记可以作为包含该像素电极的像素单元的附图标记。
如本文中使用的，像素电极可以包括透明导电薄膜，诸如ITO膜、氧化锌铟(IZO)膜、氧化锌镓(ZGO)膜、氧化锌铟镓(IZGO)膜、氧化锌(ZnO)膜、AZO(氧化锌铝)膜，或其它可以适用的或将来开发的透明导电薄膜。
图1示意性地示出了一种双栅线阵列基板100的结构。在如图1所示的双栅线阵列基板100中，包括多组双栅线、多条数据线及设置于由多组双栅线及多条数据线限定区域的多个像素对。在双栅线阵列基板100中，每个像素单元包含一个薄膜晶体管TFT和与该TFT连接的一个像素电极；双栅线阵列基板100中的像素单元呈矩阵排列；标记为ge的横向实线表示用于传输第一扫描信号的栅线ge1‐1,ge1‐3,ge1‐5,ge1‐7，标记为go的横向实线表示用于传输第二扫描信号的栅线go1‐2,go1‐4,go1‐6,go1‐8；纵向实线表示数据线d1‐1,d1‐2,d1‐3,d1‐4,d1‐5；在纵向方向上，相邻两个像素单元之间的两个栅线被定义为一组双栅线，例如，在像素单元1和像素单元2之间布置有一组双栅线，例如ge1‐3、go1‐4，每组双栅线包括用于传输第一扫描信号和第二扫描信号的两条栅线；双栅线阵列基板100中同一行的像素单元中每隔两个像素单元(诸如像素单元3和像素单元5)布置有一个数据线，例如d1‐2；TFT分别与其邻近的数据线和栅线连接，并且双栅线阵列基板100中同一列的像素单元的TFT的连接方式基本相同，例如TFT1‐1的源极和栅极分别与数据线d1‐1和栅线ge1‐3连接，与TFT1‐1同一列的TFT1‐2的源极和栅极分别与数据线d1‐1和栅线ge1‐5连接；双栅线阵 列基板100中同一行中相邻的像素单元的TFT的栅极分别连接传输不同扫描信号的栅线，例如TFT1‐1的栅极连接传输第一扫描信号的栅线ge1‐3，相邻的TFT1‐3的栅极连接传输第二扫描信号的栅线go1‐2。
参照图1，如框102所示，一组双栅线(ge1‐3，go1‐4)及与其相邻的两组双栅线((ge1‐1，go1‐2)和(ge1‐5，go1‐6))和相邻的两条数据线(d1‐1和d1‐2)限定区域内的两个像素对(像素单元3、4、5、6)中，像素单元3由(d1‐1，go1‐2)驱动，像素单元4由(d1‐1，go1‐4)驱动；像素单元5由(d1‐2，ge1‐3)驱动，像素单元6由(d1‐2，ge1‐5)驱动。由于栅线go1‐2，go1‐4可以传送相同时序的第二扫描信号，因此双栅线阵列基板100中上述两个像素对中的两个像素单元(例如像素单元3和像素单元4)的驱动是相同的。类似地，由于栅线ge1‐3，ge1‐5可以传送相同时序的第一扫描信号，因此像素单元5和像素单元6的驱动是相同的。
然而在双栅线阵列基板的生产中，不可避免的会存在导电材料(例如制作像素电极的材料，诸如ITO)残留，从而导致相邻像素单元之间的短路(或互通)。图2示意性地示出了具有导电材料残留的双栅线阵列基板200。
参照图2，图2的双栅线阵列基板200的结构与图1中示出的双栅线阵列基板100的结构基本一样。因此出于简洁，在此不在详细描述双栅线阵列基板200的结构。此外，双栅线阵列基板200与双栅线阵列基板100不同的是，在像素电极1’与像素电极2’之间、在像素电极3’与像素电极4’之间，在像素电极4’与像素电极5’之间，以及在像素电极3’与像素电极5’之间有导电材料(例如ITO)残留，例如导电材料残留2、导电材料残留1、导电材料残留3和导电材料残留4。在这种情况下，在对双栅线阵列基板200进行某种阵列测试中，例如向数据线d1‐1’提供数据信号并且向传输第一扫描信号的栅线提供第一扫描信号，由于像素电极1’的驱动(d1‐1’，ge1‐3’)与像素电极2’的驱动(d1‐1’，ge1‐5’)是相同的，即像素电极1’和像素电极2’可以同时被驱动并获得基本相同的电压电平，因此在这种情况下，不管像素电极1’和像素电极2’之间是否有导电材料残留2，像素电 极1’和像素电极2’可以同时被驱动并获得基本相同的电压电平，因此不能检测到像素电极1’和像素电极2’之间的导电材料残留2。类似地，例如向数据线d1‐1’提供数据信号并且向传输第二扫描信号的栅线提供第二扫描信号，也不能检测到像素电极3’和像素电极4’之间的导电材料残留1。像素电极3’的驱动(d1‐1’，go1‐2’)和像素电极5’的驱动(d1‐2’，ge1‐5’)是不同的，以及像素电极5’的驱动(d1‐2’，ge1‐5’)和像素电极4’的驱动(d1‐1’，go1‐4’)是不同的，假设在一个时间段期间只驱动它们中的一个像素电极，如果与它们相邻的像素电极也获得驱动，则可以检测到它们之间可能存在导电材料残留或它们可能是短路的。
如上所述，由于在现有的双栅线阵列基板(例如，双栅线阵列基板100、200)中，某些相邻像素电极的驱动是相同的，因此在对现有的双栅线阵列基板进行某种阵列测试中，导电材料的残留可能会造成像素检出率低的情况，例如存在将具有导电材料残留的相邻的像素单元检测为合格的情况。此外，虽然可能存在其它的阵列测试方法来检测上述的导电材料残留，但是可能导致与阵列测试相关的成本增加，例如时间成本、生产成本等。
针对现有的双栅线阵列基板的上述缺陷，本公开的实施例提供了一种改进的双栅线阵列基板。根据本公开的实施例的双栅线阵列基板包括：多组双栅线、多条数据线及设置于由多组双栅线及多条数据线限定区域的多个像素对，其中，每组双栅线包括分别用于传输第一扫描信号和第二扫描信号的两条栅线，在每组双栅线中两条栅线的相对方位相同，每个像素对包括两个像素单元，任一组双栅线及与其相邻的两组双栅线和相邻的两条数据线限定区域内的两个像素对中，每个像素对中的两个像素单元分别连接相邻的两条数据线中相同的数据线，在数据线延伸方向上两个像素对中的相邻的两个像素单元分别连接相邻的两条数据线中不同的数据线；在任一组双栅线延伸方向上相邻的两个像素对中，一个像素对中的两个像素单元所连接的数据线与另一个像素对中的两个像素单元所连接的数据线不同但是相邻；以及在数据线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线，在任一组双栅线延伸方向上相邻的 两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线。下面结合图3‐5来详细说明和解释根据本公开的一些实施例的双栅线阵列基板。
图3示意性地说明了根据本公开的实施例的双栅线阵列基板300。在双栅线阵列基板300中，包括多组双栅线、多条数据线及设置于由多组双栅线及多条数据线限定区域的多个像素对，每组双栅线包括分别用于传输第一扫描信号和第二扫描信号的两条栅线，在每组所述双栅线中两条栅线的相对方位相同，例如传输第一扫描信号的栅线在传输第二扫描信号的栅线上方，在其它实施例中，传输第一扫描信号的栅线在传输第二扫描信号的栅线下方。每个像素对包括两个像素单元。在双栅线阵列基板300中，每个像素单元包含一个薄膜晶体管TFT和与该TFT连接的一个像素电极；双栅线阵列基板300中的像素单元呈矩阵排列；标记为ge的横向实线表示用于传输第一扫描信号的栅线ge3‐1,ge3‐3,ge3‐5,ge3‐7，标记为go的横向实线表示用于传输第二扫描信号的栅线go3‐2,go3‐4,go3‐6,go3‐8；纵向实线表示数据线d3‐1,d3‐2,d3‐3,d3‐4,d3‐5；在纵向方向上，相邻两个像素单元之间的两个栅线被定义为一组双栅线，例如，在像素单元3‐1和像素单元3‐3之间布置有一组双栅线，例如ge3‐3、go3‐4，每组双栅线包括用于传输第一扫描信号和第二扫描信号的两条栅线；双栅线阵列基板300中同一行的像素单元中每隔两个像素单元(诸如像素单元3‐1和像素单元3‐2)布置有一个数据线，例如d3‐2；任一组双栅线及与其相邻的一组双栅线和相邻的两条数据线限定区域内的一个像素对包括两个像素单元，如图3中框304所示出的一个像素对包括两个像素单元。
如图3所示，在双栅线阵列基板300的结构中，任一组双栅线及与其相邻的两组双栅线和相邻的两条数据线限定区域内的两个像素对中，每个像素对中的两个像素单元分别连接该相邻的两条数据线中相同的数据线。例如，在图3中的框302中的两个像素对中，一个像素对的像素单元3‐1和3‐2与相同的数据线d3‐1连接，另一个像素对的像素单元3‐3和3‐4与相同的数据线d3‐2连接。此外，在数据线延伸方向上两个像素对中的相邻的两个像素单元分别连接该相邻的两条数据线中不同的数据线。例如，在 图3中的框302中的两个像素对中，在数据线d3‐1的延伸方向上，像素单元3‐1与数据线d3‐1连接，而在该延伸方向上，像素单元3‐1的相邻像素单元3‐3与不同的数据线d3‐2连接。
另外，在任一组双栅线延伸方向上相邻的两个像素对中，一个像素对中的两个像素单元所连接的数据线与另一个像素对中的两个像素单元所连接的数据线不同但是相邻。例如，在双栅线ge3‐1和go3‐2的延伸方向上，像素对(像素单元3‐1和3‐2)所连接的数据线为d3‐1，而与该像素对(像素单元3‐1和3‐2)相邻的像素对(像素单元3‐5和3‐6)所连接的数据线为d3‐2，并且数据线d3‐1和d3‐2相邻。
此外，在数据线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线，在任一组双栅线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线。例如，在图3中，在数据线d3‐1延伸方向上相邻的两个像素单元3‐1和3‐3分别连接与它们各自相邻的传输扫描信号不同的栅线ge3‐3和go3‐4。在任一组双栅线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线。例如，在图3中，在一组双栅线ge3‐3和go3‐4延伸方向上相邻的两个像素单元3‐1和3‐2分别连接与它们各自相邻的传输扫描信号不同的栅线ge3‐3和go3‐2。
在双栅线阵列基板300中，只有在一个数据线两侧的跨越两行的4个相邻像素单元中的一个对角线上的两个像素单元的驱动是相同的，而在图1和图2中所示出的双栅线阵列基板100、200，在任一组双栅线及与其相邻的两组双栅线和相邻的两条数据线限定区域内的两个像素对中，在数据线的延伸方向上的两个相邻像素单元的驱动是相同的。也就是说，与双栅线阵列基板100、200相比，双栅线阵列基板300中驱动相同的相邻像素单元的数量减少了50％。因此，双栅线阵列基板300的阵列测试可能更容易。在下文中，将对双栅线阵列基板300的测试进行详细描述。
根据各种实施例，每个像素单元包括像素电极及薄膜晶体管；薄膜晶体管的栅极与栅线连接，源极与数据线连接，漏极与像素电极连接。如在 图3中示出的，像素单元3‐2包括像素电极3‐2及TFT3‐2，TFT3‐2的栅极与栅线go3‐2连接，源极与数据线d3‐1连接，漏极与像素电极3‐2连接。
根据各种实施例，第一扫描信号和第二扫描信号时序不同。例如，在使用双栅线阵列基板300的显示装置中，在同一时间可以传送其中一种扫描信号。
根据各种实施例，双栅线阵列基板的像素电极可以具有不同的大小和/或形状。图4示出了根据本公开的实施例的具有不同大小的像素电极的双栅线阵列基板400。
如图4所示，除了像素电极(例如，像素电极4‐1和像素电极4‐2)的大小不同之外，双栅线阵列基板400的布置方式与图3中示出的双栅线阵列基板300的布置方式基本相同，在此不再详细描述。在一个实施例中，双栅线阵列基板300和400的像素电极的大小和/或形状可以与pentile排列方式相对应。在其它实施例中，双栅线阵列基板300和400的像素电极的大小和形状可以是任何可以适用的大小和形状以及将来开发的任何大小和任何形状。此外，需要注意的是，双栅线阵列基板300和400的像素电极的大小和形状仅是示例。
根据各种实施例，像素电极可以被布置成条状结构或三角形结构。图3‐4中的双栅线阵列基板300和400的像素电极被布置成条状结构，在条状结构中，每列的像素电极基本上对齐排列，并且每行的像素电极基本上对齐排列。在三角形结构中，每行的像素电极基本上对齐排列，而每列的像素电极不是对齐排列。图5示意性地示出了像素电极被布置成三角形结构的双栅线阵列基板500。除了像素电极被布置成三角形结构外，双栅线阵列基板500的布置方式与图3和图4中示出的双栅线阵列基板300和400的布置方式基本相同，在此不再详细描述。
在其它实施例中，双栅线阵列基板300、400和500的像素电极也可以被布置成其它任何可以适用的结构或将来开发的结构，本公开对此没有任何限制。
根据本公开的各种实施例，双栅线阵列基板300、400和500还可以 包括公共电极(Vcom)。例如，在IPS(In‐Plane Switching)类型的阵列基板中，公共电极可以被布置在双栅线阵列基板上。此外，公共电极的结构可以是网状结构或是其它已知的或将来开发的任何合适的结构，本公开对此没有任何限制。
根据本公开的各种实施例，TFT可以是以下之一：无机薄膜晶体管，或有机薄膜晶体管。无机薄膜晶体管可以包括非晶硅薄膜晶体管、多晶硅薄膜晶体管等。在其它实施例中，TFT可以是任何可以适用的或将来开发的薄膜晶体管。此外，TFT也可以是透明的。
根据本公开的各种实施例，双栅线阵列基板300、400和500可以是由任何已知的或将来开发的柔性材料制成的双栅线阵列基板。
此外，需要注意的是，出于说明和解释本公开的示例实施例的目的，图3‐5仅是根据本公开的实施例的双栅线阵列基板的示例。在实际的双栅线阵列基板中，数据线与栅线未必是直线，并且可以具体任何合适的形状和走线。另外，像素电极的形状和大小仅是示例。此外，双栅线阵列基板300、400和500可以包含任何合适数量的像素单元。另外，在一些实施例中，双栅线阵列基板300、400和500还可以存在其它组件。
本公开的实施例还公开了一种对根据本公开实施例的双栅线阵列基板进行测试的方法，其中，沿数据线延伸方向对每个栅线顺序编号，编号从1开始。注意的是，在其它实施例中，编号可以从任何合适的数字开始。
图6说明了根据本公开的实施例的双栅线阵列基板的测试方法的流程图。图7说明了根据图6的测试方法的像素单元的驱动结果，在图7中ge表示编号为1+3i的栅线，go表示编号为2+3i的栅线，gm表示编号为3+3i的栅线，i为自然数，相邻数据线中的一个数据线用de表示，另一个数据线用do表示。下面参照图6‐7来描述双栅线阵列基板的测试方法。
在步骤602中，向编号为1+3i的栅线提供相同时序的扫描信号，i为自然数，并执行步骤(a)：向相邻两条数据线中的一条数据线传输数据信号，若被驱动的像素单元和与被驱动的像素单元相邻的任何一个像素单元同时被驱动，则判定被驱动的像素单元和与被驱动的像素单元相邻的任何 一个像素单元之间可能存在短路。参照图7，在步骤(a)中，向数据线de提供数据信号，向ge提供相同时序的扫描信号，因此与数据线de和栅线ge连接的像素单元获得驱动，例如第2行第3列的像素单元。如果一个像素单元获得驱动，则与它相邻的任何一个像素单元不会获得驱动。参照图7，第2行第3列的像素单元获得驱动，而与它相邻的像素单元都没有获得驱动。因此，若被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元同时被驱动，则可以判定该被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。例如，这时可以对阵列基板进行光学检测和/或电学检测，来发现可能存在短路的像素单元。
然后，执行步骤(b)：中断向相邻两条数据线中的一条数据线传输数据信号，向相邻两条数据线中的另一条数据线传输数据信号，若被驱动的像素单元和与被驱动的像素单元相邻的任何一个像素单元同时被驱动，则判定被驱动的像素单元和与被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。参照图7，在步骤(b)中，中断向数据线de提供数据信号，而向数据线do提供数据信号，同时继续ge提供相同时序的扫描信号，因此与数据线do和栅线ge连接的像素单元获得驱动，例如第2行第5列的像素单元。如果一个像素单元获得驱动，则与它相邻的任何一个像素单元不会获得驱动。参照图7，第2行第5列的像素单元获得驱动，而与它相邻的像素单元都没有获得驱动。因此，若被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元同时被驱动，则可以判定该被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。如上所述，这时可以对阵列基板进行光学检测和/或电学检测，来发现可能存在短路的像素单元。
在步骤604中，中断提供任何数据信号和扫描信号，向编号为2+3i的栅线提供相同时序的扫描信号，并执行上述步骤(a)和(b)。参照图7，在步骤(a)中，向数据线de提供数据信号，向go提供相同时序的扫描信号，因此与数据线de和栅线go连接的像素单元获得驱动，例如第2行 第4列的像素单元。如果一个像素单元获得驱动，则与它相邻的任何一个像素单元不会获得驱动。参照图7，第2行第4列的像素单元获得驱动，而与它相邻的像素单元都没有获得驱动。因此，若被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元同时被驱动，则可以判定该被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。如上所述，这时可以对阵列基板进行光学检测和/或电学检测，来发现可能存在短路的像素单元。在步骤(b)中，向数据线do提供数据信号，向go提供相同时序的扫描信号，因此与数据线do和栅线go连接的像素单元获得驱动，例如第2行第2列的像素单元。如果一个像素单元获得驱动，则与它相邻的任何一个像素单元不会获得驱动。参照图7，第2行第2列的像素单元获得驱动，而与它相邻的像素单元都没有获得驱动。因此，若被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元同时被驱动，则可以判定该被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。如上所述，这时可以对阵列基板进行光学检测和/或电学检测，来发现可能存在短路的像素单元。
在步骤606中，中断提供任何数据信号和扫描信号，向编号为3+3i的栅线提供相同时序的扫描信号，并执行上述步骤(a)和(b)。参照图7，在步骤(a)中，向数据线de提供数据信号，向gm提供相同时序的扫描信号，因此与数据线de和栅线gm连接的像素单元获得驱动，例如第1行第5列的像素单元。如果一个像素单元获得驱动，则与它相邻的任何一个像素单元不会获得驱动。参照图7，第1行第5列的像素单元获得驱动，而与它相邻的像素单元都没有获得驱动。因此，若被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元同时被驱动，则可以判定该被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。如上所述，这时可以对阵列基板进行光学检测和/或电学检测，来发现可能存在短路的像素单元。在步骤(b)中，向数据线do提供数据信号，向gm提供相同时序的扫描信号，因此与数据线do和栅线gm连接的像素单元获得驱动，例如第1行第3列的像素单元。如果一个 像素单元获得驱动，则与它相邻的任何一个像素单元不会获得驱动。参照图7，第1行第3列的像素单元获得驱动，而与它相邻的像素单元都没有获得驱动。因此，若被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元同时被驱动，则可以判定该被驱动的像素单元和与该被驱动的像素单元相邻的任何一个像素单元之间可能存在短路。如上所述，这时可以对阵列基板进行光学检测和/或电学检测，来发现可能存在短路的像素单元。
作为对比，在双栅线阵列基板100中，提供同样的上述信号。如果一个像素单元获得驱动，则与它相邻的一个像素单元也会获得驱动。例如，图8说明了提供同样的上述信号，双栅线阵列基板100中的一部分像素单元的驱动结果。从图8中可以看出，在向数据线de提供数据信号和向栅线ge提供相同时序的扫描信号时，像素单元8‐1和像素单元8‐2同时获得了相同的驱动。因此，对双栅线阵列基板100的阵列测试，可能需要采用更加复杂和/或费时的方法。因此，相比之下，本公开的双栅线阵列基板的测试方法更简单，效率更高，像素检出率更高，成本更低。
根据本公开的各种实施例，提供了一种显示面板，其至少包括如上所述的根据本公开的实施例的双栅线阵列基板。例如，显示面板可以是各种类型的LCD、OLED等显示面板或将来开发的显示面板。
根据本公开的各种实施例，提供了一种显示装置，其至少包括如上所述的显示面板。例如，显示装置可以是包括如上所述的显示面板的各种类型的LCD、OLED等显示装置或将来开发的显示装置等。
尽管以上参照附图描述了本公开的实施例，但是本领域的技术人员可以理解以上描述仅为示例，而不是对本公开的限制。可以对本公开的实施例进行各种修改和变型，而仍落入本公开的精神和范围之内，本公开的范围仅由所附权利要求书确定。

Claims (10)

  1. 一种双栅线阵列基板，包括多组双栅线、多条数据线及设置于由多组双栅线及多条数据线限定区域的多个像素对，
    其中，每组所述双栅线包括分别用于传输第一扫描信号和第二扫描信号的两条栅线，在每组所述双栅线中两条栅线的相对方位相同，
    每个所述像素对包括两个像素单元，
    其中，任一组双栅线及与其相邻的两组双栅线和相邻的两条数据线限定区域内的两个所述像素对中，每个像素对中的两个像素单元分别连接所述相邻的两条数据线中相同的数据线，在数据线延伸方向上所述两个像素对中的相邻的两个像素单元分别连接所述相邻的两条数据线中不同的数据线；
    在所述任一组双栅线延伸方向上相邻的两个所述像素对中，一个像素对中的两个像素单元所连接的数据线与另一个像素对中的两个像素单元所连接的数据线不同但是相邻；以及
    在数据线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线，在任一组双栅线延伸方向上相邻的两个像素单元分别连接与其各自相邻的传输扫描信号不同的栅线。
  2. 根据权利要求1所述的双栅线阵列基板，其中，每个所述像素单元包括像素电极及薄膜晶体管；所述薄膜晶体管的栅极与所述栅线连接，源极与所述数据线连接，漏极与所述像素电极连接。
  3. 根据权利要求2所述的双栅线阵列基板，其中，所述像素电极具有不同的大小和/或形状。
  4. 根据权利要求2或3所述的双栅线阵列基板，其中，所述像素电极被布置成条状结构或三角形结构。
  5. 根据权利要求2‐4中的任何一项所述的双栅线阵列基板，其中，所述薄膜晶体管为以下之一：无机薄膜晶体管，或有机薄膜晶体管。
  6. 根据权利要求1‐5中的任何一项所述的双栅线阵列基板，其中，所 述第一扫描信号和第二扫描信号时序不同。
  7. 根据权利要求1‐6中的任何一项所述的双栅线阵列基板，其中，所述双栅线阵列基板还包括公共电极。
  8. 一种对权利要求1‐7中的任何一个双栅线阵列基板进行测试的方法，其中，沿所述数据线延伸方向对每个栅线顺序编号，所述编号从1开始，所述方法包括：
    向编号为1+3i的栅线提供相同时序的扫描信号，i为自然数，并执行以下步骤：
    (a)向相邻两条数据线中的一条数据线传输数据信号，若被驱动的像素单元和与所述被驱动的像素单元相邻的任何一个像素单元同时被驱动，则判定所述被驱动的像素单元和所述与所述被驱动的像素单元相邻的任何一个像素单元之间可能存在短路；
    (b)中断向所述相邻两条数据线中的所述一条数据线传输数据信号，向所述相邻两条数据线中的另一条数据线传输数据信号，若被驱动的像素单元和与所述被驱动的像素单元相邻的任何一个像素单元同时被驱动，则判定所述被驱动的像素单元和所述与所述被驱动的像素单元相邻的任何一个像素单元之间可能存在短路；
    中断提供任何数据信号和扫描信号，向编号为2+3i的栅线提供相同时序的扫描信号，并执行上述步骤(a)和(b)；以及
    中断提供任何数据信号和扫描信号，向编号为3+3i的栅线提供相同时序的扫描信号，并执行上述步骤(a)和(b)。
  9. 一种显示面板，至少包括根据权利要求1‐7中任一项所述的双栅线阵列基板。
  10. 一种显示装置，至少包括根据权利要求9所述的显示面板。
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