WO2017157289A1 - 一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件 - Google Patents

一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件 Download PDF

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WO2017157289A1
WO2017157289A1 PCT/CN2017/076687 CN2017076687W WO2017157289A1 WO 2017157289 A1 WO2017157289 A1 WO 2017157289A1 CN 2017076687 W CN2017076687 W CN 2017076687W WO 2017157289 A1 WO2017157289 A1 WO 2017157289A1
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type
region
heavily doped
disposed
oxide layer
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French (fr)
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孙伟锋
黄薛佺
黄超
张龙
祝靖
陆生礼
时龙兴
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东南大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • the invention mainly relates to the technical field of power semiconductor devices, and is a novel high-current insulator-on-silicon lateral insulated gate bipolar transistor, which is especially suitable for use in a monolithic integrated power chip for realizing accurate control of the motor system.
  • Insulated gate bipolar transistor IGBT is a composite power device developed by combining MOS gate device structure and bipolar transistor structure. It also has the characteristics of MOS tube and bipolar transistor, and has good on-state current and switching loss. A compromise between the two.
  • SOI-Lateral Insulated Gate Bipolar Transistor SOI-LIGBT is a typical SOI-based device with easy integration, high withstand voltage, strong drive current capability, and fast switching speed. Other advantages have been widely used in power integrated circuits.
  • SOI-LIGBTs are often used as core devices for monolithic integrated power chips.
  • the small current capability of the SOI-LIGBT device is a bottleneck that restricts the operating frequency of the monolithic integrated power chip, the work efficiency is better, and the chip area is smaller. Therefore, in order to improve the current capability of the device, some devices have been proposed, but these devices bring new problems while improving current capability.
  • the SOI-LIGBT structure is usually used in circuits to adjust the energy sent to various loads through the DC power supply. Occasionally, the load in the circuit will short-circuit, causing the DC power supply to be directly connected to the collector and emitter of the SOI-LIGBT. At this time, the gate bias is still turned on.
  • the device will withstand high voltage and large current at the same time.
  • the drain with large current density will have obvious thermal effect.
  • the device will thermally break down. And failed.
  • the on-state BV value of the device is significantly reduced due to thermal breakdown in the region, and the drop in withstand voltage reduces the maximum operating voltage of the device, which limits the application of the device.
  • the device is more prone to latch-up.
  • the latch-up effect causes the gate signal to lose control of the device.
  • the device structure may experience destructive failure, and the latch-up suppression capability decreases, making the device reliable. reduce.
  • the present invention proposes a high current insulator-on-silicon laterally insulated gate bipolar transistor device capable of improving injection efficiency and improving the overall current capability of the device.
  • the structure significantly increases the current density of the device while maintaining the withstand voltage of the device and suppresses the latch-up capability, and expands its effective safe working area, so that it can satisfy the high voltage of the SOI-LIGBT device in the monolithic integrated power chip of the motor system. High current and high reliability requirements.
  • a high current insulator-on-silicon laterally insulated gate bipolar transistor device comprising: a P-type substrate with buried oxygen on a P-type substrate and an N-type drift region on a buried oxygen in an N-type drift region There are N-type buffers and P-type body regions on both sides, and a heavily doped P-type collector region in the N-type buffer region, and a collector metal is connected on the heavily doped P-type collector region.
  • a heavily doped P-type emitter region is disposed in the P-type body region, and a heavily doped N-type emitter region is disposed around the heavily doped P-type emitter region, in the heavily doped P-type emitter
  • An emitter metal is connected to the region and the heavily doped N-type emitter region, and a field oxide layer is disposed above the N-type drift region, and one side boundary of the field oxide layer falls above the N-type buffer region, and the other The side boundary is connected to the P-type body region, a gate oxide layer is disposed between the field oxide layer and the heavily doped N-type emitter region, and a first polysilicon layer is disposed on the surface of the gate oxide layer and the first poly layer is The silicon layer extends above the field oxide layer, and a first gate metal is connected to the surface of the first polysilicon layer, wherein a longitudinal groove is disposed outside the P-type body region, in the longitudinal direction. Wrapping vessel provided with the second polysilicon layer of silicon dioxide or other dielectric breakdown voltage
  • the high current insulator-on-silicon laterally insulated gate bipolar transistor device is characterized in that a P-type buried layer is disposed in the P-type body region, and the P-type buried layer is located in a heavily doped P-type layer Below the emitter area.
  • the high current insulator-on-silicon laterally insulated gate bipolar transistor device is characterized in that the heavily doped P-type emitter region is composed of a heavily doped P-type emitter block body arranged in a line, adjacent The heavily doped N-type emitter region between the heavily doped P-type emitter blocks is recessed inwardly, and the gate oxide layer and the first polysilicon layer protrude and extend to occupy the recessed regions.
  • the high current insulator-on-silicon laterally insulated gate bipolar transistor device is characterized in that the P-type buried layer has a higher concentration than the P-type body region.
  • the present invention has the following advantages:
  • the present invention solves the problem of degradation of the on-state BV value.
  • the conventional SOI-LIGBT device due to the existence of the JFET region, as shown in Fig. 1, in the case where the device is turned on, this region will collect a large amount of electrons, and the current passing through this region is large, and this portion of the resistor The value is relatively large, so the region will have a significant thermal effect, causing breakdown of the device and reducing the BV value of the device.
  • the current planar structure cannot fundamentally solve the problem of device breakdown caused by local heating in the JFET region.
  • the invention provides a channel in the Z direction to effectively reduce the degree of electron accumulation in the JEFT region in the conventional planar device, thereby reducing the probability of thermal breakdown, and making the structure of the present invention more reliable in the short circuit process.
  • the present invention solves the contradiction between high current density and latch-up resistance.
  • SOI-LIGBT devices an increase in current capability results in a more easily open parasitic NPN transistor inside the device, which reduces the latch-up resistance of the device.
  • the hole current from the collector flows along the BOX layer to the P-type body region, and the electrons in the longitudinal groove of the present invention can directly recombine with the holes from the collector under the P-type body region, thereby reducing
  • the hole current density makes the latch-up effect more difficult to occur than conventional structures. As shown in composite 2 in Fig.
  • the introduction of the longitudinal grooves reduces the hole injection efficiency, making the internal parasitic NPN tube difficult to open compared to the conventional structure; on the other hand, the present invention is provided in the P-type body region.
  • the high-concentration P-type buried layer reduces its resistance, so that the voltage drop generated after the current flows is low.
  • the parasitic NPN transistor does not turn on, thereby avoiding the latch-up reliability of the device. The problem.
  • the invention increases the channel in the Z direction, thereby increasing the current capability of the device.
  • the ratio W 1 ⁇ W 2 of the lateral length of the convex square region to the N-shaped square drift region is adjustable, which is more flexible in practical applications, between increasing the conduction current density and lowering the on-resistance of the JFET region. Make a compromise.
  • the device of the invention significantly improves the latch-up current capability of the device, and expands the safe working area, thereby making it more suitable for working in a high-voltage and high-current motor drive system.
  • Figure 1 is a cross-sectional view showing the device of a conventional silicon-on-insulator laterally insulated gate bipolar transistor.
  • Figure 2 shows a top view of the structure of the present invention.
  • Figure 3 is a cross-sectional structural view showing the structure of the present invention.
  • Figure 4 is a three dimensional view of the structure of the present invention with the metal electrode removed.
  • Fig. 5 is a three-dimensional enlarged view showing a portion of the structure source region of the present invention.
  • Fig. 6 is a plan view showing the positive pressure applied to the gate after the metal electrode and the field oxide layer are removed in the structure of the present invention.
  • FIG. 7 is a schematic cross-sectional view showing the structure current generation and composition mechanism and the equivalent circuit of the present invention.
  • Figure 8 is a comparison diagram of the on-state BV of the structure of the present invention and the conventional structure at the same current density.
  • Fig. 9 is a view showing a comparison of withstand voltage of the structure of the present invention and a conventional structure.
  • Figure 10 shows the normalized current density when the structure W 2 is changed according to the present invention.
  • Figure 11 is a comparison diagram of the I-V curve of the structure of the present invention and the conventional structure.
  • a high current insulator-on-silicon laterally insulated gate bipolar transistor device comprising: a P-type substrate 1 having a buried oxide 2 on the P-type substrate 1 and an N-type drift region 3 on the buried oxide 2
  • An N-type buffer region 4 and a P-type body region 14 are respectively disposed on both sides of the N-type drift region 3, and a heavily doped P-type collector region 5 is present in the N-type buffer region 4, and the heavily doped P
  • a collector metal 21 is connected to the collector region 5, a heavily doped P-type emitter region 8 is provided in the P-type body region 14, and a re-doping is provided around the heavily doped P-type emitter region 8.
  • the impurity N-type emitter region 9 is connected with an emitter metal 18 on the heavily doped P-type emitter region 8 and the heavily doped N-type emitter region 9, and field oxide is disposed above the N-type drift region 3.
  • Layer 6, a side boundary of the field oxide layer 6 falls above the N-type buffer region 4, and the other side boundary is in contact with the P-type body region 14, in the field oxide layer 6 and the heavily doped N-type emitter region 9
  • a gate oxide layer 10 is disposed between the first polysilicon layer 7 on the surface of the gate oxide layer 10 and the first polysilicon layer 7 extends above the field oxide layer 6 in the first polysilicon layer.
  • the surface of 7 is connected with a first gate metal 20, a longitudinal groove 11 is provided outside the P-shaped body region 14, and a second polycrystalline layer covered by silicon dioxide or other pressure-resistant medium is disposed in the longitudinal groove 11.
  • the silicon layer 12 is connected to the second polysilicon layer 12 with a second gate metal 17.
  • a P-type buried layer 13 is provided in the P-type body region 14, and the P-type buried layer 13 is located under the heavily doped P-type emitter region 8; a heavily doped P-type
  • the emitter region 8 is composed of a heavily doped P-type emitter block arranged in a straight line, and the heavily doped N-type emitter region 9 between adjacent heavily doped P-type emitter blocks is recessed inward.
  • the gate oxide layer 10 and the first polysilicon layer 7 protrude and extend to occupy the recessed region, and the region occupied by the gate oxide layer 10 and the first polysilicon layer 7 protruding and extending may be a square region 16, the emitter
  • the two sides of the convex square area 15 of the region 9 are defined as a second N-type emitter region 9b and a fourth N-spaced emitter region 9d, respectively, and an emitter region connecting the inner two apexes of the convex square region 16 of the emitter region 9 Partially defined as a first N-type emitter region 9a, a bottom portion of the convex square region 15 of the emitter region 9 is defined as a third N-type emitter region 9c, the first emitter region 9a, the second emitter region 9b, The third emitter region 9c and the fourth emitter region 9d surround the P-type emitter region 8, and the convex square regions 16 are spaced apart along the third N-type emitter region 9c.
  • the two adjacent convex square regions 16 are spaced apart by an N-shaped square drift region 15, and a P-type body region 14 is disposed outside the N-type square drift region 15 and inside the third N-type emitter region, at the above P
  • a gate oxide layer 10 is provided in a region of the P-type body region 14 other than the buried layer 13 and filled with the square region 16, and the gate oxide layer 10 extends toward the field oxide layer 6 and terminates at the boundary of the field oxide layer 6 at the gate.
  • the surface of the oxide layer 10 is provided with a polysilicon layer 7 and the polysilicon layer 7 extends above the field oxide layer 6; the concentration of the P-type buried layer 13 is higher than that of the P-type body region 14.
  • the gate structure of the device consists of a planar gate and a deep trench gate in the Z direction, as shown in Figure 5.
  • an N-type lateral channel connecting the heavily doped N-type emitter region and the N-type drift region is formed in the P-type body region under the planar gate, such as Figure 6.
  • An N-type longitudinal channel connecting the heavily doped N-type emitter region and the N-type drift region is formed in the inner P-type body region of the trench gate.
  • the collector is positively pressurized, as shown in Fig. 7, the electron current I e is transferred from the N-type emitter region to the N-type drift region through the longitudinal channel and the lateral channel, respectively. The efficiency of electron injection from the channel region is improved.
  • the electron current acts as the base drive current of the PNP transistor, causing holes to be injected into the N-type drift region from the heavily doped P-type collector region, and the injected holes form the emitter current I h of the PNP transistor.
  • the device has a larger base driving current, which can attract more holes to inject the N-type drift region and increase the emitter current of the PNP transistor.
  • the current from the collector to the emitter consists of two parts, including the electron current I e passing through the channel of the MOSFET region and the hole current I h flowing through the PNP tube, which increases the current of both parts. The total current rises.
  • the device When the device is in a short-circuit condition, the device will fail due to high voltage and high current conditions. In order to have a long short-circuit working time, the device should have a large on-state BV value.
  • the inherent mechanism of causing failure during the short circuit is that when the device is turned on, the trapped square region of the conventional structure will collect a large amount of electrons, and the corresponding current density is also large due to the emitter of the device. The collector is directly shorted to the power supply, so the voltage across the device is also high. The presence of high voltage and large current will cause significant thermal effects in the region in a short period of time, causing failure.
  • the present invention introduces a longitudinal channel in the Z direction, so that electrons that can only flow in a single channel on the surface of the device can flow through the longitudinal channel, thereby reducing the degree of aggregation of the conventional structure electrons, thereby reducing the thermal effect of the JFET region, and further
  • the problem of suppressing the degradation of the on-state BV is higher in the case of high voltage and large current, and the effective range of the safe working area is expanded, so that the reliability of the invention in the short circuit process is higher.
  • the LIGBT structure is composed of four layers of N-type and P-type regions alternately, as shown in Fig. 4, which produces parasitic thyristors.
  • the LIGBT current is too large, the part of the thyristor NPN is turned on, the parasitic thyristor is latched, and the current in the device continues to increase, and the gate signal will not be able to control the turn-off of the LIGBT, causing the LIGBT structure to undergo destructive failure.
  • the on-state current density of the device the device will enter the latched state at a lower voltage, reducing device reliability.
  • the structure has a high-concentration P-type buried layer in the P-type body region.
  • the resistance value of this region is relatively small, and the voltage drop generated by the current flowing through this region is also relatively small.
  • the parasitic NPN tube does not turn on. Combining the above two aspects, the device's anti-latch ability has been improved.
  • the side lengths W 1 and W 2 of the convex square region and the N-shaped square drift region of the device are respectively adjustable.
  • the second N-type emitter region, the third N-type emitter region, and the fourth N-type emitter region enclose a JFET region.
  • the JEFT region generates an additional resistance R JEFT , but in general the drift of resistance is a major Rdrain >> R JEFT, JEFT zone resistance can be ignored.
  • the lengths of W 1 and W 2 are changed, the shape of the JEFT region also changes, and the resistance of the JEFT region changes.
  • W 2 decreases R JEFT will increase.
  • the length of the third N-type emitter region is small to a certain extent, R JEFT will not be neglected, and the total on-resistance increases and the on-current density decreases. Therefore, it is necessary to ensure that W 2 cannot be too small.
  • R JEFT cannot be ignored, so that the total on-resistance is increased and turned on. The current density is reduced, so the length of the first N-type emitter region is limited and cannot be increased without limitation.
  • the present invention compares the structure by the semiconductor device simulation software Sentaurus Tcad, as shown in FIGS. 8 to 11.
  • 8 is an open state BV of the structure of the present invention and the conventional structure at the same current density. It can be seen that the structure device of the present invention has a higher open BV value at the same current density, that is, a wider working area corresponding to the safe working area. It is more reliable in the case of high voltage and high current.
  • 9 is a comparison diagram of the withstand voltage of the structure of the present invention and a conventional device.
  • the withstand voltage of the structure of the present invention is the same as that of the conventional device, and in the case of increasing the current density of the device and improving the latch-up inhibiting capability of the device, the device There is no loss of pressure.
  • W 2 is the side length of the N-type square drift region.
  • Figure 10 shows the normalized current density value when the side length value W 2 of the N-type square drift region of the structure of the present invention is changed. It can be seen that when the side length W 2 of the N-type square drift region is decreased, R JEFT will increase. When W 2 is small to a certain extent, R JEFT will not be neglected. At this time, the total on-resistance increases and the on-current density decreases.
  • FIG. 11 is a comparison of the IV curves of the structure of the present invention and the conventional structure. It can be seen from the figure that the on-current capability of the structure of the present invention is stronger than that of the conventional structure.
  • the device of the invention significantly improves the latch-up current capability of the device, and expands the safe working area, thereby making it more suitable for working in a high-voltage and high-current motor drive system.

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Abstract

一种大电流绝缘体上硅横向绝缘栅双极型晶体管，具备：在P型衬底（1）上设有埋氧（2），埋氧（2）上设有N型漂移区（3），其上设有P型体区（14）和N型缓冲区（4），N型缓冲区（4）内设有P型集电极区（5），其上连接有集电极金属，在N型漂移区（3）的上方设有场氧层（6），在P型体区（14）内设有P型发射极区（8），其周边设有N型发射区（9），在N型发射区（9）和P型发射区（8）上连接有发射极金属，在场氧层（6）与N型发射极区（9）之间设有栅氧（10），在栅氧（10）表面设有第一多晶硅层（7），其表面连接有第一栅金属，在P型体区（14）外侧设有纵向沟槽（11），在纵向沟槽（11）内设有二氧化硅或其他介质包裹的第二多晶硅层（12），其上连接有第二栅金属。

Description

一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件 技术领域
本发明主要涉及功率半导体器件技术领域，是一种新型大电流绝缘体上硅横向绝缘栅双极型晶体管，特别适用于单片集成功率芯片中，用来实现对电机系统的准确控制。
背景技术
绝缘栅双极型晶体管IGBT是MOS栅器件结构与双极型晶体管结构相结合进化而成的复合型功率器件，同时具备MOS管与双极型晶体管的特点，具有良好的通态电流和开关损耗之间的折中关系。绝缘体上硅横向绝缘栅双极型晶体管(SOI-Lateral Insulated Gate Bipolar Transistor,SOI-LIGBT)是一种典型的基于SOI工艺的器件，具有易于集成、耐压高、驱动电流能力强、开关速度快等优点，在功率集成电路中得到了广泛应用。
由于以上所述优点，SOI-LIGBT常作为核心器件，用于单片集成功率芯片中。然而，SOI-LIGBT器件电流能力偏小是制约单片集成功率芯片工作频率更高、工作能效更佳、芯片面积更小的瓶颈。因此，为了提高器件的电流能力，目前提出了一些器件，但这些器件在提高电流能力的同时，又会带来新的问题。SOI-LIGBT结构通常用于电路中调整通过直流电源发送给各种负载的能量，偶然地，电路中的负载会形成短路，导致直流电源将直接连到SOI-LIGBT的集电极与发射极，而此时其栅偏置依然导通，此时器件会同时承受高电压与大电流，在电流密度较大的漏极会产生明显的热效应，一旦超过器件的短路工作时间，器件会发生热击穿而失效。同时，器件的开态BV值会由于该区域的热击穿而明显降低，耐压的下降会降低器件的最高工作电压，使器件的运用受到限制。
此外，由于电流能力的提升，器件会更容易发生闩锁效应，闩锁效应会使栅信号失去对器件的控制，器件结构可能经历破坏性失效，闩锁抑制能力的下降，使得器件的可靠性降低。
因此，在保持器件的耐压、不降低SOI-LIGBT的闩锁抑制能力的基础上提高SOI-LIGBT的导通电流密度及SOA能力是研制电机系统中单片集成功率芯片的主要发展方向。
发明内容
本发明针对上述问题，提出了一种能够提高注入效率且能提升器件整体电流能力的大电流绝缘体上硅横向绝缘栅双极型晶体管器件。该结构在保持器件耐压、抑制闩锁能力不降低的前提下，显著提高器件的电流密度，扩展其有效安全工作区，使之能够满足电机系统中单片集成功率芯片对SOI-LIGBT器件高压、大电流及高可靠的要求。
一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件，包括：P型衬底，在P型衬底上设有埋氧，在埋氧上设有N型漂移区，在N型漂移区的两侧分别设有N型缓冲区和P型体区，在N型缓冲区内有重掺杂的P型集电极区，重掺杂的P型集电极区上连接有集电极金属，在P型体区内设有重掺杂的P型发射极区，在重掺杂的P型发射极区的周边设有重掺杂的N型发射区，在上述重掺杂的P型发射极区和重掺杂的N型发射区上连接有发射极金属，在N型漂移区的上方设有场氧层，所述场氧层的一侧边界落在N型缓冲区的上方，另一侧边界与P型体区相接，在场氧层与重掺杂的N型发射区之间设有栅氧化层，在栅氧化层表面设有第一多晶硅层且所述第一多晶硅层延伸至场氧层的上方，在第一多晶硅层的表面连接有第一栅金属，其特征在于，在所述P型体区外侧设有纵向沟槽，在纵向沟槽内设有由二氧化硅或其它耐压介质包裹的第二多晶硅层，在第二多晶硅层上连接有第二栅金属。
所述的大电流绝缘体上硅横向绝缘栅双极型晶体管器件，其特征在于，在所述P型体区内设有P型埋层，且所述P型埋层位于重掺杂的P型发射极区的下方。
所述的大电流绝缘体上硅横向绝缘栅双极型晶体管器件，其特征在于，重掺杂的P型发射极区由呈直线排列的重掺杂的P型发射极区块体构成，相邻重掺杂的P型发射极区块体之间的重掺杂的N型发射区向内凹陷，栅氧化层及第一多晶硅层突入并延伸占据所述凹陷区域。
所述的大电流绝缘体上硅横向绝缘栅双极型晶体管器件，其特征在于，所述P型埋层的浓度高于P型体区。
与现有技术相比，本发明具有如下优点：
本发明解决了开态BV值退化的问题。在传统SOI-LIGBT器件中，由于JFET区域的存在，如图1所示，在器件导通的情况下，这一区域会聚集大量的电子，通过此区域的电流较大，而这部分的电阻值又相对较大，故此区域会产生明显的热效应，导致器件发生击穿，降低了器件的BV值。现在的平面结构无法从根本上解决JFET区域局部发热导致器件击穿的问题。本发明设有Z方向的沟道能够有效降低传统平面器件中JEFT区域的电子聚集程度，从而减小了其发生热击穿的概率，使得本发明结构在短路过程中的可靠性更高。
本发明解决了高电流密度与抗闩锁能力之间的矛盾问题。在SOI-LIGBT器件中，电流能力的提升会导致器件内部寄生NPN三极管更容易开启，使得器件的抗闩锁能力降低。本发明一方面由于Z方向的纵向沟道的存在，使得电子可以通过此纵向沟道直接进入漂 移区，来自集电极的空穴电流会沿着BOX层向P型体区流动，本发明通过纵向沟槽的电子可以与来自集电极的空穴在P型体区下方直接发生复合，从而降低了空穴电流密度，使得闩锁效应相比传统结构而言更加难以发生。如图7中的复合2所示，纵向沟槽的引入降低了空穴注入效率，使得内部寄生的NPN管相比传统结构而言难以开启；另一方面，本发明在P型体区设有高浓度P型埋层，降低其电阻，从而使得电流流过后产生的压降较低，当此压降低于PN结的开启电压时，寄生NPN三极管不会开启，从而避免器件发生闩锁可靠性的问题。
本发明增加了Z方向的沟道，进而提升了器件的电流能力。
与此同时，外凸方形区域与N型方形漂移区的边长之比W1\W2可调，在实际应用可更加灵活，在增加导通电流密度与降低JFET区域的导通电阻之间进行折中。
故本发明器件在显著提高器件的导通电流密度的基础上，又提高了器件的闩锁抑制能力，扩展了其安全工作区，使得其更适合工作在高压大电流的电机驱动系统中。
附图说明
图1所示为传统绝缘体上硅横向绝缘栅双极型晶体管的器件剖面结构图。
图2所示为本发明结构的俯视图。
图3所示为本发明结构的剖面结构图。
图4所示为本发明结构去掉金属电极的三维图。
图5所示为本发明结构源区部分放大后的三维图。
图6所示为本发明结构去掉金属电极和场氧层后栅极加正压的俯视图。
图7所示为本发明结构电流产生与构成机制及等效电路横向剖面示意图。
图8所示为本发明结构与传统结构在相同电流密度情况下的开态BV对比图。
图9所示为本发明结构与传统结构的耐压比较图。
图10所示为本发明结构W2变化时的归一化电流密度。
图11所示为本发明结构与传统结构的I-V曲线对比图。
具体实施方式
下面结合图2、图3，图4，对本发明做详细说明：
一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件，包括：P型衬底1，在P型衬底1上设有埋氧2，在埋氧2上设有N型漂移区3，在N型漂移区3的两侧分别设有N型缓冲区4和P型体区14，在N型缓冲区4内有重掺杂的P型集电极区5，重掺杂的P 型集电极区5上连接有集电极金属21，在P型体区14内设有重掺杂的P型发射极区8，在重掺杂的P型发射极区8的周边设有重掺杂的N型发射区9，在上述重掺杂的P型发射极区8和重掺杂的N型发射区9上连接有发射极金属18，在N型漂移区3的上方设有场氧层6，所述场氧层6的一侧边界落在N型缓冲区4的上方，另一侧边界与P型体区14相接，在场氧层6与重掺杂的N型发射区9之间设有栅氧化层10，在栅氧化层10表面设有第一多晶硅层7且所述第一多晶硅层7延伸至场氧层6的上方，在第一多晶硅层7的表面连接有第一栅金属20，在所述P型体区14外侧设有纵向沟槽11，在纵向沟槽11内设有由二氧化硅或其它耐压介质包裹的第二多晶硅层12，在第二多晶硅层12上连接有第二栅金属17。
在本实例中，在所述P型体区14内设有P型埋层13，且所述P型埋层13位于重掺杂的P型发射极区8的下方；重掺杂的P型发射极区8由呈直线排列的重掺杂的P型发射极区块体构成，相邻重掺杂的P型发射极区块体之间的重掺杂的N型发射区9向内凹陷，栅氧化层10及第一多晶硅层7突入并延伸占据所述凹陷区域，栅氧化层10及第一多晶硅层7突入并延伸所占据的区域可以是一方形区域16，发射极区9的外凸方形区域15的两边分别定义为第二N型发射极区9b和第四N间隔发射极区9d，连接发射极区9的外凸方形区域16的内侧两边顶点的发射极区部分定义为第一N型发射极区9a，发射极区9的外凸方形区域15的底部定义为第三N型发射极区9c，上述第一发射极区9a、第二发射极区9b、第三发射极区9c、第四发射极区9d包围P型发射极区8，上述外凸方形区域16沿着第三N型发射极区9c间隔分布，相邻两个外凸方形区域16的中间隔以N型方形漂移区15，在N型方形漂移区15外侧、第三N型发射极区的内侧设有P型体区14，在上述在P型埋层13以外的P型体区14并充满方形区域16的区域中设有栅氧化层10，所述栅氧化层10向场氧层6延伸并止于场氧层6的边界，在栅氧化层10表面设有多晶硅层7且所述多晶硅层7延伸至场氧层6的上方；所述P型埋层13的浓度高于P型体区14。
下面结合附图对本发明进行进一步说明。
本发明的工作原理：
本器件的栅极结构由平面栅和Z方向的深槽栅组成，如图5。当该器件的两个栅电极都加上正压时，在平面栅下面的P型体区中形成了一个连接重掺杂的N型发射区以及N型漂移区的N型横向沟道，如图6。在槽栅的内侧P型体区内形成了一个连接重掺杂的N型发射区以及N型漂移区的N型纵向沟道。集电极加正压时，如图7，电子电流Ie分别 通过纵向沟道和横向沟道从N型发射区传送到N型漂移区。电子从沟道区注入的效率得到提升。电子电流作为PNP晶体管的基极驱动电流，促使空穴从重掺杂的P型集电区注入N型漂移区，注入的空穴形成了PNP晶体管的发射极电流Ih。所述器件相比传统器件，因为电子电流增大的关系，基极驱动电流增大，能吸引更多的空穴注入N型漂移区，增大了PNP晶体管的发射极电流。从集电极到发射极的电流由两部分组成，包括经过MOSFET区沟道的电子电流Ie和流经PNP管的空穴电流Ih，所述器件使这两部分的电流都增大，器件的总电流上升。
当器件处于短路状态，器件会由于高电压大电流情况而引发失效，为了器件具有较长的短路工作时间，要求器件应具有较大的开态BV值。对于传统结构而言，在短路过程中引发失效的内在机理在于，在器件开启时，传统结构的内陷方形区域会聚集大量的电子，相应的电流密度也就较大，由于器件的发射极与集电极直接与电源短接，因此器件两端电压值也较高，高电压与大电流的同时存在会在短时间内导致该区域产生明显的热效应，从而引发失效。而本发明引入了Z方向的纵向沟道，使得原本只能在器件表面单沟道中流动的电子能够通过纵向沟道流动，从而降低了传统结构电子的聚集程度，使得JFET区域的热效应降低，进而抑制其开态BV退化的问题，在高压大电流的情况下可靠性更高，扩展了其安全工作区的有效范围，使得本发明在短路过程中的可靠性更高。
LIGBT结构中由4层N型和P型区域交替构成，如图4，这产生了寄生的晶闸管。当LIGBT电流太大，使晶闸管NPN的部分导通，则寄生晶闸管闩锁，此时器件中电流继续增大，而栅信号将无法控制LIGBT的关断，使LIGBT结构经历破坏性失效。增大器件的导通电流密度，器件将在更低的电压进入到闩锁状态，降低器件的可靠性。对于传统器件，当空穴从集电极流入经过N型漂移区，再经过P型体区流至发射极时，由于此区域基区电阻的存在，电流流过此区域时会产生压降，当此压降大于PN结的开启电压时，上述NPN管开启，发生闩锁效应。本结构一方面设有Z方向纵向沟道，使得电子能够通过此纵向沟道直接进入漂移区，与来自集电极的空穴发生复合，降低了空穴电流密度从而使得寄生NPN管难以开启，如图7所示的复合2，由于纵向沟道的引入降低了空穴电流，提高了寄生NPN管的开启难度，另一方面，本结构在P型体区中设有高浓度P型埋层，使得此区域的电阻值相对较小，电流流过此区域产生的压降也相对较小，当此压降低于PN结开启电压时，寄生NPN管不会开启。综合以上两个方面，器件的抗闩锁能力得到了提升。
对于所述器件的外凸方形区域与N型方形漂移区的边长W1与W2分别可调。第二N 型发射极区、第三N型发射极区、第四N型发射极区围成了一个JFET区域，图2中15区域，JEFT区产生了额外的电阻RJEFT，但在一般情况下，漂移电阻是主要的Rdrain>>RJEFT，JEFT区电阻可以忽略。在改变W1与W2的长度时，JEFT区域的形状也发生变化，JEFT区的电阻也就发生变化。当W2减小时，RJEFT将增大，第三N型发射极区的长度小到一定程度时，RJEFT将无法忽略，此时总的导通电阻增大，导通电流密度减小，因此要保证W2不能太小。
而在改变N型方形漂移区的边长W2时，第一N型发射极区的长度越长，等效沟道长度越长，电子的注入效率也就越高，导通电流密度增大。但第一N型发射极区越大，JEFT区的电阻也就越大，当第一N型发射极区的长度太大，RJEFT将无法忽略，使总的导通电阻增大，导通电流密度减小，因此第一N型发射极区的长度有一定限制，不能无限制增大。
为了验证本发明的优点，本专利通过半导体器件仿真软件Sentaurus Tcad对结构进行了对比仿真，如图8～图11所示。图8为本发明结构与传统结构在相同电流密度情况下的开态BV，由图可见本发明结构器件在相同电流密度情况下的开态BV值更高，即对应着其安全工作区更宽，在高压大电流的情况下可靠性更强。图9为本发明结构与传统器件的耐压比较图，由图可见本发明结构的耐压与传统器件相同，在提高器件的电流密度，并且提高了器件的闩锁抑制能力的情况下，器件的耐压没有损失。图10中，W2为N型方形漂移区的边长。图10表明了本发明结构的N型方形漂移区边长值W2变化时的归一化电流密度值，由图可见当N型方形漂移区的边长W2减小，RJEFT将增大，W2小到一定程度时，RJEFT将无法忽略，此时总的导通电阻增大，导通电流密度减小，因此要保证W2的值不能太小；当N型方形漂移区的边长W2太大时，外凸方形区域的边长W1减小，单位尺寸的等效沟道长度减小，电子注入效率减小，导通电流密度减小，因此N型方形漂移区的边长W2不能太大。图11为本发明结构与传统结构的I-V曲线对比图，由图可知本发明结构的导通电流能力比传统结构强。
故本发明器件在显著提高器件的导通电流密度的基础上，又提高了器件的闩锁抑制能力，扩展了其安全工作区，使得其更适合工作在高压大电流的电机驱动系统中。

Claims (4)

  1. 一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件，包括：P型衬底(1)，在P型衬底(1)上设有埋氧(2)，在埋氧(2)上设有N型漂移区(3)，在N型漂移区(3)的两侧分别设有N型缓冲区(4)和P型体区(14)，在N型缓冲区(4)内有重掺杂的P型集电极区(5)，重掺杂的P型集电极区(5)上连接有集电极金属(21)，在P型体区(14)内设有重掺杂的P型发射极区(8)，在重掺杂的P型发射极区(8)的周边设有重掺杂的N型发射区(9)，在上述重掺杂的P型发射极区(8)和重掺杂的N型发射区(9)上连接有发射极金属(18)，在N型漂移区(3)的上方设有场氧层(6)，所述场氧层(6)的一侧边界落在N型缓冲区(4)的上方，另一侧边界与P型体区(14)相接，在场氧层(6)与重掺杂的N型发射区(9)之间设有栅氧化层(10)，在栅氧化层(10)表面设有第一多晶硅层(7)且所述第一多晶硅层(7)延伸至场氧层(6)的上方，在第一多晶硅层(7)的表面连接有第一栅金属(20)，其特征在于，在所述P型体区(14)外侧设有纵向沟槽(11)，在纵向沟槽(11)内设有由二氧化硅或其它耐压介质包裹的第二多晶硅层(12)，在第二多晶硅层(12)上连接有第二栅金属(17)。
  2. 根据权利要求1所述的大电流绝缘体上硅横向绝缘栅双极型晶体管器件，其特征在于，在所述P型体区(14)内设有P型埋层(13)，且所述P型埋层(13)位于重掺杂的P型发射极区(8)的下方。
  3. 根据权利要求2所述的大电流绝缘体上硅横向绝缘栅双极型晶体管器件，其特征在于，重掺杂的P型发射极区(8)由呈直线排列的重掺杂的P型发射极区块体构成，相邻重掺杂的P型发射极区块体之间的重掺杂的N型发射区(9)向内凹陷，栅氧化层(10)及第一多晶硅层(7)突入并延伸占据所述凹陷区域。
  4. 根据权利要求2所述的大电流绝缘体上硅横向绝缘栅双极型晶体管器件，其特征在于，所述P型埋层(13)的浓度高于P型体区(14)。
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