WO2017156885A1 - 薄膜晶体管、阵列基板及其制作和驱动方法、显示装置 - Google Patents

薄膜晶体管、阵列基板及其制作和驱动方法、显示装置 Download PDF

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WO2017156885A1
WO2017156885A1 PCT/CN2016/083905 CN2016083905W WO2017156885A1 WO 2017156885 A1 WO2017156885 A1 WO 2017156885A1 CN 2016083905 W CN2016083905 W CN 2016083905W WO 2017156885 A1 WO2017156885 A1 WO 2017156885A1
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Prior art keywords
gate
layer
active layer
array substrate
thin film
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French (fr)
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张淼
孙静
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

Definitions

  • the present invention relates to the field of display, and in particular, to a thin film transistor, an array substrate, a method for fabricating and driving the same, and a display device.
  • amorphous silicon thin transistors is generally around 0.5cm 2 /Vs.
  • the LCD resolution and driving frequency are high, the mobility of existing amorphous silicon is difficult to meet the requirements.
  • the low-temperature polysilicon has a high mobility, it is not compatible with the existing amorphous silicon production line; the oxide TFT has high mobility, and the manufacturing process is compatible with the existing production line, which can better meet the increasing display. demand.
  • the technical problem to be solved by the present invention is how to solve the problem that Vth (threshold voltage) is easily caused to drift due to the high-low level signal of the gate of the oxide TFT in the operation of the display panel.
  • the technical solution of the present invention provides a thin film transistor including an active layer, a gate insulated from the active layer, a source in contact with the active layer, and the active source a drain of the layer contact, wherein the gate includes a first gate under the active layer and a second gate over the active layer.
  • the first gate is disposed directly under the active layer, and the second gate is disposed directly above the active layer.
  • the material of the active layer comprises indium gallium zinc oxide.
  • the present invention also provides an array substrate including the above-described thin film transistor.
  • the array substrate further includes:
  • first gate line electrically connected to the first gate
  • second gate line electrically connected to the second gate
  • a gate insulating layer insulating the first gate from the active layer
  • a passivation layer that insulates the active layer from the second gate
  • a transparent conductive layer serving as a common electrode layer or a pixel electrode layer over the passivation layer is disposed.
  • the second gate and the transparent conductive layer are of the same material and are disposed in the same layer.
  • the first gate, the first gate line, and the second gate line are of the same material and are disposed in the same layer.
  • the first gate, the first gate line, and the second gate line are formed on a surface of the base substrate, and the gate insulating layer is formed on the base substrate And covering the first gate, the first gate line, and the second gate line, the active layer is formed on the gate insulating layer.
  • the array substrate further includes an etch barrier layer formed on the gate insulating layer and covering the active layer, the source and the drain passing through the engraving A first via on the etch stop layer is in contact with the active layer.
  • the passivation layer is formed on the etch stop layer and covers the source and drain electrodes
  • the second gate is formed on the passivation layer, the second gate
  • the pole is electrically connected to the second gate line through a second via hole penetrating the passivation layer, the etch barrier layer and the gate insulating layer, and the transparent conductive layer passes through the passivation layer A three via is connected in contact with the drain.
  • the present invention also provides a display device including the above array substrate.
  • the present invention further provides a method of fabricating an array substrate, the array substrate comprising a thin film transistor, the thin film transistor including an active layer, a first gate insulated from the active layer, and a first a second gate, a source in contact with the active layer, and a drain in contact with the active layer, wherein the method comprises:
  • the method further includes:
  • first gate line electrically connected to the first gate and a second gate line electrically connected to the second gate on a surface of the base substrate
  • a gate insulating layer insulating the first gate from the active layer on the base substrate, the gate An insulating layer covering the first gate, the first gate line and the second gate line, and the active layer is formed on the gate insulating layer;
  • an etch barrier layer having a first via hole on the gate insulating layer Forming an etch barrier layer having a first via hole on the gate insulating layer, the etch barrier layer covering the active layer, and forming the source and drain electrodes to pass the first pass a hole in contact with the active layer;
  • a transparent conductive layer serving as a common electrode layer or a pixel electrode layer over the passivation layer, and forming a second gate on the passivation layer, the second gate passing through the passivation layer,
  • the etch stop layer and the second via of the gate insulating layer are electrically connected to the second gate line, and the transparent conductive layer contacts the drain through a third via on the passivation layer connection.
  • the second gate and the transparent conductive layer are simultaneously formed in one patterning process.
  • the first gate, the first gate line, and the second gate line are simultaneously formed in one patterning process.
  • the present invention further provides a driving method of an array substrate for driving the above array substrate, the driving method comprising:
  • a gate signal is applied to the second gate of the thin film transistor when the n+1th frame image is displayed, and the first gate is suspended.
  • the oxide thin film transistor provided by the present invention has a gate including a first gate under the active layer and a second gate above the active layer, and the first gate and the second gate are alternately controlled, It is possible to suppress drift of electrical characteristics such as threshold voltage (Vth) of the oxide thin film transistor, and improve stability of switching characteristics of the oxide thin film transistor.
  • Vth threshold voltage
  • FIG. 1 is a schematic diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • 3-8 are schematic diagrams of fabricating an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide a thin film transistor including an active layer formed of an oxide semiconductor material, a gate insulated from the active layer, a source in contact with the active layer, and a source The drain of the active layer contact, wherein the gate includes a first gate under the active layer and a second gate above the active layer.
  • An oxide thin film transistor provided by an embodiment of the present invention has a gate including a first gate under the active layer and a second gate above the active layer, by alternately performing the first gate and the second gate Control can suppress drift of electrical characteristics such as threshold voltage (Vth) of the oxide thin film transistor, and improve stability of switching characteristics of the oxide thin film transistor.
  • Vth threshold voltage
  • FIG. 1 is a schematic diagram of a thin film transistor including a first gate 110 disposed on a substrate substrate 100, an active layer 130 formed of an oxide semiconductor material, and an active layer 130.
  • the source 151, the drain 152 and the second gate 170, the source 151 and the drain 152 are in contact with the active layer 130 through the first via on the etch stop layer 140.
  • the first gate 110 is disposed under the active layer 130, preferably disposed directly under the active layer 130, and a gate insulating layer insulating the two is disposed between the first gate 110 and the active layer 130.
  • the second gate 170 is disposed above the active layer 130, preferably directly above the active layer 130, and the second gate 170 and the first gate 110 are vertically symmetrically disposed, the active layer 130 and the first A passivation layer 160 that insulates the two is disposed between the second gates 170.
  • the material of the active layer 130 may include indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • an embodiment of the present invention further provides an array substrate including a thin film transistor including an active layer formed of an oxide semiconductor material, a gate insulated from the active layer, and the active layer a source of contact and a drain in contact with the active layer, wherein the gate includes a first gate under the active layer and a second gate over the active layer.
  • the array substrate may be an array substrate of a display panel (such as an ADS mode, an IPS mode, or an FFS mode display panel) whose display mode is a horizontal electric field mode.
  • the array substrate further includes a first transistor and a thin film transistor. a first gate line electrically connected to the gate, a second gate line electrically connected to the second gate of the thin film transistor, a gate insulating layer insulating the first gate from the active layer, and the active A passivation layer having a layer insulated from the second gate, and a transparent conductive layer disposed as a common electrode layer or a pixel electrode layer over the passivation layer.
  • the second gate and the transparent conductive layer are of the same material and are disposed in the same layer.
  • the first gate, the first gate line, and the second gate line are of the same material and are disposed in the same layer.
  • FIG. 2 is a schematic diagram of an array substrate according to an embodiment of the present invention.
  • the array substrate includes a substrate substrate 100.
  • the substrate substrate 100 is provided with a thin film transistor, and the thin film transistor includes a first gate 110.
  • the active layer 130, the source 151, the drain 152, and the second gate 170 are formed of an oxide semiconductor material.
  • the source 151 and the drain 152 are in contact with the active layer 130 through the first via on the etch barrier 140, and the first gate 110 is disposed under the active layer 130, preferably disposed on the active layer 130.
  • a gate insulating layer 120 is provided between the first gate 110 and the active layer 130, and the second gate 170 is disposed above the active layer 130, preferably disposed on the active layer 130.
  • a passivation layer 160 that insulates both is disposed between the active layer 130 and the second gate 170.
  • the array substrate further includes: a first gate line 113 electrically connected to the first gate 110, wherein the first gate line is arranged along a line and is connected to the first gate Electrically connected, whereby the first gate line 113 is not shown in a cross-sectional view such as that shown in FIG. 2; the second gate line 111 electrically connected to the second gate 170, wherein the second gate line 111 and the first gate line 113 Parallel; a common electrode layer 112 formed of a transparent conductive material such as ITO and a pixel electrode layer 171 formed of a transparent conductive material.
  • the common electrode layer 112, the first gate 110, the first gate line 113, and the second gate line 111 are disposed under the gate insulating layer 120, and the pixel electrode layer 171 and the second gate 170 are disposed on the passivation layer 160.
  • the second gate 170 is electrically connected to the second gate line 111 through the gate insulating layer 120, the etch barrier layer 140, and the second via hole on the passivation layer 160.
  • the materials of the common electrode layer 112, the first gate 110, the first gate line 113, and the second gate line 111 may all be transparent conductive materials.
  • the common electrode layer 112, the first gate 110, and the first The gate line 113 and the second gate line 111 may be simultaneously formed in one patterning process.
  • the material of the pixel electrode layer 171 and the second gate 170 may also be transparent conductive materials. During fabrication, the pixel electrode layer 171 and the second gate 170 may be simultaneously formed in one patterning process. .
  • the common electrode layer 112 is disposed under the gate insulating layer 120, and the pixel electrode layer 171 is disposed above the passivation layer 160.
  • the present invention is not limited thereto.
  • the pixel electrode layer may be disposed under the gate insulating layer, and the common electrode layer may be disposed above the passivation layer.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the display device provided by the embodiment may be any product or component having a display function such as a notebook computer display screen, a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • Embodiments of the present invention also provide a method of fabricating an array substrate, the array substrate including a thin film transistor including an active layer formed of an oxide semiconductor material, and a first gate insulated from the active layer a pole and a second gate, a source in contact with the active layer, and a drain in contact with the active layer, wherein the method comprises:
  • a first gate is formed under the active layer and a second gate is formed over the active layer.
  • the array substrate may be an array substrate of a display panel having a display mode of a horizontal electric field mode (such as an ADS mode, a HADS mode, an IPS mode, or an FFS mode display panel), and the array substrate may be fabricated in addition to the above-described thin film transistor. Also includes:
  • first gate line electrically connected to the first gate and a second gate line electrically connected to the second gate on a surface of the base substrate
  • a gate insulating layer insulating the first gate from the active layer on the base substrate, the gate insulating layer covering the first gate, the first gate line, and the first a second gate line, and the active layer is formed on the gate insulating layer;
  • an etch barrier layer having a first via hole on the gate insulating layer Forming an etch barrier layer having a first via hole on the gate insulating layer, the etch barrier layer covering the active layer, and forming the source and drain electrodes to pass the first pass a hole in contact with the active layer;
  • a transparent conductive layer serving as a common electrode layer or a pixel electrode layer over the passivation layer, and forming a second gate on the passivation layer, the second gate passing through the passivation layer,
  • the etch stop layer and the second via of the gate insulating layer are electrically connected to the second gate line, and the transparent conductive layer contacts the drain through a third via on the passivation layer connection.
  • Methods can include:
  • S1 forming a common electrode layer, for example, sputtering an ITO film on a base substrate (glass substrate), then coating a photoresist, and exposing the photoresist using a mask for making a common electrode layer. After the developing process and the etching process, the remaining photoresist is stripped to form a pattern of the common electrode layer;
  • the first gate, the first gate line, and the second gate line may be simultaneously formed in one patterning process. Specifically, the metal is first performed. Sputtering process, then coating The photoresist is coated, and the photoresist is exposed by using a mask for forming a gate layer. After the developing process and the etching process, the remaining photoresist is stripped to form a first gate and a first gate line. And a pattern of the second gate line, the structure is as shown in FIG. 3, the common electrode layer 112, the first gate 110, the first gate line, and the second gate line 111 are disposed on the base substrate 100;
  • Gate Insulator may be deposited by chemical vapor deposition (CVD) SiO2 or SiONx, thereby forming a gate insulating layer 120 as shown in FIG. 4;
  • CVD chemical vapor deposition
  • an oxide semiconductor film layer may be formed by sputtering using IGZO or other oxide semiconductor material, and then a photoresist is applied, and a mask for forming an active layer is used. Exposing the photoresist, stripping the remaining photoresist after the development process and the etching process, thereby forming a pattern of the active layer 130 as shown in FIG. 5;
  • ESL Etch Stop Layer
  • SiO2 can be deposited by CVD, and then the photoresist is coated, and the photoresist is exposed by using a mask for forming an etch barrier. After the developing process and the etching process, the remaining photoresist is stripped to form a pattern of the etch stop layer 140 having the first via hole as shown in FIG. 6;
  • S6 forming a pattern of a source/drain layer (SD layer), for example, depositing a metal thin film by a sputtering method, then coating a photoresist, and exposing the photoresist using a mask for making a source/drain layer, after passing through After the developing process and the wet etching process, the remaining photoresist is stripped, thereby forming a pattern including the source electrode 151, the drain electrode 152, and the data line (Data line) as shown in FIG. 7;
  • SD layer source/drain layer
  • PVX layer a passivation layer
  • CVD chemical vapor deposition
  • a photoresist exposing the photoresist using a mask of a passivation layer, after undergoing a development process and After the etching process, the remaining photoresist is stripped to form via holes on the gate insulating layer 120, the etch barrier layer 140, and the passivation layer 160, including the drain electrode 152 for the subsequently fabricated pixel electrode layer and the thin film transistor.
  • the second gate electrode and the pixel electrode layer may be simultaneously formed in one patterning process.
  • a transparent conductive film is first formed by a sputtering process, and then the glue is applied. And exposing, developing, etching, and stripping processes to form a conductive pattern, including a slit type pixel electrode layer (PXL electrode) and a second gate, and passing through the via formed in step S7, the second gate Electrically connected to the second gate line, the pixel electrode layer is electrically connected to the drain, thereby obtaining an array substrate as shown in FIG. 2.
  • PXL electrode slit type pixel electrode layer
  • the common electrode layer, the first gate, the first gate line, and the second gate line may be patterned by the same halftone mask (HTM mask), thereby making the common electrode layer, the first gate, and the first gate
  • HTM mask halftone mask
  • the line and the second gate line are simultaneously formed in one patterning process, thereby reducing the number of patterning processes.
  • the method for fabricating the array substrate provided by the embodiment of the present invention can effectively suppress the drift of the threshold voltage (Vth) of the oxide thin film transistor, and does not add a new mask to the process, thereby effectively reducing the occurrence of defects and improving the product. rate.
  • Vth threshold voltage
  • an embodiment of the present invention provides a method for driving an array substrate, which is used in the above array substrate, and the driving method includes:
  • a gate signal is applied to the second gate of the thin film transistor when the n+1th frame image is displayed, and the first gate is suspended.
  • the VGH/VGL signal is applied to the first gate line in an odd frame, and the second gate line is floating; the VGH/VGL signal is applied to the second gate line in an even frame, and the first gate line is suspended. (floating). Since the TFT of the array substrate is a vertically symmetric double gate design, and the two gate positions are opposite, the Vth drift of the TFT is suppressed, thereby ensuring the stability of the electrical characteristics of the TFT.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
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Abstract

一种薄膜晶体管、阵列基板及其制作和驱动方法、显示装置，该薄膜晶体管包括由氧化物半导体材料形成的有源层（130）、与有源层（130）绝缘的栅极、与有源层（130）接触的源极（151）以及与有源层（130）接触的漏极（152），其中，栅极包括位于有源层（130）下方的第一栅极（110）以及位于有源层（130）上方的第二栅极（170）。通过对第一栅极（110）和第二栅极（170）交替进行控制，能够抑制氧化物薄膜晶体管的阈值电压漂移，提高氧化物薄膜晶体管开关特性的稳定性。

Description

薄膜晶体管、阵列基板及其制作和驱动方法、显示装置
本申请要求于2016年3月14日递交的、申请号为201610144790.X、发明名称为“薄膜晶体管、阵列基板及其制作和驱动方法、显示装置”的中国专利申请的优先权，其全部内容通过引用并入本申请中。
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管、阵列基板及其制作和驱动方法、显示装置。
背景技术
随着液晶显示器技术的更新，高迁移率的氧化物TFT(Thin Film Transistor，薄膜晶体管)等技术不断得到应用，成为发展的一个新方向。非晶硅薄晶体管的迁移率一般在0.5cm2/Vs左右，当LCD分辨率与驱动频率较高时，现有非晶硅的迁移率已很难满足要求。低温多晶硅虽然迁移率较高，但与现有的非晶硅产线不兼容；而氧化物TFT迁移率高，且制作工艺与现有产线兼容性好，可以更好地满足日益增长的显示需求。
然而，在显示面板工作时，由于其中的氧化物TFT的栅极持续被施加高低电平信号，导致内部电子吸引或排斥，进而容易造成薄膜晶体管的Vth(阈值电压)漂移，而Vth的漂移可能会导致众多的显示不良。
发明内容
本发明要解决的技术问题是：如何解决在显示面板工作时，由于其中氧化物TFT的栅极持续被施加高低电平信号从而容易造成Vth(阈值电压)漂移的问题。
为解决上述技术问题，本发明的技术方案提供了一种薄膜晶体管，包括有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
优选地，所述第一栅极设置在所述有源层的正下方，所述第二栅极设置在所述有源层的正上方。
优选地，所述有源层的材料包括铟镓锌氧化物。
为解决上述技术问题，本发明还提供了一种阵列基板，包括上述的薄膜晶体管。
在一实施例中，所述阵列基板还包括：
与所述第一栅极电连接的第一栅线、与所述第二栅极电连接的第二栅线；
将所述第一栅极与所述有源层绝缘的栅绝缘层；
将所述有源层与所述第二栅极绝缘的钝化层；
设置在所述钝化层上方用作公共电极层或像素电极层的透明导电层。
优选地，所述第二栅极与所述透明导电层为相同材料且同层设置。
优选地，所述第一栅极、所述第一栅线、所述第二栅线为相同材料且同层设置。
在一实施例中，所述第一栅极、所述第一栅线和所述第二栅线形成在所述衬底基板的表面上，所述栅绝缘层形成在所述衬底基板上且覆盖所述第一栅极、所述第一栅线和所述第二栅线，所述有源层形成在所述栅绝缘层上。
在一实施例中，所述阵列基板还包括刻蚀阻挡层，所述刻蚀阻挡层形成在所述栅绝缘层上且覆盖所述有源层，所述源极和漏极通过所述刻蚀阻挡层上的第一过孔与所述有源层接触。
在一实施例中，所述钝化层形成在所述刻蚀阻挡层上且覆盖所述源极和漏极，所述第二栅极形成在所述钝化层上，所述第二栅极通过贯通所述钝化层、所述刻蚀阻挡层和所述栅绝缘层的第二过孔与所述第二栅线电连接，所述透明导电层通过所述钝化层上的第三过孔与所述漏极接触连接。
为解决上述技术问题，本发明还提供了一种显示装置，包括上述的阵列基板。
为解决上述技术问题，本发明还提供了一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括有源层、与所述有源层绝缘的第一栅极和第二栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述方法包括：
在所述有源层下方形成所述第一栅极以及在所述有源层上方形成所述第二栅极。
在一实施例中，所述方法还包括：
在衬底基板的表面上形成与所述第一栅极电连接的第一栅线以及与所述第二栅极电连接的第二栅线；
在所述衬底基板上形成将所述第一栅极与所述有源层绝缘的栅绝缘层，所述栅 绝缘层覆盖所述第一栅极、所述第一栅线和所述第二栅线，且所述有源层形成在所述栅绝缘层上；
在所述栅绝缘层上形成具有第一过孔的刻蚀阻挡层，所述刻蚀阻挡层覆盖所述有源层，且形成所述源极和漏极、使其通过所述第一过孔与所述有源层接触；
在所述刻蚀阻挡层上形成将所述有源层与所述第二栅极绝缘的钝化层，所述钝化层覆盖所述源极和漏极；
在所述钝化层上方形成用作公共电极层或像素电极层的透明导电层，且在所述钝化层上形成第二栅极，所述第二栅极通过贯通所述钝化层、所述刻蚀阻挡层和所述栅绝缘层的第二过孔与所述第二栅线电连接，所述透明导电层通过所述钝化层上的第三过孔与所述漏极接触连接。
优选地，所述第二栅极与所述透明导电层在一次构图工艺中同时形成。
优选地，所述第一栅极、所述第一栅线、所述第二栅线在一次构图工艺中同时形成。
为解决上述技术问题，本发明还提供了一种阵列基板的驱动方法，用于驱动上述的阵列基板，所述驱动方法包括：
在显示第n帧图像时向所述薄膜晶体管的第一栅极施加栅信号，第二栅极悬空，n为非零的自然数；
在显示第n+1帧图像时向所述薄膜晶体管的第二栅极施加栅信号，第一栅极悬空。
本发明提供的氧化物薄膜晶体管，其栅极包括位于有源层下方的第一栅极以及位于有源层上方的第二栅极，通过对第一栅极和第二栅极交替进行控制，能够抑制氧化物薄膜晶体管的诸如阈值电压(Vth)等电学特性的漂移，提高氧化物薄膜晶体管开关特性的稳定性。
附图说明
图1是本发明实施方式提供的一种薄膜晶体管的示意图；
图2是本发明实施方式提供的一种阵列基板的示意图；
图3-8是本发明实施方式提供的一种制作阵列基板的示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实 施例用于说明本发明，但不用来限制本发明的范围。此外，本领域普通技术人员可以理解，在本发明的具体描述中，术语“第一”、“第二”、“第三”等并不表示任何时间或结构的顺序，而旨在进行部件或结构的区分。
本发明实施方式提供了一种薄膜晶体管，该薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
本发明实施方式提供的氧化物薄膜晶体管，其栅极包括位于有源层下方的第一栅极以及位于有源层上方的第二栅极，通过对第一栅极和第二栅极交替进行控制，能够抑制氧化物薄膜晶体管的诸如阈值电压(Vth)等电学特性的漂移，提高氧化物薄膜晶体管开关特性的稳定性。
参见图1，图1是本发明实施方式提供的一种薄膜晶体管的示意图，该薄膜晶体管包括设置在衬底基板100上的第一栅极110、由氧化物半导体材料形成的有源层130、源极151、漏极152和第二栅极170，源极151和漏极152通过刻蚀阻挡层140上的第一过孔与有源层130接触。
其中，第一栅极110设置在有源层130的下方，优选地设置在有源层130的正下方，第一栅极110与有源层130之间设置有将两者绝缘的栅绝缘层120，第二栅极170设置在有源层130的上方，优选地设置在有源层130的正上方，第二栅极170与第一栅极110呈上下对称设置，有源层130与第二栅极170之间设置有将两者绝缘的钝化层160。
例如，有源层130的材料可以包括铟镓锌氧化物(IGZO)。
此外，本发明实施方式还提供了一种阵列基板，包括薄膜晶体管，该薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
例如，上述阵列基板可以为显示模式为水平电场模式的显示面板(如ADS模式、IPS模式或FFS模式的显示面板)的阵列基板，除上述的薄膜晶体管外，其还包括与薄膜晶体管的第一栅极电连接的第一栅线、与薄膜晶体管的第二栅极电连接的第二栅线、将所述第一栅极与所述有源层绝缘的栅绝缘层、将所述有源层与所述第二栅极绝缘的钝化层、设置在所述钝化层上方用作公共电极层或像素电极层的透明导电层。
优选地，为减少阵列基板的构图工艺次数，所述第二栅极与所述透明导电层为相同材料且同层设置。
优选地，为减少阵列基板的构图工艺次数，所述第一栅极、所述第一栅线、所述第二栅线为相同材料且同层设置。
参见图2，图2是本发明实施方式提供的一种阵列基板的示意图，该阵列基板包括衬底基板100，衬底基板100上设置有薄膜晶体管，该薄膜晶体管包括第一栅极110、由氧化物半导体材料形成的有源层130、源极151、漏极152和第二栅极170。
其中，源极151和漏极152通过刻蚀阻挡层140上的第一过孔与有源层130接触，第一栅极110设置在有源层130的下方，优选地设置在有源层130的正下方，第一栅极110与有源层130之间设置有将两者绝缘的栅绝缘层120，第二栅极170设置在有源层130的上方，优选地设置在有源层130的正上方，有源层130与第二栅极170之间设置有将两者绝缘的钝化层160。
此外，在一个实施例中，例如如图2所示，该阵列基板还包括：与第一栅极110电连接的第一栅线113，其中第一栅线沿直线布置且与第一栅极电连接，由此在例如图2所示的剖视图中未示出第一栅线113；与第二栅极170电连接的第二栅线111，其中第二栅线111与第一栅线113平行；由透明导电材料(如ITO)形成的公共电极层112和由透明导电材料形成的像素电极层171。
其中，公共电极层112、第一栅极110、第一栅线113、第二栅线111设置在栅绝缘层120的下方，像素电极层171、第二栅极170设置在钝化层160的上方，第二栅极170通过栅绝缘层120、刻蚀阻挡层140、钝化层160上的第二过孔与第二栅线111电连接。
此外，公共电极层112、第一栅极110、第一栅线113、第二栅线111的材料可以均为透明导电材料，在制作时，公共电极层112、第一栅极110、第一栅线113、第二栅线111可以在一次构图工艺中同时形成。
此外，像素电极层171、第二栅极170的材料也可以均为透明导电材料，在制作时，像素电极层171、第二栅极170可以在一次构图工艺中同时形成。。
应该指出的是，在本发明的包括上述实施例的一些实施例中，公共电极层112设置在栅绝缘层120的下方，像素电极层171设置在钝化层160的上方。然而，本发明不限于此，例如在另一实施例中，像素电极层可以设置在栅绝缘层的下方，公共电极层可以设置在钝化层的上方。
本发明实施方式还提供了一种显示装置，包括上述的阵列基板。其中，本发明 实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本发明实施方式还提供了一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的第一栅极和第二栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中，所述方法包括：
在所述有源层的下方形成第一栅极以及在所述有源层的上方形成第二栅极。
例如，上述阵列基板可以为显示模式为水平电场模式的显示面板(如ADS模式、HADS模式、IPS模式或FFS模式的显示面板)的阵列基板，除制作上述的薄膜晶体管外，阵列基板的制作方法还包括：
在衬底基板的表面上形成与所述第一栅极电连接的第一栅线以及与所述第二栅极电连接的第二栅线；
在所述衬底基板上形成将所述第一栅极与所述有源层绝缘的栅绝缘层，所述栅绝缘层覆盖所述第一栅极、所述第一栅线和所述第二栅线，且所述有源层形成在所述栅绝缘层上；
在所述栅绝缘层上形成具有第一过孔的刻蚀阻挡层，所述刻蚀阻挡层覆盖所述有源层，且形成所述源极和漏极、使其通过所述第一过孔与所述有源层接触；
在刻蚀阻挡层上形成将所述有源层与所述第二栅极绝缘的钝化层，所述钝化层覆盖所述源极和漏极；
在所述钝化层上方形成用作公共电极层或像素电极层的透明导电层，且在所述钝化层上形成第二栅极，所述第二栅极通过贯通所述钝化层、所述刻蚀阻挡层和所述栅绝缘层的第二过孔与所述第二栅线电连接，所述透明导电层通过所述钝化层上的第三过孔与所述漏极接触连接。
例如，在一具体实施例中，例如参考图3-8(其中未简化起见，未标示出第一栅线113，第一栅线113的描述和标示参考图2)，上述的阵列基板的制作方法可以包括：
S1：制作公共电极层，例如，在衬底基板(玻璃基板)上溅射ITO薄膜，然后涂覆光刻胶，使用制作公共电极层的掩模(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，形成公共电极层的图案；
S2：制作第一栅极、第一栅线、第二栅线，例如，可以使第一栅极、第一栅线、第二栅线在一次构图工艺中同时形成，具体地，首先进行金属溅射工艺，然后涂 覆光刻胶，并使用制作栅层的掩模(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，形成包括第一栅极、第一栅线和第二栅线的图案，其结构如图3所示，公共电极层112、第一栅极110、第一栅线、第二栅线111设置在衬底基板100上；
S3：制作栅绝缘层(Gate Insulator)，例如，可以通过化学气相沉积(CVD)方式沉积SiO2或SiONx，从而如图4所示形成栅绝缘层120；
S4：制作有源层(Active layer)，例如，可以采用IGZO或其他氧化物半导体材料通过溅射方式形成氧化物半导体膜层，然后涂覆光刻胶，使用制作有源层的掩模(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，从而如图5所示形成有源层130的图案；
S5：制作刻蚀阻挡层(Etch Stop Layer，ESL)，例如，可以通过CVD方式沉积SiO2，然后涂覆光刻胶，使用制作刻蚀阻挡层的掩模(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，从而如图6所示形成具有第一过孔的刻蚀阻挡层140的图案；
S6：制作源漏层(SD层)的图案，例如，通过溅射法沉积金属薄膜，然后涂覆光刻胶，使用制作源漏层的掩模(mask)对光刻胶进行曝光，在经过显影工艺和湿蚀工艺后剥离剩余的光刻胶，从而如图7所示，形成包括源极151、漏极152及数据线(Data线)的图案；
S7：制作钝化层(PVX层)，例如，通过CVD方式沉积SiO2或SiONx，然后涂覆光刻胶，使用钝化层的掩模(mask)对光刻胶进行曝光，在经过显影工艺和刻蚀工艺后剥离剩余的光刻胶，从而在栅绝缘层120、刻蚀阻挡层140、钝化层160上形成过孔，包括用于使后续制作的像素电极层与薄膜晶体管的漏极152连接的第三过孔以及用于使后续制作的第二栅极170与第二栅线111连接的第二过孔；
S8：制作像素电极层和第二栅极，例如，可以使第二栅极与像素电极层在一次构图工艺中同时形成，例如，首先通过溅射工艺形成一层透明导电薄膜，然后经过涂胶、曝光、显影、刻蚀和剥离工艺形成导电图案，包括狭缝(slit)型的像素电极层(PXL电极)以及第二栅极，并通过步骤S7中所形成的过孔，第二栅极与第二栅线电连接，像素电极层与漏极电连接，从而得到如图2所示的阵列基板。
优选地，公共电极层、第一栅极、第一栅线、第二栅线可以通过同一个半色调掩模(HTM mask)形成图案，从而使公共电极层、第一栅极、第一栅线、第二栅线在一次构图工艺中同时形成，从而减少构图工艺次数。
本发明实施方式提供的阵列基板的制作方法，能够有效抑制氧化物薄膜晶体管的阈值电压(Vth)的漂移，并且在工艺上不增加新的掩模(mask)，有效减少不良发生，提高产品良率。
此外，本发明实施方式还提供了一种阵列基板的驱动方法，用于上述的阵列基板，所述驱动方法包括：
在显示第n帧图像时向所述薄膜晶体管的第一栅极施加栅信号，第二栅极悬空，n为非零的自然数；
在显示第n+1帧图像时向所述薄膜晶体管的第二栅极施加栅信号，第一栅极悬空。
例如，在显示屏工作时，奇数帧时向第一栅线施加VGH/VGL信号，第二栅线悬空(floating)；偶数帧时向第二栅线施加VGH/VGL信号，第一栅线悬空(floating)。由于阵列基板的TFT为上下对称双栅极设计，且两个栅极位置相反，TFT的Vth漂移受到抑制，从而保证了TFT的电学特性的稳定。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (14)

  1. 一种薄膜晶体管，包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中所述栅极包括位于所述有源层下方的第一栅极以及位于所述有源层上方的第二栅极。
  2. 根据权利要求1所述的薄膜晶体管，其中所述第一栅极设置在所述有源层的正下方，所述第二栅极设置在所述有源层的正上方。
  3. 根据权利要求1所述的薄膜晶体管，其中所述氧化物半导体材料包括铟镓锌氧化物。
  4. 一种阵列基板，其中包括权利要求1-3中任一项所述的薄膜晶体管。
  5. 根据权利要求4所述的阵列基板，其中所述阵列基板还包括：
    与所述第一栅极电连接的第一栅线、与所述第二栅极电连接的第二栅线；
    将所述第一栅极与所述有源层绝缘的栅绝缘层；
    将所述有源层与所述第二栅极绝缘的钝化层；
    设置在所述钝化层上方用作公共电极层或像素电极层的透明导电层。6、根据权利要求5所述的阵列基板，其中所述第二栅极与所述透明导电层为相同材料且同层设置。
  6. 根据权利要求5所述的阵列基板，其中所述第一栅极、所述第一栅线、所述第二栅线为相同材料且同层设置。
  7. 根据权利要求5-7中任一项所述的阵列基板，其中所述第一栅极、所述第一栅线和所述第二栅线形成在所述衬底基板的表面上，所述栅绝缘层形成在所述衬底基板上且覆盖所述第一栅极、所述第一栅线和所述第二栅线，所述有源层形成在所述栅绝缘层上。
  8. 根据权利要求8所述的阵列基板，其中还包括刻蚀阻挡层，所述刻蚀阻挡层形成在所述栅绝缘层上且覆盖所述有源层，所述源极和漏极通过所述刻蚀阻挡层上的第一过孔与所述有源层接触。
  9. 根据权利要求9所述的阵列基板，其中所述钝化层形成在所述刻蚀阻挡层上且覆盖所述源极和漏极，所述第二栅极形成在所述钝化层上，所述第二栅极通过贯通所述钝化层、所述刻蚀阻挡层和所述栅绝缘层的第二过孔与所述第二栅线电连接，所述透明导电层通过所述钝化层上的第三过孔与所述漏极电连接。
  10. 一种显示装置，其中包括权利要求4-10中任一项所述的阵列基板。
  11. 一种阵列基板的制作方法，所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括由氧化物半导体材料形成的有源层、与所述有源层绝缘的第一栅极和第二栅极、与所述有源层接触的源极以及与所述有源层接触的漏极，其中所述方法包括：
    在所述有源层下方形成所述第一栅极以及在所述有源层上方形成所述第二栅极。
  12. 根据权利要求12所述的阵列基板的制作方法，其中还包括：
    在衬底基板的表面上形成与所述第一栅极电连接的第一栅线以及与所述第二栅极电连接的第二栅线；
    在所述衬底基板上形成将所述第一栅极与所述有源层绝缘的栅绝缘层，所述栅绝缘层覆盖所述第一栅极、所述第一栅线和所述第二栅线，且所述有源层形成在所述栅绝缘层上；
    在所述栅绝缘层上形成具有第一过孔的刻蚀阻挡层，所述刻蚀阻挡层覆盖所述有源层，且形成所述源极和漏极、使其通过所述第一过孔与所述有源层接触；
    在所述刻蚀阻挡层上形成将所述有源层与所述第二栅极绝缘的钝化层，所述钝化层覆盖所述源极和漏极；
    在所述钝化层上方形成用作公共电极层或像素电极层的透明导电层，且在所述钝化层上形成第二栅极，所述第二栅极通过贯通所述钝化层、所述刻蚀阻挡层和所述栅绝缘层的第二过孔与所述第二栅线电连接，所述透明导电层通过所述钝化层上的第三过孔与所述漏极接触连接。
  13. 根据权利要求13所述的阵列基板的制作方法，其中所述第二栅极与所述透明导电层在一次构图工艺中同时形成。
  14. 根据权利要求13所述的阵列基板的制作方法，其中所述第一栅极、所述第一栅线、所述第二栅线在一次构图工艺中同时形成。16、一种阵列基板的驱动方法，用于驱动权利要求4-10中任一项所述的阵列基板，所述驱动方法包括：
    在显示第n帧图像时向所述薄膜晶体管的第一栅极施加栅信号，第二栅极悬空，n为非零的自然数；
    在显示第n+1帧图像时向所述薄膜晶体管的第二栅极施加栅信号，第一栅极悬空。
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