WO2017148348A1 - 薄膜晶体管及其制造方法、显示面板及显示装置 - Google Patents

薄膜晶体管及其制造方法、显示面板及显示装置 Download PDF

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WO2017148348A1
WO2017148348A1 PCT/CN2017/075001 CN2017075001W WO2017148348A1 WO 2017148348 A1 WO2017148348 A1 WO 2017148348A1 CN 2017075001 W CN2017075001 W CN 2017075001W WO 2017148348 A1 WO2017148348 A1 WO 2017148348A1
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Prior art keywords
thin film
film transistor
layer
gate
protective layer
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PCT/CN2017/075001
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English (en)
French (fr)
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单奇
胡坤
林立
刘嵩
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昆山工研院新型平板显示技术中心有限公司
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Priority to EP17759199.7A priority Critical patent/EP3425677B1/en
Priority to US16/066,796 priority patent/US10424667B2/en
Priority to KR1020187021458A priority patent/KR102155434B1/ko
Priority to JP2018533945A priority patent/JP6749400B2/ja
Publication of WO2017148348A1 publication Critical patent/WO2017148348A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of flexible display technologies, and in particular, to a thin film transistor, a method of manufacturing the same, a display panel, and a display device.
  • An organic light-emitting device also known as an Organic Electroluminescence Display (OLED)
  • OLED Organic Electroluminescence Display
  • the ester film or film is used as the substrate, and the OLED screen can be made thinner or even folded or rolled up to realize flexible soft screen display.
  • the flexible display device that can be folded or rolled up, and the flexible display is compared with the conventional rigid display device (ie, the display device made on a non-bendable substrate such as glass).
  • the device has many advantages, such as light weight, small size, more convenient carrying, higher impact resistance and stronger seismic performance.
  • the multilayer structure may have a large number of defects at the interface due to different Young's modulus of the layers, thereby affecting device performance, and the thin film transistor is an important functional device in the flexible display device. Its performance has a major impact on the overall performance of flexible products.
  • the prior art generally reduces the thickness of the high-hardness film layer by optimizing the device structure, so that the hardness of the adjacent structure film layer is as close as possible, thereby reducing the damage of the functional layer.
  • variations in the thickness of the layers of the thin film transistor may have an effect on the performance of the thin film transistor, resulting in a final product that does not achieve the desired effect.
  • An object of the present invention is to provide a thin film transistor, a manufacturing method thereof, a display panel and a display device, which protect a semiconductor material in a thin film transistor, reduce stress applied to a material of a thin film transistor during bending, and prevent the thin film transistor device from being bent. Damage to the semiconductor material may occur during the process.
  • the present invention provides a thin film transistor including an active region, a gate insulating layer, a gate, a source, a drain, a passivation layer, and a flat layer which are sequentially formed over a flexible substrate.
  • a protective layer is formed between the passivation layer and the planarization layer, and the protection layer is located directly above the active region and the gate.
  • the protective layer completely covers the gate directly above the active region and the gate.
  • the protective layer is made of an organic material.
  • the protective layer is made of metal.
  • the protective layer covers a gap between the gate and the source and the drain in a direction perpendicular to the gate.
  • the protective layer has a Young's modulus of more than 300 N/m 2 .
  • the method further includes: an upper protective film, a lower protective film and a barrier layer;
  • the upper protective film is disposed on the planarization layer, the lower protective film is disposed under the flexible substrate, and the barrier layer is disposed between the flexible substrate and the gate insulating layer .
  • the present invention further provides a method of fabricating a thin film transistor, the method comprising: sequentially forming an active region, a gate insulating layer, a gate, a source and a drain, and a blunt on a flexible substrate. And forming a protective layer on the passivation layer, forming a planarization layer on the protective layer; the protective layer is located directly above the active region and the gate.
  • the present invention also provides a display panel including the thin film transistor as described above.
  • the present invention also provides a display device comprising the display panel as described above.
  • the display panel and the display device provided by the invention have the following beneficial effects:
  • the protective layer when the protective layer is made of a metal material, the protective layer covers the gap between the active region, the gate, the source and the drain in a direction perpendicular to the gate, and the material of the gate may also For better support, the structure in which the protective layer and the gate material overlap each other can also protect the underlying semiconductor material, and the protective layer and the gate have a small overlap area to reduce the protective layer due to The effect of parasitic capacitance on thin film transistors.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • the core idea of the present invention is to form a protective layer between the passivation layer and the planarization layer of the thin film transistor, the protective layer is located directly above the active region and the gate, and the semiconductor material in the vertical region thereof
  • the protection is generated to reduce the stress on the material of the thin film transistor during the bending process, and the thin film transistor device may be damaged during the bending process, thereby improving the quality of the device.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • the thin film transistor according to the embodiment includes an active region 11 and a gate insulating layer sequentially formed on the flexible substrate 10 . 12.
  • a gate electrode 13 a source electrode 14 , a drain electrode 15 , a passivation layer 16 , and a planarization layer 17 .
  • a protective layer 18 is formed between the passivation layer 16 and the planarization layer 17 . 18 is located directly above the active region 11 and the gate electrode 13.
  • the protective layer 18 is located directly above the active region 11 and the gate electrode 13, and the protective layer 18 completely covers the direction perpendicular to the gate electrode 13.
  • the gate 13 is described.
  • the protective layer 18 may cover (preferably completely cover) the gap between the gate 13 and the source 14 and the drain 15 at least in addition to completely covering the gate 13 in the vertical direction. Area.
  • the material of the protective layer 18 is organic or metal, and may be other materials known to those skilled in the art.
  • the protective layer 18 protects the semiconductor material in the vertical region, thereby reducing the material of the thin film transistor. The stresses encountered in the process can prevent the thin film transistor device from causing damage to the semiconductor material during the bending process, thereby improving the quality of the device.
  • the Young's modulus of the protective layer 18 is larger than 300N / m 2, for example, 350N / m 2, 400N / m 2, 450N / m 2 or 500N / m 2, which can effectively reduce the protective layer 18 below The stress that the thin film transistor portion is subjected to during bending.
  • the protective layer 18 is metal, since parasitic capacitance may be generated between the metal protective layer and the gate electrode 13 to affect the performance of the thin film transistor, as another structural scheme of the thin film transistor, it is possible to reduce the metal.
  • the protective layer 18 is made of a metal material, and the protective layer 18 covers a portion of the active region 11 in a direction perpendicular to the gate electrode 13 and can completely cover the gate electrode 13
  • the protective layer 18 is mainly used for the gate 13 and the source 14
  • the gap region between the drain 15 and the drain 15 is protected.
  • the protective layer 18 and the gate electrode 13 may have only a small overlapping area in the vertical direction, and the structure may be overlapped by the protective layer 18 and the gate electrode 13 (both metal materials). Protection of the underlying semiconductor material, and the overlapping area of the protective layer 18 and the gate electrode 13 is small, so that the parasitic capacitance can be controlled within an acceptable range, for example, less than a predetermined threshold, thereby reducing the parasitic capacitance to the thin film transistor. influences.
  • the thin film transistor further includes an upper protective film 20, a lower protective film 20, and a barrier film 30.
  • the upper protective film 20 is disposed on the planarization layer 17, and the lower protective film 20 is disposed on the Under the flexible substrate 10, the barrier layer 30 is disposed between the flexible substrate 10 and the gate insulating layer 12 for blocking water oxygen molecules.
  • an interlayer insulating layer 19 is formed in the structure shown in FIGS. 1 and 2, and the interlayer insulating layer 19 covers the gate electrode 13.
  • the thin film transistor provided by the present invention forms a protective layer between the passivation layer and the planarization layer on the basis of the conventional thin film transistor for protecting the underlying semiconductor material, and thus only the components of the thin film transistor are Make a simple explanation.
  • the present invention provides a method of fabricating the thin film transistor of the first embodiment, comprising: sequentially forming an active region 11, a gate insulating layer 12, a gate electrode 13, a source electrode 14 and a drain electrode on the flexible substrate 10. And a passivation layer 16 on which a protective layer 18 is formed, and a planarization layer 17 is formed on the protective layer 18; the protective layer 18 is located at the active region 11 and the gate Just above the 13th.
  • the structure shown in Fig. 1 or Fig. 2 is finally formed.
  • the protective layer 18 protects the semiconductor material in the vertical region thereof, thereby reducing stress on the material of the thin film transistor during the bending process, and avoiding damage of the semiconductor material during the bending process of the thin film transistor device, thereby improving the device. the quality of.
  • the protective layer 18 is formed into a different structure as described in the first embodiment according to the material of the protective layer, and is shown in FIGS. 1 and 2, respectively.
  • the embodiment provides a display panel including the thin film transistor of the first embodiment.
  • the display panel of this embodiment has the thin film transistor of the first embodiment, so that a protective layer is formed between the passivation layer and the planarization layer of the thin film transistor, and the protective layer is located at the active region and the gate. Directly above, the semiconductor material in the vertical region is protected, thereby reducing the stress on the material of the thin film transistor during the bending process, and avoiding the damage of the semiconductor material during the bending process of the thin film transistor device, thereby improving the quality of the device.
  • the protective layer is made of a metal material
  • the protective layer covers a portion of the active region in a direction perpendicular to the gate and completely covers a gap between the gate and the source and the drain due to the gate.
  • the material of the pole can also play a better supporting role, and the structure in which the protective layer and the gate material overlap each other can also protect the underlying semiconductor material, and the overlapping area of the protective layer and the gate is small, so Reduce the effects of parasitic capacitance on thin film transistors.
  • the embodiment provides a display device including the display panel of the third embodiment.
  • the display device in this embodiment has the display panel in the third embodiment, so that a protective layer is formed between the passivation layer and the planarization layer of the thin film transistor, and the protective layer is located at the active region and the gate. Directly above, protects the semiconductor material in its vertical region, thereby reducing the thinness The stress of the material of the film transistor during the bending process prevents the thin film transistor device from causing damage to the semiconductor material during the bending process, thereby improving the quality of the device; when the protective layer is made of a metal material, the protective layer is perpendicular to the Covering a portion of the active region in a direction of the gate and completely covering a gap between the gate and the source and the drain, the material of the gate can also serve as a better support, the protective layer and the gate The structure in which the pole materials overlap each other can also protect the underlying semiconductor material, and the small overlapping area of the protective layer and the planarization layer can reduce the influence of the protective layer on the thin film transistor due to the parasitic capacitance problem.
  • the thin film transistor and the manufacturing method thereof, the display panel and the display device of the present invention form a protective layer between the passivation layer and the planarization layer of the thin film transistor, and the protective layer is located in the active region and Directly above the gate, the semiconductor material in the vertical region is protected, thereby reducing stress on the material of the thin film transistor during bending, and avoiding damage of the semiconductor material during the bending process of the thin film transistor device. Further improving the quality of the device; when the protective layer is made of a metal material, the protective layer covers a portion of the active region in a direction perpendicular to the gate and completely covers the gate and the source and the drain The gap can be better supported by the material of the gate.
  • the structure in which the protective layer and the gate material overlap each other can also protect the underlying semiconductor material, and the overlapping area of the protective layer and the gate. Smaller, so the effect of parasitic capacitance on the thin film transistor can be reduced.

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Abstract

提供一种薄膜晶体管及其制造方法、显示面板及显示装置，薄膜晶体管包括依次形成于柔性衬底(10)上的有源区(11)、栅极绝缘层(12)、栅极(13)、源极(14)、漏极(15)、钝化层(16)以及平坦化层(17)，在钝化层(16)与平坦化层(17)之间形成有保护层(18)，保护层(18)位于有源区(11)及栅极(13)的正上方；通过保护层(18)对薄膜晶体管垂直区域的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成的半导体材料的损伤，进而提高器件的质量。

Description

薄膜晶体管及其制造方法、显示面板及显示装置 技术领域
本发明涉及柔性显示技术领域，具体涉及一种薄膜晶体管及其制造方法、显示面板及显示装置。
背景技术
有机发光器件，即有机发光二极管(Organic Light-Emitting Diode，简称OLED)，又称为有机电致发光显示(Organic Electroluminesence Display)具有全固态特性，机械性能好，抗震动性强，使用塑料、聚酯薄膜或胶片作为基板，OLED屏可以做到更薄，甚至可以折叠或卷起来，实现柔性软屏显示。
随着显示技术的发展，研发人员对可折叠或卷起的柔性显示装置不断作出改进，与传统的刚性显示装置(即制作在玻璃等不可弯曲的基材上的显示装置)相比，柔性显示装置具有诸多优势，如重量轻、体积小、携带更为方便，更高的耐冲击性以及更强的抗震性能等。
但是，柔性显示装置在弯曲的情况下，多层结构由于各层材料杨氏模量不同，会在界面处产生大量缺陷，从而影响器件性能，而薄膜晶体管作为柔性显示装置中重要的功能器件，其性能对于柔性产品的整体性能有重大的影响。现有技术一般通过优化器件结构，减少高硬度膜层的厚度，使相邻结构膜层硬度尽可能接近，从而减少功能层受到的损伤。但是，薄膜晶体管中各层材料的厚度的改变可能对薄膜晶体管的性能产生影响，导致最终的产品达不到预计的效果。
因此，亟需提供一种避免薄膜晶体管器件在弯曲过程中可能会造成损伤的方法。
发明内容
本发明的目的在于提供一种薄膜晶体管及其制造方法、显示面板及显示装置，对薄膜晶体管中的半导体材料形成保护，降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤。
为实现上述目的，本发明提供一种薄膜晶体管，所述薄膜晶体管包括依次形成于柔性衬底之上的有源区、栅极绝缘层、栅极、源极、漏极、钝化层以及平坦化层，在所述钝化层与所述平坦化层之间形成有保护层，所述保护层位于所述有源区及所述栅极的正上方。
可选的，在所述的薄膜晶体管中，所述保护层位于所述有源区及所述栅极的正上方完全覆盖所述栅极。
可选的，在所述的薄膜晶体管中，所述保护层的材质为有机物。
可选的，在所述的薄膜晶体管中，所述保护层的材质为金属。
可选的，在所述的薄膜晶体管中，所述保护层在垂直于所述栅极的方向上覆盖所述栅极与源极和漏极之间的间隙。
可选的，在所述的薄膜晶体管中，所述保护层的杨氏模量大于300N/m2。
可选的，在所述的薄膜晶体管中，还包括：上层保护膜、下层保护膜与阻挡层；
所述上层保护膜设置于所述平坦化层之上，所述下层保护膜设置于所述柔性衬底之下，所述阻挡层设置于所述柔性衬底与所述栅极绝缘层之间。
相应的，本发明还提供一种薄膜晶体管的制造方法，制造上述薄膜晶体管，其方法包括：在柔性衬底上依次形成有源区、栅极绝缘层、栅极、源极与漏极以及钝化层，在所述钝化层上形成保护层，在所述保护层上形成平坦化层；所述保护层位于所述有源区及所述栅极的正上方。
相应的，本发明还提供一种显示面板，所述显示面板包括如上所述的薄膜晶体管。
相应的，本发明还提供一种显示装置，所述显示装置包括如上所述的显示面板。
与现有技术相比，本发明提供的薄膜晶体管及其制造方法、显示面板及显示装置具有以下有益效果：
1、在薄膜晶体管的钝化层与平坦化层之间形成一层保护层，保护层位于所述有源区及所述栅极的正上方，对其垂直区域的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高器件的质量；
2、保护层采用金属材质时，所述保护层在垂直于所述栅极的方向上覆盖所述有源区、栅极、源极及漏极之间的间隙，由于栅极的材料也可以起到较好的支撑作用，保护层与栅极材料相互交叠的结构也可以起到对下方半导体材料的保护，并且所述保护层与栅极存在较小的交叠面积可以减少保护层由于寄生电容问题对薄膜晶体管的影响。
附图说明
图1为本发明实施例提供的一种薄膜晶体管的结构示意图；
图2为本发明实施例提供的另一种薄膜晶体管的结构示意图。
具体实施方式
为使本发明的内容更加清楚易懂，以下结合说明书附图，对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例，本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。
其次，本发明利用示意图进行了详细的表述，在详述本发明实例时，为了便于说明，示意图不依照一般比例局部放大，不应对此作为本发明的限定。
本发明的核心思想在于，在薄膜晶体管的钝化层与平坦化层之间形成一层保护层，保护层位于所述有源区及所述栅极的正上方，对其垂直区域的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高器件的质量。
【实施例一】
图1为本发明实施例提供的一种薄膜晶体管的结构示意图，如图1所示，本实施例提出的薄膜晶体管，包括依次形成于柔性衬底10上的有源区11、栅极绝缘层12、栅极13、源极14、漏极15、钝化层16以及平坦化层17，在所述钝化层16与所述平坦化层17之间形成有保护层18，所述保护层18位于所述有源区11及所述栅极13的正上方。
从图1中可以看出，所述保护层18位于所述有源区11及所述栅极13的正上方，且所述保护层18在垂直于所述栅极13的方向上完全覆盖所述栅极13。优选地，所述保护层18除了在垂直方向上完全覆盖所述栅极13之外，还可以至少覆盖(优选完全覆盖)所述栅极13与源极14和漏极15之间的间隙对应的区域。所述保护层18的材质为有机物或者金属，也可以是本领域技术人员已知的其他材料，所述保护层18对其垂直区域内的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高器件的质量。
优选的，所述保护层18的杨氏模量大于300N/m2，例如350N/m2、400N/m2、450N/m2或500N/m2，从而可以有效减小保护层18下方的薄膜晶体 管部分在弯曲过程中受到的应力。
当所述保护层18的材质为金属时，由于金属保护层与栅极13之间可能会产生寄生电容从而可能影响薄膜晶体管的性能，因此作为薄膜晶体管的另一种结构方案，可以设法减少金属保护层与栅极13之间的交叠面积。如图2所示，所述保护层18采用金属材质，所述保护层18在垂直于所述栅极13的方向上覆盖所述有源区11的一部分，且能完全覆盖所述栅极13与源极14和漏极15之间的间隙，由于栅极13也是采用金属材料制成，其本身即可起到较好的支撑作用，因此主要采用保护层18对栅极13与源极14和漏极15之间的间隙区域进行保护。在图2所示结构中，保护层18与栅极13在垂直方向上可以只有很小的交叠面积，通过保护层18与栅极13(均为金属材料)相互交叠的结构可以起到对下方半导体材料的保护，并且保护层18与栅极13的交叠面积较小，因此可以将寄生电容控制在可接受范围以内，例如小于某一预设阈值，从而减少寄生电容对薄膜晶体管的影响。
所述薄膜晶体管还包括上层保护膜20、下层保护膜20与阻挡层30(Barrier film)，所述上层保护膜20设置于所述平坦化层17之上，所述下层保护膜20设置于所述柔性衬底10之下，所述阻挡层30设置于所述柔性衬底10与栅极绝缘层12之间，用于阻挡水氧分子。另外在图1与图2所示结构中还形成有层间绝缘层19，所述层间绝缘层19覆盖所述栅极13。
可以理解的是，本发明所提供的薄膜晶体管是在传统薄膜晶体管的基础上在钝化层与平坦化层之间形成保护层，用于保护下方的半导体材料，因此对薄膜晶体管的组成部分仅作简单的说明。
【实施例二】
本发明提供一种制备实施例一所述的薄膜晶体管的方法，包括：在柔性衬底10上依次形成有源区11、栅极绝缘层12、栅极13、源极14与漏极 15以及钝化层16，在所述钝化层16上形成保护层18，在所述保护层18上形成平坦化层17；所述保护层18位于所述有源区11及所述栅极13的正上方。最终形成图1或图2所示的结构。
所述保护层18对其垂直区域内的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高器件的质量。
所述保护层18根据保护层材料的不同制作成如实施例一所述的不同的结构，分别示于图1和图2中。
【实施例三】
本实施例提供一种显示面板，其包括实施例一所述的薄膜晶体管。
本实施例的显示面板中具有实施例一中的薄膜晶体管，故在薄膜晶体管的钝化层与平坦化层之间形成一层保护层，保护层位于所述有源区及所述栅极的正上方，对其垂直区域的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高了器件的质量；保护层采用金属材质时，所述保护层在垂直于所述栅极的方向上覆盖所述有源区的一部分以及完全覆盖所述栅极与源极和漏极之间的间隙，由于栅极的材料也可以起到较好的支撑作用，保护层与栅极材料相互交叠的结构也可以起到对下方半导体材料的保护，并且保护层与栅极的交叠面积较小，因此可以减少寄生电容对薄膜晶体管的影响。
【实施例四】
本实施例提供一种显示装置，其包括实施例三所述的显示面板。
本实施例中的显示装置具有实施例三中的显示面板，故在薄膜晶体管的钝化层与平坦化层之间形成一层保护层，保护层位于所述有源区及所述栅极的正上方，对其垂直区域内的半导体材料产生保护作用，从而降低薄 膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高器件的质量；保护层采用金属材质时，所述保护层在垂直于所述栅极的方向上覆盖所述有源区的一部分以及完全覆盖所述栅极与源极和漏极之间的间隙，由于栅极的材料也可以起到较好的支撑作用，保护层与栅极材料相互交叠的结构也可以起到对下方半导体材料的保护，并且保护层与平坦化层较小的交叠面积可以减少保护层由于寄生电容问题对薄膜晶体管的影响。
综上所述，本发明提供的薄膜晶体管及其制造方法、显示面板及显示装置，在薄膜晶体管的钝化层与平坦化层之间形成一层保护层，保护层位于所述有源区及所述栅极的正上方，对其垂直区域内的半导体材料产生保护作用，从而降低薄膜晶体管部分材料在弯曲过程中受到的应力，避免薄膜晶体管器件在弯曲过程中可能会造成半导体材料的损伤，进而提高器件的质量；保护层采用金属材质时，所述保护层在垂直于所述栅极的方向上覆盖所述有源区的一部分以及完全覆盖所述栅极与源极和漏极之间的间隙，由于栅极的材料也可以起到较好的支撑作用，保护层与栅极材料相互交叠的结构也可以起到对下方半导体材料的保护，并且保护层与栅极的交叠面积较小，因此可以减少寄生电容对薄膜晶体管的影响。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (10)

  1. 一种薄膜晶体管，包括依次形成于柔性衬底之上的有源区、栅极绝缘层、栅极、源极、漏极、钝化层以及平坦化层，其特征在于，在所述钝化层与所述平坦化层之间形成有保护层，所述保护层位于所述有源区及所述栅极的正上方。
  2. 如权利要求1所述的薄膜晶体管，其特征在于，所述保护层在垂直于所述栅极的方向上完全覆盖所述栅极。
  3. 如权利要求1所述的薄膜晶体管，其特征在于，所述保护层的材质为有机物。
  4. 如权利要求1所述的薄膜晶体管，其特征在于，所述保护层的材质为金属。
  5. 如权利要求4所述的薄膜晶体管，其特征在于，所述保护层在垂直于所述栅极的方向上覆盖所述栅极与源极和漏极之间的间隙。
  6. 如权利要求1所述的薄膜晶体管，其特征在于，所述保护层的杨氏模量大于300N/m2。
  7. 如权利要求1～6中任一项所述的薄膜晶体管，其特征在于，还包括：上层保护膜、下层保护膜与阻挡层；
    所述上层保护膜设置于所述平坦化层之上，所述下层保护膜设置于所述柔性衬底之下，所述阻挡层设置于所述柔性衬底与栅极绝缘层之间。
  8. 一种制造如权利要求1～7中任一项所述的薄膜晶体管的方法，包括：在柔性衬底上依次形成有源区、栅极绝缘层、栅极、源极与漏极以及钝化层，其特征在于，在所述钝化层上形成保护层，在所述保护层上形成平坦化层；所述保护层位于所述有源区及所述栅极的正上方。
  9. 一种显示面板，其特征在于，包括如权利要求1～7中任一项所述的 薄膜晶体管。
  10. 一种显示装置，其特征在于，包括如权利要求9所述的显示面板。
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