WO2017140550A1 - Procédé de fabrication d'un support de circuit, support de circuit, procédé de fabrication d'un module à semi-conducteur et module à semi-conducteur - Google Patents

Procédé de fabrication d'un support de circuit, support de circuit, procédé de fabrication d'un module à semi-conducteur et module à semi-conducteur Download PDF

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Publication number
WO2017140550A1
WO2017140550A1 PCT/EP2017/052742 EP2017052742W WO2017140550A1 WO 2017140550 A1 WO2017140550 A1 WO 2017140550A1 EP 2017052742 W EP2017052742 W EP 2017052742W WO 2017140550 A1 WO2017140550 A1 WO 2017140550A1
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WIPO (PCT)
Prior art keywords
layer
copper
circuit carrier
alloy
semiconductor device
Prior art date
Application number
PCT/EP2017/052742
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German (de)
English (en)
Inventor
Ronald Eisele
Original Assignee
Heraeus Deutschland GmbH & Co. KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Heraeus Deutschland GmbH & Co. KG filed Critical Heraeus Deutschland GmbH & Co. KG
Priority to JP2018539831A priority Critical patent/JP2019510367A/ja
Priority to CN201780011455.5A priority patent/CN108701671A/zh
Priority to US15/999,684 priority patent/US20210210406A1/en
Priority to KR1020187022865A priority patent/KR20180103097A/ko
Publication of WO2017140550A1 publication Critical patent/WO2017140550A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/4882—Assembly of heatsink parts
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    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
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Definitions

  • the invention relates to a method for producing a circuit carrier, in particular a stamped grid or a printed conductor, for a
  • the invention relates to a circuit carrier, in particular a stamped grid or a printed conductor, for a semiconductor module. Moreover, the invention relates to a method for producing a
  • Semiconductor module comprising a circuit carrier and at least one semiconductor device, which is connected to the circuit carrier. Furthermore, the invention relates to a semiconductor module, comprising a circuit carrier and at least one semiconductor device, which is connected to the circuit carrier.
  • Power electronic power semiconductors usually consist of low-expansion materials and must be used for electrical contact and a
  • the circuit carrier is a conductor track, in particular a copper conductor track, which serves as a carrier for one or more power semiconductors.
  • Power semiconductors typically include silicon (Si) or silicon carbide (SiC). Silicon has a thermal strain of 2.6 ppm / K, whereas silicon carbide has a thermal strain of 3.7 ppm / K. These coefficients of expansion are significantly lower than the coefficients of expansion of typical circuit board materials.
  • circuit carriers which are in the form of a stamped grid or a printed conductor, are made of copper (Cu). Copper has an expansion coefficient of 17.8 ppm / K.
  • the power semiconductors In order to achieve a safe electrical and thermal contact, the power semiconductors with the help of tin (Sn) or lead (Pb) as a base solder on the Soldered circuit board.
  • tin (Sn) or lead (Pb) As a base solder on the Soldered circuit board.
  • Pb lead
  • the sintering of semiconductor devices on a circuit carrier is known. In all cases, however, the power semiconductor and the circuit carrier have a clear thermal-mechanical
  • Metals used There are, for example, copper-tungsten alloys (CuW) and copper-molybdenum alloys (CuMo). This results in thermal expansions between 8 ppm / K and 12 ppm / K.
  • CuW copper-tungsten alloys
  • CuMo copper-molybdenum alloys
  • CuW and CuMo alloys are technologically complex to produce and extremely expensive.
  • the alloy formation requires due to the high melting point difference between copper and the alloy components tungsten (W) and molybdenum (Mo) extremely extensive process steps to successful alloy.
  • the thermal conductivity of the pure copper is greatly reduced by the alloy formation. This constitutes one
  • this object is achieved with regard to the method for producing a circuit carrier, in particular a stamped grid or a conductor track for a semiconductor device by the subject of claim 1, with a view of the circuit substrate, in particular the lead frame or the conductor track, for a semiconductor device through the object of claim 6, in view of the method of manufacturing a semiconductor module, comprising
  • Circuit carrier and at least one semiconductor device, with the
  • the invention is based on the idea of specifying a method for producing a circuit carrier, in particular a stamped grid or a printed conductor, for a semiconductor module, wherein at least one first copper layer or a first copper alloy layer with a first expansion coefficient and at least one second layer made of a second, low-expansion Material with a second coefficient of expansion, smaller than the first
  • Coefficient of expansion is to be interconnected at a bond temperature of 150 ° C to 300 ° C. This is particularly preferably done
  • the circuit carrier to be produced for at least one semiconductor component can be formed as a stamped grid or as a conductor track.
  • the bonding material may produce a compound which withstands temperatures above the bonding temperature and preferably a diffusion metal, in particular silver (Ag) and / or a silver alloy and / or gold (Au) and / or a gold alloy and / or copper (Cu) and / or a copper alloy.
  • a diffusion metal in particular silver (Ag) and / or a silver alloy and / or gold (Au) and / or a gold alloy and / or copper (Cu) and / or a copper alloy.
  • the compound temperature may be 200 ° C.-280 ° C., in particular 220 ° C.-270 ° C., in particular 240 ° C.-260 ° C., in particular 250 ° C.
  • the connection temperature substantially corresponds to the mounting temperature in the connection of the manufactured circuit substrate with at least one semiconductor device.
  • the second, low-expansion material with the second coefficient of expansion of the at least second layer preferably has a nickel alloy,
  • Invar Fe 65 Ni 3 5
  • Invar 36 Fe 64 Ni 36
  • Kovar Fe 54 Ni 2 9Coi 7
  • tungsten W
  • FeNiCo iron-nickel-cobalt alloy
  • all metals which have a lower coefficient of expansion than copper or the copper alloy can be used as second materials.
  • Conductivity is physically linked to thermal conductivity. Therefore, all metals that have good thermal and / or electrical conductivity as well as low thermal expansion are well suited to be used as the second material or to be comprised by the second material.
  • Coefficient of expansion than copper are therefore suitable to serve as a second material or to be used as a second material.
  • the bonding of the at least first copper layer or the at least first copper alloy layer to the at least second layer and optionally the bonding layer can be effected by pressurization, in particular with a pressure of 5 MPa-30 MPa, in particular 10 MPa-28 MPa, in particular 25 MPa.
  • Copper alloy layer and the at least second layer and optionally the bonding layer is preferably carried out at temperatures of 150 ° C - 300 ° C. and at an applied pressure of 5 MPa - 30 MPa.
  • the low-temperature sintering is particularly preferably carried out at a temperature of 250 ° C. and a pressure of 25 MPa, the sintering preferably being carried out for 1 to 10 minutes, for example 4 minutes.
  • Circuit carrier corresponds substantially to the mounting temperature in the connection of the circuit substrate produced with at least one
  • connection temperature can be exactly the
  • Bonding temperature at most 20%, in particular at most 15%, in particular at most 10%, in particular at most 5%, of the
  • the percentage calculation of the deviation of the connection temperature from the installation temperature is based on a calculation of the difference between the connection temperature in Kelvin and the installation temperature in Kelvin.
  • the connecting material is preferably introduced as sintering material or component of the sintering material between the at least first copper layer or the at least first copper alloy layer and the at least second layer. Accordingly, a composition sinterable to a conductive layer can be used for producing a sintered bond between the layers to be bonded. The still sinterable
  • Composition may have the form of application of an ink, a paste or a sintered preform in the form of a layered compact.
  • Sinter preforms or so-called sinter preforms are formed by application and drying of metal pastes or metal sintering pastes. Such sinter preforms are still sinterable.
  • the bonding material is formed as a film, in particular as a metal foil, and this foil, in particular this metal foil, is arranged between the first copper layer or the first copper alloy layer and the second layer.
  • the sintering paste which comprises the bonding material or consists of the bonding material, by printing, in particular screen or stencil printing, on the first copper layer or first
  • Copper alloy layer and / or the second layer is applied.
  • the sintering paste is applied to a first copper layer, if present, or to a first copper alloy layer, if present, and / or to the second layer.
  • the sintering paste or the metal sintering paste can be dried before carrying out the actual sintering process. Without passing through the liquid state, the metal particles of the sintering paste combine during diffusion by diffusion to form a solid, electrical current and heat-conductive metallic compound between the at least first copper layer or the at least first layer
  • Copper alloy layer and the at least second layer are particularly preferred. It is particularly preferred to use a sintering paste which comprises silver and / or a silver alloy and / or silver carbonate and / or silver oxide when joining the layers. In a further embodiment of the invention, it is possible that on the at least first copper layer or on the at least first
  • Connecting layer one, for example by electroplating or sputtering
  • the second layer is a molybdenum layer or the second material of the second layer comprises molybdenum
  • a nickel-silver layer (NiAg layer) can be galvanically applied to the side of the second layer to be connected.
  • the bonding material in particular silver, adhere particularly well.
  • the invention is based in a sidelined aspect further on the idea of a circuit carrier, in particular a stamped grid or a
  • circuit carrier is preferably prepared by a method according to the invention mentioned above.
  • the circuit carrier according to the invention comprises:
  • the second material comprising a nickel alloy, in particular Invar (Fe 65 Ni 3 5) or Invar 36 (Fe 64 Ni 36 ) or Kovar (Fe 54 Ni 2 9Coi 7 ), and / or tungsten (W) and / or an iron-nickel-cobalt alloy (FeNiCo alloy), particularly preferably molybdenum (Mo).
  • a nickel alloy in particular Invar (Fe 65 Ni 3 5) or Invar 36 (Fe 64 Ni 36 ) or Kovar (Fe 54 Ni 2 9Coi 7 ), and / or tungsten (W) and / or an iron-nickel-cobalt alloy (FeNiCo alloy), particularly preferably molybdenum (Mo).
  • the second material comprises molybdenum (Mo) or the second material is molybdenum (Mo). It is also possible that the second material comprises a molybdenum alloy or is a molybdenum alloy.
  • At least one first connection layer may be formed, preferably diffusion metal, in particular silver (Ag) and / or a silver alloy and / or gold (Au) and / or a gold alloy and / or copper (Cu) and / or a copper alloy.
  • the at least first connection layer can be used as a boundary layer of the first
  • Copper layer or the first copper alloy layer and / or the second layer may be formed. It is possible that the tie layer is an independent visible layer. If the connecting material is only applied with a smaller layer thickness during the production of the circuit carrier according to the invention, the connecting layer in the product produced, namely in the
  • the produced circuit carrier be formed as a boundary layer of the first copper layer or the first copper alloy layer and / or the second layer.
  • the bonding material may, for example, be diffused into the first copper layer or the first copper alloy layer and / or the second layer at least in sections.
  • Boundary layer in the first copper layer or the first copper alloy layer and / or the second layer is partially diffused.
  • the circuit carrier has at least one second copper layer or a second copper alloy layer, which is preferably connected to the second layer of the second, low-expansion material by means of a second connecting layer made of one / the connecting material.
  • the circuit carrier may therefore comprise three layers which are interconnected by means of two interconnection layers.
  • the circuit carrier may comprise at least a fourth layer, which is formed from a / the second material.
  • the fourth layer is preferably by means of a third
  • the circuit carrier comprises four layers which are formed either from copper or a copper alloy or from a second material, wherein these four layers are interconnected by at least three tie layers.
  • the circuit carrier may comprise at least a third copper layer or a third copper alloy layer.
  • the third copper layer or third copper alloy layer may be connected to a copper layer or copper alloy layer. This connection can also be made by means of a connecting layer of one
  • Connecting material can be produced.
  • the circuit carrier may have a symmetrical arrangement of the individual layers and connection layer (s).
  • the symmetrical arrangement of the individual layers and bonding layer (s) is such
  • a symmetrical arrangement of the individual layers is to be understood in such a way that with a theoretical formation of an axis of symmetry by the circuit carrier, both above and below the symmetry axis, a symmetrical arrangement of the individual layers and connecting layer (s)
  • Symmetryeachse halves the arrangement of the individual layers with respect to the total thickness of the circuit substrate, wherein the total thickness of the
  • Circuit carrier is formed by the addition of the individual layer thicknesses.
  • the surface on which at least one semiconductor device is applied is completely flat. This prevents, for example, a bleeding of contacting material and thus a "slippage" of a semiconductor device connected to the circuit carrier by means of the contacting material.
  • the individual layers and bonding layer (s) are arranged asymmetrically.
  • the individual layers and connecting layer (s) are in particular such arranged asymmetrically that a convex or concave shaped circuit carrier is formed.
  • a convexly or concavely shaped circuit carrier can also be referred to as a circuit carrier with crowning or with a convex side.
  • the circuit carrier has a controlled convex or concave shape. In other words, the crowning maximum is defined.
  • the symmetry axis halves the total thickness of the arrangement of the individual layers, the total thickness being defined by the addition of the individual layer thicknesses of the circuit carrier.
  • the crown or the convex or concave shape of the circuit substrate is controlled by arranging and / or forming the second layer and / or the at least fourth layer of a / the second material, namely the low-expansion material.
  • the second layer and / or the at least fourth layer is or are formed asymmetrically in relation to the overall arrangement of all layers and connecting layer (s), so that an axis of symmetry is produced specifically from the elongation of the fabric produced
  • Circuit carrier produced by means of the aforementioned method according to the invention and connected to the yet-mentioned inventive method for producing a semiconductor module with at least one semiconductor device.
  • the copper alloy layer can be, for example, the first copper layer or first copper alloy layer or the second copper layer or second copper alloy layer.
  • the second layer of a second, low-expansion material is formed like a frame and / or lattice and / or wire. Preferably, this formation of the second layer and / or a fourth layer in combination with the embedding of the respective layer in a copper layer or a copper alloy layer.
  • the second layer of a second, low-expansion material has a smaller width or length than the copper layer or copper alloy layer arranged above and / or below it.
  • the second layer is formed like a lattice and / or a wire, shearing stresses can be absorbed in an improved manner between the second layer of a low-expansion material and a copper layer or copper alloy layer located above and / or below it.
  • Interspaces of the wires or of the grid may be connecting material, in particular solder or sintered material or conductive adhesive.
  • a copper layer or copper alloy layer formed below the second layer may be pressed into the interstices of the wires or the grid during the bonding of the layers.
  • the circuit carrier according to the invention carries according to the invention to a maximum heat dissipation of a connected to the circuit carrier
  • the invention is based in a sidelined aspect further on the idea of a method for manufacturing a semiconductor module comprising a circuit carrier and at least one semiconductor device, which is connected to the
  • Circuit carrier is connected to specify.
  • the circuit carrier is preferably a circuit carrier according to the invention mentioned above or a circuit carrier which has been produced by means of a method according to the invention mentioned above.
  • the inventive method for producing a semiconductor module based on the fact that the semiconductor device is connected by means of a bonding layer with the circuit substrate at a mounting temperature of 150 ° C - 300 ° C, wherein the mounting temperature substantially corresponds to the connection temperature in the connection of / layers of the circuit substrate ,
  • the mounting temperature can correspond exactly to the connection temperature.
  • the mounting temperature deviates at most 20%, in particular at most 15%, in particular at most 10%, in particular at most 5%, from the bonding temperature.
  • the percentage calculation of the deviation of the installation temperature from the connection temperature is based on a calculation of the difference between the installation temperature in Kelvin and the connection temperature in Kelvin.
  • the assembly temperature may be 200 ° C - 280 ° C, in particular 220 ° C - 270 ° C, in particular 240 ° C - 260 ° C, in particular 250 ° C.
  • the semiconductor device is preferably applied to the surface of the
  • Circuit substrate applied or connected to the surface of the circuit substrate wherein the surface is preferably formed of a copper layer or a copper alloy layer.
  • the surface can also be referred to as the top side of the circuit carrier.
  • the contacting layer may be, for example, a sintering paste. It is also possible that the contacting layer is an adhesive layer or a solder layer.
  • Circuit carrier done simultaneously.
  • all layers, connecting layer (s) and the semiconductor device to be connected are arranged one above the other and, for example, by means of a
  • the asymmetrical arrangement of layers and interconnect layer (s) is interconnected at a connection temperature that substantially corresponds to the mounting temperature of the semiconductor device to the circuit carrier. This is followed by the connection of the semiconductor component to the circuit carrier. This shows that the concave or convex deformation on reheating of the manufactured asymmetric circuit substrate is formed back and after the connection of the semiconductor device with the substrate plate in a new
  • the temperature-stable final shape can be a defined maximum crown. For example, a defined maximum crowning 100 ⁇ .
  • the thermally stable final shape may also be a completely planar semiconductor module.
  • the invention is further based on the idea of specifying a semiconductor module, wherein the semiconductor module is preferably produced by a method according to the invention mentioned above.
  • the semiconductor module comprises a circuit carrier and at least one semiconductor component, which is connected to the
  • Circuit carrier is connected.
  • the circuit carrier is preferably a circuit carrier according to the invention or a
  • Circuit carrier which is produced by means of a method according to the invention mentioned above.
  • the semiconductor device may be a diode or an IGBT
  • the semiconductor device is power semiconductor.
  • the second layer of the circuit carrier is according to a preferred
  • the area of the second layer is substantially smaller than the area of the at least one copper layer or the at least one copper alloy layer.
  • the area of the second layer is not less than 80% of the area of the semiconductor device.
  • "above” is to be understood as meaning a position of the semiconductor component in a vertical extension to the second layer, and a further layer may be present between the second layer and the semiconductor component.
  • the second layer has the same aspect ratio as the semiconductor device arranged above.
  • Copper alloy layer reduces strain mismatching in a concentrated and localized manner in the area of the low-expansion semiconductor device.
  • a portion is formed which has no second layer or, in other words, is free from the second layer.
  • This section contains only copper or a copper alloy.
  • z-thermal conductivity is the thermal conductivity, starting from the semiconductor device in the direction of the underlying layers of the circuit substrate to understand.
  • the semiconductor device may be formed congruent to the second layer.
  • the second layer may be embedded in a copper layer or a copper alloy layer, the second layer being frame-shaped and framing a copper layer section or a copper alloy layer section, wherein the semiconductor device is above the copper layer section or copper alloy layer section is trained.
  • "above” is to be understood as meaning a position of the semiconductor component in a vertical extension to the second layer, and a further layer may be present between the second layer and the semiconductor component.
  • Copper alloy layer section maximum 150% of the edge lengths of the
  • the width of the frame-like second layer is preferably 10% -100% of the shortest edge length of the semiconductor device.
  • the frame-like design of the second layer of low-stretch material causes a reduction in strain within the semiconductor module.
  • the copper layer section causes maximum z-thermal conductivity due to the copper material or copper alloy material.
  • the area size of the second layer which is preferably formed between at least two copper layers and / or copper alloy layers, to one for the distribution of the mechanical shear stress between the semiconductor device and the
  • Circuit board adapted shape limited. Often the shearing voltage between the semiconductor device and the circuit carrier along the
  • Shear stress distribution is essentially point symmetrical with respect to
  • a minimized area of the second layer of low-expansion material is consequently a surface which extends proportionately further in the diagonals of the semiconductor component than in the region of the coordinate axes of the semiconductor component
  • the second layer has a
  • Semiconductor device is larger than in the range of the coordinate axes of
  • the formed surface shape of the second layer resembles a four-leaf clover.
  • In the middle of the surface of the second layer can be a
  • Copper layer portion or a copper alloy layer portion formed which is embedded in the second layer improves the thermal conductivity by dispensing with low-stretch material and due to the use of copper or a copper alloy.
  • FIG. 1b circuit carrier according to FIG. 1a in the connected state
  • FIG. 2 shows a semiconductor module according to a first exemplary embodiment
  • FIG. 3 shows a semiconductor module according to a second embodiment
  • Fig. 4 shows a semiconductor module according to a third embodiment
  • Fig. 5 shows a semiconductor module according to a fourth embodiment
  • Fig. 6 shows a semiconductor module according to a fifth embodiment
  • Fig. 7 shows a semiconductor module according to a sixth exemplary embodiment.
  • Fig. la are the individual layers of a product to be produced
  • Circuit carrier 10 (see Fig. Lb) shown. Accordingly, the circuit carrier 10 to be produced comprises a first layer 20 of copper, a second layer 30 of a second material M2, and a second copper layer 25.
  • the material M2 is a low-stretch material with a second
  • the second material M2 may be a nickel alloy, in particular Invar (Fe 65 Ni 3 5) or Invar 36 (Fe 64 Ni 36 ) or Kovar (Fe 54 Ni 2 9Coi 7 ), and / or tungsten (W) and / or an iron-nickel-cobalt (FeNiCo) alloy.
  • the material M2 is molybdenum.
  • first bonding layer 40 made of a bonding material VM is formed between the first copper layer 20 and the second layer 30 .
  • a second bonding layer 40 made of a bonding material VM is formed between the second layer 30 and the second copper layer 25 .
  • the bonding material VM of the tie layers 40 and 41 provides a bond between the layers 20, 25 and 30 that withstands temperatures above a bonding temperature.
  • the bonding material VM of the tie layers 40 and 41 provides a bond between the layers 20, 25 and 30 that withstands temperatures above a bonding temperature.
  • the bonding layer is formed as a sintered layer, in particular as a sintering paste.
  • This sintering paste which preferably has one of the listed diffusion metals, can be applied, for example, by means of a printing process.
  • connection temperature for connecting the layers 20, 25 and 30 by means of the connecting layers 40 and 41 substantially corresponds to the mounting temperature in the connection of the manufactured circuit substrate 10 with an applied
  • the bonding of the first copper layer 20 to the second layer 30 and to the second copper layer 25 preferably takes place by means of pressurization, in particular with a pressure of 5 MPa-30 MPa, in particular of 25 MPa.
  • Fig. 1b the circuit carrier 10 produced can be seen.
  • the connection layers 40 and 41 can be seen. It is possible that the
  • Connecting layers 40 and 41 are formed as boundary layers of the first copper layer 20, the second copper layer 25 and the second layer 30.
  • the layer thicknesses d 1 of the first copper layer 20, d 2 of the second layer 30 and d 3 of the second one are
  • Circuit substrate 10 is a symmetrical structure of the individual layers 20, 25 and 30 and the connecting layers 40 and 41 acts.
  • Symmetry axis S halves the total thickness D of the circuit substrate 10.
  • the total thickness D is formed by adding the layer thicknesses d 1, d 2 and d 3 and the layer thicknesses of the connecting layers 40, 41.
  • Above and below the symmetry axis S shows a symmetrical structure of the circuit substrate 10th
  • the layer thickness d1 of the first copper layer 20 is 0.5 mm - 3.0 mm
  • the layer thickness d2 of the second layer 30 0, 1 mm - 1.0 mm
  • the layer thickness d3 of the second copper layer 25 0.5 mm - 3.0 mm.
  • Bonding layer are preferably 1 ⁇ - 50 ⁇ .
  • the semiconductor module 100 includes a semiconductor device 90 and a circuit carrier 10. In the
  • Semiconductor device 90 may be, for example, a diode or an IGBT or a MOSFET transistor.
  • the semiconductor component 90 is connected to the circuit carrier 10 by means of a contacting layer 50.
  • the contacting layer 50 may be, for example, a solder layer or an electrically conductive adhesive layer or a sintered layer.
  • the illustrated circuit carrier 10 consists of a first copper layer 20 and a second layer 30 of second material M2. At the second
  • Material M2 is molybdenum.
  • the first layer 20 is by means of a Connecting layer 40, which consists of bonding material VM, connected to the second layer 30.
  • the semiconductor component 90 is applied with the aid of the contacting layer 50 to the semiconductor component 90 facing side 15 of the circuit substrate 10.
  • Circuit carrier 10 is the first side 15 of the first
  • Copper layer 20 wherein the first side 15 of the copper layer 20 is formed facing away from the second layer 30.
  • the indicated symmetry axis S shows that in the embodiment according to FIG. 2 an asymmetrical arrangement of the layers 20, 30 and 40 is present.
  • the layer thickness d 1 of the first copper layer 20 is greater than the layer thickness d 2 of the second layer 30.
  • FIG. 3 a semiconductor module 100 according to a second exemplary embodiment is shown.
  • the circuit carrier 10 of FIG. 3 is the circuit carrier 10 illustrated in FIG. 1b, that is to say a circuit carrier 10 with a symmetrical arrangement. Also in this embodiment is
  • Semiconductor device 90 is applied by means of a contacting layer 50 on the first side 15 of the first copper layer 20.
  • Fig. 4 will be another embodiment with respect to a
  • the second layer 30 of second material M2 is embedded in the second copper layer 25.
  • Both the width b2 of the second layer 30 and the thickness d2 of the second layer 30 are less than the width b3 of the second copper layer 25 and the thickness d3 of the second
  • the semiconductor device 90 is mounted above the second layer 30 on the circuit carrier 10.
  • the width b2 of the second layer is slightly larger than the width bH L of the semiconductor device 90.
  • the circuit carrier 10 comprises a first copper layer 20, which is arranged in sections above the second copper layer 25 and above the second layer 30.
  • a bonding layer 40 of bonding material VM is formed between the first copper layer 20 and the second layer 30 of second material M2, a bonding layer 40 of bonding material VM. Since the layer thickness d2 of the second layer 30 is less than the layer thickness d3 of the second copper layer 25, the first connection layer 40 may be
  • the first copper layer 20 is a
  • a method according to the invention for producing the circuit carrier 10 or the semiconductor module 100 initially provides that the second layer 30 is connected to the first copper layer 20, for example by a low-temperature sintering method. Due to the asymmetrical structure of the circuit carrier 10, a deformation initially occurs upon cooling of the circuit carrier 10 to room temperature. Now, in a second operation, in particular by sintering, diffusion soldering or gluing, the semiconductor element 90 on the
  • Circuit board 10 mounted creates a mechanical stress compensation, which in turn leads to a flat conductor track.
  • This type of voltage balanced connection can also be used in one
  • the first copper layer 20, in particular the copper interconnect is positioned on the second layer 30, which is embedded in the second copper layer 25, and in turn the semiconductor chip 90. Between the first copper layer 20 and the second layer 30 of second material M2 is located the connection layer 40 and between the
  • both in the contacting layer 50 and in the first connection layer 40 is a silver sintered layer, so that all layers and the semiconductor device 90 can be connected together in a single process step.
  • FIG. 5 an embodiment of a semiconductor module 100 similar to that of FIG. 4 is shown. Also in this case, the second layer 30 is in embedded the second copper layer 25. Between the semiconductor device 90 and the second layer 30, the first copper layer 20 is formed. Furthermore, a third copper layer 26 is formed. The second copper layer 25 and the second layer 30 are connected to the third copper layer 26 by means of a second bonding layer 41 of bonding material VM.
  • the surface of the second layer 30 of low-stretch material such. As molybdenum, much smaller than the surfaces of the second
  • the reduction of the area of the second layer 30 is not less than 80% of the area of the
  • the surface of the second layer 30, as indicated by the width b2 of the second layer, is larger than the surface of the semiconductor device 90.
  • the surface of the second layer 30 preferably has the same aspect ratio as of the
  • Semiconductor device 90 The reduction of the area of the second layer 30 of low-expansion material relative to the surfaces of the second copper layer 25 and the third copper layer 26 reduces the expansion mismatch
  • the first copper layer 20 completely covers the second layer 30. In a pressing connection technique may be due to an applied
  • Assembly print a contour following first copper layer 20 are formed. It can be formed a plateau, which carries the semiconductor device 90.
  • Fig. 6 will be another semiconductor module 100 with another
  • the second layer 30 of the circuit substrate 10 is in this
  • Embodiment designed as a rectangular frame.
  • the trained as a rectangular frame second layer 30 of low-stretch material is embedded in the second copper layer 25.
  • the second layer 30 is connected to the first via a first bonding layer 40 of bonding material VM
  • Copper layer 20 connected. Also, the first copper layer 20 is formed as a rectangular frame.
  • the second layer 30 frames one
  • Copper layer portion 29 is formed. Maximum should be the edge lengths of the Copper layer portion 29 are 150% of the edge lengths of the semiconductor device 90.
  • the width b2 of the frame-like second layer 30 is at least 10% and at most 100% of the smallest edge length of the
  • the circuit carrier 10 further comprises a third copper layer 26.
  • This third copper layer 26 is connected to the second layer 30 and the second copper layer 25 by means of a second connection layer 41.
  • the frame-like design of the second layer 30 causes a
  • Semiconductor device 90 is applied by means of a contacting layer 50, causes a maximum z-thermal conductivity due to the copper material.
  • thermal conductivity the thermal conductivity is defined starting from the semiconductor component 90 in the direction of the third copper layer 26.
  • a pressing connection technology such. B. due to a sintering process, a contour-following copper layer can be formed due to the mounting pressure.
  • the covered with the first copper layer 20 second layer 30 forms a flat, lowered in the direction of the copper layer portion 29 plateau, the
  • Semiconductor device 90 carries.
  • the circuit carrier 10 of the semiconductor module 100 of FIG. 7 also has a first copper layer 20, a second copper layer 25, and a third one
  • the first copper layer 20 is square or rectangular
  • the first copper layer 20 is connected to the second layer 30 by means of a frame-like first connecting layer 40 made of bonding material VM.
  • the second copper layer 25 is in turn connected to a second connection layer 41 with the third copper layer 26.
  • low-stretch material M2 is limited in this embodiment to a distribution of the mechanical shear stress between the semiconductor device 90 and the circuit substrate 10 adapted shape.
  • the shear stress is particularly large between the semiconductor device 90 and the circuit carrier 10 along the diagonal (and beyond) of the semiconductor device 90.
  • the shear stress distribution is substantially point-symmetrical to the center M of the semiconductor device 90.
  • a minimal formation in this case with respect to the surface of the second layer 30 thus results in an area which extends somewhat beyond the diagonal of the semiconductor device 90.
  • the surface of the second layer 30 extends further beyond the diagonal than in the region of
  • a copper layer section 29 may be formed in the second layer 30 in the region of the center M of the semiconductor device 90.

Abstract

L'invention concerne un procédé de fabrication d'un support de circuit (10), en particulier d'une grille de connexion découpée ou d'une piste conductrice, pour un composant à semi-conducteur (90), procédé selon lequel au moins une première couche de cuivre (20) ou une première couche d'alliage de cuivre présentant un premier coefficient de dilatation et au moins une deuxième couche (30), constituée d'un deuxième matériau (M2) à faible dilatation présentant un deuxième coefficient de dilation qui est inférieur au premier coefficient de dilatation, sont reliées entre elles à une température comprise entre 150 °C et 300 °C, en particulier par un procédé de frittage basse température.
PCT/EP2017/052742 2016-02-19 2017-02-08 Procédé de fabrication d'un support de circuit, support de circuit, procédé de fabrication d'un module à semi-conducteur et module à semi-conducteur WO2017140550A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2018539831A JP2019510367A (ja) 2016-02-19 2017-02-08 回路キャリアの製造方法、回路キャリア、半導体モジュールの製造方法、及び半導体モジュール
CN201780011455.5A CN108701671A (zh) 2016-02-19 2017-02-08 制造电路载体的方法、电路载体、制造半导体模块的方法和半导体模块
US15/999,684 US20210210406A1 (en) 2016-02-19 2017-02-08 Method for producing a circuit carrier, circuit carrier, method for producing a semiconductor module and semiconductor module
KR1020187022865A KR20180103097A (ko) 2016-02-19 2017-02-08 회로 캐리어를 제조하는 방법, 회로 캐리어, 반도체 모듈을 제조하는 방법, 및 반도체 모듈

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP16156491.9A EP3208845B1 (fr) 2016-02-19 2016-02-19 Procede de fabrication d'un porte-circuit, porte-circuit, procede de fabrication d'un module semi-conducteur et module semi-conducteur
EP16156491.9 2016-02-19

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WO2017140550A1 true WO2017140550A1 (fr) 2017-08-24

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CN111989771A (zh) * 2018-02-19 2020-11-24 迪德鲁科技(Bvi)有限公司 制造玻璃框架扇出型封装的系统和方法
CN116562101B (zh) * 2023-05-27 2023-10-20 苏州工业园区明源金属股份有限公司 压接型igbt应力平衡时变可靠性优化模型设计方法及装置

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JP2011003800A (ja) * 2009-06-19 2011-01-06 Hitachi Cable Ltd 低熱膨張複合放熱板及びその製造方法
JP2011071301A (ja) * 2009-09-25 2011-04-07 Honda Motor Co Ltd 金属ナノ粒子を用いた接合方法及び接合体
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JP2019510367A (ja) 2019-04-11
TWI657514B (zh) 2019-04-21
US20210210406A1 (en) 2021-07-08
TW201740474A (zh) 2017-11-16
EP3208845B1 (fr) 2019-12-04
CN108701671A (zh) 2018-10-23
KR20180103097A (ko) 2018-09-18

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