WO2017126210A1 - Dispositif et programme d'inspection de substrat - Google Patents

Dispositif et programme d'inspection de substrat Download PDF

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Publication number
WO2017126210A1
WO2017126210A1 PCT/JP2016/084187 JP2016084187W WO2017126210A1 WO 2017126210 A1 WO2017126210 A1 WO 2017126210A1 JP 2016084187 W JP2016084187 W JP 2016084187W WO 2017126210 A1 WO2017126210 A1 WO 2017126210A1
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WO
WIPO (PCT)
Prior art keywords
inspection
dut
semiconductor device
circuit
electrical characteristics
Prior art date
Application number
PCT/JP2016/084187
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English (en)
Japanese (ja)
Inventor
淳夫 三井
伸 内田
美世子 黒田
Original Assignee
東京エレクトロン株式会社
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Filing date
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Application filed by 東京エレクトロン株式会社 filed Critical 東京エレクトロン株式会社
Publication of WO2017126210A1 publication Critical patent/WO2017126210A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the present invention relates to a substrate inspection apparatus and program for inspecting a semiconductor device formed on a substrate without cutting out from the substrate.
  • a prober is known as a substrate inspection apparatus for inspecting electrical characteristics of a semiconductor device such as a power device or a memory formed on a semiconductor wafer (hereinafter simply referred to as “wafer”) as a substrate.
  • the prober includes a probe card having a large number of pin-shaped probes and a stage on which a wafer is placed and moves freely up and down, left and right, and each probe of the probe card contacts the electrode pads and solder bumps of the semiconductor device.
  • the electrical characteristics of the semiconductor device are inspected (for example, see Patent Document 1).
  • the IC tester connected to the prober determines the electrical characteristics and function of the semiconductor device.
  • the user creates a program for executing power supply control of the semiconductor device and measurement of the electrical characteristics performed by the IC tester, but the program for controlling the IC tester itself is Created by a prober manufacturer.
  • the circuit configuration of the IC tester is different from the circuit configuration in which the manufactured semiconductor device is mounted, for example, the circuit configuration of the mother board or the function expansion card, the IC tester is electrically connected with the semiconductor device mounted.
  • the IC tester is electrically connected with the semiconductor device mounted.
  • a prober that performs a wafer level system level test uses a plurality of types of inspection circuits corresponding to each function expansion card to electrically Inspect the characteristics.
  • a program for controlling each inspection circuit is created by the vendor. Therefore, it is necessary to request the vendor to create a program every time the user replaces the inspection circuit, and there is a problem that convenience for the user is lowered.
  • An object of the present invention is to provide a board inspection apparatus and a program that can prevent user convenience from being lowered.
  • a substrate inspection apparatus comprising a probe card having a probe that contacts each electrode of a semiconductor device formed on a substrate, wherein a circuit on which the semiconductor device is mounted is provided.
  • a simulated pseudo circuit a storage unit for at least temporarily storing a program for performing an electrical property test of the semiconductor device using the pseudo circuit, and an electrical property test of the semiconductor device according to the program
  • a control unit that executes a program, the program includes a user-created module created by a user, and the user-created module controls the pseudo circuit when executing an inspection of electrical characteristics of the semiconductor device.
  • a probe card having a probe that contacts each electrode of a semiconductor device formed on a substrate, and a pseudo circuit simulating a circuit on which the semiconductor device is mounted are provided.
  • a program for executing an inspection of electrical characteristics of the semiconductor device using the pseudo circuit, the user creating module created by a user, wherein the user creating module is the semiconductor device There is provided a program for controlling the pseudo-circuit in executing the electrical characteristic inspection.
  • a program for performing an inspection of electrical characteristics of a semiconductor device using a pseudo circuit imitating a circuit on which the semiconductor device is mounted has a user-created module created by a user, The module controls the pseudo-circuit when performing an inspection of the electrical characteristics of the semiconductor device. That is, a user can create a program module for controlling the pseudo circuit.
  • a program module for controlling the pseudo circuit it is possible to eliminate the need to request the vendor to create a program for controlling the pseudo circuit after replacement, which is required in accordance with the replacement of the pseudo circuit, thereby reducing user convenience. Can be prevented.
  • FIG. 2 It is a perspective view for demonstrating roughly the structure of the prober as a board
  • FIG. 1 is a perspective view for schematically explaining a configuration of a prober as a substrate inspection apparatus according to the present embodiment
  • FIG. 2 is a front view thereof.
  • FIG. 2 is partially drawn as a cross-sectional view and shows components incorporated in a main body 12, a loader 13 and a test box 14 to be described later.
  • the prober 10 includes a main body 12 containing a stage 11 on which a wafer W is placed, a loader 13 arranged adjacent to the main body 12, and a test arranged so as to cover the main body 12.
  • the electrical characteristics of a semiconductor device (DUT (Device Under Test)) formed on the wafer W are inspected.
  • the main body 12 has a hollow casing shape, and in addition to the stage 11 described above, a probe card 15 is disposed so as to face the stage 11, and the probe card 15 faces the wafer W.
  • a large number of needle-like probes 16 are arranged corresponding to the electrode pads and solder bumps of the DUT of the wafer W.
  • the wafer W is fixed to the stage 11 so that the relative position with respect to the stage 11 does not shift, and the stage 11 is movable in the horizontal direction and the vertical direction.
  • a pad or solder bump is brought into contact with each probe 16.
  • the test box 14 is electrically connected to the probe card 15 via the flexible wiring 17 when covering the main body 12.
  • the loader 13 takes out the wafer W on which the DUT is formed from a FOUP (not shown) as a transfer container and places the wafer W on the stage 11 inside the main body 12. Is removed from the stage 11 and accommodated in the FOUP.
  • the probe card 15 has a circuit configuration on which a DUT cut out from the wafer W and productized is mounted, for example, a card side inspection circuit 18 (pseudo circuit) that reproduces the circuit configuration of the DRAM. 18 is connected to each probe 16.
  • each probe 16 of the probe card 15 includes a power pin 16a and a signal pin 16b.
  • the power pin 16a Power is supplied to the power supply of the DUT, and the signal pin 16 b transmits a signal from the DUT to the card side inspection circuit 18.
  • the test box 14 includes an inspection control unit and a recording unit (both not shown), a circuit configuration in which the DRAM is mounted, for example, a box side inspection circuit 19 (pseudo circuit) that reproduces a part of the circuit configuration of the motherboard, And a board 21 on which a hard disk 20 made of SSD (Solid State Drive) or the like is mounted.
  • the wiring 17 transmits an electrical signal from the card side inspection circuit 18 of the probe card 15 to the box side inspection circuit 19.
  • the loader 13 incorporates a controller (control unit), a memory (storage unit) composed of ROM and RAM, and a base unit 22 composed of a simple measurement module (none of which is shown).
  • the base unit 22 is connected to the box-side inspection circuit 19 by wiring 23, and the controller at least temporarily stores a program for executing an inspection of the electrical characteristics of the DUT (hereinafter simply referred to as “inspection program”). ), For example, the card side inspection circuit 18 and the box side inspection circuit 19 are instructed to start inspection of the electrical characteristics of the DUT.
  • the DUT may be mounted on a plurality of types of DRAMs, and each DRAM may be mounted on a plurality of types of motherboards.
  • the prober 10 can reproduce the circuit configuration of a plurality of types of DRAMs by replacing the card side inspection circuit 18 of the probe card 15, and further, the box side inspection circuit 19 included in the test box 14. It is possible to reproduce the circuit configuration of multiple types of motherboards by replacing
  • the card side inspection circuit 18 is hereinafter referred to as a load board 18, and the box side inspection circuit 19 is referred to as a system level test circuit 19.
  • the box side inspection circuit 19 reproduces a part of the circuit configuration of each motherboard, while the base unit 22 reproduces a circuit configuration common to each motherboard. That is, the box side inspection circuit 19 and the base unit 22 cooperate to reproduce the entire circuit configuration for each motherboard.
  • the system level test circuit 19 transmits data to the load board 18 when performing the inspection of the electrical characteristics of the DUT. Further, the base unit 22 (the controller thereof) determines whether or not the transmitted data has been correctly processed by the load board 18 connected to the DUT via each probe 16 based on the electrical signal from the load board 18. . In the prober 10, the load board 18 connected to the DUT among the load board 18, the system level test circuit 19, and the base unit 22 is physically disposed closest to the DUT.
  • the influence of the length of the wiring between the DUT and the load board 18, for example, the influence of the change in the wiring capacity, can be suppressed as much as possible at the time of checking the electrical characteristics, and the computer as a real machine having a DRAM and a motherboard
  • the electrical characteristics of the DUT can be inspected in a wiring environment very close to the wiring environment in
  • FIG. 4 is a diagram showing the module configuration of the inspection program.
  • four DUTs are formed on the wafer W, and four system level test circuits 19 corresponding to the four DUTs are prepared in the prober 10 by the user. It is assumed that the inspection of the electrical characteristics of the DUT is performed.
  • an inspection program 24 includes a main program module 25 that controls the inspection program 24 as a whole, a multi-control module 26 that integrally controls four DUTs and four system level test circuits 19, and four A hardware control module 27 that individually controls the DUT and the four system level test circuits 19, and an interface module 28 (user-created module) that functions as an interface for linking the multi-control module 26 and the hardware control module 27.
  • the main program module 25 generally defines the power supply control of each DUT and each system level test circuit 19 and the start of measurement of the electrical characteristics of each DUT.
  • the multi-control module 26 receives various commands from the main program module 25 and regulates the power supply control of each DUT and each system level test circuit 19 and the start of measurement of the electrical characteristics of each DUT.
  • the hardware control module 27 defines specific processing in power control of individual DUTs and individual system level test circuits 19 and specific processing in measurement of electrical characteristics of individual DUTs. For example, in the hardware control module 27, unique judgment criteria in the measurement of the electrical characteristics of the DUT using the replaced system level test circuit 19 are defined, for example, a threshold value or the like.
  • the interface module 28 executes power control of which DUT or which system level test circuit 19 is executed, starts measurement of which DUT's electrical characteristics, and further determines which DUT is measured for electrical characteristics. Stipulate whether or not to be excluded.
  • the user arbitrarily creates the interface module 28 using various commands to be described later. Further, the user arbitrarily creates the main program module 25 and the hardware control module 27 according to the change of the DUT or the replacement of the system level test circuit 19. That is, in the prober 10, the user arbitrarily creates the main program module 25, the hardware control module 27, and the interface module 28, whereby the power supply of each DUT and each system level test circuit 19 and the electrical power of each DUT The measurement of characteristics can be arbitrarily controlled.
  • the vendor creates the multi-control module 26.
  • FIG. 5 is a flowchart showing the measurement process of the electrical characteristics of the DUT executed by the multi-control module 26 and the like in FIG.
  • a count value N indicating the DUT turn number is set to 1 (step S51), and it is determined whether or not the DUT having the count value N is an object for measuring electrical characteristics (step S52).
  • the user uses an individual measurement start command, which will be described later, in the interface module 28 to predefine whether or not the DUT having the count value N is an electrical characteristic measurement target.
  • step S52 determines whether the DUT having the count value N is an object for measuring electrical characteristics. If it is an object of measurement of electrical characteristics, the interface module 28 is called (step S53). In the present embodiment, the interface module 28 describes specific processing in the measurement of the electrical characteristics of the DUT having the count value N. Also, the measurement of the electrical characteristics of the DUT is performed independently (single processing), or the measurement of the electrical characteristics of the DUT is performed together with the measurement of the electrical characteristics of other DUTs (collective processing). Whether to do so is defined by the interface module 28 and the hardware control module 27.
  • the interface module 28 determines whether to execute single processing or batch processing according to the hardware control module 27 (step S54), and then executes the single processing or batch processing.
  • the multi-control module 26 issues an individual measurement start command indicating that the measurement of the electrical characteristics of each DUT is started to the hardware control module 27 according to the interface module 28 when single processing or batch processing is executed.
  • the data is transmitted to the hardware control module 27 individually or collectively.
  • step S55 1 is added to the count value N (step S55), and whether or not the added count value N has reached the maximum N (4 in the present embodiment), which is the number of DUTs formed on the wafer W. Is determined by the multi-control module 26 (step S56). As a result of the determination in step S56, if the added count value N has not reached the maximum N, the process returns to step S52, and if it has reached the maximum N, this process is terminated. Thereby, in the present embodiment, the measurement of electrical characteristics is executed individually or collectively for all the DUTs formed on the wafer W.
  • the multi-control module 26 when the multi-control module 26 receives an overall power control command from the main program module 25, the DUT and the system level test circuit are related to each DUT and each system level test circuit 19 in accordance with the interface module 28. An individual power control command indicating that only 19 power sources are to be turned on or off is transmitted to the hardware control module 27.
  • the multi-control module 26 may collectively transmit individual power control commands for all DUTs and all system level test circuits 19 to the hardware control module 27 in accordance with the interface module 28.
  • the multi-control module 26 receives an overall exclusion command from the main program module 25, according to the interface module 28, for the specific DUT, the individual exclusion that excludes the DUT from the measurement target of the electrical characteristics The command is transmitted to the hardware control module 27. Note that the multi-control module 26 may collectively transmit the individual exclusion command to the hardware control module 27 for all the DUTs according to the interface module 28.
  • FIG. 6 is a block diagram schematically showing the configuration of the platform in the prober of FIG.
  • the prober 10 includes a wafer level system level test platform 29, a system level test power supply module 30, and a user custom module 31.
  • the wafer level system level test platform 29 includes a tester controller 32 that is a main control unit for measuring the electrical characteristics of the DUT, a DIO (Data Input Output) module 33, and a control board 34.
  • the user custom module 31 includes a load board 18, a system level test (SLT) circuit 19, and a power controller 35.
  • the user custom module 31 has three system level test circuits 19, and three DUTs 36 are electrically connected to the load board 18 via the probes 16, and each DUT 36 is connected to the load board 18. It is controlled by the arranged DUT controller 37.
  • each system level test circuit 19 and load board 18 in the user custom module 31 can be replaced by the user.
  • the tester controller 32 controls the DIO module 33 and the control board 34. Specifically, the tester controller 32 controls the power controller 35 via the control board 34 and supplies power to each system level test circuit 19 and each DUT 36. Further, the tester controller 32 controls the power supply of each DUT 36 via the DIO module 33 and further the DUT controller 37. In particular, when measurement of electrical characteristics of a certain DUT 36 is interrupted due to overcurrent or the like, the tester controller 32 controls the power controller 35 to supply power to the DUT 36 and the system level test circuit 19 corresponding to the DUT 36. Stop. Note that the DUT controller 37 stops the control of the DUT 36 in which the measurement of the electrical characteristics is interrupted.
  • the tester controller 32 when measuring the electrical characteristics of each DUT 36, controls each system level test circuit 19 and measures the electrical characteristics of each DUT 36 corresponding to each system level test circuit 19. Execute. At this time, the tester controller 32 transmits various commands to each system level test circuit 19, and further, information from each system level test circuit 19, for example, measurement results of electrical characteristics (for example, measurement interruption or measurement Information on success). In particular, when the measurement of the electrical characteristics of a certain DUT 36 is interrupted, the tester controller 32 stops communication between the DUT 36 and the corresponding system level test circuit 19.
  • the DUT 36 may be mounted on a plurality of types of DRAMs, and further, each prober may be mounted on a plurality of types of motherboards.
  • the board 18 and the system level test circuit 19 are configured to be replaceable. Before and after the replacement of the load board 18 and the system level test circuit 19, for example, the number of power supplies of the system level test circuit 19 may be changed, and the inherent judgment criteria in the measurement of the electrical characteristics of the DUT 36 may be changed. . Further, the number of DUTs 36 formed on the wafer W, that is, the number of DUTs 36 connected to the load board 18 may be changed.
  • the hardware control module 27 that controls the DUT 36 and the interface module 28 that functions as an interface of the hardware control module 27 are configured to be generated by the user.
  • various instructions for controlling each DUT 36 and each system level test circuit 19 of the load board 18 are provided.
  • the various commands correspond to the individual setting command for individually specifying the DUT 36 that is the target of power control and measurement of electrical characteristics, the individual measurement start command, the individual power control command, and the individual exclusion command described above.
  • the user generates the interface module 28 using these various instructions.
  • the user uses the individual setting command in the interface module 28 to set the DUT 36 that performs power control.
  • the tester controller 32 accesses the power controller 35 via the control board 34 and the DIO module 33 according to the individual setting command, and sets the DUT 36 that performs power supply control.
  • the user uses the individual power control command in the interface module 28 to specify the DUT 36 or the system level test circuit 19 for turning on or off the power.
  • the tester controller 32 accesses the power controller 35 via the control board 34 and the DIO module 33 in accordance with the individual power control command, and controls the power on / off of the designated DUT 36 and system level test circuit 19.
  • the user uses the individual measurement start command in the interface module 28 to specify the DUT 36 that performs the measurement of the electrical characteristics and the system level test circuit 19 corresponding to the DUT 36.
  • the tester controller 32 accesses the designated system level test circuit 19 or the load board 18 via the control board 34 or the DIO module 33 in accordance with the individual measurement start command, and designates it using the designated system level test circuit 19.
  • the measurement of the electrical characteristics of the DUT 36 is performed, and the measurement result is obtained.
  • the main program module 25 is also configured to be generated by the user.
  • the user generates the main program module 25 using the overall setting command for setting each DUT 36 to be measured, and the above-described overall power control command, overall measurement start command, and overall measurement exclusion command.
  • the user does not generate the main program module 25, the hardware control module 27, and the interface module 28 described above with the device owned by the user, for example, a PC.
  • the inspection program 24 for executing the inspection of the electrical characteristics of the DUT 36 using the system level test circuit 19 has the interface module 28 created by the user.
  • the interface module 28 is the DUT 36.
  • the system level test circuit 19 is controlled when the electrical characteristic test is executed. That is, a user can create a program (interface module 28) for controlling the system level test circuit 19.
  • a user can create a program (interface module 28) for controlling the system level test circuit 19.
  • various instructions provided for creating the interface module 28 include not only the individual power supply control instruction and the individual measurement start instruction but also the individual setting instruction and the individual exclusion instruction. Even if the DUTs 36 are formed, execution and non-execution of inspection of each DUT 36 can be controlled by one inspection program 24. That is, the inspection of the electrical characteristics of the plurality of DUTs 36 can be realized only by executing one inspection program 24, and the efficiency of the inspection can be improved.
  • the interface between the multi-control module 26 and the hardware control module 27 is realized by the interface module 28 which is a program, but the interface may be realized by a hardware circuit.
  • the hardware circuit is configured to be replaceable in accordance with replacement of the system level test circuit 19.
  • the system level test circuit 19 and the base unit 22 reproduce the circuit configuration of the motherboard, and the load board 18 reproduces the circuit configuration of the DRAM.
  • the circuit configuration reproduced by the system level test circuit 19 and the base unit 22 is the motherboard.
  • the circuit configuration reproduced by the load board 18 is not limited to the DRAM circuit configuration. That is, the circuit configuration reproduced by the load board 18, the system level test circuit 19, and the base unit 22 may be a circuit configuration in which the DUT 36 is mounted.
  • the configuration of the DUT 36 is not particularly limited.
  • the DUT 36 may be an MPU (Main Processing Unit) and is at the system level.
  • the semiconductor device may be an APU (Accelerated Processing Unit) or a GPU (Graphics Processing Unit), and the load board 18.
  • the semiconductor device may be an RF tuner.
  • Another object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the above-described embodiments to the base unit 22, and the CPU of the controller of the base unit 22 is stored in the storage medium. It is also achieved by reading and executing the program code.
  • the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the program code and the storage medium storing the program code constitute the present invention.
  • Examples of the storage medium for supplying the program code include RAM, NV-RAM, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD (DVD). -ROM, DVD-RAM, DVD-RW, DVD + RW) and other optical disks, magnetic tapes, non-volatile memory cards, and other ROMs that can store the program code.
  • the program code may be supplied to the base unit 22 by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.
  • the function expansion board or function is read based on the instruction of the program code. This includes the case where the CPU or the like provided in the expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.
  • the form of the program code may be in the form of object code, program code executed by an interpreter, script data supplied to the OS, and the like.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un dispositif d'inspection de substrat apte à empêcher la détérioration de la commodité pour l'utilisateur. Un programme d'inspection (24) servant à exécuter, au moyen d'un circuit de test de niveau de système (19), une inspection des caractéristiques électriques d'un dispositif à l'essai (DUT) (36) comprend un module d'interface (28) créé par un utilisateur, et le module d'interface (28) contrôle le circuit de test de niveau de système (19) au moment de l'exécution de l'inspection des caractéristiques électriques du DUT (36).
PCT/JP2016/084187 2016-01-22 2016-11-11 Dispositif et programme d'inspection de substrat WO2017126210A1 (fr)

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JP2016010943A JP2017129544A (ja) 2016-01-22 2016-01-22 基板検査装置及びプログラム
JP2016-010943 2016-01-22

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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
JP7337503B2 (ja) * 2019-01-15 2023-09-04 株式会社アドバンテスト 試験装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11265299A (ja) * 1998-03-16 1999-09-28 Mitsubishi Electric Corp 論理検証装置
JP2001210685A (ja) * 1999-11-19 2001-08-03 Hitachi Ltd テストシステムおよび半導体集積回路装置の製造方法
JP2002544489A (ja) * 1999-05-10 2002-12-24 テラダイン・インコーポレーテッド 伝送路損失補償を備えたドライバ
JP2006162285A (ja) * 2004-12-02 2006-06-22 Innotech Corp 半導体集積回路のテスト装置および方法
JP2007149031A (ja) * 2005-11-30 2007-06-14 Fujitsu Ltd 回路評価方法、回路評価装置
JP2007534943A (ja) * 2004-04-21 2007-11-29 フォームファクター， インコーポレイテッド インテリジェントなプローブカードのアーキテクチャ
US7906982B1 (en) * 2006-02-28 2011-03-15 Cypress Semiconductor Corporation Interface apparatus and methods of testing integrated circuits using the same
WO2014133653A1 (fr) * 2013-02-28 2014-09-04 Advantest Corporation Appareil d'essai avec accélération pour la construction de paquets dans un bloc fpga

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11265299A (ja) * 1998-03-16 1999-09-28 Mitsubishi Electric Corp 論理検証装置
JP2002544489A (ja) * 1999-05-10 2002-12-24 テラダイン・インコーポレーテッド 伝送路損失補償を備えたドライバ
JP2001210685A (ja) * 1999-11-19 2001-08-03 Hitachi Ltd テストシステムおよび半導体集積回路装置の製造方法
JP2007534943A (ja) * 2004-04-21 2007-11-29 フォームファクター， インコーポレイテッド インテリジェントなプローブカードのアーキテクチャ
JP2006162285A (ja) * 2004-12-02 2006-06-22 Innotech Corp 半導体集積回路のテスト装置および方法
JP2007149031A (ja) * 2005-11-30 2007-06-14 Fujitsu Ltd 回路評価方法、回路評価装置
US7906982B1 (en) * 2006-02-28 2011-03-15 Cypress Semiconductor Corporation Interface apparatus and methods of testing integrated circuits using the same
WO2014133653A1 (fr) * 2013-02-28 2014-09-04 Advantest Corporation Appareil d'essai avec accélération pour la construction de paquets dans un bloc fpga

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JP2017129544A (ja) 2017-07-27

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