WO2017124594A1 - 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法 - Google Patents

薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法 Download PDF

Info

Publication number
WO2017124594A1
WO2017124594A1 PCT/CN2016/074066 CN2016074066W WO2017124594A1 WO 2017124594 A1 WO2017124594 A1 WO 2017124594A1 CN 2016074066 W CN2016074066 W CN 2016074066W WO 2017124594 A1 WO2017124594 A1 WO 2017124594A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
drain
source
hole
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/074066
Other languages
English (en)
French (fr)
Inventor
姚江波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/033,624 priority Critical patent/US10115748B2/en
Publication of WO2017124594A1 publication Critical patent/WO2017124594A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/875—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being semiconductor metal oxide, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention claims the priority of the prior art application entitled “Semiconductor Array Array Substrate and Thin Film Transistor Array Substrate Preparation Method", which is filed on Jan. 22, 2016, the priority of which is incorporated herein by reference. Into this text.
  • the present invention relates to the field of liquid crystal display, and in particular to a method for fabricating a thin film transistor array substrate and a thin film transistor array substrate.
  • a thin film transistor array In the field of liquid crystal display, a thin film transistor array (Thin Film Transistor Array) includes a plurality of thin film transistors (TFTs) distributed in an array.
  • TFTs thin film transistors
  • a thin film transistor is generally used as a switching element to control the operation of a pixel electrode, or as a driving element to drive a pixel.
  • the active layer of the thin film transistor in the thin film transistor array substrate is usually covered with an etch protection layer for the purpose of protecting the active layer from damage during source and gate etching, in the thin film transistor of this structure. It is often desirable to pattern the etch stop layer to add a mask process to pattern the etch stop layer, thereby increasing the fabrication time of the thin film transistor array substrate.
  • the present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising:
  • the substrate including opposite first and second surfaces;
  • An active layer disposed on a surface of the first insulating layer away from the substrate;
  • the source and the drain are respectively disposed on the first insulating layer and respectively disposed at opposite ends of the active layer, and the source and the drain Contacting the end faces of the active layer, respectively;
  • a second insulating layer covering the active layer, the source, and the drain, a through hole for exposing the source or the drain is disposed on the second insulating layer;
  • a pixel electrode disposed on the second insulating layer and connected to the source or the drain through the through hole.
  • the thin film transistor array substrate further includes:
  • a first through hole and a second through hole are defined in the second insulating layer, the first through hole is disposed corresponding to the source, the second through hole is disposed corresponding to the drain, and the pixel electrode passes The second through hole is connected to the drain;
  • the thin film transistor array substrate further includes a first electrode, and the first electrode is connected to the source through the first through hole.
  • the first electrode and the pixel electrode are prepared in the same process.
  • the active layer comprises a metal oxide semiconductor
  • the source and drain electrodes comprise an ion-implanted metal oxide semiconductor
  • the active layer includes one or any combination of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, or zinc oxide.
  • the invention also provides a method for preparing a thin film transistor array substrate, and the method for preparing the thin film transistor array substrate comprises:
  • the substrate comprising opposite first and second surfaces
  • Ion implantation is performed on both end regions of the metal oxide semiconductor layer, and both ends of the metal oxide semiconductor layer subjected to ion implantation are a source and a drain, respectively, and a region of the metal oxide semiconductor layer not subjected to ion implantation is Active layer
  • the step of “opening a through hole for exposing the source or the drain on the second insulating layer” includes:
  • a first through hole and a second through hole are defined in the second insulating layer, the first through hole is disposed corresponding to the source, and the second through hole is disposed corresponding to the drain;
  • the step of “forming a pixel electrode, the pixel electrode being disposed on the second insulating layer and connected to the source or the drain through the through hole” includes:
  • the pixel electrode is disposed on the second insulating layer, and the pixel electrode is connected to the drain through the second through hole;
  • the method for preparing the thin film transistor array substrate further includes:
  • Forming a first electrode Forming a first electrode, the first electrode being connected to the source through the first through hole.
  • the step "implants the two end regions of the metal oxide semiconductor layer, and the two ends of the metal oxide semiconductor layer subjected to ion implantation are source and drain, respectively, and the metal is not ion-implanted.
  • Forming an active layer in a region of the semiconductor layer includes:
  • the metal oxide semiconductor layer is ion-implanted by using the patterned first photoresist layer as a mask, and the two ends of the ion-implanted metal oxide semiconductor layer are the source and the drain, respectively a region of the metal oxide semiconductor that has not been ion-implanted is an active layer;
  • the first photoresist layer is stripped.
  • the second photoresist layer is stripped.
  • the transparent conductive layer is the pixel electrode.
  • the method for fabricating a thin film transistor array substrate of the present invention forms a metal oxide semiconductor layer on a first insulating layer (gate insulating layer), and ion-implants both end regions of the metal oxide semiconductor layer.
  • a source and a drain are respectively formed at both end regions of the ion-implanted metal oxide semiconductor layer, and a region of the metal oxide semiconductor layer not subjected to ion implantation is an active layer. It can be seen that the formation of the source and the drain and the formation of the active layer can be prepared in the same process without additionally increasing the barrier patterning of the source and the drain during preparation. The process, thereby saving the preparation time of the thin film transistor array substrate.
  • FIG. 1 is a cross-sectional structural view of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a flow chart of a method of fabricating a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • 3 to 17 are schematic structural views corresponding to respective processes of a method of fabricating a thin film transistor array substrate.
  • FIG. 1 is a cross-sectional structural diagram of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • the thin film transistor array substrate 100 includes a substrate 110, a gate 120, and a first The edge layer 130, the active layer 140, the source 150, the drain 160, the second insulating layer 170, and the pixel electrode 190.
  • the substrate 110 includes a first surface 110a and a second surface 110b disposed opposite to each other.
  • the gate 120 is disposed on the first surface 110a, and the first insulating layer 130 covers the gate 120.
  • the active layer 140 is disposed on a surface of the first insulating layer 130 away from the substrate 110.
  • the source 150 and the drain 160 are respectively disposed on the first insulating layer 130 and respectively disposed at opposite ends of the active layer 140, and the source 150 and the drain 160 are respectively disposed. Contact with the end faces of the active layer 140, respectively.
  • the source 150 and the drain 160 are in the same layer as the active layer 140.
  • the second insulating layer 170 covers the active layer 140, the source 150, and the drain 160.
  • the second insulating layer 170 is disposed on the second insulating layer 170 for exposing the source 150 or the drain 160.
  • the pixel electrode 190 is disposed on the second insulating layer 170 and connected to the source 150 or the drain 160 through the through hole.
  • the first through hole 171 and the second through hole 172 are defined in the second insulating layer 170.
  • the first through hole 171 is disposed corresponding to the source 150, and the second through hole 172 corresponds to the The drain 160 is set.
  • the pixel electrode 190 is connected to the drain 160 through the second through hole 172.
  • the thin film transistor array substrate 100 further includes a first electrode 180 connected to the source 150 through the first through hole 171.
  • the first electrode 180a is used to improve the electrical conductivity of the source 150.
  • the first electrode 180 and the pixel electrode 190 are prepared in the same process.
  • the substrate 110 may be a glass substrate, or may be a plastic substrate or other insulating substrate.
  • the thin film transistor array substrate 100 has other components than the substrate 110 (ie, the gate 120, the first insulating layer 130, the active layer, the The source 150, the drain 160, the second insulating layer 170, the first electrode 180, and the pixel electrode 190 are directly or indirectly disposed on the first surface 110a of the substrate 110 as an example.
  • other components of the thin film transistor array substrate 100 other than the substrate 110 may be disposed between the second surface 110b of the substrate 110.
  • the thin film transistor array substrate 100 further includes a buffer layer (not shown) disposed on the first surface 110a.
  • the buffer layer is used to buffer stress received during fabrication of other structures of the thin film transistor array substrate 100 on the substrate 110 to avoid damage or cracking of the substrate 110.
  • the gate electrode 120, the first insulating layer 130, the active layer 140, the source 150, and the The drain 160, the second insulating layer 170, the first electrode 180, and the pixel electrode 190 are disposed directly or indirectly on the first surface 110a of the substrate 110 through the buffer layer.
  • the buffer layer is disposed on the second surface 110b, the gate 120, the first insulating layer 130, the active layer 140, and the source 150 in the thin film transistor array substrate 100.
  • the drain 160, the second insulating layer 170, the first electrode 180a, and the pixel electrode 190 are disposed directly or indirectly on the second surface 110b of the substrate 110 through the buffer layer.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the gate 120 is disposed on the first surface 110a, and the gate 120 is made of metal or a metal alloy. In one embodiment, the material of the gate 120 is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the first insulating layer 130 is a gate insulating layer, and the material of the first insulating layer 130 is one of silicon oxide, silicon nitride layer, silicon oxynitride layer and a combination thereof.
  • the material of the second insulating layer 170 is selected from one of silicon oxide, silicon nitride layer, silicon oxynitride layer and combinations thereof. It can be understood that the materials of the second insulating layer 170 and the first insulating layer 130 may be the same or different.
  • the active layer 140 includes a metal oxide semiconductor.
  • the active layer 140 includes Indium Gallium Zinc Oxide (IGZO), indium tin oxide, One or any combination of indium zinc oxide, indium oxide or zinc oxide.
  • IGZO Indium Gallium Zinc Oxide
  • the source 150 and the drain 160 comprise an ion implanted metal oxide semiconductor.
  • the source 150, the drain 160, and the active layer 140 are located in the same layer.
  • the ion implantation may be hydrogen ion implantation. Ion implantation of the metal oxide semiconductor layer allows the region where ion implantation is performed to have metal conduction characteristics.
  • the first electrode 180 and the corresponding electrode are formed corresponding to the source 150.
  • the formation of the pixel electrode 190 by the drain 160 can enhance the conductivity of the source 150 and the drain 160.
  • FIG. 2 is a flowchart of a method for fabricating a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • the method for preparing the thin film transistor array substrate includes the following steps.
  • a substrate 110 is provided, and the substrate 110 includes a first surface 110a and a second surface 110b disposed opposite to each other.
  • the substrate 110 can be, but is not limited to, a glass substrate, a plastic substrate, or other insulating substrate.
  • a gate electrode 120 is formed, and the gate electrode 120 is disposed on the first surface 110a.
  • the gate electrode 120 can be formed by the following steps. First, an entire metal layer is formed on the first surface 110a of the substrate 110, and an entire metal layer is patterned to form the gate 120 disposed on the first surface 110a in this embodiment. .
  • step S130 a first insulating layer 130 is formed, and the first insulating layer 130 covers the gate electrode 120. Please refer to Figure 5.
  • Step S140 forming a metal oxide semiconductor layer 210 on the first insulating layer 130. Please refer to Figure 6.
  • step S150 ion implantation is performed on both end regions of the metal oxide semiconductor layer 210.
  • the two end regions of the ion-implanted metal oxide semiconductor layer 210 are a source 150 and a drain 160, respectively, and a metal that has not been ion-implanted.
  • the region of the oxide semiconductor layer is the active layer 140.
  • the ion implantation of the metal oxide semiconductor layer 210 can make the region where ion implantation is performed to have metal conduction characteristics.
  • the ion implantation may be hydrogen ion implantation.
  • the step S150 includes the following steps.
  • step S151 the first photoresist layer 220 is covered on the metal oxide semiconductor layer 210. Please refer to Figure 7.
  • Step S152 patterning the first photoresist layer 220 to leak out both end regions of the metal oxide semiconductor layer 210. Please refer to Figure 8.
  • Step S153 ion-implanting the metal oxide semiconductor layer 210 with the patterned first photoresist layer 210 as a mask (indicated by an arrow in FIG. 9), and ion-implanted metal oxide semiconductor layer 210
  • the both end regions are the source 150 and the drain 160, respectively, and the region of the metal oxide semiconductor layer that has not been ion-implanted is the active layer 140.
  • step S154 the first photoresist layer 220 is peeled off. Please refer to Figure 10.
  • Step 160 forming a second insulating layer 170 covering the source 150, the drain 160, and the active layer 140. Please refer to Figure 11.
  • Step S170 opening the second insulating layer 170 for exposing the source 150 or the The through hole of the drain 160 is described.
  • the step S170 includes: a step S171, a first through hole 171 and a second through hole 172 are defined in the second insulating layer 170, and the first through hole 171 is disposed corresponding to the source 150.
  • the second through hole 172 is disposed corresponding to the drain 160.
  • the step S171 specifically includes the following steps.
  • step S171a the second photoresist layer 230 is covered on the second insulating layer 170. Please refer to Figure 12.
  • Step S171b patterning the second photoresist layer 230 to remove the second photoresist layer 230 corresponding to the source 150 and the drain 160 to leak a portion of the second insulating layer 170. Please refer to Figure 13.
  • Step S171c etching the second insulating layer 170 with the patterned second photoresist layer 230 as a mask to open the first through hole 171 and the second through hole on the second insulating layer 170. 172. Please refer to Figure 14.
  • step S171d the second photoresist layer 230 is peeled off. Please refer to Figure 15.
  • a pixel electrode 190 is formed.
  • the pixel electrode 190 is disposed on the second insulating layer 170 and connected to the source 150 or the drain 160 through the through hole.
  • the step S180 includes: step S181, forming a pixel electrode 190, the pixel electrode 190 is disposed on the second insulating layer 170, and the second pixel electrode 190 passes the second The through hole 172 is connected to the drain 160.
  • the method for preparing the thin film transistor array substrate further includes:
  • step S190 a first electrode 180 is formed, and the first electrode 180 is connected to the source 150 through the first through hole 171.
  • the pixel electrode 190 and the first electrode 180 are prepared in the same preparation process.
  • the step S180 and the step S190 may be the same preparation process.
  • preparing the pixel electrode 190 and the first electrode 180 includes the following steps.
  • a transparent conductive layer 240 is formed, and the transparent conductive layer 240 covers the second insulating layer 170, the source 150, and the drain 160.
  • the transparent conductive material may include one or any combination of indium gallium zinc oxide, indium tin oxide, indium zinc oxide, indium oxide, or zinc oxide.
  • Step b patterning the transparent conductive layer 240, remaining in the source 150 and the drain a transparent conductive layer 240 on the pole 160, and a transparent conductive layer connected to the transparent conductive layer disposed on the drain 160, wherein the transparent conductive layer is disposed on the source 150 and connected to the source 150
  • the layer 240 is the first electrode 180
  • the transparent conductive layer 240 connected to the drain 160 is the pixel electrode 190. Please refer to Figure 17.
  • the method of fabricating the thin film transistor array substrate further includes: forming a buffer layer disposed on the first surface 110a of the substrate 110.
  • the buffer layer is used to buffer stress received during fabrication of other structures of the thin film transistor array substrate 100 on the substrate 110 to avoid damage or cracking of the substrate 110.
  • the gate 120, the first insulating layer 130, the active layer, the source 150, the drain 160, and the second in the method of fabricating the thin film transistor array substrate The insulating layer 170, the first electrode 180, and the pixel electrode 190 are directly or indirectly formed on the first surface 110a of the substrate 110 through the buffer layer.
  • the buffer layer is disposed on the second surface 110b, the gate 120, the first insulating layer 130, the active layer, and the source 150 in the thin film transistor array substrate 100
  • the drain 160, the second insulating layer 170, the first electrode 180, and the pixel electrode 190 are disposed directly or indirectly on the second surface 110b of the substrate 110 through the buffer layer.
  • the material of the buffer layer is selected from one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • the pixel electrode is connected to the drain through the second through hole, and the first electrode is connected to the source through the first through hole, but it is understood that the pixel electrode can also pass through the first through hole.
  • the source is connected, and the first electrode is connected to the drain through the second through hole to improve the conductive performance of the drain.
  • the method for fabricating the thin film transistor array substrate of the present invention forms the metal oxide semiconductor layer 210 on the first insulating layer 130 (gate insulating layer) and the both end regions of the metal oxide semiconductor layer 210
  • the ion implantation is performed, and the source 150 and the drain 160 are respectively formed at both end regions of the ion-implanted metal oxide semiconductor layer 210, and the active oxide layer 140 is the region of the metal oxide semiconductor layer 210 that is not ion-implanted. It can be seen that the formation of the source 150 and the drain 160 and the formation of the active layer 140 can be prepared in the same process without additionally increasing the preparation of the source 150 and the drain 160.
  • the barrier patterning process saves the preparation time of the thin film transistor array substrate.

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管阵列基板(100)及其制备方法。该方法包括：提供基板(110)，基板(110)包括相对设置的第一表面(110a)及第二表面(110b)；形成栅极(120)，栅极(120)设置在第一表面(110a)上；形成第一绝缘层(130)，第一绝缘层(130)覆盖在栅极(120)上；在第一绝缘层(130)上形成金属氧化物半导体层(210)；对金属氧化物半导体层(210)的两端区域进行离子注入，经过离子注入的金属氧化物半导体层(210)的两端区域分别为源极(150)和漏极(160)，未经过离子注入的金属氧化物半导体层(210)的区域为有源层(140)；形成第二绝缘层(170)，第二绝缘层(170)覆盖源极(150)、漏极(160)及有源层(140)；在第二绝缘层(170)上开设用于裸露源极(150)或漏极(160)的贯孔(171,172)；形成像素电极(190)，像素电极(190)设置在第二绝缘层(170)上，并通过贯孔(171,172)与源极(150)或漏极(160)连接。

Description

薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
本发明要求2016年1月22日递交的发明名称为“薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法”的申请号201610046347.9的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法。
背景技术
在液晶显示领域，薄膜晶体管阵列基板(Thin Film Transistor Array)包括呈阵列分布的多个薄膜晶体管(Thin Film Transistor，TFT)。薄膜晶体管一般用作开关元件来控制像素电极的作业，或者用作驱动元件来驱动像素。薄膜晶体管阵列基板中的薄膜晶体管的有源层之上通常覆盖蚀刻保护层，目的是为了在进行源极和栅极蚀刻时保护所述有源层不受破坏，在这种结构的薄膜晶体管中通常需要将蚀刻阻挡层图案化，从而增加了一道掩膜板工序来进行蚀刻阻挡层的图案化，从而增加了所述薄膜晶体管阵列基板的制备时间。
发明内容
本发明提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板，所述基板包括相对设置的第一表面及第二表面；
栅极，设置在所述第一表面上；
第一绝缘层，覆盖在所述栅极上；
有源层，设置在所述第一绝缘层远离所述基板的表面上；
源极和漏极，所述源极和所述漏极分别设置在所述第一绝缘层上且分别设置于所述有源层的相对的两端，并且所述源极和所述漏极分别与所述有源层的端面接触；
第二绝缘层，所述第二绝缘层覆盖所述有源层、所述源极及所述漏极，所 述第二绝缘层上设置用于裸露所述源极或所述漏极的贯孔；
像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接。
其中，所述薄膜晶体管阵列基板还包括：
所述第二绝缘层上开设有第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置，所述像素电极通过所述第二贯孔与所述漏极连接；
所述薄膜晶体管阵列基板还包括第一电极，所述第一电极通过所述第一贯孔与所述源极相连。
其中，所述第一电极与所述像素电极在同一工序中制备。
其中，所述有源层包括金属氧化物半导体，所述源极和漏极包括经离子注入的金属氧化物半导体。
其中，所述有源层包括铟镓锌氧化物、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
本发明还提供了一种薄膜晶体管阵列基板的制备方法，所述薄膜晶体管阵列基板的制备方法包括：
提供基板，所述基板包括相对设置的第一表面及第二表面；
形成栅极，所述栅极设置在所述第一表面上；
形成第一绝缘层，所述第一绝缘层覆盖在所述栅极上；
在所述第一绝缘层上形成金属氧化物半导体层；
对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层；
形成第二绝缘层，所述第二绝缘层覆盖所述源极、所述漏极及所述有源层；
在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔；
形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接。
其中，所述步骤“在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔”包括：
在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置；
相应地，所述步骤“形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接”包括：
形成像素电极，所述像素电极设置在所述第二绝缘层上，且所述像素电极通过所述第二贯孔与所述漏极连接；
所述薄膜晶体管阵列基板的制备方法还包括：
形成第一电极，所述第一电极通过所述第一贯孔与所述源极相连。
其中，所述步骤“对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域形成有源层”包括：
在所述金属氧化物半导体层上覆盖第一光阻层；
图案化所述第一光阻层，以露出所述金属氧化物半导体层的两端区域；
以图案化的所述第一光阻层为掩膜对所述金属氧化物半导体层进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为所述源极和所述漏极，未经过离子注入的金属氧化物半导体的区域为有源层；
剥离所述第一光阻层。
其中，所述步骤“在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置”包括：
在所述第二绝缘层上覆盖第二光阻层；
图案化所述第二光阻层，以移除对应所述源极及所述漏极正上方的第二光阻层，以漏出部分第二绝缘层；
以图案化的第二光阻层为掩膜，蚀刻所述第二绝缘层，以在所述第二绝缘层上开设所述第一贯孔及所述第二贯孔；
剥离所述第二光阻层。
其中，所述像素电极与所述第一电极在同一工序中制备：
形成透明导电层，所述透明导电层覆盖所述第二绝缘层、所述源极及所述漏极；
图案化所述透明导电层，保留设置在所述源极上及所述漏极上的透明导电 层，以及与设置在所述漏极上的透明导电层相连的透明导电层，其中，设置在所述源极上的透明导电层为所述第一电极，设置在所述漏极上的透明导电层为所述像素电极。
相较于现有技术，本发明的薄膜晶体管阵列基板的制备方法在第一绝缘层(栅极绝缘层)上形成金属氧化物半导体层，并对金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别形成源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层。由此可见，所述源极和所述漏极的形成与所述有源层的形成可以在同一工序中制备，不需要额外增加所述源极和所述漏极制备时的阻挡层图案化的工序，从而节约了薄膜晶体管阵列基板的制备时间。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管阵列基板的剖面结构示意图。
图2为本发明一较佳实施方式的薄膜晶体管阵列基板的制备方法的流程图。
图3至图17为薄膜晶体管阵列基板的制备方法的各流程对应的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，图1为本发明一较佳实施方式的薄膜晶体管阵列基板的剖面结构示意图。所述薄膜晶体管阵列基板100包括基板110、栅极120、第一绝 缘层130、有源层140、源极150、漏极160、第二绝缘层170及像素电极190。所述基板110包括相对设置的第一表面110a及第二表面110b，所述栅极120设置在所述第一表面110a上，所述第一绝缘层130覆盖在所述栅极120上。所述有源层140设置在所述第一绝缘层130远离所述基板110的表面上。所述源极150和所述漏极160分别设置在所述第一绝缘层130上且分别设置于所述有源层140的相对的两端，并且所述源极150和所述漏极160分别与所述有源层140的端面接触。所述源极150及所述漏极160与所述有源层140位于同一层。所述第二绝缘层170覆盖所述有源层140、所述源极150及所述漏极160，所述第二绝缘层170上设置有用于裸露所述源极150或所述漏极160的贯孔。所述像素电极190设置在所述第二绝缘层170上，并通过所述贯孔与所述源极150或者所述漏极160连接。
具体地，所述第二绝缘层170上开设有第一贯孔171及第二贯孔172，所述第一贯孔171对应所述源极150设置，所述第二贯孔172对应所述漏极160设置。所述像素电极190通过所述第二贯孔172与所述漏极160连接。所述薄膜晶体管阵列基板100还包括第一电极180，所述第一电极180通过所述第一贯孔171与所述源极150连接。所述第一电极180a用于改善所述源极150的导电性能。优选地，所述第一电极180与所述像素电极190在同一工序中制备。
所述基板110可以为玻璃基板，也可以为塑料基板或者是其他绝缘基板。
可以理解地，在本实施方式中所述薄膜晶体管阵列基板100除所述基板110以外的其他部件(即，所述栅极120、所述第一绝缘层130、所述有源层、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190)直接或者间接设置在所述基板110的第一表面110a为例进行说明，在其他实施方式中，所述薄膜晶体管阵列基板100除所述基板110以外的其他部件也可以之间或间接设置在所述基板110的第二表面110b。
在其他实施方式中，所述薄膜晶体管阵列基板100还包括一缓冲层(图未示)，所述缓冲层设置在所述第一表面110a上。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管阵列基板100的其他结构的过程中受到的应力，以避免所述基板110的损坏或者破裂。此时，所述薄膜晶体管阵列基板100中的所述栅极120、所述第一绝缘层130、所述有源层140、所述源极150、所述 漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接设置在所述基板110的第一表面110a上。或者所述缓冲层设置在所述第二表面110b上，所述薄膜晶体管阵列基板100中的所述栅极120、所述第一绝缘层130、所述有源层140、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180a及所述像素电极190通过所述缓冲层直接或者间接设置在所述基板110的第二表面110b上。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
所述栅极120设置在所述第一表面110a上，所述栅极120的材质为金属或者为金属合金。在一实施方式中，所述栅极120的材质选自铜、钨、铬、铝及其组合的其中之一。
所述第一绝缘层130为栅极绝缘层，所述第一绝缘层130的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
所述第二绝缘层170的材质选自氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。可以理解地，所述第二绝缘层170与所述第一绝缘层130的材质可以相同也可以不同。
在本实施方式中，所述有源层140包括金属氧化物半导体，在一实施方式中，所述有源层140包括铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。优选地，所述源极150和所述漏极160包括经离子注入的金属氧化物半导体。所述源极150、所述漏极160及所述有源层140位于同一层。在一实施方式中，所述离子注入可以为氢离子注入。对金属氧化物半导体层进行离子注入可以使得进行离子注入的区域具有金属导电的特性。另外，因通过将金属氧化物半导体层进行离子注入而得到的所述源极150及所述漏极160导电性能均一性较差，因此，对应所述源极150形成第一电极180及对应所述漏极160形成像素电极190能够提升所述源极150及所述漏极160的导电性能。
下面结合图1及前述对薄膜晶体管阵列基板的相关描述对本发明的薄膜晶体管阵列基板的制备方法进行描述。请一并参阅图2，图2为本发明一较佳实施方式的薄膜晶体管阵列基板的制备方法的流程图。所述薄膜晶体管阵列基板的制备方法包括如下步骤。
步骤S110，提供基板110，所述基板110包括相对设置的第一表面110a及第二表面110b。请一并参阅图3，所述基板110可以为但不仅限于为玻璃基板、塑料基板或者是其他绝缘基板。
步骤S120，形成栅极120，所述栅极120设置在所述第一表面110a上。请参阅图4。所述栅极120可以通过如下步骤形成。首先，在所述基板110的第一表面110a上形成一整层的金属层，将一整层的金属层进行图案化以形成本实施方式中设置在所述第一表面110a上的栅极120。
步骤S130，形成第一绝缘层130，所述第一绝缘层130覆盖在所述栅极120上。请参阅图5。
步骤S140，在所述第一绝缘层130上形成金属氧化物半导体层210。请参阅图6。
步骤S150，对所述金属氧化物半导体层210的两端区域进行离子注入，经过离子注入的金属氧化物半导体层210的两端区域分别为源极150和漏极160，未经过离子注入的金属氧化物半导体层的区域为有源层140。对金属氧化物半导体层210进行离子注入可以使得进行离子注入的区域具有金属导电的特性。所述离子注入可以为氢离子注入。
具体地，所述步骤S150包括如下步骤。
步骤S151，在所述金属氧化物半导体层210上覆盖第一光阻层220。请参阅图7。
步骤S152，图案化所述第一光阻层220，以漏出所述金属氧化物半导体层210的两端区域。请参阅图8。
步骤S153，以图案化的所述第一光阻层210为掩膜对所述金属氧化物半导体层210进行离子注入(在图9中以箭头表示)，经过离子注入的金属氧化物半导体层210的两端区域分别为所述源极150和所述漏极160，未经过离子注入的金属氧化物半导体层的区域为有源层140。请参阅图9。
步骤S154，剥离所述第一光阻层220。请参阅图10。
步骤160，形成第二绝缘层170，所述第二绝缘层170覆盖所述源极150、所述漏极160及所述有源层140。请参阅图11。
步骤S170，在所述第二绝缘层170上开设用于裸露所述源极150或者所 述漏极160的贯孔。
具体地，所述步骤S170包括：步骤S171，在所述第二绝缘层170上开设第一贯孔171及第二贯孔172，所述第一贯孔171对应所述源极150设置，所述第二贯孔172对应所述漏极160设置。
所述步骤S171具体包括如下步骤。
步骤S171a，在所述第二绝缘层170上覆盖第二光阻层230。请参阅图12。
步骤S171b，图案化所述第二光阻层230，以移除对应所述源极150和所述漏极160正上方的第二光阻层230，以漏出部分第二绝缘层170。请参阅图13。
步骤S171c，以图案化的第二光阻层230为掩膜蚀刻所述第二绝缘层170，以在所述第二绝缘层170上开设所述第一贯孔171及所述第二贯孔172。请参阅图14。
步骤S171d，剥离所述第二光阻层230。请参阅图15。
步骤S180，形成像素电极190，所述像素电极190设置在所述第二绝缘层170上，并通过所述贯孔与所述源极150或所述漏极160连接。
与所述步骤S171相应，所述步骤S180包括：步骤S181，形成像素电极190，所述像素电极190设置在所述第二绝缘层170上，且所述第二像素电极190通过所述第二贯孔172与所述漏极160连接。
相应地，所述薄膜晶体管阵列基板的制备方法还包括：
步骤S190，形成第一电极180，所述第一电极180通过所述第一贯孔171与所述源极150相连。
优选地，所述像素电极190和所述第一电极180在同一制备工序中制备。换句话说，所述步骤S180和所述步骤S190可以为同一制备工序。具体地，制备所述像素电极190及所述第一电极180包括如下步骤。
步骤a，形成透明导电层240，所述透明导电层240覆盖所述第二绝缘层170、所述源极150及所述漏极160。请参阅图16。所述透明导电材料可以包括铟镓锌氧化物、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
步骤b，图案化所述透明导电层240，保留设置在所述源极150及所述漏 极160上的透明导电层240，以及与设置在所述漏极160上的透明导电层相连的透明导电层，其中，设置在所述源极150上且与所述源极150相连的透明导电层240为所述第一电极180，与所述漏极160相连的透明导电层240为所述像素电极190。请参阅图17。
在其他实施方式中，所述薄膜晶体管阵列基板的制备方法还包括：形成缓冲层，所述缓冲层设置在所述基板110的第一表面110a上。所述缓冲层用于缓冲在所述基板110上制作所述薄膜晶体管阵列基板100的其他结构的过程中受到的应力，以避免所述基板110的损坏或者破裂。此时，所述薄膜晶体管阵列基板的制备方法中的所述栅极120、所述第一绝缘层130、所述有源层、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接制备在所述基板110的第一表面110a上。或者，所述缓冲层设置在所述第二表面110b上，所述薄膜晶体管阵列基板100中的所述栅极120、所述第一绝缘层130、所述有源层、所述源极150、所述漏极160、所述第二绝缘层170、所述第一电极180及所述像素电极190通过所述缓冲层直接或者间接设置在所述基板110的第二表面110b上。所述缓冲层的材质选自氧化硅层，氮化硅层，氮氧化硅层及其组合的其中之一。
在本发明提供的实施例中，像素电极通过第二贯孔与漏极连接，第一电极通过第一贯孔与源极连接，但可以理解的是，像素电极也可以通过第一贯孔与源极连接，第一电极通过第二贯孔与漏极连接以改善漏极的导电性能，其结构和制作方法与本申请实施例类似，在此不再赘述。
相较于现有技术，本发明的薄膜晶体管阵列基板的制备方法在第一绝缘层130(栅极绝缘层)上形成金属氧化物半导体层210，并对金属氧化物半导体层210的两端区域进行离子注入，经过离子注入的金属氧化物半导体层210的两端区域分别形成源极150和漏极160，未经过离子注入的金属氧化物半导体层210的区域为有源层140。由此可见，所述源极150和所述漏极160的形成与所述有源层140的形成可以在同一工序中制备，不需要额外增加所述源极150和所述漏极160制备时的阻挡层图案化的工序，从而节约了薄膜晶体管阵列基板的制备时间。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发 明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基板，所述基板包括相对设置的第一表面及第二表面；
    栅极，设置在所述第一表面上；
    第一绝缘层，覆盖在所述栅极上；
    有源层，设置在所述第一绝缘层远离所述基板的表面上；
    源极和漏极，所述源极和所述漏极分别设置在所述第一绝缘层上且分别设置于所述有源层的相对的两端，并且所述源极和所述漏极分别与所述有源层的端面接触；
    第二绝缘层，所述第二绝缘层覆盖所述有源层、所述源极及所述漏极，所述第二绝缘层上设置有用于裸露所述源极或所述漏极的贯孔；
    像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，
    所述第二绝缘层上开设有第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置，所述像素电极通过所述第二贯孔与所述漏极连接；
    所述薄膜晶体管阵列基板还包括第一电极，所述第一电极通过所述第一贯孔与所述源极相连。
  3. 如权利要求2所述的薄膜晶体管阵列基板，其中，所述第一电极与所述像素电极在同一工序中制备。
  4. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述有源层包括金属氧化物半导体；所述源极和漏极包括经离子注入的金属氧化物半导体。
  5. 如权利要求3所述的薄膜晶体管阵列基板，其中，所述有源层包括铟镓 锌氧化物、铟锡氧化物、铟锌氧化物、氧化铟或者氧化锌等之一或者任意组合。
  6. 一种薄膜晶体管阵列基板的制备方法，其中，所述薄膜晶体管阵列基板的制备方法包括：
    提供基板，所述基板包括相对设置的第一表面及第二表面；
    形成栅极，所述栅极设置在所述第一表面上；
    形成第一绝缘层，所述第一绝缘层覆盖在所述栅极上；
    在所述第一绝缘层上形成金属氧化物半导体层；
    对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域为有源层；
    形成第二绝缘层，所述第二绝缘层覆盖所述源极、所述漏极及所述有源层；
    在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔；
    形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接。
  7. 如权利要求6所述的薄膜晶体管阵列基板的制备方法，其中，所述步骤“在所述第二绝缘层上开设用于裸露所述源极或所述漏极的贯孔”包括：
    在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置；
    相应地，所述步骤“形成像素电极，所述像素电极设置在所述第二绝缘层上，并通过所述贯孔与所述源极或所述漏极连接”包括：
    形成像素电极，所述像素电极设置在所述第二绝缘层上，且所述像素电极通过所述第二贯孔与所述漏极连接；
    所述薄膜晶体管阵列基板的制备方法还包括：
    形成第一电极，所述第一电极通过所述第一贯孔与所述源极相连。
  8. 如权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，所述步骤“对所述金属氧化物半导体层的两端区域进行离子注入，经过离子注入的金属 氧化物半导体层的两端区域分别为源极和漏极，未经过离子注入的金属氧化物半导体层的区域形成有源层”包括：
    在所述金属氧化物半导体层上覆盖第一光阻层；
    图案化所述第一光阻层，以露出所述金属氧化物半导体层的两端区域；
    以图案化的所述第一光阻层为掩膜对所述金属氧化物半导体层进行离子注入，经过离子注入的金属氧化物半导体层的两端区域分别为所述源极和所述漏极，未经过离子注入的金属氧化物半导体的区域为有源层；
    剥离所述第一光阻层。
  9. 如权利要求7所述的薄膜晶体管的制备方法，其中，所述步骤“在所述第二绝缘层上开设第一贯孔及第二贯孔，所述第一贯孔对应所述源极设置，所述第二贯孔对应所述漏极设置”包括：
    在所述第二绝缘层上覆盖第二光阻层；
    图案化所述第二光阻层，以移除对应所述源极及所述漏极正上方的第二光阻层，以漏出部分第二绝缘层；
    以图案化的第二光阻层为掩膜，蚀刻所述第二绝缘层，以在所述第二绝缘层上开设所述第一贯孔及所述第二贯孔；
    剥离所述第二光阻层。
  10. 如权利要求9所述的薄膜晶体管阵列基板的制备方法，其中，所述像素电极与所述第一电极在同一工序中制备：
    形成透明导电层，所述透明导电层覆盖所述第二绝缘层、所述源极及所述漏极；
    图案化所述透明导电层，保留设置在所述源极上及所述漏极上的透明导电层，以及与设置在所述漏极上的透明导电层相连的透明导电层，其中，设置在所述源极上的透明导电层为所述第一电极，设置在所述漏极上的透明导电层为所述像素电极。
PCT/CN2016/074066 2016-01-22 2016-02-18 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法 Ceased WO2017124594A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/033,624 US10115748B2 (en) 2016-01-22 2016-02-18 Thin film transistor array substrate and manufacture method of thin film transistor array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610046347.9 2016-01-22
CN201610046347.9A CN105489618B (zh) 2016-01-22 2016-01-22 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法

Publications (1)

Publication Number Publication Date
WO2017124594A1 true WO2017124594A1 (zh) 2017-07-27

Family

ID=55676499

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/074066 Ceased WO2017124594A1 (zh) 2016-01-22 2016-02-18 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法

Country Status (3)

Country Link
US (1) US10115748B2 (zh)
CN (1) CN105489618B (zh)
WO (1) WO2017124594A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10121710B2 (en) 2016-06-14 2018-11-06 Innolux Corporation Methods for manufacturing a display device
CN106229297B (zh) * 2016-09-18 2019-04-02 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法
US10566401B2 (en) 2017-06-28 2020-02-18 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor array substrate and preparing method therefor, and OLED display device
CN107134461A (zh) * 2017-06-28 2017-09-05 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制备方法、oled显示装置
CN111180471A (zh) * 2020-03-02 2020-05-19 南京中电熊猫平板显示科技有限公司 阵列基板及其制造方法
CN111244115B (zh) * 2020-03-09 2022-12-02 合肥鑫晟光电科技有限公司 一种显示用基板及其制备方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091465A (en) * 1996-03-26 2000-07-18 Lg Electronics Inc. Method for fabricating liquid crystal display
CN103050410A (zh) * 2012-10-30 2013-04-17 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN103915508A (zh) * 2013-01-17 2014-07-09 上海天马微电子有限公司 一种底栅结构的氧化物薄膜晶体管及其制作方法
CN104779139A (zh) * 2015-03-31 2015-07-15 深超光电（深圳）有限公司 半导体薄膜的制造方法及薄膜晶体管的制造方法
CN105097841A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 Tft基板的制作方法及tft基板
CN105140271A (zh) * 2015-07-16 2015-12-09 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制造方法及显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3479375B2 (ja) * 1995-03-27 2003-12-15 科学技術振興事業団 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法
WO2002016679A1 (en) * 2000-08-18 2002-02-28 Tohoku Techno Arch Co., Ltd. Polycrystalline semiconductor material and method of manufacture thereof
KR100958006B1 (ko) * 2008-06-18 2010-05-17 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
TWI540647B (zh) * 2008-12-26 2016-07-01 半導體能源研究所股份有限公司 半導體裝置及其製造方法
WO2012004925A1 (ja) * 2010-07-08 2012-01-12 シャープ株式会社 半導体装置及びその製造方法並びに液晶表示装置
KR101826069B1 (ko) * 2010-10-26 2018-03-23 삼성디스플레이 주식회사 유기발광표시장치 및 그 제조방법
KR20130117558A (ko) * 2012-04-18 2013-10-28 삼성디스플레이 주식회사 박막 트랜지스터, 박막 트랜지스터 표시판 및 박막 트랜지스터 표시판 제조 방법
CN104124277B (zh) * 2013-04-24 2018-02-09 北京京东方光电科技有限公司 一种薄膜晶体管及其制作方法和阵列基板
KR102075530B1 (ko) * 2013-09-11 2020-02-11 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그 제조방법, 및 이를 포함하는 표시장치
US9590111B2 (en) * 2013-11-06 2017-03-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
CN103915379B (zh) * 2014-03-24 2017-07-04 京东方科技集团股份有限公司 一种氧化物薄膜晶体管阵列基板的制造方法
KR102191997B1 (ko) * 2014-06-19 2020-12-17 삼성디스플레이 주식회사 디스플레이 장치의 열처리 장치 및 이를 이용한 열처리 방법
KR20160053001A (ko) * 2014-10-30 2016-05-13 삼성디스플레이 주식회사 투명 표시 기판, 투명 표시 장치 및 투명 표시 장치의 제조 방법
KR102368593B1 (ko) * 2015-04-03 2022-03-03 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이를 구비하는 표시 패널

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091465A (en) * 1996-03-26 2000-07-18 Lg Electronics Inc. Method for fabricating liquid crystal display
CN103050410A (zh) * 2012-10-30 2013-04-17 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN103915508A (zh) * 2013-01-17 2014-07-09 上海天马微电子有限公司 一种底栅结构的氧化物薄膜晶体管及其制作方法
CN104779139A (zh) * 2015-03-31 2015-07-15 深超光电（深圳）有限公司 半导体薄膜的制造方法及薄膜晶体管的制造方法
CN105140271A (zh) * 2015-07-16 2015-12-09 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制造方法及显示装置
CN105097841A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 Tft基板的制作方法及tft基板

Also Published As

Publication number Publication date
US20180047765A1 (en) 2018-02-15
US10115748B2 (en) 2018-10-30
CN105489618A (zh) 2016-04-13
CN105489618B (zh) 2019-04-26

Similar Documents

Publication Publication Date Title
US9437627B2 (en) Thin film transistor and manufacturing method thereof
WO2017124594A1 (zh) 薄膜晶体管阵列基板及薄膜晶体管阵列基板的制备方法
TWI604529B (zh) 薄膜電晶體及其製造方法
CN107994066B (zh) Tft、制作方法、阵列基板、显示面板及装置
CN104409518B (zh) 薄膜晶体管及其制备方法
CN105428243B (zh) 一种薄膜晶体管及制作方法、阵列基板和显示装置
WO2016008226A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示设备
CN108550625B (zh) 一种薄膜晶体管及其制作方法
CN104241389A (zh) 薄膜晶体管和有源矩阵有机发光二极管组件及制造方法
CN105938800A (zh) 薄膜晶体管的制造方法及阵列基板的制造方法
CN110190031A (zh) 一种薄膜晶体管基板的制备方法
WO2017008347A1 (zh) 阵列基板、阵列基板的制造方法及显示装置
US20150380565A1 (en) Thin film transistor and method for manufacturing the same, array substrate and display device
CN104241390B (zh) 薄膜晶体管和有源矩阵有机发光二极管组件及制造方法
US10770487B2 (en) Method for manufacturing LTPS type TFT
CN108574013B (zh) 半导体装置及其操作方法
CN104882415A (zh) Ltps阵列基板及其制造方法
CN109545798B (zh) 一种阵列基板及其制作方法
CN106611794B (zh) 薄膜晶体管及其制作方法
WO2020056805A1 (zh) 阵列基板及其制作方法、显示面板
KR20160084923A (ko) 박막 트랜지스터 기판 및 그 제조 방법
CN109860107B (zh) 阵列基板及其制作方法
CN106571389B (zh) 晶体管及其形成方法
JPH06209010A (ja) 薄膜トランジスタの製造方法
CN109638034B (zh) 显示面板的制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15033624

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16885867

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16885867

Country of ref document: EP

Kind code of ref document: A1