WO2017114296A1 - 一种铝镓氮化合物/氮化镓高电子迁移率晶体管 - Google Patents

一种铝镓氮化合物/氮化镓高电子迁移率晶体管 Download PDF

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WO2017114296A1
WO2017114296A1 PCT/CN2016/111609 CN2016111609W WO2017114296A1 WO 2017114296 A1 WO2017114296 A1 WO 2017114296A1 CN 2016111609 W CN2016111609 W CN 2016111609W WO 2017114296 A1 WO2017114296 A1 WO 2017114296A1
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layer
gan
mobility transistor
gallium nitride
drain electrode
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PCT/CN2016/111609
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English (en)
French (fr)
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任春江
陈堂胜
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中国电子科技集团公司第五十五研究所
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Priority to RU2017143211A priority Critical patent/RU2017143211A/ru
Priority to US15/580,436 priority patent/US20180182879A1/en
Priority to JP2017563253A priority patent/JP2018533837A/ja
Priority to EP16881085.1A priority patent/EP3316314A4/en
Publication of WO2017114296A1 publication Critical patent/WO2017114296A1/zh

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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds

Definitions

  • the present invention relates to a nitride high mobility transistor having a strain balance of an aluminum gallium nitride compound intercalation layer.
  • Aluminum gallium nitride compound (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) as a third-generation wide bandgap compound semiconductor device has the characteristics of large output power, high operating frequency, high temperature resistance, etc. Some high-frequency, high-power characteristics are not available in existing semiconductor technologies such as Si and GaAs, which makes it a unique advantage in microwave applications, and has become a hot spot in semiconductor microwave power devices.
  • AlN insertion layer L. Shen et al., IEEE Electron Device Lett., vol. 22, pp. 457-459, Oct.
  • FIG. 1 is a schematic view of a conventional AlGaN/GaN HEMT device having an AlN insertion layer, wherein the AlN insertion layer functions to reduce electrons in the two-dimensional electron gas (2DEG) in the GaN channel layer from the AlGaN barrier layer alloy.
  • the effect of order scattering is to improve the mobility of 2DEG.
  • the AlN insertion layer has a wider band gap and stronger piezoelectric polarization and spontaneous planning effect, which can effectively improve the areal density of 2DEG in the channel.
  • the 2DEG mobility and the increase in areal density will ultimately improve the performance of the device.
  • the AlN insertion layer can bring about an improvement in device performance, it has a large lattice mismatch with the upper AlGaN barrier layer and the underlying GaN channel layer, so that its thickness cannot exceed 1 nm, and the thickness exceeds 1 nm.
  • the crystal quality of the AlN intercalation layer will be greatly deteriorated, and the defect density will be significantly increased, which is not conducive to improving the performance of the device.
  • the epitaxial layers used in existing AlGaN/GaN HEMT devices are generally obtained by organic vapor phase chemical deposition (MOCVD), the control of epitaxial layer thickness is far less accurate than molecular beam epitaxy (MBE) technology, and therefore does not exceed 1 nm.
  • MBE molecular beam epitaxy
  • the role of the GaN cap layer in the conventional AlGaN/GaN HEMT device shown in FIG. 1 is to balance the strain force introduced by the AlN insertion layer and the AlGaN barrier layer, and the thickness of the GaN cap layer is generally between 1-5 nm.
  • Another use for the introduction of GaN cap layers is to contain current collapse of AlGaN/GaN HEMTs (R. Coffie et al., IEEE Electron Device Lett., Vol. 23, No. 10, pp. 588-590, 2002.),
  • the downside is that it will cause a decrease in the concentration of 2DEG in the channel.
  • the source and drain electrodes of conventional AlGaN/GaN HEMT devices are directly deposited on the GaN cap layer, and ohmic contact with the underlying epitaxial layer is required by a superalloy process.
  • the source electrode and the drain electrode metal need to penetrate the GaN cap layer, the AlGaN barrier layer, and the AlN insertion layer to form an ohmic contact with the 2DEG in the channel, generally having a GaN cap layer and an AlN insertion layer.
  • Better ohmic contact requires a higher alloy temperature, which will make the source and drain electrodes gold
  • the thermal expansion and contraction in the alloy process is more serious, and even the redistribution of the epitaxial layer stress adversely affects the consistency and reliability of the device performance.
  • the present invention provides an aluminum gallium nitride compound/gallium nitride high electron mobility transistor, comprising: a substrate composed of silicon carbide, silicon or sapphire, and the substrate is optimally selected from silicon carbide;
  • the GaN buffer layer on the bottom, the GaN buffer layer thickness is preferably 1500-2000 nm;
  • the Al y Ga 1-y N insertion layer is on the GaN buffer layer, wherein 0.35 ⁇ y ⁇ 0.5, and the Al y Ga 1-y N insertion layer is the most
  • the preferred thickness is 1-3 nm;
  • the present invention replaces an AlN intercalation layer with an AlGaN intercalation layer having a high Al composition, and the AlGaN intercalation layer is smaller than that of the GaN channel layer, and can be grown thicker, so that the epitaxial material grows.
  • the process is more controllable, which helps to improve the consistency of the device.
  • the 2DEG concentration and mobility can be improved.
  • the GaN cap layer and the partial AlGaN barrier layer under the source and drain electrodes of the AlGaN/GaN HEMT device are removed by etching, so that the source and drain electrodes are closer to the 2DEG in the channel, so that the source and drain electrodes pass through the lower
  • the alloy temperature can form an ohmic contact with the 2DEG in the channel to avoid the redistribution of the epitaxial layer stress caused by the thermal expansion and contraction of the source electrode and the drain electrode metal during the high temperature process, thereby improving the consistency and reliability of the device performance.
  • 1 is a schematic view showing the general structure of an AlGaN/GaN HEMT.
  • FIG. 2 is a schematic view showing the structure of an AlGaN/GaN HEMT according to an embodiment of the present invention.
  • FIG 3 is a schematic view showing the structure of an AlGaN/GaN HEMT according to another embodiment of the present invention.
  • the AlGaN/GaN HEMT according to the present invention has a substrate 21 which is any one of sapphire, Si and SiC, preferably semi-insulating. 4H-SiC and semi-insulating 6H-SiC as substrates, using semi-insulating 4H-SiC (0001) and semi-insulating 6H-SiC (0001) as substrates, which have high thermal conductivity and GaN lattice The characteristics of small mismatch, not only easy to grow high-quality GaN epitaxial materials, but also facilitate the heat dissipation of the device. At present, Cree and II-VI companies in the United States have 4CH and 6H SiC substrates for sale.
  • the GaN buffer layer 22 is located on the substrate 21 to the top, and the GaN buffer layer thickness is preferably 1500-2000 nm.
  • the GaN buffer layer 22 generally has a high background carrier concentration, which is disadvantageous for device breakdown, so it can be considered For Fe doping, refer to the related literature for Fe doping technology, but it is necessary to control the concentration and thickness of Fe doping.
  • the concentration of Fe doping is generally controlled within 4 ⁇ 10 18 cm -3 , and the doping thickness is
  • the substrate does not exceed 500-1000 nm upward, that is, the thickness of the top of the GaN buffer layer is about 1000 nm to be undoped.
  • the nucleation layer is mainly used as a transition to reduce the GaN buffer layer 22 and the lining.
  • the stress introduced by the bottom lattice mismatch, the selection of the nucleation layer is related to the substrate material, which is well known in the art and will not be further described.
  • the Al y Ga 1-y N insertion layer 23 is on the GaN buffer layer, wherein 0.35 ⁇ y ⁇ 0.5, and the Al y Ga 1-y N insertion layer 23 has an optimum thickness of 1-3 nm, and Al y Ga 1-y N is inserted.
  • the band gap at the interface between the layer 23 and the GaN buffer layer 22 is larger than that of the GaN buffer layer, such that a triangular potential well is formed near the GaN buffer layer at the interface between the GaN buffer layer 22 and the Al y Ga 1-y N insertion layer 23, plus III
  • the strong self-polarization and piezoelectric polarization effects of the group nitride itself form a two-dimensional electron gas having a high areal density near the interface between the GaN buffer layer 22 and the Al y Ga 1-y N insertion layer 23.
  • the Al x Ga 1-x N barrier layer 24 is located on the Al y Ga 1-y N insertion layer 23 opposite to the GaN buffer layer 22, wherein 0.2 ⁇ x ⁇ 0.28, and the Al x Ga 1-x N barrier layer 24 is the most
  • the excellent thickness is 10-20 nm, and the interface between the GaN buffer layer 22 and the Al y Ga 1-y N insertion layer 23 can be made close by the spontaneous polarization and piezoelectric polarization effect of the Al x Ga 1-x N barrier layer 24.
  • the triangular potential well formed at the GaN buffer layer is deeper, resulting in a higher areal density of 2DEG, which contributes to the improvement of device performance.
  • the GaN cap layer 25 is on the Al x Ga 1-x N barrier layer 24, and the GaN cap layer has an optimum thickness of 1-3 nm.
  • the GaN cap layer 25 functions to balance the Al y Ga 1-y N intercalation layer 23 and Al.
  • the strain force introduced by the x Ga 1-x N barrier layer 24 can simultaneously suppress the current collapse effect ubiquitous in the AlGaN/GaN HEMT, and improve the microwave performance of the device.
  • the GaN buffer layer 22 (along with the nucleation layer between the GaN buffer layer 22 and the substrate 21), the Al y Ga 1-y N insertion layer 23, the Al x Ga 1-x N barrier layer 24, and the GaN cap layer 25 may
  • the substrate 21 is epitaxially grown by any suitable growth method such as MOCVD, RF-MBE, etc., preferably by MOCVD.
  • the GaN cap layer 25 under the source electrode 26 and the drain electrode 27 and the partial thickness Al x Ga 1-x N barrier layer 24 are removed to form a groove, and the formation of the groove needs to be obtained by dry etching, for drying
  • the etching of both GaN and AlGaN compounds is well known in the art. Reference may be made to the related literature, in which the source and drain electrodes are provided, and the source and drain electrode portions are located on the GaN cap layer to form a " ⁇ " type source.
  • the electrode and the drain electrode, the source/drain electrode 26 and the drain electrode 27 are made of the same metal layer, including but not limited to a multilayer metal system such as Ti/Al/Ni/Au, Ti/Al/Mo/Au, etc., and are passed through a superalloy.
  • 2DEG forms an ohmic contact, with a preferred alloy temperature of 680-780 °C.
  • a gate electrode 28 is provided between the source electrode 26 and the drain electrode 27.
  • the gate electrode 28 functions to form a Schottky contact with the GaN cap layer 25, so that the voltage change on the gate electrode 28 can modulate the groove while the device is operating.
  • Two-dimensional electron gas in the channel; another function is to reduce the gate resistance of the device and improve the frequency characteristics of the device.
  • the metal used for the gate electrode 28 includes but is not limited to Ni/Au/Ti or Ni/Pt/Au/Pt/Ti or A multilayer metal system such as Ni/Pt/Au/Ni.
  • FIG. 3 shows another embodiment of an AlGaN/GaN HEMT according to the present invention, which adds an Al z Ga 1-z N intercalation layer 35 to the Al z Ga 1-
  • the z N insertion layer 35 is on the Al x Ga 1-x N barrier layer 34, where 0.3 ⁇ z ⁇ 0.4, and the thickness of the Al z Ga 1-z N insertion layer 35 is 1-3 nm, using Al z Ga 1-z
  • the spontaneous polarization and piezoelectric polarization effects of the N insertion layer 35 further enhance the 2DEG areal density formed at the interface between the GaN buffer layer 32 and the Al y Ga 1-y N insertion layer 33 near the GaN buffer layer, further improving device performance.
  • the purpose of the high Al composition AlGaN intercalation layer on the GaN buffer layer in the two embodiments of the present invention is to increase the areal density and mobility of the 2DEG in the channel to achieve the effect of the AlN insertion layer in FIG. Since the high Al composition AlGaN insertion and the GaN buffer layer have a smaller lattice mismatch than the AlN insertion layer, it can be designed to be thicker, which is more favorable for control in the process.
  • the role of the GaN cap layer is mainly to balance the underlying AlGaN intercalation layer and The AlGaN barrier layer or the like is used for stress caused by lattice mismatch with the GaN buffer layer.
  • the GaN cap layer Since the introduction of the GaN cap layer causes a decrease in the 2DEG areal density in the channel, the thickness thereof must not be too thick.
  • the GaN cap layer has a large lattice mismatch with the AlGaN intercalation layer and the AlGaN barrier layer, and is subjected to a large compressive stress, so that the effect of lowering the 2DEG concentration in the channel is further enhanced by introducing a " ⁇ " type source electrode and After the drain electrode, the partial stress of the GaN cap layer can be released, and the reduction of the 2DEG concentration in the channel by the introduction of the GaN cap layer can be alleviated, which is a compromise between device performance and reliability.
  • the source electrode and the drain electrode of the " ⁇ " type After the introduction of the source electrode and the drain electrode of the " ⁇ " type, it is more advantageous for the electrons in the channel to enter the source electrode or the drain electrode through the tunneling effect, and vice versa, thereby reducing the ohmic contact resistance of the device, which contributes to further improvement. Device performance.

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Abstract

提供一种具有铝镓氮化合物插入层应变平衡的氮化物高迁移率晶体管。包括：衬底（21）和位于衬底（21）上的GaN缓冲层（22）；AlyGa1-yN插入层（23）位于GaN缓冲层（22）上；与GaN缓冲层（22）相对的位于AlyGa1-yN插入层（23）上的AlxGa1-xN势垒层（24）；位于AlxGa1-xN势垒层（24）上的GaN帽层（25）；GaN帽层（25）和部分厚度的AlxGa1-xN势垒层（24）被去除形成凹槽，凹槽中提供"Г"型源电极（26）和漏电极（27）；栅电极（28）位于源电极（26）和漏电极（27）之间。另外还提供了一种氮化物高迁移率晶体管，在AlxGa1-xN势垒层（24）和GaN帽层（25）之间还包含了一AlzGa1-zN插入层（35）。上述氮化物高迁移率晶体管采用高Al组分AlGaN插入层实现AlN插入层的性能，使工艺可控性更强；引入"Г"型源电极和漏电极便于形成欧姆接触，同时结合GaN帽层可更好的对外延层整体应力进行控制，保证器件可靠性同时使性能最优化。

Description

一种铝镓氮化合物/氮化镓高电子迁移率晶体管 技术领域
本发明涉及的是一种具有铝镓氮化合物插入层应变平衡的氮化物高迁移率晶体管。
背景技术
铝镓氮化合物(AlGaN)/氮化镓(GaN)高电子迁移率晶体管(HEMT)作为第三代宽禁带化合物半导体器件具有输出功率大、工作频率高、耐高温等特点，特别是其兼有的高频、大功率特性是现有Si和GaAs等半导体技术所不具备的，这使得其在微波应用领军具有独特的优势，从而成为了半导体微波功率器件研究的热点。通过AlN插入层的引入(L.Shen et al.,IEEE Electron Device Lett.,vol.22,pp.457–459,Oct.2001.)结合外延材料晶体质量的提升、SiN表面钝化技术的引入(B.M.Green,et al.,IEEE Electron Device Lett.,Vol.21no.6,pp.268-270,2000.)结合场板结构的采用(Ando et al.IEEE Electron Device Lett.，Vol.24，No.5，pp.289-291，2003.)，研究人员在AlGaN/GaN HEMT的微波性能方面已取得了很好的突破。特别是输出功率能力方面，目前公开的小尺寸AlGaN/GaN HEMT的输出功率密度在X波段可达30W/mm以上(Wu et al.IEEE Electron Device Lett.，Vol.25，No.3，pp.117-119，2004.)、Ka波段其输出功率甚至也达到了10W/mm以上(T.Palacios et al.,IEEE ELECTRON DEVICE LETTERS,VOL.26,NO.11,pp.781-783，2005.)。
图1所示为常规的具有AlN插入层的AlGaN/GaN HEMT器件示意图，其中AlN插入层的作用一方面是降低GaN沟道层中二维电子气(2DEG)中电子受到AlGaN势垒层合金无序散射的作用，实现2DEG迁移率的提升；另外AlN插入层具有更宽的禁带和更强的压电极化和自发计划效应，可以有效提高沟道中2DEG的面密度，通过对GaN沟道中2DEG迁移率和面密度的提升，最终实现对器件性能的提升。AlN插入层虽然可以带来器件性能的提升，但是自身由于与上方的AlGaN势垒层和下方的GaN沟道层具有较大的晶格失配，使得其厚度不能超过1nm，超过1nm厚度后的AlN插入层晶体质量将大大恶化，缺陷密度显著增加，不利于提升器件的性能。由于现有AlGaN/GaN HEMT器件所用的外延层普遍采用有机气相化学淀积(MOCVD)的方法获取，对于外延层厚度的控制远没有分子束外延(MBE)技术来的精确，因此不超过1nm的AlN插入层生长难度较大。
图1所示常规AlGaN/GaN HEMT器件中GaN帽层的作用是平衡AlN插入层和AlGaN势垒层所引入的应变力，GaN帽层的厚度一般在1-5nm之间。GaN帽层的引入的另一个用途是遏制AlGaN/GaN HEMT的电流崩塌(R.Coffie et al.,IEEE Electron Device Lett.,Vol.23，No.10,pp.588-590,2002.)，但是其不利的一面是将引起沟道中2DEG浓度的降低，另外常规AlGaN/GaN HEMT器件源电极和漏电极直接淀积在GaN帽层上，并需要通过高温合金过程与其下的外延层形成欧姆接触，高温过程中源电极和漏电极金属需要穿透GaN帽层、AlGaN势垒层以及AlN插入层与沟道中的2DEG形成欧姆接触，一般来说具有GaN帽层和AlN插入层时，要想获得更好的欧姆接触，需要采用更高的合金温度，这将使得源电极和漏电极金 属在合金过程中的热胀冷缩更加严重，甚至导致外延层应力的再分布，对器件性能的一致性和可靠性都带来不利影响。
发明内容
发明目的：本发明的目的在于提供一种性能可靠，生长过程可控的晶体管。
技术方案：本发明提供了一种具有铝镓氮化合物/氮化镓高电子迁移率晶体管，包括：由碳化硅、硅或者蓝宝石构成的衬底，衬底最优的选材为碳化硅；位于衬底上的GaN缓冲层，GaN缓冲层厚度优选的为1500-2000nm；AlyGa1-yN插入层位于GaN缓冲层上，其中0.35≤y≤0.5，AlyGa1-yN插入层最优的厚度为1-3nm；与GaN缓冲层相对的位于AlyGa1-yN插入层上的AlxGa1-xN势垒层，其中0.2≤x≤0.25，AlxGa1-xN势垒层最优的厚度为10-20nm；位于AlxGa1-xN势垒层上的AlzGa1-zN插入层，其中0.30≤z≤0.4，AlzGa1-zN插入层最优的厚度为1-3nm；位于AlzGa1-zN插入层上的GaN帽层，GaN帽层最优的厚度为1-3nm；源电极和漏电极下的GaN帽层、AlzGa1-zN插入层和部分厚度的AlxGa1-xN势垒层被去除形成凹槽，凹槽中提供源电极和漏电极，源电极和漏电极部分位于GaN帽层上形成“Г”型的源电极和漏电极；栅电极位于源电极和漏电极之间。
有益效果：本发明用具有高Al组分的AlGaN插入层替代AlN插入层，AlGaN插入层与GaN沟道层的失配相比AlN插入层来的小，可以生长得更厚，使得外延材料生长过程更加可控，有利于提升器件的一致性，同时通过优化Al组分，同样可以实现对2DEG浓度和迁移率的提升。另外通过刻蚀去除AlGaN/GaN HEMT器件源电极和漏电极下的GaN帽层和部分AlGaN势垒层，使得源电极和漏电极更加靠近沟道中的2DEG，使得源电极和漏电极通过较低的合金温度便可与沟道中的2DEG形成欧姆接触，避免高温过程中源电极和漏电极金属的热胀冷缩引起外延层应力的再分布，从而提升器件性能的一致性和可靠性。
附图说明
图1是AlGaN/GaN HEMT的一般结构示意图。
图2是本发明一个实施例的AlGaN/GaN HEMT结构示意图。
图3是本发明另一个实施例的AlGaN/GaN HEMT结构示意图。
具体实施方式
下面结合说明书附图对本发明进行进一步详述：
图2所示为按照本发明的AlGaN/GaN HEMT的一个实施例，按照本发明的AlGaN/GaNHEMT具有衬底21，衬底21为蓝宝石、Si及SiC中的任意一种，优选地采用半绝缘的4H-SiC和半绝缘的6H-SiC作为衬底，采用半绝缘的4H-SiC(0001)和半绝缘的6H-SiC(0001)作为衬底，它们具有热导率高、与GaN晶格失配小等特点，不仅易于生长高质量的GaN外延材料，同时也有利于器件的散热，目前美国的Cree公司和II-VI公司都有4H和6H两种形态的SiC衬底出售。
GaN缓冲层22位于衬底21至上，GaN缓冲层厚度优选的为1500-2000nm，GaN缓冲层22一般都具有较高的背景载流子浓度，不利于器件击穿的提高，因此可以考虑对其进行Fe掺杂，关于Fe掺杂技术可以参考相关文献，但是必须要控制Fe掺杂的浓度和厚度，Fe掺杂的 浓度一般要控制在4×1018cm-3以内，且掺杂厚度由衬底向上不超过500-1000nm，也就是GaN缓冲层的顶部1000nm左右的厚度要保持非掺杂。为了获得良好质量的GaN缓冲层，一般的位于GaN缓冲层22和衬底21之间还存在一成核层，成核层的主要用来作为过渡作用，以减小由于GaN缓冲层22和衬底21晶格失配所引入的应力，成核层的选取与衬底材料有关，这在本领域是众所周知的，不再进一步描述。
AlyGa1-yN插入层23位于GaN缓冲层上，其中0.35≤y≤0.5，AlyGa1-yN插入层23最优的厚度为1-3nm，AlyGa1-yN插入层23与GaN缓冲层22界面处的带隙大于GaN缓冲层，这样将在GaN缓冲层22和AlyGa1-yN插入层23界面靠近GaN缓冲层处形成一三角形势阱，加上III族氮化物自身较强的自发极化和压电极化效应，使得在GaN缓冲层22和AlyGa1-yN插入层23界面附近形成具有高面密度的二维电子气。
AlxGa1-xN势垒层24位于GaN缓冲层22相对的位于AlyGa1-yN插入层23上，其中0.2≤x≤0.28，AlxGa1-xN势垒层24最优的厚度为10-20nm，利用AlxGa1-xN势垒层24的自发极化和压电极化效应，可以使得GaN缓冲层22和AlyGa1-yN插入层23界面靠近GaN缓冲层处形成的三角形势阱更深，从而获得更高面密度的2DEG，有助于器件性能的提升。
GaN帽层25位于AlxGa1-xN势垒层24上，GaN帽层最优的厚度为1-3nm，GaN帽层25的作用是平衡AlyGa1-yN插入层23和AlxGa1-xN势垒层24所引入的应变力，同时可对AlGaN/GaNHEMT普遍存在的电流崩塌效应启动抑制作用，提升器件的微波性能。
GaN缓冲层22(连同GaN缓冲层22和衬底21之间的成核层)、AlyGa1-yN插入层23、AlxGa1-xN势垒层24、GaN帽层25可以采用如MOCVD、RF-MBE等任何合适的生长方法在衬底21上依次外延生长得到，优选的采用MOCVD的方法。
源电极26和漏电极27下的GaN帽层25和部分厚度的AlxGa1-xN势垒层24被去除形成凹槽，凹槽的形成需要通过干法刻蚀的方法获取，对于干法刻蚀去除GaN和AlGaN两种化合物在本领域是众所周知的，可参考相关文献，凹槽中提供源电极和漏电极，源电极和漏电极部分位于GaN帽层上形成“Г”型的源电极和漏电极，源漏电极26和漏电极27采用相同的金属层，包括但不仅限于Ti/Al/Ni/Au、Ti/Al/Mo/Au等多层金属体系，并且要通过高温合金与2DEG形成欧姆接触，优选的合金温度为680-780℃。
源电极26和漏电极27之间提供栅电极28，栅电极28的作用一个方面是与GaN帽层25形成肖特基接触，从而在器件工作的时候，栅电极28上的电压变化能够调制沟道中二维电子气；另外一个作用是降低器件的栅阻，提升器件的频率特性，栅电极28可采用的金属包括但不限于Ni/Au/Ti或者Ni/Pt/Au/Pt/Ti或则Ni/Pt/Au/Ni等多层金属体系。
图3所示为按照本发明的AlGaN/GaN HEMT的另一个个实施例，其在第一个实施例的基础上增加了AlzGa1-zN插入层35，所述AlzGa1-zN插入层35位于AlxGa1-xN势垒层34上，其中0.3≤z≤0.4，AlzGa1-zN插入层35的厚度为1-3nm，利用AlzGa1-zN插入层35的自发极化和压电极化效应，进一步提升GaN缓冲层32和AlyGa1-yN插入层33界面靠近GaN缓冲层处形成的2DEG面密度，进一步提升器件性能。
需要说明的是本发明两个实施例中位于GaN缓冲层上的高Al组分AlGaN插入层的目的是提升沟道中2DEG的面密度和迁移率，以达到图1中AlN插入层的效果，同时由于高Al组分AlGaN插入与GaN缓冲层的晶格失配相较AlN插入层来的小，因此可以设计的更厚，有利于工艺过程中更加精确的控制。另外GaN帽层的作用主要是用来平衡其下的AlGaN插入层和 AlGaN势垒层等用于与GaN缓冲层晶格失配带来的应力，由于GaN帽层的引入会引起沟道中2DEG面密度的降低，因此其厚度势必不能太厚。GaN帽层由于与AlGaN插入层和AlGaN势垒层晶格失配大，承受了较大的压应力，使得其对沟道中2DEG浓度的降低作用进一步增强，通过引入“Г”型的源电极和漏电极后可以释放GaN帽层受到的部分应力，缓解GaN帽层引入对沟道中2DEG浓度的降低作用，起到对器件性能和可靠性的折中。“Г”型的源电极和漏电极引入后，更利于沟道中电子通过遂穿效应进入源电极或者漏电极，反之亦然，从而起到降低器件欧姆接触电阻的作用，这有助于进一步改善器件性能。

Claims (6)

  1. 一种铝镓氮化合物/氮化镓高电子迁移率晶体管，其特征在于：包括自下而上依次设置的衬底(21)，GaN缓冲层(22)，AlyGa1-yN插入层(23)，0.35≤y≤0.5，AlxGa1-xN势垒层(24)，0.2≤x≤0.28，GaN帽层(25)，在GaN帽层的两端设置源电极(26)和漏电极(27)，源电极(26)和漏电极(27)所处位置的GaN帽层和部分厚度的AlxGa1-xN势垒层被去除形成凹槽，所述源电极(26)和漏电极(27)设置在凹槽内，在源电极(26)和漏电极(27)之间设置栅电极(28)。
  2. 根据权利要求1所述的一种铝镓氮化合物/氮化镓高电子迁移率晶体管，其特征在于：还包括位于AlxGa1-xN势垒层(24)上的AlzGa1-zN插入层(35)，其中0.30≤z≤0.4，AlzGa1- zN插入层(35)厚度为1-3nm。
  3. 根据权利要求1所述的一种铝镓氮化合物/氮化镓高电子迁移率晶体管，其特征在于：所述GaN缓冲层(22)进行了Fe掺杂，Fe掺杂的浓度不大于4×1018cm-3，且掺杂厚度由衬底向上介于500-1000nm。
  4. 根据权利要求1所述的一种铝镓氮化合物/氮化镓高电子迁移率晶体管，其特征在于：衬底(21)为碳化硅、硅或者蓝宝石中的一种。
  5. 根据权利要求1所述的一种铝镓氮化合物/氮化镓高电子迁移率晶体管，其特征在于：GaN缓冲层(22)厚度为1500-2000nm。
  6. 根据权利要求1所述的一种铝镓氮化合物/氮化镓高电子迁移率晶体管，其特征在于：源电极(26)和漏电极(27)部分位于GaN帽层(25)上形成“Г”型。
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