CN113363320B - 降低栅极漏电的p-GaN栅增强型GaN-HEMT器件及其制作方法 - Google Patents

降低栅极漏电的p-GaN栅增强型GaN-HEMT器件及其制作方法 Download PDF

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CN113363320B
CN113363320B CN202110622461.2A CN202110622461A CN113363320B CN 113363320 B CN113363320 B CN 113363320B CN 202110622461 A CN202110622461 A CN 202110622461A CN 113363320 B CN113363320 B CN 113363320B
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施媛媛
张敏
倪志龙
王彪
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Shanghai Xiyuan New Energy Technology Co ltd
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Abstract

本发明公开了一种降低栅极漏电的p‑GaN栅增强型GaN‑HEMT器件及其制作方法，其包括从下至上依次排布的衬底、GaN缓冲层和AlGaN势垒层，AlGaN势垒层上设置有由AlN高势垒层、p‑GaN层和栅极组成的栅极结构；位于栅极结构两侧的AlGN势垒层上设置有源极和漏极；栅极与源极、栅极与漏极之间的AlGN势垒层上设置钝化层；栅极金属下方形成p‑GaN/AlN/AlGaN/GaN的p‑i‑n结势垒耗尽栅极下方沟道处二维电子气，使器件在零栅压下处于关断状态。本发明在p‑GaN和AlGaN沟道层之间插入1～2nm的AlN高势垒层，由于该AlN高势垒层具有较低电子亲和势和较高的禁带宽度，从而能够使既能限制沟道电子向p‑GaN层输运，又能抑制p‑GaN层空穴向沟道注入，从而降低正常工作中栅电流，进而能够提高增强型GaN‑HEMT器件的安全可靠性。

Description

降低栅极漏电的p-GaN栅增强型GaN-HEMT器件及其制作方法
技术领域
本发明属于微电子技术领域，涉及增强型GaN-HEMT材料，尤其涉及一种降低栅极漏电的p-GaN栅增强型GaN-HEMT器件及其制作方法。
背景技术
因具有宽带隙、高饱和漂移速度、高热导率等突出优点，GaN材料极大提高功率器件的耐压容量、工作频率和电流密度，大大降低了导通损耗。GaN功率器件具有大功率运行能力和高温条件下工作能力，是现代电力转换系统中的核心器件。
GaN器件要实现增强型工作模式，才能应用在功率电路中。而AlGaN/GaN异质结界面具有高浓度二维电子气(2DEG)，传统的肖特基栅GaN-HEMT器件为耗尽型器件。p-GaN型栅结构利用PN结势垒耗尽栅下沟道处电子，实现从耗尽型到增强型的转变，是目前业界广泛应用的一种增强型GaN-HEMT功率器件。在一定栅压下，p-GaN栅增强型GaN-HEMT功率器件中栅极下方p-GaN层中空穴注入沟道，吸引沟道电子形成电导调制，具有较高的电流驱动能力。但是高栅压下p-GaN层空穴向沟道注入使得GaN-HEMT器件的栅电流迅速增加，降低器件安全工作栅压，导致栅极退化，从而限制了栅极可靠性。栅漏电的增加还会增加GaN-HEMT器件在功率电路中的功耗，降低其功率转换效率。
因此，通过进一步优化其栅结构设计来降低增强型GaN-HEMT器件栅电流具有必要性和紧迫性。
发明内容
本发明目的旨在针对传统的p-GaN栅增强型GaN-HEMT器件结构存在的栅电流过高引起器件应用限制及栅极退化问题，提供一种新型p-GaN增强型GaN-HEMT器件，通过在p-GaN层和AlGaN势垒层之间插入一薄层AlN高势垒层，降低正常工作中栅电流，提高器件的安全栅压摆幅，避免栅极退化，提高栅极可靠性。
为了达到上述目的，本发明采取以下技术方案来实现。
本发明提供的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件，其包括从下至上依次排布的衬底、GaN缓冲层和AlGaN势垒层，AlGaN势垒层上设置有由AlN高势垒层、p-GaN层和栅极组成的栅极结构；位于栅极结构两侧的AlGN势垒层上设置有源极和漏极；所述栅极与源极、栅极与漏极之间的AlGaN势垒层上设置钝化层；栅极下方形成p-GaN/AlN/AlGaN/GaN的p-i-n结势垒耗尽栅极下方沟道处二维电子气(2DEG)，使器件在零栅压下处于关断状态。
上述p-GaN栅增强型GaN-HEMT器件，GaN缓冲层、AlGaN势垒层、AlN高势垒层、p-GaN层、栅极、源极、漏极和钝化层的结构尺寸可以根据工艺要求设计；在优选实施方案中，GaN缓冲层厚度为1～3μm；AlGaN势垒层厚度为5～15nm；AlN高势垒层厚度为1～2nm；p-GaN层厚度为30～120nm，空穴浓度为1×1017～5×1017cm-3；栅极厚度为50～200nm；源极和漏极厚度相等，厚度为200～500nm。
上述p-GaN栅增强型GaN-HEMT器件，AlGaN势垒层中Al组分占Al和Ga组分总质量的百分比为10～30％。
上述p-GaN栅增强型GaN-HEMT器件，在p型GaN和AlGaN势垒层之间插入薄层AlN高势垒层。由于AlN材料具有较低电子亲和势(2.1eV)，较高的禁带宽度(6.2eV)，而GaN材料的电子亲和势和禁带宽度均为3.4eV。因此，AlN高势垒层导带能量高度高于AlGaN和GaN材料，限制沟道电子向p-GaN层输运。特别的，AlN高势垒层价带能量高度低于AlGaN和GaN材料，能抑制p-GaN层空穴向沟道注入。因此，AlN层能同时作为栅极电子和空穴的高势垒层，抑制高栅压下电子和空穴的输运，降低正常工作中栅电流，对提高增强型器件的安全栅压摆幅具有重要意义。
本发明进一步提供了上述p-GaN栅增强型GaN-HEMT器件的制作方法，包括以下步骤：
S1采用MOCVD方法在衬底上依次外延生长GaN缓冲层、AlGaN势垒层、AlN高势垒层和p-GaN层的异质结外延结构，形成p-GaN/AlN/AlGaN/GaN异质结结构；
S2对p-GaN/AlN/AlGaN/GaN外延材料进行光刻和干法ICP干法刻蚀，形成有源区台面；
S3在步骤S2基础上，对制备好台面的p-GaN/AlN/AlGaN/GaN外延片上进行光刻，保留栅极区域，然后采用ICP干法刻蚀技术，将栅极区域外p-GaN层和AlN高势垒层刻蚀；
S4在步骤S3基础上，对器件进行光刻，形成源极和漏极待蒸镀区域，然后采用电子束蒸镀技术在源极和漏极待蒸镀区域进行金属沉积，并进行退火处理，形成欧姆接触。
S5在步骤S4基础上，对器件进行光刻，形成栅极待蒸镀区域，然后采用电子束蒸镀技术在栅极待蒸镀区域进行金属沉积，形成与p-GaN层肖特基接触的栅极；
S6在步骤S5基础上，利用PECVD生长技术制备钝化层；
S7在步骤S6基础上，对器件进行光刻，刻蚀栅极和源漏极金属上方的钝化层。
上述p-GaN栅增强型GaN-HEMT器件，基于MOCVD外延生长技术是制备的p-GaN/AlN/AlGaN/GaN外延层，界面质量良好，缺陷浓度较低。所述光刻、ICP干法刻蚀技术、PECVD技术均采用本领域已经披露的常规技术来实现。
与现有技术相比，本发明提供的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件具有以下有益效果：
(1)本发明在p-GaN和AlGaN势垒层之间插入1～2nm的AlN高势垒层，由于该AlN高势垒层具有较低电子亲和势和较高的禁带宽度，从而能够使既能限制沟道电子向p-GaN层输运，又能抑制p-GaN层空穴向沟道注入，从而降低正常工作中栅电流，进而能够提高增强型GaN-HEMT器件的安全可靠性。
(2)本发明插入的AlN高势垒层只有1～2nm，虽然有可能增加栅下沟道处二维电子气浓度，但可以通过适当降低AlGaN势垒层厚度来维持器件的阈值电压。
(3)本发明插入的AlN层能够在外延生长p-GaN条件下生长，不需要增加额外的制备工艺条件；因此，传统GaN-HEMT器件加工设备均可满足要求，适于在本领域内推广，具有良好的市场前景。
附图说明
图1为本发明降低栅极漏电的p-GaN增强型GaN-HEMT器件的结构示意图；
附图中，1-衬底，2-GaN缓冲层，3-AlGaN势垒层，4-AlN高势垒层，5-p-GaN层，6-栅极，7-钝化层，8-源极，9-漏极。
图2为实施例1中p-GaN增强型GaN-HEMT器件的能带图。
图3为实施例1中p-GaN增强型GaN-HEMT器件与金属/60nm p-GaN/15nm AlGaN/3μmGaN/衬底(对比器件，无AlN高势垒层)在不同栅压下的漏极电流对比图。
图4为实施例1中p-GaN增强型GaN-HEMT器件与金属/60nm p-GaN/15nm AlGaN/3μmGaN/衬底(对比器件，无AlN高势垒层)在不同栅压下的栅电流对比图。
具体实施方式
拟结合附图对本发明各实施例的技术方案进行清楚、完整的描述。显然，所描述实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所得到的所有其它实施例，都属于本发明。
实施例1
本实施例发明提供的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件，如图1所示，其包括从下至上依次排布的衬底1、GaN缓冲层2和AlGaN势垒层3，AlGaN势垒层3上设置有由AlN高势垒层4、p-GaN层5和栅极6组成的栅极结构；位于栅极结构两侧的AlGN势垒层上设置有源极8和漏极9；所述栅极与源极、栅极与漏极之间的AlGN势垒层上设置钝化层7。本实施例，栅极p-GaN/AlN/AlGaN/GaN形成p-i-n结，消耗栅极下方AlGaN/GaN沟道处二维电子气，使器件在零栅压下处于关断状态，实现增强型。这样的结构可以使得器件需要施加正向的大于阈值电压的栅压，栅极下方二维电子气体恢复后，器件处于导通状态；当栅压小于阈值电压时处于器件处于截止状态。
上述p-GaN栅增强型GaN-HEMT器件，GaN缓冲层、AlGaN势垒层、AlN高势垒层、p-GaN层、栅极、源极、漏极和钝化层的结构尺寸可以根据工艺要求设计。其中，GaN缓冲层厚度为1～3μm；AlGaN势垒层厚度为5～15nm；AlN高势垒层厚度为1～2nm；p-GaN层厚度为30～120nm，通过掺杂Mg控制空穴浓度为1×1017～5×1017cm-3；栅极厚度为50～200nm；源极和漏极厚度相等，厚度为200～500nm；钝化层高度与源极和漏极厚度相等。
上述AlGaN势垒层中Al组分占Al和Ga组分总质量的百分比为10～30％。
为了对本实施例提供的p-GaN栅增强型GaN-HEMT器件性能进行说明，本实施例以满足如下尺寸要求的p-GaN栅增强型GaN-HEMT器件为例，对其进行了仿真分析，并将其与对比器件(金属/60nm p-GaN/15nm AlGaN/3μm GaN/衬底器件)的器件性能进行了对比分析。该p-GaN栅增强型GaN-HEMT器件具体尺寸如下：GaN缓冲层厚度为3μm；AlGaN势垒层厚度为10nm，AlGaN势垒层中Al组分占Al和Ga组分总质量的百分比为20％；AlN高势垒层厚度为1nm；p-GaN层厚度为60nm，通过掺杂Mg控制空穴浓度为3×1017cm-3；栅极厚度为150nm；源极和漏极厚度相等，厚度为300nm；钝化层为Si3N4钝化层，钝化层的厚度与源极和漏极相同。
对p-GaN栅增强型GaN-HEMT器件，通过仿真分析在零栅压下p-GaN/AlN/AlGaN/GaN异质结结构能带，分析结果如图2所示。从图中可以看出，AlN高势垒层导带能量高度高于AlGaN和GaN材料，且AlN高势垒层的电子亲和势低于AlGaN和GaN材料，能阻挡沟道电子向p-GaN层输运；特别的，AlN层价带能量低于AlGaN和GaN材料，能阻挡p-GaN层空穴向AlGaN层以及GaN沟道层注入，从而能降低器件的栅电流。
以金属/60nm p-GaN/15nm AlGaN/3μm GaN/衬底器件作为对比器件，与本发明所提出的金属/60nm p-GaN/1nm AlN/10nm AlGaN/3μm GaN/衬底，区别在于减少了AlN高势垒层，AlGaN势垒层厚度为15nm，对这两种器件进行仿真分析。对本发明所提出具有AlN高势垒层的的p-GaN栅增强型GaN-HEMT器件与对比器件施加栅压，测量当栅压从0增加到10V时，两者的漏极电流对比图如图3所示，和栅电流对比图4所示。从图3中可以看出，AlGaN层厚度变化使得两种结构具有可类比的工作电流及阈值电压。从图4可以看出，本实施例制备的p-GaN栅增强型GaN-HEMT器件，在保持GaN-HEMT功率器件正常工作电流的条件下，AlN高势垒层的引入，GaN-HEMT功率器件在高栅压下的栅电流下降两个数量级，进而能增加GaNHEMT功率器件的安全工作栅压范围，提高其栅极可靠性。
综上所述，本发明所述的p-GaN栅增强型GaN-HEMT器件，AlN作为高势垒层降低器件栅电流的工作原理表现在两个方面：
(1)AlN层电子亲和势能低于AlGaN层和GaN层，在高栅压下降低沟道中的电子向p-GaN层输运；
(2)特别的，AlN层价带能量高度低于pGaN层和AlGaN层，在高栅压下抑制p-GaN层的空穴向AlGaN层和GaN沟道层输运。
实施例2
本实施例提供了制作实施例1中降低栅极漏电的p-GaN栅增强型GaN-HEMT器件的制作方法，包括以下步骤：
S1采用MOCVD外延生长技术在硅基衬底上依次外延生长GaN缓冲层、AlGaN势垒层、AlN高势垒层和p-GaN层，形成p-GaN/AlN/AlGaN/GaN异质结结构；
S2对p-GaN/AlN/AlGaN/GaN外延材料进行光刻和干法ICP干法刻蚀，形成有源区台面；
S3在步骤S2基础上，对制备好台面的p-GaN/AlN/AlGaN/GaN外延片上进行光刻，保留栅极区域，然后采用ICP干法刻蚀技术，纵向去除栅极区域外p-GaN层和AlN高势垒层；
S4在步骤S3基础上，对器件进行光刻，形成源极和漏极待蒸镀区域，然后采用电子束蒸镀技术在源极和漏极待蒸镀区域进行金属沉积，并进行850℃退火处理，与AlGaN势垒层形成欧姆接触，制得源极和漏极。
S5在步骤S4基础上，对器件进行光刻，形成栅极待蒸镀区域，然后采用电子束蒸镀技术在栅极待蒸镀区域进行金属沉积，与p-GaN层形成肖特基接触，得到栅极。
S6在步骤S5基础上，利用PECVD生长技术制备钝化层，保护器件。
S7在步骤S6基础上，对器件进行光刻，去除栅极、源极和漏极上方的钝化层，暴露出源极、漏极和栅极。
本领域的普通技术人员将会意识到，这里所述的实施例是为了帮助读者理解本发明的原理，应被理解为本发明的保护范围并不局限于这样的特别陈述和实施例。本领域的普通技术人员可以根据本发明公开的这些技术启示做出各种不脱离本发明实质的其它各种具体变形和组合，这些变形和组合仍然在本发明的保护范围内。

Claims (5)

1.一种降低栅极漏电的p-GaN栅增强型GaN-HEMT器件，其特征在于，包括从下至上依次排布的衬底、GaN缓冲层和AlGaN势垒层，AlGaN势垒层上设置有由AlN高势垒层、p-GaN层和栅极组成的栅极结构；位于栅极结构两侧的AlGN势垒层上设置有源极和漏极；所述栅极与源极、栅极与漏极之间的AlGaN势垒层上设置钝化层；栅极下方形成p-GaN/AlN/AlGaN/GaN的p-i-n结势垒耗尽栅极下方沟道处二维电子气，使器件在零栅压下处于关断状态。
2.根据权利要求1所述的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件，其特征在于，GaN缓冲层厚度为1～3μm；AlGaN势垒层厚度为5～15nm；AlN高势垒层厚度为1～2nm；p-GaN层厚度为30～120nm；栅极厚度为50～200nm；源极和漏极厚度相等，厚度为200～500nm。
3.根据权利要求1或2所述的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件，其特征在于，AlGaN势垒层中Al组分占Al和Ga组分总质量的百分比为10～30％。
4.根据权利要求1所述的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件，其特征在于，p-GaN层中空穴浓度为1×1017～5×1017cm-3。
5.权利要求1至4任一权利要求所述的降低栅极漏电的p-GaN栅增强型GaN-HEMT器件的制作方法，包括以下步骤：
S1采用MOCVD方法在衬底上依次外延生长GaN缓冲层、AlGaN势垒层、AlN高势垒层和p-GaN层的异质结外延结构，形成p-GaN/AlN/AlGaN/GaN异质结结构；
S2对p-GaN/AlN/AlGaN/GaN外延材料进行光刻和干法ICP干法刻蚀，形成有源区台面；
S3在步骤S2基础上，对制备好台面的p-GaN/AlN/AlGaN/GaN外延片上进行光刻，保留栅极区域，然后采用ICP干法刻蚀技术，将栅极区域外p-GaN层和AlN高势垒层刻蚀；
S4在步骤S3基础上，对器件进行光刻，形成源极和漏极待蒸镀区域，然后采用电子束蒸镀技术在源极和漏极待蒸镀区域进行金属沉积，并进行退火处理，形成欧姆接触；
S5在步骤S4基础上，对器件进行光刻，形成栅极待蒸镀区域，然后采用电子束蒸镀技术在栅极待蒸镀区域进行金属沉积，形成与p-GaN层肖特基接触的栅极；
S6在步骤S5基础上，利用PECVD生长技术制备钝化层；
S7在步骤S6基础上，对器件进行光刻，刻蚀栅极和源漏极金属上方的钝化层。
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