WO2017113451A1 - 半导体层结构及其制备方法 - Google Patents

半导体层结构及其制备方法 Download PDF

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Publication number
WO2017113451A1
WO2017113451A1 PCT/CN2016/071710 CN2016071710W WO2017113451A1 WO 2017113451 A1 WO2017113451 A1 WO 2017113451A1 CN 2016071710 W CN2016071710 W CN 2016071710W WO 2017113451 A1 WO2017113451 A1 WO 2017113451A1
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Prior art keywords
semiconductor layer
access terminal
signal access
layer pattern
body portions
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English (en)
French (fr)
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赵瑜
张占东
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/915,225 priority Critical patent/US10109648B2/en
Publication of WO2017113451A1 publication Critical patent/WO2017113451A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer

Definitions

  • the present invention relates to the field of display, and in particular to a semiconductor layer structure in a thin film transistor, and a method of fabricating the semiconductor layer structure.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • ppi pixel per inch
  • the thin film transistor production process is to form a traditional metal oxide semiconductor layer structure, the mobility of electrons in amorphous silicon is 0.5-1.0, the mobility in polycrystalline silicon is 30-300, and the process causes the migration of electrons to be reduced. rate. Therefore, designing a semiconductor layer and a thin film transistor with reduced resistance to increase the charging speed has become an urgent problem to be solved.
  • the present invention provides a semiconductor layer structure including an insulating substrate and a semiconductor layer on the insulating substrate.
  • the semiconductor layer includes a source signal access terminal, a drain signal access terminal, a first semiconductor layer pattern, and a second semiconductor layer pattern.
  • the first semiconductor layer pattern and the second semiconductor layer pattern are disposed in parallel between the source signal input terminal and the drain signal access terminal.
  • the semiconductor layer structure further includes a buffer layer between the semiconductor layer and the insulating substrate.
  • first semiconductor layer pattern and the second semiconductor layer pattern both have an "n" shape and straddle between the source signal input terminal and the drain signal access terminal.
  • the first semiconductor layer pattern includes two first body portions and a first connecting portion connecting the two first body portions, wherein two ends of the first body portion are respectively connected to the source signal input terminal and The first connecting portion is connected, and the two ends of the other first main body portion are respectively connected to the drain signal access terminal And the first connecting portion is connected, the second semiconductor layer pattern includes two second body portions and a second connecting portion connecting the two second body portions, wherein two ends of the second body portion and the source are respectively The signal access terminal and the second connecting portion are connected, and two ends of the other second main body portion are respectively connected to the drain signal access terminal and the second connecting portion.
  • first body portions are parallel to the two second body portions, and the first connecting portion is parallel to the second connecting portion.
  • the insulating substrate is a glass substrate.
  • a thin film transistor comprising the semiconductor layer structure as described above.
  • a semiconductor layer structure preparation method comprising the steps of: providing an insulating substrate; forming a semiconductor layer on the insulating substrate, the semiconductor layer comprising a source signal access terminal, a drain signal access terminal, and a first semiconductor layer And a pattern and a second semiconductor layer pattern, the first semiconductor layer pattern and the second semiconductor layer pattern being disposed in parallel between the source signal input terminal and the drain signal access terminal.
  • a semiconductor layer structure preparation method comprising the steps of: providing an insulating substrate; forming a buffer layer on the insulating substrate; forming a semiconductor layer on the buffer layer, the semiconductor layer including a source signal access terminal, and a drain a pole signal access terminal, a first semiconductor layer pattern, and a second semiconductor layer pattern, the first semiconductor layer pattern and the second semiconductor layer pattern being disposed in parallel between the source signal input terminal and the drain signal access terminal .
  • the first semiconductor layer pattern includes two first body portions and a first connecting portion connecting the two first body portions, wherein two ends of the first body portion are respectively connected to the source signal input terminal and The first connecting portion is connected, and the two ends of the other first main body portion are respectively connected to the drain signal access terminal and the first connecting portion
  • the second semiconductor layer pattern comprises two second main body portions and one connecting two a second connecting portion of the second main body portion, wherein two ends of the second main body portion are respectively connected to the source signal access terminal and the second connecting portion, and the two ends of the other second main body portion respectively and the drain The pole signal access terminal is connected to the second connecting portion.
  • the semiconductor layer structure, the thin film transistor, and the semiconductor layer structure preparation method provided by the present invention can reduce the resistance and improve the charging speed of the thin film transistor having the semiconductor layer structure by disposing the first semiconductor layer pattern and the second semiconductor layer pattern in parallel; On the other hand, when the first semiconductor layer pattern If a defect occurs on the pixel, the first semiconductor layer pattern in which the defect occurs may be cut off. At this time, the second semiconductor layer pattern maintains the channel conduction to ensure the normal operation of the semiconductor layer structure.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a semiconductor layer according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view showing a semiconductor layer of the semiconductor layer structure of FIG. 1.
  • a semiconductor layer structure 10 provided by an embodiment of the present invention is an indispensable part of a thin film transistor.
  • the semiconductor layer structure 10 includes an insulating substrate 12, a buffer layer 14, and a semiconductor layer 16.
  • the insulating substrate 12 may be a glass substrate.
  • the buffer layer 14 and the semiconductor layer 16 are sequentially pasted on the insulating substrate 12, and the buffer layer 14 is located between the semiconductor layer 16 and the insulating substrate 12. In other words, the buffer layer 14 is attached on both sides.
  • the semiconductor layer 16 includes a source signal access terminal 160 , a drain signal access terminal 161 , a first semiconductor layer pattern 162 , and a second semiconductor layer pattern 164 .
  • the source signal access terminal 160 and the drain signal access terminal 161 are spaced apart from each other on the buffer layer 14 .
  • the first semiconductor layer pattern 162 and the second semiconductor layer pattern 164 both have an "n" shape and straddle between the source signal input terminal 160 and the drain signal access terminal 161.
  • the first semiconductor layer pattern 162 includes two first body portions 165 and a first connecting portion 166 connecting the two first body portions 165.
  • the two ends of the first main body portion 165 are respectively connected to the source signal access terminal 160 and the first connecting portion 166, and the two ends of the other first main body portion 165 are respectively connected to the drain signal access terminal 161 and The first connecting portion 166 is connected.
  • the second semiconductor layer pattern 164 includes two second body portions 167 and a second connecting portion 168 connecting the two second body portions 167, wherein two ends of the second body portion 167 are respectively connected to the source signal.
  • the terminal 160 and the second connecting portion 168 are connected, and the other ends of the other second main body portion 167 are respectively connected to the drain signal access terminal 161 and the second connecting portion 168.
  • the two first body portions 165 are parallel to the two second body portions 167
  • the first connecting portion 166 is parallel to the second connecting portion 168 .
  • the second semiconductor layer pattern 164 is housed in the first semiconductor layer pattern 162.
  • the semiconductor layer structure 10 is provided with the first semiconductor layer pattern 162 and the second semiconductor layer pattern 164 in parallel, which can reduce the electric resistance and improve the charging speed of the thin film transistor having the semiconductor layer structure 10; on the other hand, when the first semiconductor If a defect occurs in the layer pattern 162 to cause a pixel abnormality, the defective first semiconductor layer pattern 162 can be cut off, and at this time, the second semiconductor layer pattern 164 remains in the channel conduction.
  • the buffer layer 14 can be omitted.
  • the first semiconductor layer pattern 162 and the second semiconductor layer pattern 164 are not limited to the "n" shape in the present embodiment, and may be other arbitrary shapes such as a wave shape, a spiral shape, an inverted V shape, and the like, and only need to satisfy the first semiconductor.
  • the layer pattern 162 and the second semiconductor layer pattern 164 do not overlap each other, and can be electrically connected to the source signal access terminal 160 and the drain signal access terminal 161.
  • an embodiment of the present invention provides a method for fabricating a semiconductor layer structure including the following steps:
  • An insulating substrate 12 is provided, which may be a glass substrate.
  • a buffer layer 14 is formed on the insulating substrate 12.
  • a semiconductor layer 16 is formed on the buffer layer 14.
  • the semiconductor layer 16 includes a source signal access terminal 160, a drain signal access terminal 161, a first semiconductor layer pattern 162, and a second semiconductor layer pattern 164.
  • the source signal access terminal 160 and the drain signal access terminal 161 are spaced apart Placed on the buffer layer 14.
  • the first semiconductor layer pattern 162 and the second semiconductor layer pattern 164 both have an "n" shape and straddle between the source signal input terminal 160 and the drain signal access terminal 161.
  • the first semiconductor layer pattern 162 includes two first body portions 165 and a first connecting portion 166 connecting the two first body portions 165, wherein two ends of the first body portion 165 and the source are respectively The signal access terminal 160 and the first connection portion 166 are connected, and the other ends of the other first body portion 165 are respectively connected to the drain signal access terminal 161 and the first connection portion 166.
  • the second semiconductor layer pattern 164 includes two second body portions 167 and a second connecting portion 168 connecting the two second body portions 167, wherein two ends of the second body portion 167 are respectively connected to the source signal.
  • the terminal 160 and the second connecting portion 168 are connected, and the other ends of the other second main body portion 167 are respectively connected to the drain signal access terminal 161 and the second connecting portion 168.
  • the two first body portions 165 are parallel to the two second body portions 167
  • the first connecting portion 166 is parallel to the second connecting portion 168 .
  • the second semiconductor layer pattern 164 is housed in the first semiconductor layer pattern 162.
  • the semiconductor layer structure 10 prepared by the semiconductor layer structure preparation method is provided with a first semiconductor layer pattern 162 and a second semiconductor layer pattern 164 in parallel, which can reduce the resistance and improve the charging speed of the thin film transistor having the semiconductor layer structure 10;
  • the defective first semiconductor layer pattern 162 can be trimmed, and at this time, the second semiconductor layer pattern 164 remains in the channel conduction.
  • the buffer layer 14 is formed on the insulating substrate 12, and the semiconductor layer 16 is directly formed on the insulating substrate 12.
  • the first semiconductor layer pattern 162 and the second semiconductor layer pattern 164 are not limited to the "n" shape in the present embodiment, and may be other arbitrary shapes such as a wave shape, a spiral shape, an inverted V shape, and the like, and only need to satisfy the first semiconductor.
  • the layer pattern 162 and the second semiconductor layer pattern 164 do not overlap each other, and can be electrically connected to the source signal access terminal 160 and the drain signal access terminal 161.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种半导体层结构（10），包括绝缘衬底（12）及位于该绝缘衬底（12）上的半导体层（16）。该半导体层（16）包括源极信号接入端子（160）、漏极信号接入端子（161）、第一半导体层图案（162）以及第二半导体层图案（164）。该第一半导体层图案（162）及第二半导体层图案（164）并联设置在该源极信号接入端子（160）与该漏极信号接入端子（161）之间。同时提供了一种半导体层结构（10）的制备方法。

Description

半导体层结构及其制备方法 技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管中的半导体层结构、一种制备该半导体层结构的方法。
背景技术
目前薄膜晶体管液晶显示屏(Thin Film Transistor Liquid Crystal Display，TFT-LCD)正向高像素/英寸(pixel per inch,ppi)方向发展，而限制高ppi发展的一大阻碍就是薄膜晶体管的充电速度。薄膜晶体管生产工艺都是形成传统的金属氧化物半导体层结构，电子在非晶硅中的迁移率为0.5-1.0，在多晶硅中的迁移率为30-300，同时工艺原因也会降低电子的迁移率。因此，设计出一种降低电阻的半导体层及薄膜晶体管以提高充电速度成为亟需解决的问题。
发明内容
为了解决上述技术问题，本发明提供了一种半导体层结构，包括绝缘衬底及位于该绝缘衬底上的半导体层。该半导体层包括源极信号接入端子、漏极信号接入端子、第一半导体层图案以及第二半导体层图案。该第一半导体层图案及第二半导体层图案并联设置在该源极信号接入端子与该漏极信号接入端子之间。
进一步地，该半导体层结构还包括位于该半导体层与该绝缘衬底之间缓冲层。
进一步地，该第一半导体层图案及该第二半导体层图案均呈“n”形并横跨在该源极信号接入端子及该漏极信号接入端子之间。
进一步地，该第一半导体层图案包括两个第一主体部及一个连接两个第一主体部的第一连接部，其中一个第一主体部的两端分别与该源极信号接入端子及该第一连接部连接，另外一个第一主体部的两端分别与该漏极信号接入端子 及该第一连接部连接，该第二半导体层图案包括两个第二主体部及一个连接两个第二主体部的第二连接部，其中一个第二主体部的两端分别与该源极信号接入端子及该第二连接部连接，另外一个第二主体部的两端分别与该漏极信号接入端子及该第二连接部连接。
进一步地，该两个第一主体部与该两个第二主体部平行，该第一连接部与该第二连接部平行。
进一步地，该绝缘衬底为玻璃衬底。
一种薄膜晶体管，其包括如上所述的半导体层结构。
一种半导体层结构制备方法，包括如下步骤：提供一个绝缘衬底；在该绝缘衬底上形成半导体层，该半导体层包括源极信号接入端子、漏极信号接入端子、第一半导体层图案以及第二半导体层图案，该第一半导体层图案及第二半导体层图案并联设置在该源极信号接入端子与该漏极信号接入端子之间。
一种半导体层结构制备方法，包括如下步骤：提供一个绝缘衬底；在该绝缘衬底上形成一缓冲层；在该缓冲层上形成半导体层，该半导体层包括源极信号接入端子、漏极信号接入端子、第一半导体层图案以及第二半导体层图案，该第一半导体层图案及第二半导体层图案并联设置在该源极信号接入端子与该漏极信号接入端子之间。
进一步地，该第一半导体层图案包括两个第一主体部及一个连接两个第一主体部的第一连接部，其中一个第一主体部的两端分别与该源极信号接入端子及该第一连接部连接，另外一个第一主体部的两端分别与该漏极信号接入端子及该第一连接部连接，该第二半导体层图案包括两个第二主体部及一个连接两个第二主体部的第二连接部，其中一个第二主体部的两端分别与该源极信号接入端子及该第二连接部连接，另外一个第二主体部的两端分别与该漏极信号接入端子及该第二连接部连接。
本发明提供的半导体层结构、薄膜晶体管及半导体层结构制备方法通过并联设置第一半导体层图案及第二半导体层图案，一方面能够降低电阻，提高具有该半导体层结构的薄膜晶体管的充电速度；另一方面，当第一半导体层图案 上出现缺陷造成像素异常，则可以剪掉出现缺陷的第一半导体层图案，此时仍有第二半导体层图案维持沟道导电，保证半导体层结构正常运作。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施方式提供的半导体层结构的剖面结构示意图。
图2是图1中的半导体层结构的半导体层的剖面结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
第一实施方式
请参阅图1，本发明实施方式提供的半导体层结构10为薄膜晶体管的必不可少的部分。该半导体层结构10包括一个绝缘衬底12、一个缓冲层14、以及一个半导体层16。该绝缘衬底12可为玻璃衬底。该缓冲层14及该半导体层16依次贴覆在该绝缘衬底12，且该缓冲层14位于该半导体层16与该绝缘衬底12之间，换言之，该缓冲层14在两侧贴覆有该半导体层16及该绝缘衬底12。
请参阅图2，该半导体层16包括源极信号接入端子160、漏极信号接入端子161、第一半导体层图案162、以及第二半导体层图案164。该源极信号接入端子160及该漏极信号接入端子161间隔设置在该缓冲层14上。该第一半导体层图案162及该第二半导体层图案164均呈“n”形并横跨在该源极信号接入端子160及该漏极信号接入端子161之间。具体地，该第一半导体层图案162包括两个第一主体部165及一个连接两个第一主体部165的第一连接部166， 其中一个第一主体部165的两端分别与该源极信号接入端子160及该第一连接部166连接，另外一个第一主体部165的两端分别与该漏极信号接入端子161及该第一连接部166连接。该第二半导体层图案164包括两个第二主体部167及一个连接两个第二主体部167的第二连接部168，其中一个第二主体部167的两端分别与该源极信号接入端子160及该第二连接部168连接，另外一个第二主体部167的两端分别与该漏极信号接入端子161及该第二连接部168连接。本实施方式中，该两个第一主体部165与该两个第二主体部167平行，该第一连接部166与该第二连接部168平行。该第二半导体层图案164收容在该第一半导体层图案162内。
该半导体层结构10并联设置有第一半导体层图案162及第二半导体层图案164，一方面能够降低电阻，提高具有该半导体层结构10的薄膜晶体管的充电速度；另一方面，当第一半导体层图案162上出现缺陷造成像素异常，则可以剪掉出现缺陷的第一半导体层图案162，此时仍有第二半导体层图案164维持沟道导电。
可以理解，在其他实施方式中，该缓冲层14可以省略。第一半导体层图案162及第二半导体层图案164并不局限于本实施方式中的“n”形，还可以是波浪形、螺旋形、倒V形等其他任意形状，只需要满足第一半导体层图案162及第二半导体层图案164彼此无交集，并均能电性连接源极信号接入端子160及漏极信号接入端子161即可。
第二实施方式
请一并参阅图1及图2，本发明实施方式提供半导体层结构制备方法包括以下步骤：
提供一个绝缘衬底12，该绝缘衬底12可为玻璃衬底。
在该绝缘衬底12上形成一缓冲层14。
在该缓冲层14上形成一半导体层16。具体地，该半导体层16包括源极信号接入端子160、漏极信号接入端子161、第一半导体层图案162、以及第二半导体层图案164。该源极信号接入端子160及该漏极信号接入端子161间隔设 置在该缓冲层14上。该第一半导体层图案162及该第二半导体层图案164均呈“n”形并横跨在该源极信号接入端子160及该漏极信号接入端子161之间。具体地，该第一半导体层图案162包括两个第一主体部165及一个连接两个第一主体部165的第一连接部166，其中一个第一主体部165的两端分别与该源极信号接入端子160及该第一连接部166连接，另外一个第一主体部165的两端分别与该漏极信号接入端子161及该第一连接部166连接。该第二半导体层图案164包括两个第二主体部167及一个连接两个第二主体部167的第二连接部168，其中一个第二主体部167的两端分别与该源极信号接入端子160及该第二连接部168连接，另外一个第二主体部167的两端分别与该漏极信号接入端子161及该第二连接部168连接。本实施方式中，该两个第一主体部165与该两个第二主体部167平行，该第一连接部166与该第二连接部168平行。该第二半导体层图案164收容在该第一半导体层图案162内。
该半导体层结构制备方法制备出的半导体层结构10并联设置有第一半导体层图案162及第二半导体层图案164，一方面能够降低电阻，提高具有该半导体层结构10的薄膜晶体管的充电速度；另一方面，当第一半导体层图案162上出现缺陷造成像素异常，则可以剪掉出现缺陷的第一半导体层图案162，此时仍有第二半导体层图案164维持沟道导电。
可以理解，在其他实施方式中，在该绝缘衬底12上形成缓冲层14在步骤可以省略，此时，半导体层16是直接形成在该绝缘衬底12上。第一半导体层图案162及第二半导体层图案164并不局限于本实施方式中的“n”形，还可以是波浪形、螺旋形、倒V形等其他任意形状，只需要满足第一半导体层图案162及第二半导体层图案164彼此无交集，并均能电性连接源极信号接入端子160及漏极信号接入端子161即可。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (10)

  1. 一种半导体层结构，包括：
    绝缘衬底；及
    位于该绝缘衬底上的半导体层，该半导体层包括源极信号接入端子、漏极信号接入端子、第一半导体层图案以及第二半导体层图案，该第一半导体层图案及第二半导体层图案并联设置在该源极信号接入端子与该漏极信号接入端子之间。
  2. 如权利要求1所述的半导体层结构，其中，该半导体层结构还包括位于该半导体层与该绝缘衬底之间缓冲层。
  3. 如权利要求1所述的半导体层结构，其中，该第一半导体层图案及该第二半导体层图案均呈“n”形并横跨在该源极信号接入端子及该漏极信号接入端子之间。
  4. 如权利要求1所述的半导体层结构，其中，该第一半导体层图案包括两个第一主体部及一个连接两个第一主体部的第一连接部，其中一个第一主体部的两端分别与该源极信号接入端子及该第一连接部连接，另外一个第一主体部的两端分别与该漏极信号接入端子及该第一连接部连接，该第二半导体层图案包括两个第二主体部及一个连接两个第二主体部的第二连接部，其中一个第二主体部的两端分别与该源极信号接入端子及该第二连接部连接，另外一个第二主体部的两端分别与该漏极信号接入端子及该第二连接部连接。
  5. 如权利要求4所述的半导体层结构，其中，该两个第一主体部与该两个第二主体部平行，该第一连接部与该第二连接部平行。
  6. 如权利要求1所述的半导体层结构，其中，该绝缘衬底为玻璃衬底。
  7. 一种半导体层结构制备方法，包括如下步骤：
    提供一个绝缘衬底；及
    在该绝缘衬底上形成半导体层，该半导体层包括源极信号接入端子、漏极信号接入端子、第一半导体层图案以及第二半导体层图案，该第一半导体层图案及第二半导体层图案并联设置在该源极信号接入端子与该漏极信号接入端 子之间。
  8. 如权利要求7所述的半导体层结构制备方法，其中，该第一半导体层图案包括两个第一主体部及一个连接两个第一主体部的第一连接部，其中一个第一主体部的两端分别与该源极信号接入端子及该第一连接部连接，另外一个第一主体部的两端分别与该漏极信号接入端子及该第一连接部连接，该第二半导体层图案包括两个第二主体部及一个连接两个第二主体部的第二连接部，其中一个第二主体部的两端分别与该源极信号接入端子及该第二连接部连接，另外一个第二主体部的两端分别与该漏极信号接入端子及该第二连接部连接。
  9. 一种半导体层结构制备方法，包括如下步骤：
    提供一个绝缘衬底；
    在该绝缘衬底上形成一缓冲层；及
    在该缓冲层上形成半导体层，该半导体层包括源极信号接入端子、漏极信号接入端子、第一半导体层图案以及第二半导体层图案，该第一半导体层图案及第二半导体层图案并联设置在该源极信号接入端子与该漏极信号接入端子之间。
  10. 如权利要求9所述的半导体层结构制备方法，其中，该第一半导体层图案包括两个第一主体部及一个连接两个第一主体部的第一连接部，其中一个第一主体部的两端分别与该源极信号接入端子及该第一连接部连接，另外一个第一主体部的两端分别与该漏极信号接入端子及该第一连接部连接，该第二半导体层图案包括两个第二主体部及一个连接两个第二主体部的第二连接部，其中一个第二主体部的两端分别与该源极信号接入端子及该第二连接部连接，另外一个第二主体部的两端分别与该漏极信号接入端子及该第二连接部连接。
PCT/CN2016/071710 2015-12-28 2016-01-22 半导体层结构及其制备方法 Ceased WO2017113451A1 (zh)

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