WO2017113418A1 - 半导体器件及半导体器件的制备方法 - Google Patents

半导体器件及半导体器件的制备方法 Download PDF

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WO2017113418A1
WO2017113418A1 PCT/CN2015/100348 CN2015100348W WO2017113418A1 WO 2017113418 A1 WO2017113418 A1 WO 2017113418A1 CN 2015100348 W CN2015100348 W CN 2015100348W WO 2017113418 A1 WO2017113418 A1 WO 2017113418A1
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gate
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PCT/CN2015/100348
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English (en)
French (fr)
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赵静
张臣雄
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华为技术有限公司
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Priority to CN201580084892.0A priority Critical patent/CN108369946B/zh
Priority to PCT/CN2015/100348 priority patent/WO2017113418A1/zh
Publication of WO2017113418A1 publication Critical patent/WO2017113418A1/zh
Priority to US16/024,562 priority patent/US10483381B2/en

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method of fabricating the same.
  • CMOS Complementary Metal Oxide Semiconductor
  • Its size and operating voltage follow Moore's law to achieve better performance and higher integration density.
  • CMOS Complementary Metal Oxide Semiconductor
  • the power supply voltage of CMOS devices is difficult to reduce mainly because the subthreshold swing of CMOS devices is large, generally higher than 60mV/dec.
  • the Tunnel Field Effect Transistor is considered to be a better component to replace CMOS devices due to its lower leakage current and steep subthreshold slope.
  • a TFET is constructed with a conventional planar structure (such as a MOS transistor, or a capacitor or a resistor)
  • a conventional planar structure such as a MOS transistor, or a capacitor or a resistor
  • a non-planar TFET is integrated with a planar structure, a TFET is formed first, and then a planar structure is formed, and then the TFET and the planar structure are combined, which greatly increases the complexity of the process and the implementation cost.
  • the present invention provides a semiconductor device including a tunneling field effect transistor and a planar device, the tunneling field effect transistor including a first substrate and a first electrical component, the first electrical An element is formed on one side of the first substrate, the planar device includes a second substrate and a second electrical component, the second substrate and the first substrate are in a unitary structure and form a central lining a second electrical component formed on one side of the second substrate, and the second electrical component and the first electrical component are disposed on a same side of the total substrate, wherein the plane
  • the device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.
  • the first substrate includes a first surface and a second surface that are oppositely disposed
  • the second substrate includes oppositely disposed third surfaces and fourth surfaces, the first substrate is in contact with the second substrate, and the third surface is flush with the first surface, The fourth surface is flush with the third surface.
  • the first electrical component in conjunction with the first embodiment, in a second embodiment, includes a first shallow trench isolation region and a second shallow trench isolation region, the first shallow trench isolation region and the a second shallow trench isolation region is embedded in the first substrate from the first surface, and one end of the first shallow trench isolation region is flush with the first surface, the second shallow trench isolation One end of the region is flush with the first surface, and the second shallow trench isolation region is opposite to the first shallow trench isolation region and is spaced apart from the first substrate.
  • the first electrical component further includes a first drain region, a second drain region, a first source region, a first insulating layer, a first gate dielectric layer, and a first a gate region
  • the first drain region and the second drain region are embedded in the first substrate from the first surface, and one end of the first drain region is flush with the first surface, One end of the second drain region is flush with the first surface, and the first drain region is opposite to the second drain region and is disposed at the first shallow channel isolation region by a portion of the first substrate
  • the second shallow trench isolation region the first drain region is in contact with the first shallow trench isolation region, and the second drain region is in contact with the second shallow trench isolation region;
  • the first source region is convexly disposed on the first surface, and the first source region is located between the first drain region and the second drain region;
  • the first insulating layer is convexly disposed at the a first surface;
  • the first insulating layer is symmetrically disposed on two sides of the first source region
  • the first gate dielectric layer includes a first gate dielectric portion and a second gate dielectric portion, and the first gate dielectric portion is stacked on the first insulation On the layer, one end of the second gate dielectric portion is connected to the first gate dielectric portion and the second gate dielectric portion is bonded to a surface of the first source region.
  • the first gate region includes a first portion and a second portion, the first portion is stacked on the first gate dielectric portion, and the second portion One end is connected to one end of the first portion and the second portion is attached to a surface of the second gate dielectric portion.
  • the first gate dielectric layer further includes a third gate dielectric portion, the third gate dielectric portion connecting the second gate dielectric portion away from the first One end of the gate dielectric portion, and the third gate dielectric portion covers an end of the first source region away from the substrate, the first gate region further including a third portion, the third portion connecting the first portion The two portions are away from one end of the first portion, and the third portion is overlying the third gate dielectric portion.
  • the first electrical component further includes a first drain, a second drain, a first source, and two first gates, the first drain The first drain, the first source, and the two first gates respectively connect the first drain region, the second drain region, the first source region, and the a second portion of the first gate region, and two first gates are respectively disposed on opposite sides of the first source.
  • the first electrical component further includes a first isolation layer, the first isolation layer covering the first drain region, the second drain region, the first source region, and the first gate region
  • the first isolation layer is provided with a first through hole, a second through hole, a third through hole, a fourth through hole and a fifth through hole, and the first through hole is disposed corresponding to the first drain region,
  • the first drain passes through the first through hole to connect the first drain region, the second through hole corresponds to the second drain region, and the second drain passes through the second through hole Connecting the second drain region,
  • the third through hole is disposed corresponding to the first source region, and the first source passes through the third through hole to connect the first source region
  • the fourth through The hole and the fifth through hole are respectively disposed on two sides of the third through hole, and the fourth through hole and the fifth through hole are respectively disposed corresponding to the second portion of the first gate region,
  • the two first gates are connected to the second portion of the first gate region through the fourth through hole and the fifth through hole, respectively.
  • the first electrical component further includes at least one of a first ohmic contact layer, a second ohmic contact layer, a third ohmic contact layer, a third ohmic contact layer, a fourth ohmic contact layer, and a fifth ohmic contact layer
  • the first ohmic contact layer is disposed between the first drain and the first drain region to connect the first drain and the first drain region
  • the second ohmic contact a layer is disposed between the second drain and the second drain region to connect the second drain and the second drain region
  • the third ohmic contact layer is disposed on the first source
  • the fourth ohmic contact layer is disposed on the first one of the first gate and the first gate
  • the fifth ohmic contact layer is disposed on the second first gate and Between the second portions of the regions to connect the first one of the first gate and the second portion of the first gate region, Connecting a second one of
  • the first electrical component further includes a first drain, a second drain, a first source, and three first gates, the first drain The first drain, the first source, and the third first gate respectively connect the first drain region, the second drain region, the first source region, and the first The gate region is disposed, wherein the two first gates are connected to the second portion and are respectively disposed on two sides of the first source, and the other first gate is connected to the third portion.
  • the first electrical component further includes a first isolation layer, the first isolation layer covering the first drain region, the second drain region, the first source region, and the first gate region
  • the first isolation layer is provided with a first through hole, a second through hole, a third through hole, a third through hole, a fifth through hole and a sixth through hole, and the first through hole corresponds to the first through hole a drain region is disposed, the first drain passes through the first through hole to connect the first drain region, the second through hole is disposed corresponding to the second drain region, and the second drain passes through the a second through hole is connected to the second drain region, the third through hole is disposed corresponding to the first source region, and the first source passes through the third through hole to connect the first source region,
  • the fourth through hole and the fifth through hole are respectively disposed on two sides of the third through hole, and the fourth through hole and the fifth through hole respectively correspond to the second portion of the first through block Partially disposed, the sixth through hole is disposed corresponding to the third portion, wherein the two
  • the first electrical component further includes a first ohmic contact layer, a second ohmic contact layer, a third ohmic contact layer, a third ohmic contact layer, a fourth ohmic contact layer, a fifth ohmic contact layer, and the sixth At least one of the ohmic contact layers, wherein the first ohmic contact layer is disposed between the first drain and the first drain region to connect the first drain and the first drain region The second ohmic contact layer is disposed between the second drain and the second drain region to connect the second drain and the second drain region, and the third ohmic contact layer is disposed Between the first source and the first source region to connect the first source and the first source region, the fourth ohmic contact layer is disposed on the first first gate And a second portion of the first gate region connecting the first one of the first gate and the first gate region, wherein the fifth ohmic contact layer is disposed in the second portion Between the first gate and the second portion of the first gate region to connect the second first gate and
  • the second electrical component includes a third shallow trench isolation region and a fourth shallow trench isolation region
  • the third shallow trench isolation region and the fourth shallow trench isolation region are embedded in the second substrate from the third surface, and one end of the third shallow trench isolation region is The third surface is flush, one end of the fourth shallow trench isolation region is flush with the third surface, and the fourth shallow trench isolation region is opposite to the third shallow trench isolation region and the spacer portion Second substrate.
  • the second electrical component when the planar device is a metal oxide semiconductor transistor, the second electrical component includes a second source region, a third drain region, and a second gate dielectric layer And a second gate region, the second source region and the third drain region are embedded in the second substrate from the third surface, and one end of the second source region is flat with the third surface One end of the third drain region is flush with the third surface, and the second source region is opposite to the third drain region and is disposed at the third shallow channel by a portion of the second substrate Between the isolation region and the fourth shallow trench isolation region, the second source region is in contact with the third shallow trench isolation region, and the third drain region is in contact with the fourth shallow trench isolation region a second gate dielectric layer is disposed on the third surface, and the second gate dielectric layer is disposed between the second source region and the third drain region, and the second gate region is stacked And on the second gate dielectric layer, and the second gate region is in contact with the second gate dielectric layer.
  • the second electrical component further includes a second source, a third drain, and a second gate, the second source, the third The drain and the second gate are respectively connected to the second source region, the third drain region, and the second gate region.
  • the second electrical component further includes a second isolation layer, the second isolation layer and the first isolation layer being in the same layer, the The second isolation layer covers the second source region, the third drain region and the second gate region, and the second isolation layer is provided with a seventh through hole, an eighth through hole and a ninth through hole.
  • the seventh through hole is disposed corresponding to the second source region
  • the second source is connected to the second source region through the seventh through hole
  • the eighth through hole is disposed corresponding to the third drain region
  • the third drain is connected to the third drain region through the eighth through hole
  • the ninth through hole is disposed corresponding to the second gate region
  • the second gate is connected through the ninth through hole The second gate region.
  • the second electrical component further includes at least one of a seventh ohmic contact layer, an eighth ohmic contact layer, and a ninth ohmic contact layer, wherein the seventh ohmic contact layer is disposed on the second source And the second source region, the eighth ohmic contact layer is disposed on the third drain and the third Between the drain regions, the ninth ohmic contact layer is disposed between the second gate and the second gate region.
  • the first drain region, the second drain region, the second source region, and the third drain region are the first type of ion heavy doping a hetero-region, the first source region being a second type of ion heavily doped region, wherein the first type of ion heavily doped region is an N-type ion heavily doped region, and the second type of ion heavily doped region A P-type ion heavily doped region; or the first type of ion heavily doped region is a P-type ion heavily doped region, and the second type of ion heavily doped region is an N-type ion heavily doped region.
  • the second electrical component when the planar device is a capacitor, the second electrical component includes a first doped region, a second insulating layer, a third gate dielectric layer, and a third gate region, the first doped region is embedded in the second substrate from the third surface, and one end of the first doped region is flush with the third surface, the first doping a region is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region, one end of the first doped region is in contact with the third shallow trench isolation region, the first The other end of the doped region is in contact with the fourth shallow trench isolation region, the second insulating layer is disposed in a middle portion of the first doped region, and the second insulating layer does not cover the first doping region
  • the third gate dielectric layer is stacked on the second insulating layer, and the third gate region is stacked on the third gate dielectric layer.
  • the second electrical component further includes a first electrode, a second electrode, and a third electrode, wherein the first electrode and the second electrode respectively correspond Connecting the two ends of the first doping region, the third electrode is connected to the third gate region.
  • the second electrical component further includes a third isolation layer disposed on the surface of the first doped region not covering the second insulating layer and the surface of the third gate region
  • the third isolation layer is provided with a tenth through hole, a tenth continuous hole and a twelfth through hole, wherein the tenth through hole is disposed corresponding to one end of the first doping region, and the first electrode passes The tenth through hole is connected to one end of the first doping region, the tenth consistent hole is disposed corresponding to the other end of the first doping region, and the second electrode passes through the tenth consistent hole Connecting the other end of the first doping region, the twelfth through hole is disposed corresponding to the third gate region, and the third electrode is connected to the third gate region through the twelfth through hole.
  • the second electrical component when the planar device is a resistor, the second electrical component includes a second doped region, and the second doped region is from the third a surface embedded in the third surface is embedded inside the second substrate, and one end of the second doping region is flat with the third surface
  • the second doped region is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region, and one end of the second doped region and the third shallow trench The isolation region contacts, and the other end of the second doped region is in contact with the fourth shallow trench isolation region.
  • the second electrical component further includes a fourth electrode and a fifth electrode, wherein the fourth electrode and the fifth electrode respectively connect the second doping Both ends of the miscellaneous area.
  • the second electrical component further includes a fourth isolation layer, the fourth isolation layer covers the second doped region, and the fourth isolation layer is provided with a twelfth through hole and a thirteenth through hole.
  • the twelfth through hole and the thirteenth through hole are respectively disposed at two ends of the second doping region, and the fourth electrode is connected to the second doping region through the twelfth through hole And at one end, the fifth electrode is connected to the other end of the second doping region through the thirteenth through hole.
  • the semiconductor device of the present invention includes a tunneling field effect transistor and a planar device, the tunneling field effect transistor including a first substrate and a first electrical circuit formed on a side of the first substrate An element, the planar device comprising a second substrate and a second electrical component formed on a side of the second substrate.
  • the first substrate and the second substrate are integrated to form a total substrate, and the first electrical component of the tunneling field effect transistor and the second electrical component of the planar device are disposed in a total
  • the semiconductor device of the present invention is smaller in volume than the prior art tunneling field effect transistor and planar device are separately fabricated on different substrates and integrated into the same substrate. The complexity of the process and the cost of implementation are reduced compared to the prior art.
  • the first insulating layer is configured to isolate the first gate region from controlling the first substrate, and prevent leakage of the first drain region and the second drain region current.
  • the present invention also provides a method of fabricating a semiconductor device, the method for fabricating the semiconductor device comprising:
  • the total substrate includes an adjacent first substrate and a second substrate, the first substrate includes a first surface and a second surface disposed opposite to each other, the second lining
  • the bottom includes oppositely disposed third surfaces and a fourth surface, the third surface being flush with the first surface, the fourth surface being flush with the second surface;
  • the first substrate and the first electrical component constitute a tunneling field effect transistor
  • the second substrate and the second electrical component constitute a planar device, wherein the planar device comprises metal oxide Any one of a semiconductor transistor, a capacitor, and a resistor.
  • the step S120 includes:
  • Step S130 forming a first shallow trench isolation region and the second shallow trench isolation region embedded in the first substrate from the first surface, and forming the second liner from the third surface a third shallow trench isolation region and a fourth shallow trench isolation region in the bottom, wherein one end of the first shallow trench isolation region is flush with the first surface, and the second shallow trench isolation region One end is flush with the first surface, the second shallow trench isolation region is opposite to the first shallow trench isolation region and is spaced apart from the first substrate; the third shallow trench isolation region One end is flush with the third surface, one end of the fourth shallow trench isolation region is flush with the third surface, and the fourth shallow trench isolation region is opposite to the third shallow trench isolation region A portion of the second substrate is disposed and spaced apart.
  • the step S120 further includes: after the step S130:
  • Step S131a forming a first drain region and a second drain region embedded in the first surface from the first surface, and forming a second source region and a third region embedded in the second surface on the second surface a drain region; wherein one end of the first drain region is flush with the first surface, one end of the second drain region is flush with the first surface, and the first drain region and the second portion
  • the drain region is oppositely disposed between the first shallow trench isolation region and the second shallow trench isolation region by a portion of the first substrate spacer, the first drain region is isolated from the first shallow trench Contacting, the second drain region is in contact with the second shallow trench isolation region; one end of the second source region is flush with the third surface, and one end of the third drain region is opposite to the first
  • the third surface is flush, the second source region is opposite to the third drain region and is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region by a portion of the second substrate spacer
  • the second source region is in contact with the third shallow trench isolation region, and the third drain region is
  • Step S132a forming a first source region, the first source region is convexly disposed on the first surface, and the first source region is located between the first drain region and the second drain region;
  • Step S133a forming a first insulating layer; the first insulating layer is convexly disposed on the surface of the substrate, and the first insulating layer is symmetrically disposed on two sides of the first source region, and is respectively connected to the first a drain region and the first source region and between the second drain region and the first source region, and the first insulating layer The thickness is less than the height of the first source region;
  • Step S134a forming a first gate dielectric layer and a second gate dielectric layer disposed at intervals; the first gate dielectric layer is symmetrically disposed on both sides of the first source region and bonding the first source region and the first a surface of the insulating layer; the second gate dielectric layer is disposed on the surface of the substrate, and the second gate dielectric layer is disposed between the second source region and the third drain region;
  • Step S135a forming a first gate region and a second gate region; the first gate region is disposed around the first gate dielectric layer; the second gate region is disposed on the second gate dielectric layer, and The second gate region is in contact with the second gate dielectric layer.
  • the step S131a includes:
  • Step S131a-I sequentially laminating an oxide layer and a first hard mask layer on the same surface of the total substrate;
  • Step S131a-II patterning the oxide layer and the first hard mask layer to retain the first oxidized portion and the first hard mask portion, and the second oxidized portion and the second hard mask portion,
  • the first oxidized portion is spaced apart from the first shallow trench isolation region and the second shallow trench isolation region, and the first hard mask portion is stacked on the first oxidized portion
  • the second The oxidizing portion is spaced apart from the third shallow trench isolation region and the fourth shallow trench isolation region
  • the second hard mask portion is stacked on the second oxidized portion;
  • Step S131a-III using the first oxidized portion and the first hard mask portion and the second oxidized portion 2 and the second hard mask portion as a mask to surface the total substrate
  • the first type of ions are heavily doped to form the first drain region, the second drain region, the second source region, and the third drain region;
  • steps S131a-IV the first oxidized portion and the first hard mask portion, the second oxidized portion, and the second hard mask portion are peeled off.
  • the method for preparing the semiconductor device further includes:
  • the total substrate is annealed.
  • the step S132a includes:
  • Step S132a-I depositing a second type of ion heavily doped semiconductor layer on the surface of the total substrate;
  • Steps S132a-II patterning the second type of ion heavily doped semiconductor layer to form the first source region.
  • step S132a-II includes:
  • Step a1 depositing a second hard mask layer and a photoresist on the second type of ion heavily doped semiconductor layer;
  • Step b1 patterning the second hard mask layer and the photoresist to retain a second hard mask layer and a photoresist corresponding to the middle of the first source region and the second source region;
  • Step c1 etching the second type of ion heavily doped semiconductor layer with the remaining second hard mask layer and the photoresist as a mask to retain the second hard mask layer and the photolithography a second type of ion-coated ion heavily doped semiconductor layer to form the first source region;
  • step d1 the photoresist corresponding to the middle of the first region is stripped.
  • the step S133a includes:
  • Step S133a-I depositing an insulating layer, the insulating layer having a thickness smaller than a height of the first source region;
  • Steps S133a-II patterning the insulating layer to retain insulation respectively connected between the first drain region and the first source region and between the second drain region and the first source region a portion of the layer to form the first insulating layer.
  • the step S134a includes:
  • Step S134a-I depositing a whole layer of gate dielectric material
  • Steps S134a-II patterning the gate dielectric material layer to retain a gate dielectric material that is affixed to the first insulating layer and the first source region and symmetrically disposed on both sides of the first source region a layer, and a gate dielectric material layer disposed between the second source region and the third drain region and in contact with the second source region and the third drain region, respectively, attached to the layer
  • An insulating layer and the surface of the first source region, and a gate dielectric material layer symmetrically disposed on both sides of the first source region is defined as a first gate dielectric layer, disposed in the second source region and the third
  • a gate dielectric material layer between the drain regions is defined as a second gate dielectric layer
  • the first gate dielectric layer includes a first gate dielectric portion and a second gate dielectric portion
  • the first gate dielectric portion is stacked on the first
  • one end of the second gate dielectric portion is connected to the first gate dielectric portion and the second gate dielectric portion is attached to a surface of the first
  • the step S135a includes:
  • Step S135a-I depositing a whole layer of gate material layers
  • Step S135a-II patterning the gate material layer to remain around the first gate dielectric layer And a gate material layer disposed on the second gate dielectric layer, the gate material layer disposed on the first gate dielectric layer being defined as a first gate region disposed on the second gate dielectric layer
  • the gate material layer is defined as a second gate region, the gate region includes a first portion and a second portion, the first portion is stacked on the first gate dielectric layer, and one end of the second portion is opposite to the first portion One end of the portion is connected and the second portion is attached to the surface of the second gate dielectric portion.
  • the method for fabricating the semiconductor device further includes:
  • Step I corresponding to the first drain region, the second drain region, the first source region, the first gate region, the second source region, the third drain region, and the second a gate region respectively forming a first drain, a second drain, a first source, two first gates, a second source, a third drain, and a second gate, the first drain, the The second drain, the first source, the two first gates, the second source, the third drain, and the second gate are respectively associated with the first drain region, The second drain region, the first source region, the second portion of the first gate region, the second source region, the third drain region, and the second gate region are electrically connected.
  • the method for preparing the semiconductor device further includes:
  • Step S136a in the first drain region, the second drain region, the first source region, and the first gate region, and the second source region, the third drain region, and the first
  • An insulating isolation layer is formed on the second gate region, and the insulating isolation layer covering the first drain region, the second drain region, the first source region and the first gate region is defined as a first isolation layer.
  • An insulating isolation layer covering the second source region, the third drain region and the second gate region is defined as a second isolation layer;
  • Step S137a the first through hole, the second through hole, the third through hole, the fourth through hole, and the fifth through hole are formed on the first isolation layer, the fourth through hole and the fifth through hole Separately disposed on two sides of the third through hole, the first through hole is disposed corresponding to the first drain region, and the first drain is through the first through hole to connect the first drain region, The second through hole is disposed corresponding to the second drain region, the second drain portion is connected to the second drain region through the second through hole, and the third through hole corresponds to the first source region The first source passes through the third through hole to connect the first source region, and the fourth through hole and the fifth through hole respectively correspond to the second portion of the first gate region The two first gates are respectively connected to the second portion of the first gate region through the fourth through hole and the fifth through hole;
  • Step S138a opening a seventh through hole, an eighth through hole, and a ninth through hole in the second isolation layer.
  • the seventh through hole is disposed corresponding to the second source region
  • the second source is connected to the second source region through the seventh through hole
  • the eighth through hole corresponds to the third drain region
  • the third drain is connected to the third drain via the eighth via
  • the ninth via is disposed corresponding to the second gate
  • the second gate is through the ninth via
  • a hole connects the second gate region.
  • the method of fabricating the semiconductor device further includes at least one of the following steps:
  • Step S139a-I forming a first ohmic contact layer between the first drain and the first drain region, the first drain connecting the first drain region through the first ohmic contact layer;
  • Step S139a-II forming a second ohmic contact layer between the second drain and the second drain region, the second drain connecting the second drain region through the second ohmic contact layer;
  • Step S139a-III forming a third ohmic contact layer between the first source and the first source region, the first source connecting the first source region through the third ohmic contact layer;
  • Steps S139a-IV forming a fourth ohmic contact layer between the first first gate and the second portion of the first gate region, the first one of the first gates passing the fourth ohmic a contact layer connecting the second portion of the first gate region;
  • Steps S139a-V forming a fifth ohmic contact layer between the second first gate and the second portion of the first gate region, and the second first gate passes the fifth ohm a contact layer connecting the second portion of the second gate region;
  • Steps S139a-VI forming a seventh ohmic contact layer between the second source and the second source region, the second source connecting the second source region through the seventh ohmic contact layer;
  • Steps S139a-VII forming an eighth ohmic contact layer between the third drain and the third drain region, the third drain connecting the third drain region through the eighth ohmic contact layer;
  • Steps S139a-VIII forming a ninth ohmic contact layer between the second gate and the second gate region, the second gate connecting the second gate region through the ninth ohmic contact layer.
  • step S120 further includes:
  • Step a2 depositing a second hard mask layer and a photoresist on the second type of ion heavily doped semiconductor layer;
  • Step b2 patterning the second hard mask layer and the photoresist to retain a second hard mask layer and a photoresist corresponding to the middle of the first source region and the second source region;
  • Step c2 etching the second type of ion heavily doped semiconductor layer with the remaining second hard mask layer and the photoresist as a mask to retain the second hard mask layer and the photolithography a second type of ion-coated ion heavily doped semiconductor layer to form the first source region;
  • step d2 the second hard mask layer corresponding to the middle of the first region and the photoresist are stripped.
  • the step S134a and the step S135a include:
  • Steps S134a-I' depositing a whole layer of gate dielectric material
  • Steps S134a-II' depositing a gate material layer on the entire gate dielectric material layer
  • Steps S134a-III' patterning the gate dielectric material layer and the gate material layer to remove overlying the first drain region, the second drain region, the second source region, and the a gate dielectric material layer and a gate material layer on the third drain region, the remaining gate dielectric material layer being a first gate dielectric layer
  • the first gate dielectric layer includes a first gate dielectric portion and a second gate dielectric portion And a third gate dielectric portion, the first gate dielectric portion is stacked on the first insulating layer, and one end of the second gate dielectric portion is connected to the first gate dielectric portion and the second gate dielectric a portion of the surface of the first source region, the third dielectric portion connecting one end of the second gate dielectric portion away from the first gate dielectric portion, and the third dielectric portion covers the first source a region away from an end of the substrate;
  • the first gate region includes a first portion, a second portion, and a third portion, wherein the first portion is stacked on the first gate dielectric layer, the second portion One end of
  • the method for fabricating the semiconductor device further includes:
  • Step II corresponding to the first drain region, the second drain region, the first source region, the first gate region, the second source region, the third drain region, and the second a gate region respectively forming a first drain, a second drain, a first source, three first gates, a second source, a third drain, and a second gate, the first drain, the a second drain, the first source, the second source, the third drain, and the second gate, respectively, the first drain region, the second drain region, and the The first source region, the second source region, the third drain region, and the second gate region are electrically connected, wherein the two first gates are connected to the second portion and are respectively disposed on the first source On both sides, another first gate is connected to the third portion.
  • the method for preparing the semiconductor device further includes:
  • Step S136b in the first drain region, the second drain region, the first source region and the first gate region, and the second source region, the third drain region, and the first
  • An insulating isolation layer is formed on the second gate region, and the insulating isolation layer covering the first drain region, the second drain region, the first source region and the first gate region is defined as a first isolation layer.
  • An insulating isolation layer covering the second source region, the third drain region and the second gate region is defined as a second isolation layer;
  • Step S137b the first through hole, the second through hole, the third through hole, the fourth through hole, the fifth through hole and the sixth through hole are formed on the first isolation layer, the fourth through hole and the The fifth through holes are respectively disposed at two sides of the third through hole, the first drain passes through the first through hole to connect the first drain region, and the second drain passes through the first a through hole for connecting the second drain region, wherein the first source passes through the third through hole to connect the first source region, wherein two first gates respectively pass through the fourth through hole and The fifth through hole is connected to the second portion of the first gate region, and the other first gate is connected to the third portion of the first gate region through the sixth through hole;
  • Step S138b a seventh through hole, an eighth through hole and a ninth through hole are formed in the second isolation layer, and the second source is connected to the second source region through the seventh through hole, The third drain is connected to the third drain region through the eighth through hole, and the second gate is connected to the second gate region through the ninth through hole.
  • the method for fabricating the semiconductor device further includes at least one of the following steps:
  • Step S139b-I forming a first ohmic contact layer between the first drain and the first drain region, the first drain connecting the first drain region through the first ohmic contact layer;
  • Step S139b-II forming a second ohmic contact layer between the second drain and the second drain region, the second drain connecting the second drain region through the second ohmic contact layer;
  • Step S139b-III forming a third ohmic contact layer between the first source and the first source region, the first source connecting the first source region through the third ohmic contact layer;
  • Steps S139b-IV forming a fourth ohmic contact layer between the first first gate and the second portion of the first gate region, the first one of the first gates passing the fourth ohmic a contact layer connecting the second portion of the first gate region;
  • Step S139b-V forming a fifth ohmic contact layer between the second first gate and the second portion of the first gate region, and the second first gate passes the fifth ohm a contact layer connecting the second portion of the second gate region;
  • Steps S139b-VI forming a sixth ohmic contact layer between the third first gate and the third portion of the first gate region, and the third of the first gates passing the sixth ohmic a contact layer connecting the third portion of the first gate region;
  • Step S139b-VII forming a seventh ohmic contact layer between the second source and the second source region, the second source connecting the second source region through the seventh ohmic contact layer;
  • Step S139b-VIII forming an eighth ohmic contact layer between the third drain and the third drain region, the third drain connecting the third drain region through the eighth ohmic contact layer;
  • Steps S139b-V-IV forming a ninth ohmic contact layer between the second gate and the second gate region, the second gate connecting the second gate through the ninth ohmic contact layer Area.
  • the first drain region, the second drain region, the second source region, and the third drain region are performed on the substrate a region obtained by heavily doping a first type of ions, the first source region being a second type of ion heavily doped region, wherein the first type of ions is heavily doped to an N-type ion heavily doped, the second The type ion is heavily doped to be P-type ion heavily doped; or the first type of ion heavily doped is P-type ion heavily doped, and the second type of ion heavily doped is N-type ion heavily doped.
  • the step S120 includes after the step S130:
  • Step S131c forming a first drain region and a second drain region embedded in the first surface from the first surface, and forming a first doped region embedded in the second surface on the second surface;
  • One end of the first drain region is flush with the first surface, one end of the second drain region is flush with the first surface, and the first drain region is opposite to the second drain region Providing a portion of the first substrate spacer between the first shallow trench isolation region and the second shallow trench isolation region, the first drain region contacting the first shallow trench isolation region, The second drain region is in contact with the second shallow trench isolation region;
  • one end of the first doped region is flush with the third surface, and the first doped region is disposed in the third shallow trench Between the channel isolation region and the fourth shallow channel isolation region, one end of the first doped region is in contact with the third shallow trench isolation region, and the other end of the first doped region is Contacting the fourth shallow trench isolation region;
  • Step S132c forming a first source region; the first source region is convexly disposed on a surface of the first substrate, and the first source region is located in the first drain region and the second drain region between;
  • Step S133c forming a first insulating layer and a second insulating layer; the first insulating layer is convexly disposed on the surface of the substrate, and the first insulating layer is symmetrically disposed on two sides of the first source region, respectively Connecting between the first drain region and the first source region and between the second drain region and the first source region, and a thickness of the first insulating layer is smaller than the first source region the height of;
  • Step S134c forming a first gate dielectric layer and a third gate dielectric layer disposed at intervals; the first gate dielectric layer is symmetrically disposed on both sides of the first source region and bonding the first source region and the first a surface of an insulating layer; the third gate dielectric layer is stacked on the second insulating layer; the second insulating layer is disposed in a middle portion of the first doping region and the second insulating layer is not Covering both ends of the first doped region, the second insulating layer is in the same layer as the first insulating layer;
  • Step S135c forming a first gate region and a third gate region; the first gate region is disposed around the first gate dielectric layer; and the third gate region is stacked on the third gate dielectric layer.
  • the step S131c includes:
  • Step S131c-I sequentially forming an oxide layer and a third hard mask layer stacked on the same surface of the substrate;
  • Step S131c-II patterning the oxide layer and the third hard mask layer to remove the oxide layer and the third hard mask layer at both ends of the first region and the second region;
  • Step S131c-III performing a first type of ion heavy doping on the surface of the substrate by using the patterned oxide layer and the third hard mask layer as a mask to form an interval in the first region.
  • the first drain region and the second drain region form the first doped region in the second region;
  • steps S131c-IV the remaining oxide layer and the third hard mask layer are peeled off.
  • the method for manufacturing the semiconductor device further includes:
  • the total substrate is annealed.
  • the step S132c includes:
  • Step S132c-I depositing a second type of ion heavily doped semiconductor layer
  • Step S132c-II patterning the second type of ion heavily doped semiconductor layer to form the first source region.
  • step S132c-II includes:
  • Step a3 depositing a fourth hard mask layer and a photoresist on the second type of ion heavily doped semiconductor layer;
  • Step b3 patterning the fourth hard mask layer and the photoresist to retain a fourth hard mask layer and a photoresist corresponding to the middle of the first source region and the second source region;
  • Step c3 etching the second type of ion heavily doped semiconductor layer with the remaining fourth hard mask layer and the photoresist as a mask to retain the fourth hard mask layer and the photolithography a second type of ion-coated ion heavily doped semiconductor layer to form the first source region;
  • step d3 the photoresist corresponding to the middle of the first region is peeled off.
  • the step S133c includes:
  • Step S133c-I depositing an insulating layer, the insulating layer having a thickness smaller than a height of the first source region;
  • Step S133c-II patterning the insulating layer to retain a portion of the insulating layer surrounding the first source region and a portion of the insulating layer disposed at a middle portion of the first doping region, wherein the first A portion of the insulating layer of the source region is the first insulating layer, and a portion of the insulating layer disposed at a middle portion of the first doping region is a second insulating layer.
  • the step S134c includes:
  • Step S134c-I depositing a whole layer of gate dielectric material layer
  • Step S134c-II patterning the gate dielectric material layer to retain a gate dielectric material that is affixed to the first insulating layer and the first source region and symmetrically disposed on both sides of the first source region a layer, and a gate dielectric material layer disposed on the second insulating layer, adhered to the first insulating layer and the surface of the first source region, and symmetrically disposed on both sides of the first source region
  • a gate dielectric material layer is defined as a first gate dielectric layer
  • a gate dielectric material layer disposed on the second insulating layer is defined as a third gate dielectric layer, the first gate dielectric layer including a first gate dielectric portion and a second a gate dielectric portion, the first gate dielectric portion is stacked on the first insulating layer, one end of the second gate dielectric portion is connected to the first gate dielectric portion, and the second gate dielectric portion is bonded The surface of the first source region.
  • step S135c includes:
  • Step S135c-I depositing a whole layer of gate material layers
  • Step S135c-II patterning the gate material layer to retain a gate material layer surrounding the first gate dielectric layer and disposed on the third gate dielectric layer, disposed on the first gate dielectric layer a gate material layer is defined as a first gate region, a gate material layer disposed on the third gate dielectric layer is defined as a third gate region, and the first gate region includes a first portion and a second portion, the first portion A portion is stacked on the first gate dielectric layer, one end of the second portion is connected to one end of the first portion d and the second portion is attached to a surface of the second gate dielectric portion.
  • the method for fabricating the semiconductor device further includes:
  • Step III forming a first drain, a second drain, a first source, and a first gate respectively corresponding to the first drain region, the second drain region, the first source region, and the first gate region And forming a first electrode corresponding to one end of the first doping region, forming a second electrode corresponding to the other end of the first doping region, and forming a third electrode corresponding to the third gate region.
  • the method for preparing the semiconductor device further includes:
  • Step S136c forming an insulating isolation layer on the first drain region, the second drain region, the first source region, the first gate region, and the third gate region, covering the first
  • the insulating isolation layer of the drain region, the second drain region, the first source region, and the first gate region is defined as a first isolation layer
  • the insulating isolation layer covering the third gate region is defined as Three isolation layers;
  • Step S137c opening a first through hole, a second through hole, a third through hole, a fourth through hole, and a fifth through hole in the first isolation layer, the fourth through hole and the fifth through hole Separately disposed on two sides of the third through hole, the first through hole is disposed corresponding to the first drain region, and the first drain is through the first through hole to connect the first drain region, The second through hole is disposed corresponding to the second drain region, the second drain portion is connected to the second drain region through the second through hole, and the third through hole corresponds to the first source region The first source passes through the third through hole to connect the first source region, and the fourth through hole and the fifth through hole respectively correspond to the second portion of the first gate region The two first gates are respectively connected to the first gate region through the fourth through hole and the fifth through hole;
  • Step S138c a tenth through hole, a tenth consistent hole and a twelfth through hole are formed in the third isolation layer, and the first electrode is connected to the first doped region through the tenth through hole One end, the second electrode is connected to the other end of the first doping region through the tenth consistent hole, and the third electrode passes the A twelfth through hole connects the third gate region.
  • the step S120 further includes: after the step S130:
  • Step S131d forming a first drain region and a second drain region embedded in the first surface from the first surface, and forming a second doped region embedded in the second surface on the second surface;
  • One end of the first drain region is flush with the first surface, one end of the second drain region is flush with the first surface, and the first drain region is opposite to the second drain region Providing a portion of the first substrate spacer between the first shallow trench isolation region and the second shallow trench isolation region, the first drain region contacting the first shallow trench isolation region, The second drain region is in contact with the second shallow trench isolation region; one end of the second doped region is flush with the third surface, and the second doped region is disposed at the third shallow trench Between the channel isolation region and the fourth shallow channel isolation region, one end of the second doping region is in contact with the third shallow channel isolation region, and the other end of the second doping region is Contacting the fourth shallow trench isolation region;
  • Step S132d forming a first source region; the first source region is convexly disposed on a surface of the first substrate, and the first source region is located in the first drain region and the second drain region between;
  • Step S133d forming a first insulating layer; the first insulating layer is convexly disposed on the surface of the first substrate, and the first insulating layer is symmetrically disposed on two sides of the first source region, respectively connected to the Between the first drain region and the first source region and between the second drain region and the first source region, and a thickness of the first insulating layer is smaller than a height of the first source region;
  • Step S134d forming a first gate dielectric layer; the first gate dielectric layer is symmetrically disposed on both sides of the first source region and conforming to the surfaces of the first source region and the first insulating layer;
  • Step S135d forming a first gate region, the first gate region being disposed around the first gate dielectric layer.
  • the method for fabricating the semiconductor device further includes:
  • Step IV forming a first drain, a second drain, a first source, and two corresponding to the first drain region, the second drain region, the first source region, and the first gate region, respectively.
  • the first gate and the two ends of the second doped region respectively form a fourth electrode and a fifth electrode.
  • the method for fabricating the semiconductor device before the step IV further includes:
  • Step S136d in the first drain region, the second drain region, the first source region, and the first Forming an insulating isolation layer on the gate region and the second doped region to cover insulating isolation on the first drain region, the second drain region, the first source region and the first gate region a layer is defined as a first isolation layer, and an insulating isolation layer overlying the second doped region is defined as a fourth isolation layer;
  • Step S137d the first through hole, the second through hole, the third through hole, the fourth through hole, and the fifth through hole are formed on the first isolation layer, the fourth through hole and the fifth through hole Separatingly disposed on two sides of the third through hole, the first drain passes through the first through hole to connect the first drain region, and the second drain passes through the second through hole to connect In the second drain region, the first source passes through the third through hole to connect the first source region, and the two first gates pass through the fourth through hole and the fifth a through hole connecting the first gate region;
  • Step S138d a twelfth through hole and a thirteenth through hole are formed in the fourth isolation layer, and the fourth electrode is connected to one end of the second doping region through the twelfth through hole, The fifth electrode is connected to the other end of the second doping region through the thirteenth through hole.
  • the same material in the tunneling field effect transistor and the planar device is formed in the same process, thereby reducing the complexity of the fabrication process of the semiconductor device. And implementation costs.
  • the first drain region and the second drain region in the first region and the second source region and the third region of the MOS transistor in the second region in the method for fabricating the semiconductor device of the present invention The doping type of the drain region is the same, which can be achieved by one ion implantation, which reduces the process steps for preparing the semiconductor device, and the process complexity, that is, the cost.
  • the preparation process of the semiconductor device of the present invention is compatible with the standard process of the existing CMOS of the betta, without adding unnecessary complicated processes.
  • FIG. 1 is a cross-sectional structural view of a semiconductor device in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a preferred embodiment of the semiconductor device in the semiconductor device of FIG. Schematic diagram of the cross-section;
  • FIG. 3 is a cross-sectional structural view showing another preferred embodiment of the semiconductor device in the semiconductor device of FIG. 1 according to the present invention.
  • FIG. 4 is a cross-sectional structural view along I-I of a preferred embodiment of the semiconductor device of FIG. 1 in the case of a capacitor in FIG. 1;
  • FIG. 5 is a cross-sectional structural view along I-I of another preferred embodiment of the semiconductor device of FIG. 1 in which the planar device is a capacitor;
  • FIG. 6 is a cross-sectional structural view along I-I of a preferred embodiment of the semiconductor device of FIG. 1 in the case of a resistor in the semiconductor device of FIG. 1;
  • FIG. 7 is a cross-sectional structural view along I-I of another preferred embodiment of the semiconductor device of FIG. 1 in the semiconductor device of FIG. 1;
  • FIG. 8 is a flow chart of a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.
  • FIG. 34 are schematic diagrams showing respective preparation steps in a method of fabricating a planar device in a MOS device in a semiconductor device according to a preferred embodiment of the present invention.
  • FIG. 50 are schematic diagrams showing respective preparation steps in a method for preparing a planar device in a semiconductor device according to a preferred embodiment of the present invention.
  • FIG. 51 to FIG. 56 are schematic diagrams showing respective preparation steps in a preparation method in which a planar device in a semiconductor device is an electric resistance according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention
  • FIG. 2 is a preferred embodiment of the semiconductor device of the semiconductor device of FIG. Schematic diagram of the cross section structure.
  • the semiconductor device 10 includes a tunneling field effect transistor 100 and a planar device 200.
  • the tunneling field effect transistor 100 includes a first substrate 100a and a first electrical component 100b, and the first electrical component 100b is disposed on one side of the first substrate 100a.
  • Said The planar device 200 includes a second substrate 200a and a second electrical component 200b, the second substrate 200a being integrally formed with the first substrate 100a and forming a total substrate 20, and the second electrical component 200b is formed On the same side of the total substrate 20.
  • the planar device 200 includes any one of a metal oxide semiconductor transistor (MOS), a capacitor, and a resistor.
  • MOS metal oxide semiconductor transistor
  • the MOS transistor is labeled 300
  • the capacitance is labeled 400
  • the first substrate 100a includes a first surface 100c and a second surface 100d disposed opposite to each other, and the second substrate 200a includes a third surface 200c and a fourth surface 200d disposed opposite to each other.
  • the second substrate 200a is in contact with the first substrate 100a, and the third surface 200c is flush with the first surface 100c, and the fourth surface 200d is flush with the second surface 100d.
  • the first surface 100c is an upper surface of the first substrate 100a
  • the second surface 100d is a lower surface of the first substrate 100a.
  • the third surface 200c is an upper surface of the second substrate 200a
  • the fourth surface 200d is a lower surface of the second substrate 200a.
  • the first electrical component 100a includes a first shallow trench isolation (STI) region 11 and a second shallow trench isolation region 12.
  • the first shallow trench isolation region 11 and the second shallow trench isolation region 12 are embedded in the first substrate 100a from the first surface 100c, and the first shallow trench isolation region 11 One end is flush with the first surface 100c, one end of the second shallow trench isolation region 12 is flush with the first surface 100c, and the second shallow trench isolation region 12 is opposite to the first shallow trench
  • the track isolation region 11 is oppositely disposed and spaced apart from the portion of the first substrate 100a.
  • the second electrical component 200a includes a third shallow trench isolation region 13 and a fourth shallow trench isolation region 14.
  • the third shallow trench isolation region 13 and the fourth shallow trench isolation region 14 are embedded in the second substrate 200a from the third surface 200c, and the third shallow trench isolation region 13 One end is flush with the third surface 200c, one end of the fourth shallow trench isolation region 14 is flush with the third surface 200c, and the fourth shallow trench isolation region 14 and the third shallow trench
  • the track isolation regions 13 are oppositely disposed and spaced apart from the second substrate 200a.
  • the first shallow trench isolation region 11, the second shallow trench isolation region 12, the third shallow trench isolation region 13 and the fourth shallow trench isolation region 14 may be formed in a manner
  • the substrate first substrate 100a and the second substrate 200a are realized by using a CMOS process to achieve shallow grass isolation.
  • the first electrical component 100b of the tunneling field effect transistor 100 further includes a first drain region 110, The second drain region 120, the first source region 130, the first insulating layer 140, the first gate dielectric layer 150, and the first gate region 160.
  • the first drain region 110 and the second drain region 120 are embedded in the first substrate 100a from the first surface 100c, and one end of the first drain region 110 is flat with the first surface 100c.
  • One end of the second drain region 120 is flush with the first surface 100c, and the first drain region 110 is opposite to the second drain region 120 and is disposed at intervals by a portion of the first substrate 100a.
  • the first drain region 110 is in contact with the first shallow trench isolation region 11, and the second drain region 120 is The second shallow trench isolation region 12 is in contact.
  • the first source region 130 is convexly disposed on the first surface 100c, and the first source region 130 is located between the first drain region 110 and the second drain region 120.
  • the structure of the first source region 130 of the present invention can improve the speed at which the tunneling field effect transistor controls the opening and closing between the first drain region and the second drain region 120.
  • the first insulating layer 140 is symmetrically disposed on the first surface 100c, and the first insulating layer 140 is symmetrically disposed on two sides of the first source region 130, and is respectively connected to the first drain region 110 and Between the first source regions 130 and between the second drain regions 120 and the first source regions 130, and the height of the first insulating layer 140 is smaller than the height of the first source regions 130.
  • the first insulating layer 140 is used to isolate the first gate region 160 from the control of the first substrate 100a, and prevent leakage of currents of the first drain region 110 and the second drain region 120.
  • the first gate dielectric layer 150 is symmetrically disposed on both sides of the first source region 130 and conforms to the surfaces of the first source region 130 and the first insulating layer 140.
  • the first gate region 160 is disposed around the first gate dielectric layer 150.
  • the first substrate 100a and the second substrate 200a may be silicon (Si) substrates.
  • the first substrate 100a and the second substrate 200a may also be germanium (Ge) or silicon germanium, gallium arsenide, etc. II-IV, or III-V, or IV-IV. Any of a family of binary or ternary compound semiconductors, silicon on insulator (SOI), or germanium on an insulating substrate.
  • the first drain region 110 and the second drain region 120 may be formed by implanting a first type of ion heavily doped on the first surface 100c of the first substrate 100a.
  • the first gate dielectric layer 150 includes a first gate dielectric portion 151 and a second gate dielectric portion 152.
  • the first gate dielectric portion 151 is stacked on the first insulating layer 140, and the second gate dielectric portion is One end of the 152 is connected to the first gate dielectric portion 151 and the second gate dielectric portion 152 is attached to the surface of the first source region 130.
  • the first gate region 160 includes a first portion 161 and a second portion 162.
  • the first portion 161 is stacked on the first gate dielectric layer 150, and one end of the second portion 162 and the first portion 161 One end is connected and the second portion 162 is attached to the surface of the second gate dielectric portion 152.
  • the first electrical component 100b of the tunneling field effect transistor 100 further includes a first drain 171, a second drain 172, a first source 173, and two first gates 174.
  • the first drain 171, the second drain 172, the first source 173, and the two first gates 174 are respectively connected to the first drain region 110 and the second drain region. 120.
  • the two first gates 174 are connected to the second portion 162 and are respectively disposed on two sides of the first source 173.
  • the first electrical component 100b of the tunneling field effect transistor 100 includes a first drain 171, a second drain 172, a first source 173, and two first gates 174.
  • the first drain 171 is connected to the first drain region 110
  • the second drain 172 is connected to the second drain region 120
  • the first source 173 is connected to the first source region 130
  • two The first gate 174 is connected to the second portion 162 of the first gate region 160 and the two first gates 174 are located on both sides of the first source 173.
  • the first electrical component 100b of the tunneling field effect transistor 100 further includes a first isolation layer 180, the first isolation layer 180 covering the first drain region 110, the second drain region 120, and the first source region
  • the first isolation layer 180 is provided with a first through hole 181, a second through hole 182, a third through hole 183, a fourth through hole 184, and a fifth through hole 185.
  • the fourth through hole 184 and the fifth through hole 185 are disposed on both sides of the third through hole 183 .
  • the first through hole 181 is disposed corresponding to the first drain region 110 , and the first drain electrode 171 is connected to the first drain region 110 through the first through hole 181 .
  • the second through hole 182 is disposed corresponding to the second drain region 120, and the second drain hole 172 is connected to the second drain region 120 through the second through hole 182.
  • the third through hole 183 is disposed corresponding to the first source region 130 , and the first source 173 is connected to the first source region 130 through the third through hole 183 .
  • the fourth through hole 184 and the fifth through hole 185 are respectively disposed corresponding to the second portion 162 of the first gate region 160, and the two first gates 174 respectively pass through the fourth through hole 184 and The fifth through hole 185 is connected to the second portion 162 of the first gate region 160.
  • the first electrical component 100b of the tunneling field effect transistor 100 further includes a first ohmic contact layer 181, a second ohmic contact layer 182, a third ohmic contact layer 183, a fourth ohmic contact layer 184, and a fifth At least one of the ohmic contact layers 185.
  • the first ohmic contact layer 181 is disposed between the first drain 171 and the first drain region 110 to connect the first drain 171 and the first drain region 110.
  • the first ohmic contact layer 181 is for reducing a contact resistance between the first drain 171 and the first drain region 110.
  • the second ohmic contact layer 182 is disposed between the second drain 172 and the second drain region 120 to connect the second drain 172 and the second drain region 120, the second The ohmic contact layer 182 is for reducing the contact resistance between the second drain 172 and the second drain region 120.
  • the third ohmic contact layer 183 is disposed between the first source 173 and the first source region 130 to connect the first source 173 and the first source region 130, the third The ohmic contact layer 183 serves to reduce the contact resistance between the first source 173 and the first source region 130.
  • the fourth ohmic contact layer 184 is disposed between the first first gate 174 and the second portion 162 of the first gate region 160 to connect the first first gate 174 and the a second portion 162 of the first gate region 160, the fourth ohmic contact layer 184 is for reducing between the first first gate 174 and the second portion 162 of the first gate region 160 Contact resistance.
  • the fifth ohmic contact layer 185 is disposed between the second first gate 174 and the second portion 162 of the first gate region 160 to connect the second first gate 174 and the a second portion 162 of the first gate region 160, the fifth ohmic contact layer 185 is for reducing contact between the second first gate 174 and the geothermal portion 162 of the first gate region 160 resistance.
  • FIG. 3 is a cross-sectional structural diagram of another preferred embodiment of the semiconductor device in the semiconductor device of FIG.
  • the first gate dielectric layer 150 further includes a third gate dielectric portion 153 that connects one end of the second gate dielectric portion 152 away from the first gate dielectric portion 151, and the third The dielectric portion 153 covers an end of the first source region 130 away from the first substrate 100a.
  • the first gate region 160 includes a third portion 163 that connects the second portion 162 away from one end of the first portion 161, and the third portion 163 covers the first portion The upper surface of the tri-gate dielectric portion 153.
  • the electrical component 100b of the tunneling field effect transistor 100 further includes a first drain 171, a second drain 172, a first source 173, and three first gates 174.
  • the first drain 171, the second drain 172, the first source 173, and the three first gates 174 respectively connect the first drain region 110 and the second drain region. 120.
  • the first source region 130 and the first gate region 160 are disposed.
  • two of the three first gates 174 are connected to the first gate 174.
  • the second portions 162 are respectively disposed on both sides of the first source 173, and the other first gate 174 is connected to the third portion 163.
  • the tunneling field effect transistor 100 includes a first drain 171, a second drain 172, a first source 173, and three first gates 174.
  • the first drain 171 is connected to the first drain region 110
  • the second drain 172 is connected to the second drain region 120
  • the first source 173 is connected to the first source region 130
  • two The first gate 174 is connected to the second portion 162 of the first gate region 160 and the two first gates 174 are located on opposite sides of the first source 173, and the third first gate 174 is connected Said the third part 163.
  • the first electrical component 100b of the tunneling field effect transistor 100 further includes a first isolation layer 180, the first isolation layer 180 covering the first drain region 110, the second drain region 120,
  • the first isolation region 180 and the first isolation region 180 are provided with a first through hole 181, a second through hole 182, a third through hole 183, and a fourth through hole 184.
  • the first through hole 181 is disposed corresponding to the first drain region 110, and the first drain electrode 171 passes through the first through hole 181 to connect the first drain region 110.
  • the second through hole 182 is disposed corresponding to the second drain region 120, and the second drain hole 172 is connected to the second drain region 120 through the second through hole 182.
  • the third through hole 183 is disposed corresponding to the first source region 130 , and the first source 173 passes through the third through hole 183 to connect the first source region 130 .
  • the fourth through hole 184 and the fifth through hole 185 are respectively disposed at two sides of the third through hole 183, and the fourth through hole 184 and the fifth through hole 185 respectively correspond to the first
  • the second portion 162 of the gate region 160 is disposed, and the sixth through hole 186 is disposed corresponding to the third portion 163, wherein the two first gates 174 pass through the fourth through hole 184 and the fifth through hole 185, respectively.
  • a second portion 162 of the first gate region 160 is connected, and another first gate 174 is connected to the third portion 163 through the sixth through hole 186.
  • the first electrical component 100b of the tunneling field effect transistor 100 further includes a first ohmic contact layer 181, a second ohmic contact layer 182, a third ohmic contact layer 183, a fourth ohmic contact layer 184, and a fifth ohmic contact layer 185. And at least one of the sixth ohmic contact layers 186.
  • the first ohmic contact layer 181 is disposed between the first drain 171 and the first drain region 110 to connect the first drain 171 and the first drain region 110.
  • the first ohmic contact layer 181 is for reducing a contact resistance between the first drain 171 and the first drain region 110.
  • the second ohmic contact layer 182 is disposed between the second drain 172 and the second drain region 120 to connect the second drain 172 and the second drain region 120, the second An ohmic contact layer 182 is configured to reduce the second drain 172 and the first Contact resistance between the two drain regions 120.
  • the third ohmic contact layer 183 is disposed between the first source 173 and the first source region 130 to connect the first source 173 and the first source region 130, the third The ohmic contact layer 183 serves to reduce the contact resistance between the first source 173 and the first source region 130.
  • the fourth ohmic contact layer 184 is disposed between the first first gate 174 and the second portion 162 of the first gate region 160 to connect the first first gate 174 and the a second portion 162 of the first gate region 160, the fourth ohmic contact layer 184 is for reducing between the first first gate 174 and the second portion 162 of the first gate region 160 Contact resistance.
  • the fifth ohmic contact layer 185 is disposed between the second first gate 174 and the second portion 162 of the first gate region 160 to connect the second first gate 174 and the a second portion 162 of the first gate region 160, the fifth ohmic contact layer 185 is for reducing between the second first gate 174 and the second portion 162 of the first gate region 160 Contact resistance.
  • the sixth ohmic contact layer is disposed between the third first gate 174 and the third portion 163 of the first gate region 160 to connect the third first gate 174 and a third portion 163 of the first gate region 160, the sixth ohmic contact layer 186 is for reducing between the third first gate 174 and the third portion 162 of the first gate region 160 Contact resistance.
  • the second electrical component 200b when the planar device 200 is a metal oxide semiconductor transistor, the second electrical component 200b includes a second source region 310, a third drain region 320, a second gate dielectric layer 330, and a portion The second gate region 340.
  • the second source region 310 and the third drain region 320 are embedded in the second substrate 200a from the third surface 200c, and one end of the second source region 310 is flat with the third surface 200c. One end of the third drain region 320 is flush with the third surface 200c, and the second source region 310 is opposite to the third drain region 320 and is disposed at intervals by a portion of the second substrate 200a. Between the third shallow trench isolation region 13 and the fourth shallow trench isolation region 14, the second source region 310 is in contact with the third shallow trench isolation region 13, and the third drain region 320 is The fourth shallow trench isolation region 14 is in contact. In the embodiment, the second source region 310 and the third drain region 320 are located in the same layer as the first drain region 110 and the second drain region 120.
  • the second gate dielectric layer 330 is disposed on the third surface 200c, and the second gate dielectric layer 330 is disposed between the second source region 310 and the third drain region 320.
  • the second gate region 340 is disposed on the second gate dielectric layer 330, and the second gate region 340 is in contact with the second gate dielectric layer 330.
  • the second electrical component 200b further includes a second source 351, a third drain 352, and a second gate 353.
  • the second source 351, the third drain 352, and the second gate 353 are respectively connected to the second source region 310, the third drain region 320, and the second gate region 340.
  • the second electrical component 200b of the MOS transistor 300 includes a second source 351, a third drain 352, and a second gate 353, and the second source 351 is connected to the second source.
  • the third drain 352 is connected to the third drain region 320, and the second gate 353 is connected to the second gate region 340.
  • the second electrical component 200b further includes a second isolation layer 360, the second isolation layer 360 is located in the same layer as the first isolation layer 180, and the second isolation layer 360 covers the second source region 310, The third drain region 320 and the second gate region 340.
  • the second isolation layer 360 is provided with a seventh through hole 361, an eighth through hole 362 and a ninth through hole 363.
  • the seventh through hole 361 is disposed corresponding to the second source region 310, and the second source 351 is connected to the second source region 310 through the seventh through hole 361.
  • the eighth through hole 362 is disposed corresponding to the third drain region 320, and the third drain 352 is connected to the third drain region 320 through the eighth through hole 362.
  • the ninth through hole 363 is disposed corresponding to the second gate region 340, and the second gate 353 is connected to the second gate region 340 through the ninth through hole 363.
  • the second electrical component 200b further includes at least one of a seventh ohmic contact layer 381, an eighth ohmic contact layer 382, and a ninth ohmic contact layer 383.
  • the seventh ohmic contact layer 381 is disposed between the second source 351 and the second source region 310 for reducing the second source 351 and the second source region 310.
  • the eighth ohmic contact layer 382 is disposed between the third drain 352 and the third drain region 320, and the eighth ohmic contact layer 382 is configured to reduce the third drain 352 and the Contact resistance between the third drain regions 320.
  • the ninth ohmic contact layer 383 is disposed between the second gate 353 and the second gate region 340, and the ninth ohmic contact layer 383 is configured to reduce the second gate 353 and the Contact resistance between the second gate regions 340.
  • the first drain region 110, the second drain region 120, the second source region 310, and the third drain region 320 are first type ion heavily doped regions, and the first source region 130 is Two types of ion heavily doped regions.
  • the first type of ion heavily doped region is an N-type ion heavily doped region
  • the second type of ion heavily doped region is a P-type ion heavily doped region; or the first type of ion heavily doped region
  • the region is a P-type ion heavily doped region
  • the second type ion heavily doped region is an N-type ion heavily doped region.
  • FIG. 4 is a cross-sectional structural view of a preferred embodiment of the semiconductor device of FIG. 1 in a semiconductor device according to a preferred embodiment of the present invention
  • FIG. 5 is a schematic view of the semiconductor device of FIG.
  • a cross-sectional structural view along II of another preferred embodiment of the planar device is a capacitor.
  • the planar device 200 is a capacitor
  • the second electrical component 200b includes a first doped region 410, a second insulating layer 420, a third gate dielectric layer 430, and a third gate region 440.
  • the first doping region 410 is embedded in the second substrate 200a from the third surface 200c, and one end of the first doping region 410 is flush with the third surface 200c, the first doping
  • the impurity region 410 is disposed between the third shallow trench isolation region 13 and the fourth shallow trench isolation region 14 , and one end of the first doping region 410 and the third shallow trench isolation region 13 Contacting, the other end of the first doping region 410 is in contact with the fourth shallow trench isolation region 14, and the first doping region 410 and the first drain region 110 and the second drain region 120 is on the same floor.
  • the second insulating layer 420 is disposed at a middle portion of the first doping region 410 and the second insulating layer 420 does not cover both ends of the first doping region 410, and the second insulating layer 420 is The first insulating layer 140 is located in the same layer.
  • the third gate dielectric layer 430 is stacked on the second insulating layer 420, and the third gate region 440 is stacked on the third gate dielectric layer 430.
  • the first doped region 410 and the third gate region 440 constitute two opposite plates of the capacitor 400
  • the second insulating layer 420 and the third gate dielectric layer 430 constitutes a dielectric layer of the capacitor 400.
  • the first doped region 410 may be formed by performing a first type of ion heavy doping on the substrate 20.
  • the second electrical component 200b further includes a first electrode 451, a second electrode 452, and a third electrode 453.
  • the first electrode 451 and the second electrode 452 are respectively connected to two ends of the first doping region 410, and the third electrode 453 is connected to the third gate region 440.
  • the first electrode 451 and the second electrode 452 are respectively disposed on two sides of the third electrode 453, and two electrodes of the first electrode 451 and the second electrode 452 are disposed.
  • Connected to both ends of the first doping region 410 to selectively connect the first electrode 451 and the third electrode 453 or connect according to a positional relationship between the capacitor 400 and other devices when the capacitor 400 is applied.
  • the second electrical component 200b further includes a third isolation layer 460 disposed on the surface of the first doping region 410 not covering the second insulating layer 420 and the third gate region The surface of 440.
  • the third isolation layer 460 is provided with a tenth through hole 461, a tenth consistent hole 462, and a third Twelve through holes 463.
  • the tenth through hole 461 is disposed at one end of the first doping region 410, and the first electrode 451 is connected to one end of the first doping region 410 through the tenth through hole 461.
  • the tenth uniform hole 462 is disposed corresponding to the other end of the first doping region 420, and the second electrode 452 is connected to the other end of the first doping region 410 through the tenth uniform hole 462.
  • the twelfth through hole 463 is disposed corresponding to the third gate region 440, and the third electrode 453 is connected to the third gate region 440 through the twelfth through hole 463.
  • the second electrical component 200b further includes at least one ohmic contact layer disposed on the first electrode 451, the second electrode 452, and the third The electrode 453 is between the layers corresponding to the respective electrodes to reduce the contact resistance between the respective electrodes and the correspondingly connected layers.
  • the ohmic contact layer is disposed between the first electrode 451 and the first doping region 410 to connect the first electrode 451 and the first doping region 410 for reducing The contact resistance between the first electrode 451 and the first doping region 410 is described.
  • FIG. 6 is a cross-sectional structural view along the II of a preferred embodiment of the semiconductor device of FIG. 1 according to the present invention
  • FIG. 7 is a schematic diagram of the planar device in the semiconductor of FIG.
  • the second electrical component 200b includes a second doped region 510, and the second doped region 510 is embedded in the third surface 200c from the third surface 200c to embed the Inside the second substrate 200a, one end of the second doping region 510 is flush with the third surface 200c, the second doping region 510 is disposed in the third shallow trench isolation region 13 and the Between the fourth shallow trench isolation regions 14, one end of the second doped region 510 is in contact with the third shallow trench isolation region 13, and the other end of the second doped region 510 is opposite to the fourth The shallow trench isolation region 14 is in contact, and the second doped region 510 is in the same layer as the first drain region 110 and the second drain region 120.
  • the magnitude of the resistance value of the resistor 500 can be controlled by controlling the concentration of ions doped in the second doping region 510.
  • the second doped region 510 may be formed by performing a first type of ion heavy doping on the substrate 20.
  • the second electrical component 200b further includes a fourth electrode 520 and a fifth electrode 530.
  • the fourth electrode 520 and the fifth electrode 530 are respectively connected to two ends of the second doping region 510.
  • the fourth electrode 520 and the fifth electrode 530 are used to electrically connect the resistor 500 with other components.
  • the second electrical component 200b further includes a fourth isolation layer 540, the fourth isolation layer 540 covers the second doping region 510, and the fourth isolation layer 540 is provided with a twelfth through hole 541 and a tenth three Through hole 542.
  • the twelfth through hole 541 and the thirteenth through hole 542 are disposed at two ends of the second doping region 510, and the fourth electrode 520 is connected to the first through the twelfth through hole 541.
  • One end of the second doping region 510, the fifth electrode 530 is connected to the other end of the second doping region 510 through the thirteenth through hole 542.
  • the semiconductor device 10 of the present invention includes a tunneling field effect transistor 100 and a planar device 200.
  • the tunneling field effect transistor 100 includes a first substrate 100a and is formed on the first substrate 100a.
  • a first electrical component 100b on one side, the planar device 200 includes a second substrate 200a and a second electrical component 200b formed on one side of the second substrate 200a.
  • the first substrate 100a and the second substrate 200a are a unitary structure, forming a total substrate 20, and the first electrical component 100b of the tunneling field effect transistor 100 and the second of the planar device 200
  • the electrical component 200b is disposed on the same surface of a total substrate 20.
  • the tunneling field effect transistor 100 and the planar device 200 are separately fabricated on different substrates and integrated into the same substrate.
  • the semiconductor device 10 of the present invention is small in size, which reduces the complexity of the process and the cost of implementation compared to the prior art.
  • FIG. 8 is a flow chart of a method for fabricating a semiconductor device according to a preferred embodiment of the present invention.
  • the method of fabricating the semiconductor device of the present invention realizes a process scheme of integrating a Tunnel Field Effect Transistor (TFET) 100 with a planar device 200, which is called a drain-first process scheme.
  • the drain-first process first realizes the first drain region 110, the second drain region 120 of the internal tunneling field effect transistor 100, and the second source of the MOS transistor 300 in the second region 20b by an ion implantation process.
  • Zone 310 and the third drain zone 320 Zone 310 and the third drain zone 320.
  • the first source region 130 is then achieved by an in-situ doping process and an etching process.
  • the first gate region 160 and the second gate region 340 are realized by depositing a gate dielectric material layer 217 and a gate material layer 218 plus an etching process.
  • the metal contact of the entire semiconductor device 10 is achieved according to a contact process of a CMOS standard process. Specifically, the method of fabricating the semiconductor device includes, but is not limited to, the following steps.
  • a total substrate 20 is provided.
  • the total substrate includes an adjacent first substrate 100a and a second substrate 200a.
  • the first substrate 100a includes a first surface 100c and a second surface disposed opposite to each other. 100d
  • the second substrate 200a includes a third surface 200c and a fourth surface 200d disposed opposite to each other.
  • the third surface 200c is flush with the first surface 100c
  • the fourth surface 200d is flush with the second surface 100d.
  • the total substrate 20 may be a silicon (Si) substrate.
  • the total substrate 20 may also be a binary or ternary compound semiconductor of group II-IV, or group III-V, or group IV-IV of germanium (Ge) or silicon germanium, gallium arsenide, or the like. Any of silicon (Silicon on Insulator, SOI) on an insulating substrate, or germanium on an insulating substrate.
  • Step S120 forming a first electrical component 100b on one side of the first substrate 100a, and forming a second electrical component 200b on a side of the second substrate 200a, the second electrical component 200b and the first An electrical component 100b is disposed on the same side of the total substrate 20.
  • the first substrate 100a and the first electrical component 100b constitute a tunneling field effect transistor 100
  • the second electrical component 200b constitutes a planar device 200, wherein the planar device 200 includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.
  • the first electrical component 100b includes an N-layer material layer
  • the second electrical component 200b includes an M-layer material layer
  • the M is less than or equal to N
  • the M-layer material layer is in the N-layer material layer
  • the layers of the same material are formed in the same process.
  • Step S120 in the method of fabricating the semiconductor device further includes step S130.
  • Step S130 forming a first shallow trench isolation region 11 and the second shallow trench isolation region 12 embedded in the first substrate 100a from the first surface 100c, forming an embedded from the third surface 200c a third shallow trench isolation region 13 and a fourth shallow trench isolation region 14 in the second substrate 200a, wherein one end of the first shallow trench isolation region 11 is flush with the first surface 100c One end of the second shallow trench isolation region 12 is flush with the first surface 100c, and the second shallow trench isolation region 12 is opposite to the first shallow trench isolation region 11 and the spacer portion is a substrate 100a; one end of the third shallow trench isolation region 13 is flush with the third surface 200c, and one end of the fourth shallow trench isolation region 14 is flush with the third surface 200c.
  • the fourth shallow trench isolation region 14 is disposed opposite to the third shallow trench isolation region 13 and spaces a portion of the second substrate.
  • the planar device 200 can be a MOS transistor 300 or a capacitor 400 or a resistor 500.
  • the step S120 further includes the following steps after the step S130.
  • Step S131a forming a first drain region 110 and a second drain region 120 embedded in the first surface 100c from the first surface 100c, and forming the second surface 200c on the second surface 200c.
  • a second source region 310 and a third drain region 320 wherein one end of the first drain region 110 is flush with the first surface 100c, and one end of the second drain region 120 is opposite to the first surface 100c is flush, the first drain region 110 is opposite to the second drain region 120 and is spaced apart from the first shallow trench isolation region 11 and the second shallow trench isolation by a portion of the first substrate 100a
  • the first drain region 110 is in contact with the first shallow trench isolation region 11, and the second drain region 120 is in contact with the second shallow trench isolation region 12;
  • the second source One end of the region 310 is flush with the third surface 200c, one end of the third drain region 320 is flush with the third surface 200c, and the second source region 310 is opposite to the third drain region 320.
  • the second source region 310 is isolated from the third shallow trench The region 13 is in contact, and the third drain region 320 is in contact with the fourth shallow trench isolation region 14. .
  • step S132a the first source region 130 is formed.
  • the first source region 130 is convexly disposed on the first surface 100c, and the first source region 130 is located between the first drain region 110 and the second drain region 120.
  • the first insulating layer 140 is formed.
  • the first insulating layer 140 is disposed on the surface of the substrate, and the first insulating layer 140 is symmetrically disposed on two sides of the first source region 130, and is respectively connected to the first drain region 110 and the Between the first source regions 130 and between the second drain regions 120 and the first source regions 130, and the thickness of the first insulating layer 140 is smaller than the height of the first source regions 130.
  • step S134a the first gate dielectric layer 150 and the second gate dielectric layer 330 are formed at intervals.
  • the first gate dielectric layer 150 is symmetrically disposed on both sides of the first source region 130 and conforms to the surfaces of the first source region 130 and the first insulating layer 140.
  • the second gate dielectric layer 330 is disposed on a surface of the substrate 20 , and the second gate dielectric layer 330 is disposed between the second source region 310 and the third drain region 320 .
  • a first gate region 160 and a second gate region 340 are formed.
  • the first gate region 160 is disposed around the first gate dielectric layer 150.
  • the second gate region 340 is disposed on the second gate dielectric layer 330, and the second gate region 340 is in contact with the second gate dielectric layer 330.
  • the first drain region 110, the second drain region 120, the second source region 310, and the third drain region 320 are the first type of ions for the total substrate 200.
  • the first source region 130 being a second type of ion heavily doped region, wherein the first type of ions Heavy doping is heavily doped with N-type ions, the second type of ions are heavily doped with P-type ions heavily doped; or the first type of ions are heavily doped with P-type ions heavily doped, the second Type ion heavy doping is heavily doped with N-type ions.
  • the impurities may be Li, Sb, P, As, Bi, Te, Ti, C, Mg, Se, Cr, Ta, Cs, Ba when the N-type ions are doped. Any one or more of S, Mn, Ag, Cd, and Pt; when the P-type ions are doped, the impurities may be B, Al, Ga, In, Ti, Pd, Na, Be, Zn, Au, Co, V Any one or more of Ni, MO, Hg, Sr Ge, W, Pb, O, and Fe.
  • the impurity when the N-type ions are doped may be any one or more of Li, Sb, P, As, S, Se, Te, Cu, Au, Ag.
  • the impurity may be any one or more of B, Al, In, Ga, In, Be, Zn, Cr, Cd, Hg, Co, Ni, Mn, Fe, and Pt.
  • P-type ion doping the ion doping concentration is 1e 18 to 1e 21 cm -3 ; when N-type ion doping is performed, the ion doping concentration is 1e 18 to 1e 20 cm -3 .
  • the method for preparing the semiconductor device further comprises: annealing the total substrate 20.
  • Annealing the total substrate 20 may be performed by using a rapid annealing process or a laser annealing process to activate the first drain region 110, the second drain region 120, and the The ions doped in the second source region 310 and the third drain region 320.
  • the step S131a includes the following steps.
  • step S131a-I an oxide layer 211 and a first hard mask layer 212 are sequentially laminated on the same surface of the total substrate 20. Please refer to Figure 11.
  • Step S131a-II patterning the oxide layer 211 and the first hard mask layer 212 to retain the first oxidized portion 211a and the first hard mask portion 212a, and the second oxidized portion 212a and the second hard mask a film portion 212b, the first oxidized portion 211a is spaced apart from the first shallow trench isolation region 11 and the second shallow trench isolation region 12, and the first hard mask portion 212a is stacked on the The first oxidized portion 211a is spaced apart from the third shallow trench isolation region 13 and the fourth shallow trench isolation region 14, and the second hard mask portion 212b is stacked. On the second oxidizing portion 212b. Please refer to Figure 12 together.
  • Step S131a-III using the first oxidized portion 211a and the first hard mask portion 212a and the second oxidized portion 211b and the second hard mask portion 212b as a mask to the total substrate
  • the surface of 20 is heavily doped with a first type of ions to form the first drain region 110, the second drain region 120, the second source region 310, and the third drain region 320.
  • the first type of ion ion heavy doping is N-type ion heavy doping as an example, and is represented by N + in the figure, wherein FIG.
  • FIG. 13 illustrates Performing the first surface of the substrate 20 with the first oxidized portion 211a and the first hard mask portion 212a and the second oxidized portion 211b and the second hard mask portion 212b as masks
  • the type ions are heavily doped
  • FIG. 14 illustrates the first drain region 110 and the second drain region 120 formed, and the second source region 310 and the third drain region 320.
  • steps S131a-IV the first oxidized portion 211a and the first hard mask portion 211a, the second oxidized portion 211b, and the second hard mask portion 212b are peeled off. Please refer to Figure 15.
  • step S132a includes the following steps.
  • Step S132a-I depositing a second type of ion heavily doped semiconductor layer 213 on the surface of the total substrate 20.
  • the deposition step may be performed by Low Pressure Chemical Vapor Deposition (LPCVD) or Physical Vapor Deposition (PVD).
  • LPCVD Low Pressure Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • Steps S132a-II patterning the second type of ion heavily doped semiconductor layer 213 to form the first source region 130.
  • the steps S132a-II include the following steps.
  • step a1 a second hard mask layer 214 and a photoresist 215 are deposited on the second type of ion heavily doped semiconductor layer 213. Please refer to FIG. 17 together.
  • Step b1 patterning the second hard mask layer 214 and the photoresist 215 to retain a second hard mask layer corresponding to the middle of the first source region 110 and the second source region 120 214 and photoresist 215, please refer to FIG. 18 together.
  • step c1 the second type of ion heavily doped semiconductor layer 213 is etched by using the remaining second hard mask layer 214 and the photoresist 215 as a mask to retain the second hard mask layer 214 and The second type of ions covered by the photoresist 215 are heavily doped with the semiconductor layer 213 to form the first source region 130. Please refer to FIG. 19 together.
  • step d1 the photoresist 215 corresponding to the middle of the first region 20a is peeled off, please refer to FIG.
  • step S133a in an embodiment comprises the following steps.
  • Step S133a-I depositing an insulating layer 216, the insulating layer 216 having a thickness smaller than the first See Figure 21 for the height of a source zone 130.
  • the step S134a includes the following steps.
  • Step S134a-II patterning the gate dielectric material layer 217 to remain adhered to the first insulating layer 140 and the first source region 130, and symmetrically disposed on both sides of the first source region 130 a gate dielectric material layer 217, and a gate dielectric remaining between the second source region 310 and the third drain region 320 and in contact with the second source region 3310 and the third drain region 320, respectively a material layer 217 is attached to the surface of the first insulating layer 140 and the first source region 130, and a gate dielectric material layer 217 symmetrically disposed on opposite sides of the first source region 130 is defined as a first gate dielectric layer. 150.
  • a gate dielectric material layer 217 disposed between the second source region 310 and the third drain region 320 is defined as a second gate dielectric layer 330, and the first gate dielectric layer 150 includes a first gate dielectric portion 151 and a second gate dielectric portion 152, the first gate dielectric portion 151 is stacked on the first insulating layer 140, and one end of the second gate dielectric portion 152 is connected to the first gate dielectric portion 151 The second gate dielectric portion 152 is attached to the surface of the first source region 130, as shown in FIG. 2 4.
  • the step S135a includes the following steps.
  • Steps S135a-I depositing a full layer of gate material layer 218, see Figure 25.
  • Steps S135a-II patterning the gate material layer 218 to remain around the first gate dielectric layer 150 and the gate material layer 218 disposed on the second gate dielectric material layer 330, disposed in the A gate material layer 218 on the first gate dielectric material layer 150 is defined as a first gate region 160, and a gate material layer 218 disposed on the second gate dielectric layer 330 is defined as a second gate region 340,
  • the gate region 160 includes a first portion 161 and a second portion 162.
  • the first portion 161 is stacked on the first gate dielectric layer 150, and one end of the second portion 162 is connected to one end of the first portion 161.
  • the second portion 162 is attached to the surface of the second gate dielectric portion 152, see FIG.
  • the method of fabricating the semiconductor device further includes the following steps.
  • Step I corresponding to the first drain region 110, the second drain region 120, the first source region 130,
  • the first gate region 160, the second source region 310, the third drain region 320, and the second gate region 340 form a first drain 171, a second drain 172, and a first source 173, respectively.
  • the two first gates 174, the second source 351, the third drain 352, and the second gate 353 are respectively associated with the first drain region 110 and the second drain region 120.
  • the first source region 130, the second portion 162 of the first gate region 160, the second source region 310, the third drain region 320, and the second gate region 340 are electrically connected.
  • the method for preparing the semiconductor device further includes the following steps before the step I.
  • Step S136a in the first drain region 110, the second drain region 120, the first source region 130 and the first gate region 160, and the second source region 310, the third drain An insulating isolation layer 219 is formed on the region 320 and the second gate region 340 to cover the first drain region 110, the second drain region 120, the first source region 130, and the first gate region 160.
  • the upper insulating isolation layer 219 is defined as a first isolation layer 180, and the insulating isolation layer 219 overlying the second source region 310, the third drain region 320, and the second gate region 340 is defined as a second isolation.
  • Layer 360 is defined as a first isolation layer 180, and the insulating isolation layer 219 overlying the second source region 310, the third drain region 320, and the second gate region 340 is defined as a second isolation.
  • Step S137a a first through hole 181, a second through hole 182, a third through hole 183, a fourth through hole 184, and a fifth through hole 185 are formed in the first isolation layer 180, and the fourth through hole 184 is formed in the first isolation layer 180.
  • the fifth through holes 185 are respectively disposed on two sides of the third through hole 183, the first through holes 181 are disposed corresponding to the first drain region 110, and the first drain electrode 171 passes through the first a uniform hole 181 for connecting the first drain region 110, the second through hole 182 for the second drain region 120, and the second drain hole 172 for connecting the second through hole 182 a second drain region 120, the third through hole 183 is disposed corresponding to the first source region 130, and the first source electrode 173 is connected to the first source region 130 through the third through hole 183.
  • the fourth through hole 184 and the fifth through hole 185 are respectively disposed corresponding to the second portion 162 of the first gate region 160, and the two first gate electrodes 174 respectively pass through the fourth through hole 184 and the A fifth via 185 connects the second portion 162 of the first gate region 160.
  • Step S138a a seventh through hole 361, an eighth through hole 362, and a ninth through hole 363 are defined in the second isolation layer 360.
  • the seventh through hole 361 is disposed corresponding to the second source region 310.
  • the second source 351 is connected to the second source region 310 through the seventh through hole 361.
  • the eighth through hole 362 is disposed corresponding to the third drain region 320, and the third drain 352 passes through the first
  • the eight through holes 362 are connected to the third drain region 320
  • the ninth through holes 363 are disposed corresponding to the second gate region 340, and the second gate electrode 353
  • the second gate region 340 is connected through the ninth through hole 363. Please refer to FIG. 27 in the above steps S136a to S138a.
  • the method of fabricating the semiconductor device further includes at least one of the following steps.
  • Step S139a-I forming a first ohmic contact layer 181 between the first drain electrode 171 and the first drain region 110, the first drain electrode 171 connecting the first ohmic contact layer 181 The first drain region 110.
  • the first ohmic contact layer 181 is disposed between the first drain 171 and the first drain region 110 to connect the first drain 171 and the first drain region 110, the first The ohmic contact layer 181 serves to reduce the contact resistance between the first drain 171 and the first drain region 110.
  • Step S139a-II a second ohmic contact layer 182 is formed between the second drain 172 and the second drain region 120, and the second drain 172 is connected to the second ohmic contact layer 182.
  • the second ohmic contact layer 182 is disposed between the second drain 172 and the second drain region 120 to connect the second drain 172 and the second drain region 120, the second The ohmic contact layer 182 is for reducing the contact resistance between the second drain 172 and the second drain region 120.
  • Steps S139a-III forming a third ohmic contact layer 183 between the first source 173 and the first source region 130, the first source 173 being connected by the third ohmic contact layer 183 The first source region 130.
  • the third ohmic contact layer 183 is disposed between the first source 173 and the first source region 130 to connect the first source 173 and the first source region 130, the third The ohmic contact layer 183 serves to reduce the contact resistance between the first source 173 and the first source region 130.
  • Steps S139a-IV forming a fourth ohmic contact layer 184 between the first first gate 174 and the second portion 162 of the first gate region 160, the first one of the first gates 174 passing
  • the fourth ohmic contact layer 184 is connected to the second portion 162 of the first gate region 160.
  • the fourth ohmic contact layer 184 is disposed between the first first gate 174 and the second portion 162 of the first gate region 160 to connect the first first gate 174 and the a second portion 162 of the first gate region 160, the fourth ohmic contact layer 184 is for reducing between the first first gate 174 and the second portion 162 of the first gate region 160 Contact resistance.
  • Steps S139a-V forming a fifth ohmic contact layer 185 between the second first gate 174 and the second portion 162 of the first gate region 160, and the second first gate 174 passes
  • the fifth ohmic contact 185 connects the second portion 162 of the first gate region 160.
  • the fifth ohmic contact layer 185 Between the second first gate 174 and the second portion 162 of the first gate region 160 to connect the second first gate 174 and the first gate region 160
  • the second portion 162 is for reducing the contact resistance between the second first gate 174 and the second portion 162 of the first gate region 160.
  • Steps S139a-VI forming a seventh ohmic contact layer 381 between the second source 351 and the second source region 310, the second source 351 connecting the seventh ohmic contact layer 381 The second source area 310.
  • the seventh ohmic contact layer 381 is disposed between the second source 351 and the second source region 310 to connect the second source 351 and the second source region 310, the seventh The ohmic contact layer 381 serves to reduce the contact resistance between the second source 351 and the second source region 310.
  • Steps S139a-VII forming an eighth ohmic contact layer 382 between the third drain electrode 173 and the third drain region 320, the third drain electrode 173 being connected by the eighth ohmic contact layer 382 The third drain region 320.
  • the eighth ohmic contact layer 382 is disposed between the third drain 173 and the third drain region 320 to connect the third drain 173 and the third drain region 320, the eighth The ohmic contact layer 382 serves to reduce the contact resistance between the third drain 173 and the third drain region 320.
  • Steps S139a-VIII forming a ninth ohmic contact layer 383 between the second gate 353 and the second gate region 340, the second gate electrode 353 being connected by the ninth ohmic contact layer 383 The second gate region 340.
  • the ninth ohmic contact layer 383 is disposed between the second gate 353 and the second gate region 340 to connect the second gate 353 and the second gate region 340, the ninth The ohmic contact layer 383 serves to reduce the contact resistance between the second gate 353 and the second gate region 340.
  • the step S120 when the planar device 200 is a metal oxide semiconductor transistor, the step S120 includes the following steps after the step S130.
  • step a2 a second hard mask layer 214 and a photoresist 215 are deposited on the second type of ion heavily doped semiconductor layer 213, see FIG.
  • Step b2 patterning the second hard mask layer 214 and the photoresist 215 to retain a second hard mask layer 214 corresponding to the first source region 110 and the second source region 120 Photoresist 215, see Figure 29.
  • step c2 the second type of ion heavily doped semiconductor layer 213 is etched by using the remaining second hard mask layer 214 and the photoresist 215 as a mask to retain the second hard mask layer 214 and a second type of ion-covered semiconductor layer 213 covered by the photoresist 215 to form the first source region 130, please refer to Figure 30.
  • step d2 the second hard mask layer 214 corresponding to the middle of the first region 20a and the photoresist 215 are stripped, please refer to FIG.
  • step S134a and the step S135a comprise the following steps.
  • Steps S134a-I' deposit an entire layer of gate dielectric material layer 217.
  • Steps S134a-II' deposit a full layer of gate material layer 218 over the entire gate dielectric material 217, see FIG.
  • Steps S134a-III' patterning the gate dielectric material layer 217 and the gate material layer 218 to remove the first drain region 110, the second drain region 120, and the second source
  • the gate dielectric material layer 217 and the gate material layer 218 on the region 310 and the third drain region 320, and the remaining gate dielectric material layer 217 is the first gate dielectric layer 150, wherein the first gate dielectric layer 150 includes a first gate dielectric portion 151, a second gate dielectric portion 152, and a third gate dielectric portion 153.
  • the first gate dielectric portion 151 is stacked on the first insulating layer 140, and the second gate dielectric portion 152 is One end is connected to the first gate dielectric portion 151 and the second gate dielectric portion 152 is attached to the surface of the first source region 130, and the third dielectric portion 153 is connected to the second gate dielectric portion 152 away from the surface.
  • the first gate region 160 includes a first portion 161, a second portion 162 and a third portion 163, wherein the first portion 161 is stacked and disposed in the On the first gate dielectric layer 150, one end of the second portion 162 is connected to one end of the first portion 161 and the second portion 162 is attached to the surface of the second gate dielectric portion 152, the third portion 163 connects the second portion 162 away from one end of the first portion 161, and the third portion 163 covers the third gate dielectric portion 153, please refer to FIG.
  • the method of fabricating the semiconductor device further includes the following steps.
  • Step II corresponding to the first drain region 110, the second drain region 120, the first source region 130, the first gate region 160, the second source region 310, and the third drain region 320 and the second gate region 340 respectively form a first drain 171, a second drain 172, a first source 173, three first gates 174, second source 351, third drain 352, and a second gate 353, the first drain 171, the second drain 172, the first source 173, the second source 351, the third drain 352, and the first a second gate 353 and the first drain region 110, the second drain region 120, the first source region 130, the second source region 310, the third drain region 320, and the second
  • the gate region 340 is electrically connected, wherein the two first gates 174 are connected to the second portion 162 and are respectively disposed on two sides of the first source 173, and the other first gate 174 is connected to the third portion 163.
  • the method for preparing the semiconductor device further includes the following steps before the step II.
  • Step S136b in the first drain region 110, the second drain region 120, the first source region 130 and the first gate region 160, and the second source region 310, the third drain An insulating isolation layer 219 is formed on the region 320 and the second gate region 340 to cover the first drain region 110, the second drain region 120, the first source region 130, and the first gate region 160.
  • the upper insulating isolation layer 219 is defined as a first isolation layer 180, and the insulating isolation layer 219 overlying the second source region 310, the third drain region 320, and the second gate region 340 is defined as a second isolation.
  • Layer 360 is defined as a first isolation layer 180, and the insulating isolation layer 219 overlying the second source region 310, the third drain region 320, and the second gate region 340 is defined as a second isolation.
  • Step S137b a first through hole 181, a second through hole 182, a third through hole 183, a fourth through hole 184, a fifth through hole 185, and a sixth through hole 186 are defined in the first isolation layer 180.
  • the fourth through hole 184 and the fifth through hole 185 are respectively disposed on two sides of the third through hole 183, and the first through hole 181 is disposed corresponding to the first drain portion 110, the first drain
  • the pole 171 passes through the first through hole 181 to connect the first drain region 110, the second through hole 182 is disposed corresponding to the second drain region 120, and the second drain electrode 172 passes through the second drain region a hole 182 for connecting the second drain region 120, the third through hole 183 is disposed corresponding to the first source region 130, and the first source electrode 173 is connected to the first through the third through hole 183
  • the source region 130, the fourth through hole 184 and the fifth through hole 185 are respectively disposed corresponding to the second portion 162 of the first gate region 160, and
  • the two first gates 174 are respectively connected to the second portion 162 of the first gate region 160 through the fourth through hole 184 and the fifth through hole 185, and the other first gate 174 passes through the Six through hole 186 connected to the first gate region 163 of the third portion 160.
  • Step S138b a seventh through hole 361, an eighth through hole 362, and a ninth through hole 363 are defined in the second isolation layer 360.
  • the seventh through hole 361 is disposed corresponding to the second source region 310.
  • the second source 351 is connected to the second source region 310 through the seventh through hole 361.
  • the eighth through hole 362 is disposed corresponding to the third drain region 320, and the third drain 352 passes through the first
  • the eighth through hole 362 is connected to the third drain region 320
  • the ninth through hole 363 is disposed corresponding to the second gate region 340
  • the second gate electrode 353 is connected to the second through the ninth through hole 363 Gate area 340.
  • the method of fabricating the semiconductor device further includes at least one of the following steps.
  • Step S139b-I forming a first ohmic contact layer 181 between the first drain electrode 171 and the first drain region 110, the first drain electrode 171 connecting the first ohmic contact layer 181 The first drain region 110.
  • the first ohmic contact layer 181 is disposed between the first drain 171 and the first drain region 110 to connect the first drain 171 and the first drain region 110, the first The ohmic contact layer 181 serves to reduce the contact resistance between the first drain 171 and the first drain region 110.
  • Step S139b-II a second ohmic contact layer 182 is formed between the second drain 172 and the second drain region 120, and the second drain 172 is connected to the second ohmic contact layer 182.
  • the second ohmic contact layer 182 is disposed between the second drain 172 and the second drain region 120 to connect the second drain 172 and the second drain region 120, the second The ohmic contact layer 182 is for reducing the contact resistance between the second drain 172 and the second drain region 120.
  • Step S139b-III forming a third ohmic contact layer 183 between the first source 173 and the first source region 130, the first source 173 being connected by the third ohmic contact layer 183 The first source region 130.
  • the third ohmic contact layer 183 is disposed between the first source 173 and the first source region 130 to connect the first source 173 and the first source region 130, the third The ohmic contact layer 183 serves to reduce the contact resistance between the first source 173 and the first source region 130.
  • Steps S139b-IV forming a fourth ohmic contact layer 184 between the first first gate 174 and the second portion 162 of the first gate region 160, the first one of the first gates 174 passing
  • the fourth ohmic contact layer 184 is connected to the second portion 162 of the first gate region 160.
  • the fourth ohmic contact layer 184 is disposed between the first first gate 174 and the second portion 162 of the first gate region 160 to connect the first first gate 174 and the a second portion 162 of the first gate region 160, the fourth ohmic contact layer 184 is for reducing between the first first gate 174 and the second portion 162 of the first gate region 160 Contact resistance.
  • Step S139b-V forming a fifth ohmic contact layer 185 between the second first gate 174 and the second portion 162 of the first gate region 160, and the second first gate 174 passes
  • the fifth ohmic contact 185 connects the second portion 162 of the first gate region 160.
  • the fifth ohmic contact layer 185 is disposed between the second first gate 174 and the second portion 162 of the first gate region 160 to connect the second first gate 174 and the a second portion 162 of the first gate region 160, the fifth The ohmic contact layer 185 serves to reduce the contact resistance between the second first gate 174 and the second portion 162 of the first gate region 160.
  • Steps S139b-VI forming a sixth ohmic contact layer 186 between the third first gate 174 and the third portion 163 of the first gate region 160, and the third first gate 174 passes
  • the sixth ohmic contact layer 186 is connected to the third portion 163 of the first gate region 160.
  • Step S139b-VII forming a seventh ohmic contact layer 381 between the second source 351 and the second source region 310, the second source 351 connecting the seventh ohmic contact layer 381 The second source area 310.
  • the seventh ohmic contact layer 381 is disposed between the second source 351 and the second source region 310 to connect the second source 351 and the second source region 310, the seventh The ohmic contact layer 381 serves to reduce the contact resistance between the second source 351 and the second source region 310.
  • Steps S139b-VIII forming an eighth ohmic contact layer 382 between the third drain 173 and the third drain region 320, the third drain electrode 173 being connected by the eighth ohmic contact layer 382 The third drain region 320.
  • the eighth ohmic contact layer 382 is disposed between the third drain 173 and the third drain region 320 to connect the third drain 173 and the third drain region 320, the eighth The ohmic contact layer 382 serves to reduce the contact resistance between the third drain 173 and the third drain region 320.
  • Steps S139b-V-IV forming a ninth ohmic contact layer 383 between the second gate 353 and the second gate region 340, the second gate electrode 353 being connected through the ninth ohmic contact layer 383 The second gate region 340.
  • the ninth ohmic contact layer 383 is disposed between the second gate 353 and the second gate region 340 to connect the second gate 353 and the second gate region 340, the ninth The ohmic contact layer 383 serves to reduce the contact resistance between the second gate 353 and the second gate region 340.
  • the first drain region 110 and the second drain region 120 in the first region 20a and the second region of the MOS transistor 300 in the second region 20b in the method for fabricating the semiconductor device of the present invention The doping types of the source region 310 and the third drain region 320 are the same, and can be realized by one ion implantation, which reduces the process steps for preparing the semiconductor device, and the process complexity, that is, the cost is reduced. Moreover, the preparation process of the semiconductor device of the present invention is compatible with the standard process of the existing CMOS of the betta, without adding unnecessary complicated processes.
  • step S120 further includes the following steps after the step S130.
  • Step S131c forming a first surface embedded in the first surface 100c from the first surface 100c
  • the drain region 110 and the second drain region 120 form a first doping region 410 embedded in the second surface 200c on the second surface 200c; wherein one end of the first drain region 110 and the first portion
  • the surface 100c is flush, one end of the second drain region 120 is flush with the first surface 100c, and the first drain region 110 is opposite to the second drain region 120 and is spaced apart by a portion of the first substrate 100a.
  • the first drain region 110 is in contact with the first shallow trench isolation region 11, the second drain The region 120 is in contact with the second shallow trench isolation region 12; one end of the first doped region 410 is flush with the third surface 200c, and the first doped region 410 is disposed at the third shallow Between the trench isolation region 13 and the fourth shallow trench isolation region 14, one end of the first doping region 410 is in contact with the third shallow trench isolation region 13, the first doping region 410 The other end is in contact with the fourth shallow trench isolation region 14.
  • step S132c the first source region 130 is formed.
  • the first source region 130 is convexly disposed on the first surface 100c, and the first source region 130 is located between the first drain region 110 and the second drain region 120.
  • step S133c the first insulating layer 140 and the second insulating layer 420 are formed.
  • the first insulating layer 140 is disposed on the surface of the first substrate, and the first insulating layer 140 is symmetrically disposed on two sides of the first source region 130, and is respectively connected to the first drain region 110. And between the first source region 130 and between the second drain region 120 and the first source region 130, and the thickness of the first insulating layer 140 is smaller than the height of the first source region 130.
  • the second insulating layer 420 is disposed at a middle portion of the first doping region 410 and the second insulating layer 420 does not cover both ends of the first doping region 410, and the second insulating layer 420 is The first insulating layer 140 is located in the same layer.
  • step S134c the first gate dielectric layer 151 and the third gate dielectric layer 430 are formed at intervals.
  • the first gate dielectric layer 150 is symmetrically disposed on both sides of the first source region 130 and conforms to the surfaces of the first source region 130 and the first insulating layer 140.
  • the third gate dielectric layer 430 is stacked on the second insulating layer 420.
  • step S135c a first gate region 160 and a third gate region 440 are formed.
  • the first gate region 160 is disposed around the first gate dielectric layer 150.
  • the third gate region 440 is stacked on the third gate dielectric layer 430.
  • the step S131c includes the following steps.
  • Step S131c-I sequentially forming oxide layers 211 stacked on the same surface of the substrate 20.
  • the third hard mask layer 220 please refer to FIG.
  • Step S131c-II patterning the oxide layer 211 and the third hard mask layer 220 to remove the oxide layer 211 and the third layer located at both ends of the first region 20a and the second region 20b
  • the hard mask layer 220 please refer to FIG.
  • Step S131c-III performing a first type of ion heavy doping on the surface of the substrate 20 with the patterned oxide layer 211 and the third hard mask layer 220 as a mask to be in the first region 20a.
  • the first drain region 110 and the second drain region 120 are formed at intervals, and the first doping region 410 is formed in the second region 20b, please refer to FIG.
  • the method for fabricating the semiconductor device further comprises: annealing the substrate 20.
  • step S132c specifically includes the following steps.
  • Step S132c-I depositing a second type of ion heavily doped semiconductor layer 213, see FIG.
  • Step S132c-II patterning the second type of ion heavily doped semiconductor layer 213 to form the first source region 130.
  • the step S132c-II specifically includes the following steps.
  • Step a3 depositing a fourth hard mask layer 221 and a photoresist 215 on the second type of ion heavily doped semiconductor layer 213, please refer to FIG.
  • Step b3 patterning the fourth hard mask layer 221 and the photoresist 215 to retain a fourth hard mask layer 221 corresponding to the first source region 110 and the second source region 120 Photoresist 215, see Figure 41.
  • step c3 the second type of ion heavily doped semiconductor layer 213 is etched by using the remaining fourth hard mask layer 221 and the photoresist 215 as a mask to retain the fourth hard mask layer 221 and The second type of ion covered by the photoresist 215 is heavily doped with the semiconductor layer 213 to form the first source region 130, see FIG.
  • step d3 the photoresist 215 corresponding to the middle of the first region 20a is peeled off, please refer to FIG.
  • step S133c specifically includes the following steps.
  • Step S133c-I depositing an insulating layer 216, the insulating layer 216 having a thickness smaller than the height of the first source region 130, please refer to FIG.
  • Step S133c-II patterning the insulating layer 216 to retain a portion of the insulating layer 216 surrounding the first source region 130 and a portion of the insulating layer 216 disposed in the middle of the first doping region 410, wherein A portion of the insulating layer 216 surrounding the first source region 130 is the first insulating layer 140, and a portion of the insulating layer disposed in the middle of the first doping region 410 is a second insulating layer 420, see FIG. 45. .
  • step S134c specifically includes the following steps.
  • Step S134c-I depositing a full layer of gate dielectric material layer 217, see FIG.
  • Step S134c-II patterning the gate dielectric material layer 217 to remain adhered to the first insulating layer 140 and the first source region 130, and symmetrically disposed on both sides of the first source region 130 a gate dielectric material layer 217, and a gate dielectric material layer 217 disposed on the second insulating layer 420, attached to the first insulating layer 140 and the first source region 130, and symmetrically disposed at A gate dielectric material layer 217 on both sides of the first source region 130 is defined as a first gate dielectric layer 150, and a gate dielectric material layer 217 disposed on the second insulating layer 420 is defined as a third gate dielectric layer 430.
  • the first gate dielectric layer 150 includes a first gate dielectric portion 151 and a second gate dielectric portion 152.
  • the first gate dielectric portion 151 is stacked on the first insulating layer 140, and the second gate dielectric portion 152 is disposed.
  • One end is connected to the first gate dielectric portion 151 and the second gate dielectric portion 152 is attached to the surface of the first source region 130, see FIG.
  • step S135c specifically includes the following steps.
  • Step S135c-I depositing a full layer of gate material layer 218, see FIG.
  • Step S135c-II patterning the gate material layer 218 to remain around the first gate dielectric layer 150 and the gate material layer 218 disposed on the third gate dielectric layer 430, disposed in the first gate
  • a gate material layer 218 on the dielectric layer 150 is defined as a first gate region 160
  • a gate material layer disposed on the third gate dielectric layer 430 is defined as a third gate region 440
  • the first gate region 160 including a first portion 161 and a second portion 162
  • the first portion 161 is stacked on the first gate dielectric layer 150
  • one end of the second portion 162 is connected to one end of the first portion 161 and the second portion 162 is attached to the surface of the second gate dielectric portion 152, see FIG.
  • the method of fabricating the semiconductor device further includes the following steps.
  • Step III corresponding to the first drain region 110, the second drain region 120, the first source region 130, and the first gate region 160 to form a first drain 171, a second drain 172, and a first source, respectively.
  • a pole 173 and two first gates 174, and one end corresponding to the first doping region 410 form a first electrode 451, corresponding to The other end of the first doping region 410 forms a second electrode 452, and the third electrode 453 is formed corresponding to the third gate region 440.
  • the method for preparing the semiconductor device further comprises the following steps.
  • Step S136c forming an insulating isolation layer 219 on the first drain region 110, the second drain region 120, the first source region 130, the first gate region 160, and the third gate region 440
  • An insulating isolation layer 219 covering the first drain region 110, the second drain region 120, the first source region 130, and the first gate region 160 is defined as a first isolation layer 180 covering the The insulating isolation layer 219 on the third gate region 440 is defined as a third isolation layer 460.
  • Step S137c a first through hole 181, a second through hole 182, a third through hole 183, a fourth through hole 184, and a fifth through hole 185 are formed in the first isolation layer 180, and the fourth through hole 184 is formed in the first isolation layer 180.
  • the fifth through holes 185 are respectively disposed on two sides of the third through hole 183, the first through holes 181 are disposed corresponding to the first drain region 110, and the first drain electrode 171 passes through the first a uniform hole 181 for connecting the first drain region 110, the second through hole 182 for the second drain region 120, and the second drain hole 172 for connecting the second through hole 182 a second drain region 120, the third through hole 183 is disposed corresponding to the first source region 130, and the first source electrode 173 is connected to the first source region 130 through the third through hole 183.
  • the fourth through hole 184 and the fifth through hole 185 are respectively disposed corresponding to the second portion 162 of the first gate region 160, and the two first gate electrodes 174 respectively pass through the fourth through hole 184 and the A fifth via 185 is connected to the first gate region 160.
  • Step S138c a tenth through hole 461, a tenth through hole 462, and a twelfth through hole 463 are formed in the third isolation layer 460, and the first electrode 451 is connected through the tenth through hole 461.
  • One end of the first doping region 410, the second electrode 452 is connected to the other end of the first doping region 410 through the tenth uniform hole 462, and the third electrode 453 passes through the twelfth pass
  • the hole 463 is connected to the third gate region 440, and the steps S136c to 138c are referred to FIG. 50 together.
  • the step S120 further includes the following steps after the step S130.
  • Step S131d forming a first surface embedded in the first surface 100c from the first surface 100c
  • the drain region 110 and the second drain region 120 form a second doping region 410 embedded in the second surface 200c on the second surface 200c; wherein one end of the first drain region 110 and the first portion
  • the surface 100c is flush
  • one end of the second drain region 120 is flush with the first surface 100c
  • the first drain region 110 is opposite to the second drain region 120 and is spaced apart by a portion of the first substrate 100a.
  • the first drain region 110 is in contact with the first shallow trench isolation region 11, the second drain The region 120 is in contact with the second shallow trench isolation region 12; one end of the second doped region 510 is flush with the third surface 200c, and the second doped region 510 is disposed at the third shallow Between the trench isolation region 13 and the fourth shallow trench isolation region 14, one end of the second doping region 510 is in contact with the third shallow trench isolation region 13, and the second doping region 510 The other end is in contact with the fourth shallow trench isolation region 14.
  • the second doping region 510 is located on the same layer as the first drain region 110 and the second drain region 120, please refer to FIG. 51.
  • step S132d the first source region 130 is formed.
  • the first source region 130 is disposed on a surface of the first substrate 20, and the first source region 130 is located between the first drain region 110 and the second drain region 120. See Figure 52.
  • the first insulating layer 140 is formed.
  • the first insulating layer 140 is disposed on the surface of the first substrate, and the first insulating layer 140 is symmetrically disposed on two sides of the first source region 130, and is respectively connected to the first drain region 110. Between the first source region 130 and the second drain region 120 and the first source region 130, and the thickness of the first insulating layer 140 is smaller than the height of the first source region 130, Please refer to Figure 53 together.
  • a first gate dielectric layer 150 is formed.
  • the first gate dielectric layer 150 is symmetrically disposed on both sides of the first source region 130 and conforms to the surfaces of the first source region 130 and the first insulating layer 140. Please refer to Figure 54 together.
  • step S135d a first gate region 160 is formed, and the first gate region 160 is disposed around the first gate dielectric layer 150. Please refer to Figure 55 together.
  • the method of fabricating the semiconductor device further includes the following steps.
  • Step IV forming a first drain 171, a second drain 172, and a first drain region 110, the second drain region 120, the first source region 130, and the first gate region 160, respectively.
  • a source 173 and two first gates 174, and two ends of the second doped region 510 respectively form a fourth electrode 520 and a fifth electrode 530.
  • the method for preparing the semiconductor device further comprises the following steps.
  • Step S136d forming an insulating isolation layer on the first drain region 110, the second drain region 120, the first source region 130 and the first gate region 160, and the second doping region 510.
  • an insulating isolation layer 219 covering the first drain region 110, the second drain region 120, the first source region 130, and the first gate region 160 is defined as a first isolation layer 180, covering The insulating isolation layer 219 on the second doping region 510 is defined as a fourth isolation layer 540.
  • Step S137d a first through hole 181, a second through hole 182, a third through hole 183, a fourth through hole 184, and a fifth through hole 185 are formed in the first isolation layer 180, and the fourth through hole 184 is formed in the first isolation layer 180.
  • the fifth through holes 185 are respectively disposed at two sides of the third through hole 183, and the first drain 171 passes through the first through hole 181 to connect the first drain region 110, the first The second drain 172 passes through the second through hole 182 to connect the second drain region 120, and the first source 173 passes through the third through hole 183 to connect the first source region 130, the two The first gates 174 are connected to the first gate region 160 through the fourth through holes 184 and the fifth through holes 185, respectively.
  • Step S138d a twelfth through hole 541 and a thirteenth through hole 542 are formed in the fourth isolation layer 540, and the fourth electrode 520 is connected to the second doping area through the twelfth through hole 541.
  • the fifth electrode 530 is connected to the other end of the second doping region 510 through the thirteenth through hole 542. Please refer to FIG. 56 for the steps S136d to S138d.
  • the same material in the tunneling field effect transistor and the planar device is formed in the same process, thereby reducing the complexity of the fabrication process of the semiconductor device. And implementation costs.
  • the semiconductor device disposed in the first region 20a in the semiconductor device 10 of the present invention is described by taking a tunneling field effect transistor as an example, it is understood that in other embodiments, the semiconductor The device in the first region 20a in the device 10 can also be other devices with a drain region disposed at the bottom.

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Abstract

本发明提供了一种半导体器件及半导体器件的制备方法。所述半导体器件包括隧穿场效应晶体管及平面器件，所述隧穿场效应晶体管包括第一衬底和第一电气元件，所述第一电气元件形成于所述第一衬底的一侧，所述平面器件包括第二衬底及第二电气元件，所述第二衬底与所述第一衬底为一体式结构并形成一个总衬底，所述第二电气元件形成于所述第二衬底的一侧，且所述第二电气元件与所述第一电气元件设置于所述总衬底的同一侧，其中，所述平面器件包括金属氧化物半导体晶体管、电容、电阻中的任意一种。

Description

半导体器件及半导体器件的制备方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体器件及半导体器件的制备方法。
背景技术
互补金属氧化物半导体器件(Complementary Metal Oxide Semiconductor,CMOS)是微电子集成电路的核心组成器件，其尺寸和工作电压遵循摩尔(Moore)定律，以获得更优异的性能和更高的集成密度。然而，随着CMOS的尺寸的减小，其功耗也在持续增加。部分原因是短沟道效应引起的泄露电流的增加，同时也归咎于器件的供电电压越来越难以缩减。其中，CMOS器件的供电电压难以缩减主要是由于CMOS器件的亚阈值摆幅较大，一般高于60mV/dec。而隧穿场效应晶体管(Tunnel Field Effect Transistor,TFET)因具有较低的泄露电流及陡峭的亚阈值斜率而被认为是替代CMOS器件的较好元件。目前，TFET与传统的平面结构(如，MOS管、或者电容、或者电阻)共同搭建电路时，由于TFET本身结构特点的限制，导致与传统的平面结构结合存在一定的难度。目前，在非平面TFET与平面结构集成时通常采用先形成TFET，再形成平面结构，接着将TFET和平面结构结合，这样就很大程度上增加了工艺的复杂程度及实现成本。
发明内容
第一方面，本发明提供了一种半导体器件，所述半导体器件包括隧穿场效应晶体管及平面器件，所述隧穿场效应晶体管包括第一衬底和第一电气元件，所述第一电气元件形成于所述第一衬底的一侧，所述平面器件包括第二衬底及第二电气元件，所述第二衬底与所述第一衬底为一体式结构并形成一个总衬底，所述第二电气元件形成于所述第二衬底的一侧，且所述第二电气元件与所述第一电气元件设置于所述总衬底的同一侧，其中，所述平面器件包括金属氧化物半导体晶体管、电容、电阻中的任意一种。
在第一种实施方式中，所述第一衬底包括相对设置的第一表面及第二表 面，所述第二衬底包括相对设置的第三表面及第四表面，所述第一衬底与所述第二衬底接触，且所述第三表面与所述第一表面平齐，所述第四表面与所述第三表面平齐。
结合第一种实施方式，在第二种实施方式中，所述第一电气元件包括第一浅沟道隔离区及第二浅沟道隔离区，所述第一浅沟道隔离区及所述第二浅沟道隔离区自所述第一表面嵌入所述第一衬底，且所述第一浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区与所述第一浅沟道隔离区相对且间隔部分第一衬底。
结合第二种实施方式，在第三种实施方式中，所述第一电气元件还包括第一漏区、第二漏区、第一源区、第一绝缘层、第一栅电介质层及第一栅区，所述第一漏区及所述第二漏区自所述第一表面嵌入所述第一衬底内部，且所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第一源区凸出设置于所述第一表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；所述第一绝缘层凸出设置于所述第一表面；所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的高度小于所述第一源区的高度；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；所述第一栅区围绕所述第一栅电介质层设置。
结合第三种实施方式，在第四种实施方式中，所述第一栅电介质层包括第一栅电介质部及第二栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面。
结合第四种实施方式，在第五种实施方式中，所述第一栅区包括第一部分及第二部分，所述第一部分层叠设置在所述第一栅电介质部上，所述第二部分的一端与所述第一部分的一端相连且所述第二部分贴合所述第二栅电介质部的表面。
结合第五种实施方式，在第六种实施方式中，所述第一栅电介质层还包括第三栅电介质部，所述第三栅电介质部连接所述第二栅电介质部远离所述第一栅电介质部的一端，且所述第三栅电介质部覆盖所述第一源区远离所述衬底的一端，所述第一栅区还包括第三部分，所述第三部分连接所述第二部分远离所述第一部分的一端，且所述第三部分覆盖在所述第三栅电介质部上。
结合第五种实施方式，在第七种实施方式中，所述第一电气元件还包括第一漏极、第二漏极、第一源极及两个第一栅极，所述第一漏极、所述第二漏极、所述第一源极及两个所述第一栅极分别对应连接所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区的第二部分，且两个第一栅极分别设置于所述第一源极两侧。
进一步地，所述第一电气元件还包括第一隔离层，所述第一隔离层覆盖所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区，所述第一隔离层设置有第一贯孔、第二贯孔、第三贯孔、第四贯孔及第五贯孔，所述第一贯孔对应所述第一漏区设置，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二贯孔对应所述第二漏区设置，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第三贯孔对应所述第一源区设置，所述第一源极通过所述第三贯孔以连接所述第一源区，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，且所述第四贯孔及所述第五贯孔分别对应所述第一栅区的第二部分设置，所述两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区的第二部分。
进一步地，所述第一电气元件还包括第一欧姆接触层、第二欧姆接触层、第三欧姆接触层、第三欧姆接触层、第四欧姆接触层及第五欧姆接触层中的至少一个，其中，所述第一欧姆接触层设置于所述第一漏极及所述第一漏区之间，以连接所述第一漏极及所述第一漏区，所述第二欧姆接触层设置于所述第二漏极及所述第二漏区之间，以连接所述第二漏极及所述第二漏区，所述第三欧姆接触层设置于所述第一源极及所述第一源区之间，以连接所述第一源极及所述第一源区，所述第四欧姆接触层设置于第一个所述第一栅极及所述第一栅区的第二部分之间，以连接第一个所述第一栅极及所述第一栅区的第二部分，所述第五欧姆接触层设置于第二个所述第一栅极及所述第一栅区的第二部分之间， 以连接第二个所述第一栅极及所述第一栅区的第二部分。
结合第六种实施方式，在第八种实施方式中，所述第一电气元件还包括第一漏极、第二漏极、第一源极及三个第一栅极，所述第一漏极、所述第二漏极、所述第一源极及三个第一栅极分别对应连接所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区设置，其中两个第一栅极连接第二部分且分别设置于所述第一源极两侧，另外一个第一栅极连接所述第三部分。
进一步地，所述第一电气元件还包括第一隔离层，所述第一隔离层覆盖所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区，所述第一隔离层设置有第一贯孔、第二贯孔、第三贯孔、第三贯孔、第五贯孔及第六贯孔，所述第一贯孔对应所述第一漏区设置，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二贯孔对应所述第二漏区设置，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第三贯孔对应所述第一源区设置，所述第一源极通过所述第三贯孔以连接所述第一源区，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔两侧，且所述第四贯孔及所述第五贯孔分别对应所述第一栅区的第二部分设置，所述第六贯孔对应所述第三部分设置，其中两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第二部分，另外一个第一栅极通过所述第六贯孔连接所述第三部分。
进一步地，所述第一电气元件还包括第一欧姆接触层、第二欧姆接触层、第三欧姆接触层、第三欧姆接触层、第四欧姆接触层第五欧姆接触层及所述第六欧姆接触层中的至少一个，其中，所述第一欧姆接触层设置于所述第一漏极及所述第一漏区之间，以连接所述第一漏极及所述第一漏区，所述第二欧姆接触层设置于所述第二漏极及所述第二漏区之间，以连接所述第二漏极及所述第二漏区，所述第三欧姆接触层设置于所述第一源极与所述第一源区之间，以连接所述第一源极与所述第一源区，所述第四欧姆接触层设置于第一个所述第一栅极及所述第一栅区的第二部分之间，以连接第一个所述第一栅极及所述第一栅区的第二部分，所述第五欧姆接触层设置于第二个所述第一栅极及所述第一栅区的第二部分之间，以连接第二个所述第一栅极及所述第一栅区的第二部分，所述第六欧姆接触层设置于第三个所述第一栅极及所述第一栅区的第三部分之间，以连接第三个所述第一栅极及所述第一栅区的第三部分。
结合第一方面及第一方面的第八种实施方式中的任意一种，在第九种实施方式中，所述第二电气元件包括第三浅沟道隔离区及第四浅沟道隔离区；所述第三浅沟道隔离区及所述第四浅沟道隔离区自所述第三表面嵌入所述第二衬底内，且所述第三浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区与所述第三浅沟道隔离区相对设置且间隔部分第二衬底。
结合第九种实施方式，在第十种实施方式中，当所述平面器件为金属氧化物半导体晶体管时，所述第二电气元件包括第二源区、第三漏区、第二栅电介质层及第二栅区，所述第二源区及所述第三漏区自所述第三表面嵌入所述第二衬底内部，且所述第二源区的一端与所述第三表面平齐，所述第三漏区的一端与所述第三表面平齐，所述第二源区与所述第三漏区相对且通过部分第二衬底间隔设置在所述第三浅沟道隔离区及所述第四浅沟道隔离区之间，所述第二源区与所述第三浅沟道隔离区接触，所述第三漏区与所述第四浅沟道隔离区接触，第二栅电介质层凸出设置于所述第三表面，且所述第二栅电介质层设置于所述第二源区及所述第三漏区之间，所述第二栅区层叠设置于所述第二栅电介质层上，且所述第二栅区与所述第二栅电介质层接触。
结合第十种实施方式，在第十一种实施方式中，所述第二电气元件还包括第二源极、第三漏极及第二栅极，所述第二源极、所述第三漏极及所述第二栅极分别对应连接所述第二源区、所述第三漏区及所述第二栅区。
结合第十一种实施方式，在第十二种实施方式中，所述第二电气元件还包括第二隔离层，所述第二隔离层与所述第一隔离层位于同一层，所述第二隔离层覆盖所述第二源区、所述第三漏区及所述第二栅区，所述第二隔离层上设置有第七贯孔、第八贯孔及第九贯孔，所述第七贯孔对应所述第二源区设置，所述第二源极通过所述第七贯孔连接所述第二源区，所述第八贯孔对应所述第三漏区设置，所述第三漏极通过所述第八贯孔连接所述第三漏区，所述第九贯孔对应所述第二栅区设置，所述第二栅极通过所述第九贯孔连接所述第二栅区。
进一步地，所述第二电气元件还包括第七欧姆接触层、第八欧姆接触层及第九欧姆接触层中的至少一个，其中，所述第七欧姆接触层设置于所述第二源极及所述第二源区之间，所述第八欧姆接触层设置于所述第三漏极及所述第三 漏区之间，所述第九欧姆接触层设置于所述第二栅极及所述第二栅区之间。
结合第十种实施方式，在第十三种实施方式中，所述第一漏区、所述第二漏区、所述第二源区及所述第三漏区为第一类型离子重掺杂区域，所述第一源区为第二类型离子重掺杂区域，其中，所述第一类型离子重掺杂区域为N型离子重掺杂区域，所述第二类型离子重掺杂区域为P型离子重掺杂区域；或者所述第一类型离子重掺杂区域为P型离子重掺杂区域，所述第二类型离子重掺杂区域为N型离子重掺杂区域。
结合第九种实施方式，在第十四种实施方式中，当所述平面器件为电容时，所述第二电气元件包括第一掺杂区、第二绝缘层、第三栅电介质层及第三栅区，所述第一掺杂区自所述第三表面嵌入所述第二衬底内部，所述第一掺杂区的一端与所述第三表面平齐，所述第一掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第一掺杂区的一端与所述第三浅沟道隔离区接触，所述第一掺杂区的另一端与所述第四浅沟道隔离区接触，所述第二绝缘层设置于所述第一掺杂区的中部且所述第二绝缘层未覆盖所述第一掺杂区的两端，所述第三栅电介质层层叠设置于所述第二绝缘层上，所述第三栅区层叠设置于所述第三栅电介质层上。
结合第十四种实施方式，在第十五种实施方式中，所述第二电气元件还包括第一电极、第二电极及第三电极，所述第一电极及所述第二电极分别对应连接所述第一掺杂区的两端，所述第三电极连接所述第三栅区。
进一步地，所述第二电气元件还包括第三隔离层，所述第三隔离层设置于所述第一掺杂区未覆盖所述第二绝缘层的表面及所述第三栅区的表面，所述第三隔离层设置有第十贯孔、第十一贯孔及第十二贯孔，所述第十贯孔对应所述第一掺杂区的一端设置，所述第一电极通过所述第十贯孔连接所述第一掺杂区的一端，所述第十一贯孔对应所述第一掺杂区的另一端设置，所述第二电极通过所述第十一贯孔连接所述第一掺杂区的另一端，所述第十二贯孔对应所述第三栅区设置，所述第三电极通过所述第十二贯孔连接所述第三栅区。
结合第九种实施方式，在第十六种实施方式中，当所述平面器件为电阻时，所述第二电气元件包括第二掺杂区，所述第二掺杂区自所述第三表面嵌入所述第三表面嵌入所述第二衬底内部，所述第二掺杂区的一端与所述第三表面平 齐，所述第二掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第二掺杂区的一端与所述第三浅沟道隔离区接触，所述第二掺杂区的另一端与所述第四浅沟道隔离区接触。
结合第十六种实施方式，在第十七种实施方式中，第二电气元件还包括第四电极及第五电极，所述第四电极及所述第五电极分别对应连接所述第二掺杂区的两端。
进一步地，第二电气元件还包括第四隔离层，所述第四隔离层覆盖所述第二掺杂区，所述第四隔离层设置有第十二贯孔及第十三贯孔，所述第十二贯孔及所述第十三贯孔分别对应所述第二掺杂区的两端设置，所述第四电极通过所述第十二贯孔连接所述第二掺杂区的一端，所述第五电极通过所述第十三贯孔连接所述第二掺杂区的另一端。
相较于现有技术，本发明的半导体器件中包括隧穿场效应晶体管及平面器件，所述隧穿场效应晶体管包括第一衬底及形成于所述第一衬底一侧的第一电气元件，所述平面器件包括第二衬底及形成于所述第二衬底一侧的第二电气元件。所述第一衬底及所述第二衬底为一体结构，形成一个总衬底，且所述隧穿场效应晶体管的第一电气元件及所述平面器件的第二电气元件设置于一个总衬底的同一个表面上，相较于现有技术中隧穿场效应晶体管及平面器件分别制备在不同的基板上再集成到同一个衬底而言，本发明的半导体器件体积较小，相比于现有技术减小了工艺的复杂程度及实现成本。
进一步地，所述第一绝缘层用于隔绝所述第一栅区对所述第一衬底的控制，防止所述第一漏区及所述第二漏区电流的泄露。
第二方面，本发明还提供了一种半导体器件的制备方法，所述半导体器件的制备方法包括：
S110，提供一总衬底，所述总衬底包括相邻的第一衬底及第二衬底，所述第一衬底包括相对设置的第一表面及第二表面，所述第二衬底包括相对设置的第三表面及第四表面，所述第三表面与所述第一表面平齐，所述第四表面与所述第二表面平齐；
S120，在所述第一衬底的一侧形成第一电气元件，在所述第二衬底的一侧形成第二电气元件，所述第二电气元件与所述第一电气元件设置于所述总衬底 的同一侧，所述第一衬底及所述第一电气元件构成隧穿场效应晶体管，所述第二衬底及所述第二电气元件构成平面器件，其中，所述平面器件包括金属氧化物半导体晶体管、电容、电阻的任意一种。
在第一种实施方式中，所述步骤S120包括：
步骤S130，自所述第一表面形成嵌入所述第一衬底内的第一浅沟道隔离区及所述第二浅沟道隔离区，自所述第三表面形成嵌入所述第二衬底内的第三浅沟道隔离区及第四浅沟道隔离区，其中，所述第一浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区与所述第一浅沟道隔离区相对设置且间隔部分第一衬底；所述第三浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区与所述第三浅沟道隔离区相对设置且间隔部分第二衬底。
结合第一种实施方式，在第二种实施方式中，所述步骤S120在所述步骤S130之后还包括：
步骤S131a，自所述第一表面形成嵌入所述第一表面内的第一漏区及第二漏区，在所述第二表面形成嵌入所述第二表面内的第二源区及第三漏区；其中，所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第二源区的一端与所述第三表面平齐，所述第三漏区的一端与所述第三表面平齐，所述第二源区与所述第三漏区相对且通过部分第二衬底间隔设置在所述第三浅沟道隔离区及所述第四浅沟道隔离区之间，所述第二源区与所述第三浅沟道隔离区接触，所述第三漏区与所述第四浅沟道隔离区接触；
步骤S132a，形成第一源区，所述第一源区凸出设置于所述第一表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；
步骤S133a，形成第一绝缘层；所述第一绝缘层凸出设置于所述衬底表面，所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层 的厚度小于所述第一源区的高度；
步骤S134a，形成间隔设置的第一栅电介质层及第二栅电介质层；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；所述第二栅电介质层凸出设置于所述衬底的表面，且所述第二栅电介质层设置于所述第二源区及所述第三漏区之间；
步骤S135a，形成第一栅区及第二栅区；所述第一栅区围绕所述第一栅电介质层设置；所述第二栅区设置于所述第二栅电介质层上，且所述第二栅区与所述第二栅电介质层接触。
结合第二种实施方式，在第三种实施方式中，所述步骤S131a包括：
步骤S131a-I，在所述总衬底的同个表面依次层叠设置氧化层及第一硬掩膜层；
步骤S131a-II，图案化所述氧化层及所述第一硬掩膜层，以保留第一氧化部及第一硬掩膜部，以及第二氧化部及第二硬掩膜部，所述第一氧化部与所述第一浅沟道隔离区以及所述第二浅沟道隔离区间隔设置，所述第一硬掩膜部层叠设置在所述第一氧化部上，所述第二氧化部与所述第三浅沟道隔离区以及所述第四浅沟道隔离区间隔设置，所述第二硬掩膜部层叠设置在所述第二氧化部上；
步骤S131a-III，以所述第一氧化部与所述第一硬掩膜部以及所述第二氧化部2与所述第二硬掩膜部为掩膜对所述总衬底的表面进行第一类型离子重掺杂，形成间所述第一漏区、第二漏区、所述第二源区及所述第三漏区；
步骤S131a-IV，剥离所述第一氧化部及所述第一硬掩膜部以及所述第二氧化部及所述第二硬掩膜部。
结合第一种实施方式，在第四种实施方式中，在所述步骤S132a及所述步骤S133a之间，所述半导体器件的制备方法还包括：
对所述总衬底进行退火处理。
结合第三种实施方式，在第五种实施方式中，所述步骤S132a包括：
步骤S132a-I，在所述总衬底的表面沉积第二类型离子重掺杂半导体层；
步骤S132a-II，图案化所述第二类型离子重掺杂半导体层，以形成所述第一源区。
结合第五种实施方式，在第六种实施方式中，所述步骤S132a-II包括：
步骤a1，在所述第二类型离子重掺杂半导体层上沉积第二硬掩膜层及光刻胶；
步骤b1，图案化所述第二硬掩膜层及所述光刻胶，以保留对应所述第一源区和所述第二源区中部的第二硬掩膜层及光刻胶；
步骤c1，以保留的第二硬掩膜层及光刻胶为掩膜对所述第二类型离子重掺杂半导体层进行蚀刻，以保留被所述第二硬掩膜层及所述光刻胶覆盖的第二类型离子重掺杂半导体层，以形成所述第一源区；
步骤d1，剥离对应所述第一区域中部的光刻胶。
结合第六种实施方式，在第七种实施方式中，所述步骤S133a包括：
步骤S133a-I，沉积一层绝缘层，所述绝缘层的厚度小于所述第一源区的高度；
步骤S133a-II，图案化所述绝缘层，以保留分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间的绝缘层的部分，以形成所述第一绝缘层。
结合第七种实施方式，在第八种实施方式中，所述步骤S134a包括：
步骤S134a-I，沉积整层栅电介质材料层；
步骤S134a-II，图案化所述栅电介质材料层，以保留贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层，以及保留设置在所述第二源区及所述第三漏区之间且分别与所述第二源区及所述第三漏区接触的栅电介质材料层，贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层定义为第一栅电介质层，设置在所述第二源区及所述第三漏区之间的栅电介质材料层定义为第二栅电介质层，所述第一栅电介质层包括第一栅电介质部及第二栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面。
结合第八种实施方式，在第九种实施方式中，所述步骤S135a包括：
步骤S135a-I，沉积整层的栅极材料层；
步骤S135a-II，图案化所述栅极材料层，以保留围绕所述第一栅电介质层 以及设置在所述第二栅电介质层上的栅极材料层，设置在所述第一栅电介质层上的栅极材料层定义为第一栅区，设置在所述第二栅电介质层上的栅极材料层定义为第二栅区，所述栅区包括第一部分及第二部分，所述第一部分层叠设置在所述第一栅电介质层上，所述第二部分的一端与所述第一部分的一端相连且所述第二部分贴合所述第二栅电介质部的表面。
结合第九种实施方式，在第十种实施方式中，所述半导体器件的制备方法还包括：
步骤I，对应所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区、所述第二源区、所述第三漏区及所述第二栅区分别形成第一漏极、第二漏极、第一源极、两个第一栅极、第二源极、第三漏极及第二栅极，所述第一漏极、所述第二漏极、所述第一源极、所述两个第一栅极、所述第二源极、所述第三漏极及所述第二栅极分别与所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区的第二部分、所述第二源区、所述第三漏区及所述第二栅区电连接。
进一步地，在所述步骤I之前，所述半导体器件的制备方法还包括：
步骤S136a，在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区，以及所述第二源区、所述第三漏区及所述第二栅区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区上的绝缘隔离层定义为第一隔离层，覆盖在所述第二源区、所述第三漏区及所述第二栅区上的绝缘隔离层定义为第二隔离层；
步骤S137a，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔及第五贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一贯孔对应所述第一漏区设置，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二贯孔对应所述第二漏区设置，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第三贯孔对应所述第一源区设置，所述第一源极通过所述第三贯孔以连接所述第一源区，所述第四贯孔及所述第五贯孔分别对应所述第一栅区的第二部分设置，所述两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区的第二部分；
步骤S138a，在所述第二隔离层上开设第七贯孔、第八贯孔及第九贯孔， 所述第七贯孔对应所述第二源区设置，所述第二源极通过所述第七贯孔连接所述第二源区，所述第八贯孔对应所述第三漏区0设置，所述第三漏极通过所述第八贯孔连接所述第三漏区，所述第九贯孔对应所述第二栅区设置，所述第二栅极通过所述第九贯孔连接所述第二栅区。
进一步地，所述半导体器件的制备方法还包括如下步骤中的至少一个：
步骤S139a-I，在所述第一漏极及所述第一漏区之间形成第一欧姆接触层，所述第一漏极通过所述第一欧姆接触层连接所述第一漏区；
步骤S139a-II，在所述第二漏极及所述第二漏区之间形成第二欧姆接触层，所述第二漏极通过所述第二欧姆接触层连接所述第二漏区；
步骤S139a-III，在所述第一源极及所述第一源区之间形成第三欧姆接触层，所述第一源极通过所述第三欧姆接触层连接所述第一源区；
步骤S139a-IV，在第一个所述第一栅极与所述第一栅区的第二部分之间形成第四欧姆接触层，第一个所述第一栅极通过所述第四欧姆接触层连接所述第一栅区的第二部分；
步骤S139a-V，在第二个所述第一栅极与所述第一栅区的第二部分之间形成第五欧姆接触层，第二个所述第一栅极通过所述第五欧姆接触层连接所述第二栅区的第二部分；
步骤S139a-VI，在所述第二源极与所述第二源区之间形成第七欧姆接触层，第二源极通过所述第七欧姆接触层连接所述第二源区；
步骤S139a-VII，在所述第三漏极与所述第三漏区之间形成第八欧姆接触层，所述第三漏极通过所述第八欧姆接触层连接所述第三漏区；
步骤S139a-VIII，在所述第二栅极与所述第二栅区之间形成第九欧姆接触层，所述第二栅极通过所述第九欧姆接触层连接所述第二栅区。
结合第六种实施方式，在第十一种实施方式中，所述步骤S120在所述步骤S130还包括：
步骤a2，在所述第二类型离子重掺杂半导体层上沉积第二硬掩膜层及光刻胶；
步骤b2，图案化所述第二硬掩膜层及所述光刻胶，以保留对应所述第一源区和所述第二源区中部的第二硬掩膜层及光刻胶；
步骤c2，以保留的第二硬掩膜层及光刻胶为掩膜对所述第二类型离子重掺杂半导体层进行蚀刻，以保留被所述第二硬掩膜层及所述光刻胶覆盖的第二类型离子重掺杂半导体层，以形成所述第一源区；
步骤d2，剥离对应所述第一区域中部的第二硬掩膜层及光刻胶。
结合第十一种实施方式，在第十二种实施方式中，所述步骤S134a及所述步骤S135a包括：
步骤S134a-I’，沉积整层栅电介质材料层；
步骤S134a-II’，整层的栅电介质材料层上沉积栅极材料层；
步骤S134a-III’，图案化所述栅电介质材料层及所述栅极材料层，以移除覆盖在所述第一漏区、所述第二漏区、所述第二源区及所述第三漏区上的栅电介质材料层及栅极材料层，剩余的栅电介质材料层为第一栅电介质层，其中，所述第一栅电介质层包括第一栅电介质部、第二栅电介质部及第三栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面，所述第三电介质部连接所述第二栅电介质部远离所述第一栅电介质部的一端，且所述第三电介质部覆盖所述第一源区远离所述衬底的一端；所述第一栅区包括第一部分、第二部分及第三部分，其中，所述第一部分层叠设置在所述第一栅电介质层上，所述第二部分的一端与所述第一部分的一端相连且所述第二部分贴合所述第二栅电介质部的表面，所述第三部分连接所述第二部分远离所述第一部分的一端，且所述第三部分覆盖在所述第三栅电介质部上。
结合第十二种实施方式，在第十三种实施方式中，所述半导体器件的制备方法还包括：
步骤II，对应所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区、所述第二源区、所述第三漏区及所述第二栅区分别形成第一漏极、第二漏极、第一源极、三个第一栅极、第二源极、第三漏极及第二栅极，所述第一漏极、所述第二漏极、所述第一源极、所述第二源极、所述第三漏极及所述第二栅极分别与所述第一漏区、所述第二漏区、所述第一源区、所述第二源区、所述第三漏区及所述第二栅区电连接，其中两个第一栅极连接第二部分且分别设置于所述第一源极的两侧，另外一个第一栅极连接所述第三部分。
结合第十三种实施方式，在第十四种实施方式中，在所述步骤II之前，所述半导体器件的制备方法还包括：
步骤S136b，在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区，以及所述第二源区、所述第三漏区及所述第二栅区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区上的绝缘隔离层定义为第一隔离层，覆盖在所述第二源区、所述第三漏区及所述第二栅区上的绝缘隔离层定义为第二隔离层；
步骤S137b，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔、第五贯孔及第六贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第一源极通过所述第三贯孔以连接所述第一源区，其中两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区的第二部分，另外一个第一栅极通过所述第六贯孔连接所述第一栅区的第三部分；
步骤S138b，在所述第二隔离层上开设第七贯孔、第八贯孔及第九贯孔，所述第二源极通过所述第七贯孔连接所述第二源区，所述第三漏极通过所述第八贯孔连接所述第三漏区，所述第二栅极通过所述第九贯孔连接所述第二栅区。
进一步地，其特征在于，所述半导体器件的制备方法还包括如下步骤中的至少一个：
步骤S139b-I，在所述第一漏极及所述第一漏区之间形成第一欧姆接触层，所述第一漏极通过所述第一欧姆接触层连接所述第一漏区；
步骤S139b-II，在所述第二漏极及所述第二漏区之间形成第二欧姆接触层，所述第二漏极通过所述第二欧姆接触层连接所述第二漏区；
步骤S139b-III，在所述第一源极与所述第一源区之间形成第三欧姆接触层，所述第一源极通过所述第三欧姆接触层连接所述第一源区；
步骤S139b-IV，在第一个所述第一栅极与所述第一栅区的第二部分之间形成第四欧姆接触层，第一个所述第一栅极通过所述第四欧姆接触层连接所述第一栅区的第二部分；
步骤S139b-V，在第二个所述第一栅极与所述第一栅区的第二部分之间形成第五欧姆接触层，第二个所述第一栅极通过所述第五欧姆接触层连接所述第二栅区的第二部分；
步骤S139b-VI，在第三个所述第一栅极与所述第一栅区的第三部分之间形成第六欧姆接触层，第三个所述第一栅极通过所述第六欧姆接触层连接所述第一栅区的第三部分；
步骤S139b-VII，在所述第二源极与所述第二源区之间形成第七欧姆接触层，第二源极通过所述第七欧姆接触层连接所述第二源区；
步骤S139b-VIII，在所述第三漏极与所述第三漏区之间形成第八欧姆接触层，所述第三漏极通过所述第八欧姆接触层连接所述第三漏区；
步骤S139b-V-IV，在所述第二栅极与所述第二栅区之间形成第九欧姆接触层，所述第二栅极通过所述第九欧姆接触层连接所述第二栅区。
结合第二种实施方式，在第十五种实施方式中，所述第一漏区、所述第二漏区、所述第二源区及所述第三漏区为对所述衬底进行第一类型离子重掺杂得到的区域，所述第一源区为第二类型离子重掺杂区域，其中，所述第一类型离子重掺杂为N型离子重掺杂，所述第二类型离子重掺杂为P型离子重掺杂；或者所述第一类型离子重掺杂为P型离子重掺杂，所述第二类型离子重掺杂为N型离子重掺杂。
结合第一种实施方式，在第十六种实施方式中，所述步骤S120在所述步骤S130之后包括：
步骤S131c，自所述第一表面形成嵌入所述第一表面内的第一漏区及第二漏区，在所述第二表面形成嵌入所述第二表面内的第一掺杂区；其中，所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第一掺杂区的一端与所述第三表面平齐，所述第一掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第一掺杂区的一端与所述第三浅沟道隔离区接触，所述第一掺杂区的另一端与所述第四浅沟道隔离区接触；
步骤S132c，形成第一源区；所述第一源区凸出设置于所述第一衬底的表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；
步骤S133c，形成第一绝缘层及第二绝缘层；所述第一绝缘层凸出设置于所述衬底表面，所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的厚度小于所述第一源区的高度；
步骤S134c，形成间隔设置的第一栅电介质层及第三栅电介质层；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；所述第三栅电介质层层叠设置于所述第二绝缘层上；所述第二绝缘层设置于所述第一掺杂区的中部且所述第二绝缘层的未覆盖所述第一掺杂区域的两端，所述第二绝缘层与所述第一绝缘层位于同一层；
步骤S135c，形成第一栅区及第三栅区；所述第一栅区围绕所述第一栅电介质层设置；所述第三栅区层叠设置于所述第三栅电介质层上。
结合第十五种实施方式，在第十七种实施方式中，所述步骤S131c包括：
步骤S131c-I，在所述衬底的同个表面依次形成层叠设置的氧化层及第三硬掩膜层；
步骤S131c-II，图案化所述氧化层及所述第三硬掩膜层，以移除位于所述第一区域的两端以及所述第二区域的氧化层及第三硬掩膜层；
步骤S131c-III，以图案化后的氧化层及第三硬掩膜层为掩膜对所述衬底的表面进行第一类型离子重掺杂，以在所述第一区域内形成间隔设置的所述第一漏区及所述第二漏区，在第二区域内形成所述第一掺杂区；
步骤S131c-IV，剥离剩余的氧化层及第三硬掩膜层。
结合第十六种实施方式，在第十八种实施方式中，在所述步骤S131c与所述步骤S132c之间，所述半导体器件的制备方法还包括：
对所述总衬底进行退火处理。
结合第十八种实施方式，在第十九种实施方式中，所述步骤S132c包括：
步骤S132c-I，沉积第二类型离子重掺杂半导体层；
步骤S132c-II，图案化所述第二类型离子重掺杂半导体层，以形成所述第一源区。
结合第十九种实施方式，在第二十种实施方式中，所述步骤S132c-II包括：
步骤a3，在所述第二类型离子重掺杂半导体层上沉积第四硬掩膜层及光刻胶；
步骤b3，图案化所述第四硬掩膜层及所述光刻胶，以保留对应所述第一源区及所述第二源区中部的第四硬掩膜层及光刻胶；
步骤c3，以保留的第四硬掩膜层及光刻胶为掩膜对所述第二类型离子重掺杂半导体层进行蚀刻，以保留被所述第四硬掩膜层及所述光刻胶覆盖的第二类型离子重掺杂半导体层，以形成所述第一源区；
步骤d3，剥离对应所述第一区域中部的光刻胶。
结合第二十种实施方式，在第二十一种实施方式中，所述步骤S133c包括：
步骤S133c-I，沉积一层绝缘层，所述绝缘层的厚度小于所述第一源区的高度；
步骤S133c-II，图案化所述绝缘层，以保留围绕所述第一源区的绝缘层的部分以及设置在所述第一掺杂区中部的绝缘层的部分，其中，围绕所述第一源区的绝缘层的部分为所述第一绝缘层，设置在所述第一掺杂区中部的绝缘层的部分为第二绝缘层。
结合第二十种实施方式，在第二十二种实施方式中，所述步骤S134c包括：
步骤S134c-I，沉积整层栅电介质材料层；
步骤S134c-II，图案化所述栅电介质材料层，以保留贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层，以及保留设置在所述第二绝缘层上的栅电介质材料层，贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层定义为第一栅电介质层，设置在所述第二绝缘层上的栅电介质材料层定义为第三栅电介质层，所述第一栅电介质层包括第一栅电介质部及第二栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面。
结合第二十二种实施方式，在第二十三种实施方式中，所述步骤S135c包括：
步骤S135c-I，沉积整层的栅极材料层；
步骤S135c-II，图案化所述栅极材料层，以保留围绕第一栅电介质层以及设置在所述第三栅电介质层上的栅极材料层，设置在所述第一栅电介质层上的栅极材料层定义为第一栅区，设置在所述第三栅电介质层上的栅极材料层定义为第三栅区，所述第一栅区包括第一部分及第二部分，所述第一部分层叠设置在所述第一栅电介质层上，所述第二部分的一端与所述第一部分d一端相连且所述第二部分贴合所述第二栅电介质部的表面。
结合第十六种实施方式，在第二十四种实施方式中，所述半导体器件的制备方法还包括：
步骤III，对应所述第一漏区、所述第二漏区、所述第一源区及第一栅区分别形成第一漏极、第二漏极、第一源极及第一栅极，及对应所述第一掺杂区的一端形成第一电极，对应所述第一掺杂区的另一端形成第二电极，对应所述第三栅区形成第三电极。
结合第二十三种实施方式，在第二十五种实施方式中，在所述步骤III之前，所述半导体器件的制备方法还包括：
步骤S136c，在所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区及所述第三栅区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区的绝缘隔离层定义为第一隔离层，覆盖在所述第三栅区上的绝缘隔离层定义为第三隔离层；
步骤S137c，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔及第五贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一贯孔对应所述第一漏区设置，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二贯孔对应所述第二漏区设置，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第三贯孔对应所述第一源区设置,所述第一源极通过所述第三贯孔以连接所述第一源区，所述第四贯孔及所述第五贯孔分别对应所述第一栅区的第二部分设置，所述两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区；
步骤S138c，在所述第三隔离层上开设第十贯孔、第十一贯孔及第十二贯孔，所述第一电极通过所述第十贯孔连接所述第一掺杂区的一端，所述第二电极通过所述第十一贯孔连接所述第一掺杂区的另一端，所述第三电极通过所述 第十二贯孔连接所述第三栅区。
结合第一种实施方式，在第二十六种实施方式中，所述步骤S120在所述步骤S130之后还包括：
步骤S131d，自所述第一表面形成嵌入所述第一表面内的第一漏区及第二漏区，在所述第二表面形成嵌入所述第二表面内的第二掺杂区；其中，所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第二掺杂区的一端与所述第三表面平齐，所述第二掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第二掺杂区的一端与所述第三浅沟道隔离区接触，所述第二掺杂区的另一端与所述第四浅沟道隔离区接触；
步骤S132d，形成第一源区；所述第一源区凸出设置于所述第一衬底的表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；
步骤S133d，形成第一绝缘层；所述第一绝缘层凸出设置于所述第一衬底表面，所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的厚度小于所述第一源区的高度；
步骤S134d，形成第一栅电介质层；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；
步骤S135d，形成第一栅区，所述第一栅区围绕所述第一栅电介质层设置。
结合第二十六种实施方式，在第二十七种实施方式中，所述半导体器件的制备方法还包括：
步骤IV，对应所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区分别形成第一漏极、第二漏极、第一源极及两个第一栅极，及对应所述第二掺杂区的两端分别形成第四电极及第五电极。
结合第二十七种实施方式，在第二十八种实施方式中，在所述步骤IV之前所述半导体器件的制备方法还包括：
步骤S136d，在所述第一漏区、所述第二漏区、所述第一源区及所述第一 栅区，以及所述第二掺杂区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区上的绝缘隔离层定义为第一隔离层，覆盖在所述第二掺杂区上的绝缘隔离层定义为第四隔离层；
步骤S137d，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔及第五贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第一源极通过所述第三贯孔以连接所述第一源区，所述两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区；
步骤S138d，在所述第四隔离层上开设第十二贯孔及第十三贯孔，所述第四电极通过所述第十二贯孔连接所述第二掺杂区的一端，所述第五电极通过所述第十三贯孔连接所述第二掺杂区的另一端。
相较于现有技术，本发明的半导体器件的制备方法中隧穿场效应晶体管中和平面器件中材料相同的层在同道工序中形成，从而减小了所述半导体器件的制备工艺的复杂程度及实现成本。
相较于现有技术，本发明的半导体器件的制备方法中第一区域中的第一漏区及第二漏区与所述第二区域内金属氧化物半导体晶体管的第二源区及第三漏区的掺杂类型相同，通过一次离子注入便可以实现，减少了制备所述半导体器件的工艺步骤，以及工艺复杂程度，即降低了成本。且本发明的半导体器件的制备工艺斗鱼现有CMOS的标准工艺兼容，没有增加多余复杂的工艺方法。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的半导体器件的剖面结构示意图；
图2为本发明图1中半导体器件中的平面器件为MOS时一较佳实施方式 的剖面结构示意图；
图3为本发明图1中半导体器件中的平面器件为MOS时另一较佳实施方式的剖面结构示意图；
图4为本发明图1中半导体器件中的平面器件为电容时一较佳实施方式的沿I-I的剖面结构示意图；
图5为本发明图1中半导体器件中的平面器件为电容时另一较佳实施方式的沿I-I的剖面结构示意图；
图6为本发明图1中半导体器件中的平面器件为电阻时一较佳实施方式的沿I-I的剖面结构示意图；
图7为本发明图1中半导体器件中的平面器件为电阻时另一较佳实施方式的沿I-I的剖面结构示意图；
图8为本发明一较佳实施方式的半导体器件的制备方法的流程图；
图9～图34为本发明一较佳实施方式中半导体器件中的平面器件为MOS时的制备方法中各个制备步骤的示意图；
图35～图50为本发明一较佳实施方式中半导体器件中的平面器件为电容时的制备方法中各个制备步骤的示意图；
图51～图56为本发明一较佳实施方式中半导体器件中的平面器件为电电阻时的制备方法中各个制备步骤的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1和图2，图1为本发明一较佳实施方式的半导体器件的剖面结构示意图；图2为本发明图1中半导体器件中的平面器件为MOS时一较佳实施方式的剖面结构示意图。所述半导体器件10包括隧穿场效应晶体管100及平面器件200。所述隧穿场效应晶体管100包括第一衬底100a及第一电气元件100b，所述第一电气元件100b设置于所述第一衬底100a的一侧。所述 平面器件200包括第二衬底200a及第二电气元件200b，所述第二衬底200a与所述第一衬底100a为一体结构并形成一个总衬底20，所述第二电气元件200b形成于所述总衬底20的同一侧。其中，所述平面器件200包括金属氧化物半导体晶体管(Metal Oxide Semiconductor,MOS)、电容、电阻中的任意一种。为了方便描述，所述金属氧化物半导体晶体管标记为300，所述电容标记为400，所述电阻标记为500。
所述第一衬底100a包括相对设置的第一表面100c及第二表面100d，所述第二衬底200a包括相对设置的第三表面200c及第四表面200d。所述第二衬底200a与所述第一衬底100a接触，且所述第三表面200c与所述第一表面100c平齐，所述第四表面200d与所述第二表面100d平齐。在本实施方式中，所述第一表面100c为所述第一衬底100a的上表面，所述第二表面100d为所述第一衬底100a的下表面。所述第三表面200c为所述第二衬底200a的上表面，所述第四表面200d为所述第二衬底200a的下表面。
在本实施方式中，所述第一电气元件100a包括第一浅沟道隔离(Shallow Trench Isolation,STI)区11及第二浅沟道隔离区12。所述第一浅沟道隔离区11及所述第二浅沟道隔离区12自所述第一表面100c嵌入所述第一衬底100a内，且所述第一浅沟道隔离区11的一端与所述第一表面100c平齐，所述第二浅沟道隔离区12的一端与所述第一表面100c平齐，所述第二浅沟道隔离区12与所述第一浅沟道隔离区11相对设置且间隔部分第一衬底100a。
所述第二电气元件200a包括第三浅沟道隔离区13及第四浅沟道隔离区14。所述第三浅沟道隔离区13及所述第四浅沟道隔离区14自所述第三表面200c嵌入所述第二衬底200a内，且所述第三浅沟道隔离区13的一端与所述第三表面200c平齐，所述第四浅沟道隔离区14的一端与所述第三表面200c平齐，所述第四浅沟道隔离区14与所述第三浅沟道隔离区13相对设置且间隔部分第二衬底200a。所述第一浅沟道隔离区11、所述第二浅沟道隔离区12、所述第三浅沟道隔离区13及所述第四浅沟道隔离区14的形成方式可以为在所述衬底第一衬底100a及所述第二衬底200a上采用CMOS工艺实现浅草隔离来实现的。
所述隧穿场效应晶体管100的第一电气元件100b还包括第一漏区110、 第二漏区120、第一源区130、第一绝缘层140、第一栅电介质层150及第一栅区160。所述第一漏区110及所述第二漏区120自所述第一表面100c嵌入所述第一衬底100a内部，且所述第一漏区110的一端与所述第一表面100c平齐，所述第二漏区120的一端与所述第一表面100c平齐，所述第一漏区110与所述第二漏区120相对且通过部分第一衬底100a间隔设置在所述第一浅沟道隔离区11及所述第二浅沟道隔离区12之间，所述第一漏区110与所述第一浅沟道隔离区11接触，所述第二漏区120与所述第二浅沟道隔离区12接触。所述第一源区130凸出设置于所述第一表面100c，且所述第一源区130位于所述第一漏区110和所述第二漏区120之间。本发明的所述第一源区130的结构能够改善隧穿场效应晶体管的控制所述第一漏区及所述第二漏区120之间的开启及关闭的速度。所述第一绝缘层140凸出设置于所述第一表面100c，所述第一绝缘层140对称设置于所述第一源区130的两侧，分别连接于所述第一漏区110和所述第一源区130之间以及所述第二漏区120和所述第一源区130之间，且所述第一绝缘层140的高度小于所述第一源区130的高度。所述第一绝缘层140用于隔绝所述第一栅区160对所述第一衬底100a的控制，防止所述第一漏区110及所述第二漏区120电流的泄露。所述第一栅电介质层150对称设置在所述第一源区130两侧且贴合所述第一源区130与所述第一绝缘层140的表面。所述第一栅区160围绕所述第一栅电介质层150设置。
在本实施方式中，所述第一衬底100a及所述第二衬底200a可以为硅(Si)衬底。在其他实施方式中，所述第一衬底100a及所述第二衬底200a也可以为锗(Ge)或硅锗、镓砷等II-IV族、或III-V族、或IV-IV族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator,SOI)、或者绝缘衬底上的锗中的任意一种。
所述第一漏区110及所述第二漏区120可以为在所述第一衬底100a的第一表面100c注入第一类型离子重掺杂而形成。
所述第一栅电介质层150包括第一栅电介质部151及第二栅电介质部152，所述第一栅电介质部151层叠设置在所述第一绝缘层140上，所述第二栅电介质部152的一端与所述第一栅电介质部151相连且所述第二栅电介质部152贴合所述第一源区130的表面。
所述第一栅区160包括第一部分161及第二部分162，所述第一部分161层叠设置在所述第一栅电介质层150上，所述第二部分162的一端与所述第一部分161的一端相连且所述第二部分162贴合所述第二栅电介质部152的表面。
所述隧穿场效应晶体管100的第一电气元件100b还包括第一漏极171、第二漏极172、第一源极173及两个第一栅极174。所述第一漏极171、所述第二漏极172、所述第一源极173及两个所述第一栅极174分别对应连接所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160。在本实施方式中，所述两个第一栅极174连接所述第二部分162且分别设置于所述第一源极173的两侧。换句话说，所述隧穿场效应晶体管100的第一电气元件100b包括第一漏极171、第二漏极172、第一源极173及两个第一栅极174。所述第一漏极171连接所述第一漏区110，所述第二漏极172连接所述第二漏区120，所述第一源极173连接所述第一源区130，两个第一栅极174连接所述第一栅区160的第二部分162且两个所述第一栅极174位于所述第一源极173的两侧。
所述隧穿场效应晶体管100的第一电气元件100b还包括第一隔离层180，所述第一隔离层180覆盖所述第一漏区110、第二漏区120、所述第一源区130及所述第一栅区160，所述第一隔离层180设置有第一贯孔181、第二贯孔182、第三贯孔183、第四贯孔184及第五贯孔185。所述第四贯孔184及所述第五贯孔185设置于所述第三贯孔183的两侧。所述第一贯孔181对应所述第一漏区110设置，所述第一漏极171通过所述第一贯孔181连接所述第一漏区110。所述第二贯孔182对应所述第二漏区120设置，所述第二漏极172通过所述第二贯孔182连接所述第二漏区120。所述第三贯孔183对应所述第一源区130设置，所述第一源极173通过所述第三贯孔183连接所述第一源区130。所述第四贯孔184及所述第五贯孔185分别对应所述第一栅区160的第二部分162设置，所述两个第一栅极174分别通过所述第四贯孔184及所述第五贯孔185连接所述第一栅区160的第二部分162。
所述隧穿场效应晶体管100的第一电气元件100b还包括第一欧姆接触层181、第二欧姆接触层182、第三欧姆接触层183、第四欧姆接触层184及第五 欧姆接触层185中的至少一个。其中，所述第一欧姆接触层181设置于所述第一漏极171及所述第一漏区110之间，以连接所述第一漏极171及所述第一漏区110，所述第一欧姆接触层181用于减小所述第一漏极171与所述第一漏区110之间的接触电阻。所述第二欧姆接触层182设置于所述第二漏极172与所述第二漏区120之间，以连接所述第二漏极172及所述第二漏区120，所述第二欧姆接触层182用于减小所述第二漏极172与所述第二漏区120之间的接触电阻。所述第三欧姆接触层183设置于所述第一源极173及所述第一源区130之间，以连接所述第一源极173及所述第一源区130，所述第三欧姆接触层183用于减小所述第一源极173与所述第一源区130之间的接触电阻。所述第四欧姆接触层184设置于第一个所述第一栅极174与所述第一栅区160的第二部分162之间，以连接第一个所述第一栅极174及所述第一栅区160的第二部分162，所述第四欧姆接触层184用于减小第一个所述第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。所述第五欧姆接触层185设置于第二个所述第一栅极174与所述第一栅区160的第二部分162之间，以连接第二个所述第一栅极174及所述第一栅区160的第二部分162，所述第五欧姆接触层185用于减小第二个所述第一栅极174与所述第一栅区160的地热部分162之间的接触电阻。
在另一实施方式中，请参阅图3，图3为本发明图1中半导体器件中的平面器件为MOS时另一较佳实施方式的剖面结构示意图。所述第一栅电介质层150还包括第三栅电介质部153，所述第三电介质部153连接所述第二栅电介质部152远离所述第一栅电介质部151的一端，且所述第三电介质部153覆盖所述第一源区130远离所述第一衬底100a的一端。相应地，所述第一栅区160包括第三部分163，所述第三部分163连接所述第二部分162远离所述第一部分161的一端，且所述第三部分163覆盖在所述第三栅电介质部153上。
相应地，所述隧穿场效应晶体管100的电气元件100b还包括第一漏极171、第二漏极172、第一源极173及三个第一栅极174。所述第一漏极171、所述第二漏极172、所述第一源极173及三个所述第一栅极174分别对应连接所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160设置。在本实施方式中，三个所述第一栅极174中的两个第一栅极174连接所述 第二部分162且分别设置于所述第一源极173的两侧，另外一个第一栅极174连接所述第三部分163。换句话说，所述隧穿场效应晶体管100包括第一漏极171、第二漏极172、第一源极173及三个第一栅极174。所述第一漏极171连接所述第一漏区110，所述第二漏极172连接所述第二漏区120，所述第一源极173连接所述第一源区130，两个第一栅极174连接所述第一栅区160的第二部分162且两个所述第一栅极174位于所述第一源极173的两侧，第三个第一栅极174连接所述第三部分163。
在本实施方式中，所述隧穿场效应晶体管100的第一电气元件100b还包括第一隔离层180，所述第一隔离层180覆盖所述第一漏区110、第二漏区120、所述第一源区130及所述第一栅区160，所述第一隔离层180设置有第一贯孔181、第二贯孔182、第三贯孔183、第四贯孔184、第五贯孔185及第六贯孔186。所述第一贯孔181对应所述第一漏区110设置，所述第一漏极171通过所述第一贯孔181以连接所述第一漏区110。所述第二贯孔182对应所述第二漏区120设置，所述第二漏极172通过所述第二贯孔182以连接所述第二漏区120。所述第三贯孔183对应所述第一源区130设置，所述第一源极173通过所述第三贯孔183以连接所述第一源区130。所述第四贯孔184及所述第五贯孔185分别设置于所述第三贯孔183的两侧，且述第四贯孔184及所述第五贯孔185分别对应所述第一栅区160的第二部分162设置，所述第六贯孔186对应第三部分163设置，其中两个第一栅极174分别通过所述第四贯孔184及所述第五贯孔185以连接所述第一栅区160的第二部分162，另外一个第一栅极174通过所述第六贯孔186连接所述第三部分163。
所述隧穿场效应晶体管100的第一电气元件100b还包括第一欧姆接触层181、第二欧姆接触层182、第三欧姆接触层183、第四欧姆接触层184、第五欧姆接触层185及第六欧姆接触层186中的至少一个。其中，所述第一欧姆接触层181设置于所述第一漏极171及所述第一漏区110之间，以连接所述第一漏极171及所述第一漏区110，所述第一欧姆接触层181用于减小所述第一漏极171与所述第一漏区110之间的接触电阻。所述第二欧姆接触层182设置于所述第二漏极172与所述第二漏区120之间，以连接所述第二漏极172及所述第二漏区120，所述第二欧姆接触层182用于减小所述第二漏极172与所述第 二漏区120之间的接触电阻。所述第三欧姆接触层183设置于所述第一源极173及所述第一源区130之间，以连接所述第一源极173及所述第一源区130，所述第三欧姆接触层183用于减小所述第一源极173与所述第一源区130之间的接触电阻。所述第四欧姆接触层184设置于第一个所述第一栅极174与所述第一栅区160的第二部分162之间，以连接第一个所述第一栅极174及所述第一栅区160的第二部分162，所述第四欧姆接触层184用于减小第一个所述第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。所述第五欧姆接触层185设置于第二各所述第一栅极174与所述第一栅区160的第二部分162之间，以连接第二个所述第一栅极174及所述第一栅区160的第二部分162，所述第五欧姆接触层185用于减小第二个所述第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。所述第六欧姆接触层设置于所述第三个所述第一栅极174与所述第一栅区160的第三部分163之间，以连接第三个所述第一栅极174及所述第一栅区160的第三部分163，所述第六欧姆接触层186用于减小第三个所述第一栅极174与所述第一栅区160的第三部分162之间的接触电阻。
请参阅图2及图3，当所述平面器件200为金属氧化物半导体晶体管时，所述第二电气元件200b包括第二源区310、第三漏区320、第二栅电介质层330及第二栅区340。
所述第二源区310及所述第三漏区320自所述第三表面200c嵌入所述第二衬底200a内部，且所述第二源区310的一端与所述第三表面200c平齐，所述第三漏区320的一端与所述第三表面200c平齐，所述第二源区310与所述第三漏区320相对且通过部分第二衬底200a间隔设置在所述第三浅沟道隔离区13及所述第四浅沟道隔离区14之间，所述第二源区310与所述第三浅沟道隔离区13接触，所述第三漏区320与所述第四浅沟道隔离区14接触。在本实施方式中，所述第二源区310及所述第三漏区320与所述第一漏区110及所述第二漏区120位于同一层。所述第二栅电介质层330凸出设置于所述第三表面200c，且所述第二栅电介质层330设置于所述第二源区310及所述第三漏区320之间。所述第二栅区340设置于所述第二栅电介质层330上，且所述第二栅区340与所述第二栅电介质层330接触。
所述第二电气元件200b还包括第二源极351、第三漏极352及第二栅极353。所述第二源极351、所述第三漏极352及所述第二栅极353分别对应连接所述第二源区310、所述第三漏区320及所述第二栅区340。换句话说，所述金属氧化物半导体晶体管300的第二电气元件200b包括第二源极351、第三漏极352及第二栅极353，所述第二源极351连接所述第二源区310，所述第三漏极352连接所述第三漏区320，所述第二栅极353连接所述第二栅区340。
所述第二电气元件200b还包括第二隔离层360，所述第二隔离层360与所述第一隔离层180位于同一层，所述第二隔离层360覆盖所述第二源区310、所述第三漏区320及所述第二栅区340。所述第二隔离层360上设置有第七贯孔361、第八贯孔362及第九贯孔363。所述第七贯孔361对应所述第二源区310设置，所述第二源极351通过所述第七贯孔361连接所述第二源区310。所述第八贯孔362对应所述第三漏区320设置，所述第三漏极352通过所述第八贯孔362连接所述第三漏区320。所述第九贯孔363对应所述第二栅区340设置，所述第二栅极353通过所述第九贯孔363连接所述第二栅区340。
优选地，所述第二电气元件200b还包括第七欧姆接触层381、第八欧姆接触层382及第九欧姆接触层383中的至少一个。其中，所述第七欧姆接触层381设置于所述第二源极351与所述第二源区310之间，用于减小所述第二源极351与所述第二源区310之间的接触电阻。所述第八欧姆接触层382设置于所述第三漏极352及所述第三漏区320之间，所述第八欧姆接触层382用于减小所述第三漏极352及所述第三漏区320之间的接触电阻。所述第九欧姆接触层383设置于所述第二栅极353与所述第二栅区340之间，所述第九欧姆接触层383用于减小所述第二栅极353与所述第二栅区340之间的接触电阻。
所述第一漏区110、所述第二漏区120、所述第二源区310及所述第三漏区320为第一类型离子重掺杂区域，所述第一源区130为第二类型离子重掺杂区域。其中，所述第一类型离子重掺杂区域为N型离子重掺杂区域，所述第二类型离子重掺杂区域为P型离子重掺杂区域；或者所述第一类型离子重掺杂区域为P型离子重掺杂区域，所述第二类型离子重掺杂区域为N型离子重掺杂区域。
请参阅图4及图5，图4为本发明图1中半导体器件中的平面器件为电容时一较佳实施方式的沿I-I的剖面结构示意图；图5为本发明图1中半导体器件中的平面器件为电容时另一较佳实施方式的沿I-I的剖面结构示意图。当所述平面器件200为电容时，所述第二电气元件200b包括第一掺杂区410、第二绝缘层420、第三栅电介质层430及第三栅区440。所述第一掺杂区410自所述第三表面200c嵌入所述第二衬底200a内部，所述第一掺杂区410的一端与所述第三表面200c平齐，所述第一掺杂区410设置在所述第三浅沟道隔离区13和所述第四浅沟道隔离区14之间，所述第一掺杂区410的一端与所述第三浅沟道隔离区13接触，所述第一掺杂区410的另一端与所述第四浅沟道隔离区14接触，且所述第一掺杂区410与所述第一漏区110及所述第二漏区120位于同一层。所述第二绝缘层420设置于所述第一掺杂区410的中部且所述第二绝缘层420的未覆盖所述第一掺杂区域410的两端，所述第二绝缘层420与所述第一绝缘层140位于同一层。所述第三栅电介质层430层叠设置于所述第二绝缘层420上，所述第三栅区440层叠设置于所述第三栅电介质层430上。在本实施方式中，所述第一掺杂区域410及所述第三栅区440构成所述电容400的两个相对的极板，所述第二绝缘层420及所述第三栅电介质层430构成所述电容400的电介质层。所述第一掺杂区410可以为在所述衬底20上进行第一类型离子重掺杂而形成的。
所述第二电气元件200b还包括第一电极451、第二电极452及第三电极453。所述第一电极451及所述第二电极452分别对应连接所述第一掺杂区410的两端，所述第三电极453连接所述第三栅区440。在本实施方式中，所述第一电极451及所述第二电极452分别设置在所述第三电极453的两侧，通过设置所述第一电极451及所述第二电极452两个电极与所述第一掺杂区410的两端相连，以在所述电容400应用时根据所述电容400与其他器件之间的位置关系选择连接第一电极451与所述第三电极453或者连接所述第二电极452与所述第三电极453。
所述第二电气元件200b还包括第三隔离层460，所述第三隔离层460设置于所述第一掺杂区410未覆盖所述第二绝缘层420的表面及所述第三栅区440的表面。所述第三隔离层460设置有第十贯孔461、第十一贯孔462及第 十二贯孔463。所述第十贯孔461对应所述第一掺杂区410的一端设置，所述第一电极451通过所述第十贯孔461连接所述第一掺杂区410的一端。所述第十一贯孔462对应所述第一掺杂区420的另一端设置，所述第二电极452通过所述第十一贯孔462连接所述第一掺杂区410的另一端。所述第十二贯孔463对应所述第三栅区440设置，所述第三电极453通过所述第十二贯孔463连接所述第三栅区440。
可以理解地，在本实施方式中，所述第二电气元件200b还包括至少一个欧姆接触层，所述欧姆接触层设置于所述第一电极451、所述第二电极452、所述第三电极453与相应电极对应的层之间，以减小相应电极与相应连接的层之间的接触电阻。举例而言，所述欧姆接触层设置于第一电极451与所述第一掺杂区410之间，以连接所述第一电极451及所述第一掺杂区410，用于减小所述第一电极451与所述第一掺杂区410之间的接触电阻。
请参阅6和图7，图6为本发明图1中半导体中的平面器件为电阻时一较佳实施方式的沿I-I的剖面结构示意图；图7为本发明图1中半导体中的平面器件为电阻时另一较佳实施方式的沿I-I的剖面结构示意图。当所述平面器件200为电阻时，所述第二电气元件200b包括第二掺杂区510，所述第二掺杂区510自所述第三表面200c嵌入所述第三表面200c嵌入所述第二衬底200a内部，所述第二掺杂区510的一端与所述第三表面200c平齐，所述第二掺杂区510设置在所述第三浅沟道隔离区13和所述第四浅沟道隔离区14之间，所述第二掺杂区510的一端与所述第三浅沟道隔离区13接触，所述第二掺杂区510的另一端与所述第四浅沟道隔离区14接触，且所述第二掺杂区510与所述第一漏区110及所述第二漏区120位于同一层。通过控制所述第二掺杂区510中掺杂的离子的浓度可以控制所述电阻500的电阻值的大小。所述第二掺杂区510可以为在所述衬底20上进行第一类型离子重掺杂而形成的。
所述第二电气元件200b还包括第四电极520及第五电极530。所述第四电极520及所述第五电极530分别对应连接所述第二掺杂区510的两端。所述第四电极520及所述第五电极530用于将所述电阻500与其他元件电连接。
所述第二电气元件200b还包括第四隔离层540，所述第四隔离层540覆盖所述第二掺杂区510，所述第四隔离层540设置有第十二贯孔541及第十三 贯孔542。所述第十二贯孔541及所述第十三贯孔542对应所述第二掺杂区510的两端设置，所述第四电极520通过所述第十二贯孔541连接所述第二掺杂区510的一端，所述第五电极530通过所述第十三贯孔542连接所述第二掺杂区510的另一端。
相较于现有技术，本发明的半导体器件10中包括隧穿场效应晶体管100及平面器件200，所述隧穿场效应晶体管100包括第一衬底100a及形成于所述第一衬底100a一侧的第一电气元件100b，所述平面器件200包括第二衬底200a及形成于所述第二衬底200a一侧的第二电气元件200b。所述第一衬底100a及所述第二衬底200a为一体结构，形成一个总衬底20，且所述隧穿场效应晶体管100的第一电气元件100b及所述平面器件200的第二电气元件200b设置于一个总衬底20的同一个表面上，相较于现有技术中隧穿场效应晶体管100及平面器件200分别制备在不同的基板上再集成到同一个衬底而言，本发明的半导体器件10体积较小，相比于现有技术减小了工艺的复杂程度及实现成本。
下面结合图1、图2和图3，对本发明一较佳实施方式的半导体器件的制备方法进行介绍。请参阅图8，图8为本发明一较佳实施方式的半导体器件的制备方法的流程图。总的来说，本发明半导体器件的制备方法实现了隧穿场效应晶体管(Tunnel Field Effect Transistor，TFET)100与平面器件200的集成的工艺方案称为drain-first工艺方案。所述drain-first工艺方案首先通过离子注入工艺实现所述内隧穿场效应晶体管100的第一漏区110、第二漏区120以及第二区域20b内金属氧化物半导体晶体管300的第二源区310及所述第三漏区320。然后通过原位掺杂(in-situ doping)工艺以及蚀刻工艺实现了所述第一源区130。最后通过沉积栅电介质材料层217及栅极材料层218加上蚀刻工艺实现所述第一栅区160及第二栅区340。最后根据CMOS标准工艺的连接(contact)工艺实现整个半导体器件10的金属接触。具体地，所述半导体器件的制备方法包括但不仅限于以下步骤。
步骤S110，提供一总衬底20，所述总衬底包括相邻的第一衬底100a及第二衬底200a，所述第一衬底100a包括相对设置的第一表面100c及第二表面100d，所述第二衬底200a包括相对设置的第三表面200c及第四表面200d， 所述第三表面200c与所述第一表面100c平齐，所述第四表面200d与所述第二表面100d平齐。请参阅图9，所述总衬底20可以为硅(Si)衬底。在其他实施方式中，所述衬底总20也可以为锗(Ge)或硅锗、镓砷等II-IV族、或III-V族、或IV-IV族的二元或三元化合物半导体、绝缘衬底上的硅(Silicon on Insulator,SOI)、或者绝缘衬底上的锗中的任意一种。
步骤S120，在所述第一衬底100a的一侧形成第一电气元件100b，在所述第二衬底200a的一侧形成第二电气元件200b，所述第二电气元件200b与所述第一电气元件100b设置于所述总衬底20的同一侧，所述第一衬底100a及所述第一电气元件100b构成隧穿场效应晶体管100，所述第二衬底200a及所述第二电气元件200b构成平面器件200，其中，所述平面器件200包括金属氧化物半导体晶体管、电容、电阻的任意一种。
所述第一电气元件100b包括N层材料层，所述第二电气元件200b包括M层材料层，所述M小于或等于N，且所述M层材料层中与所述N层材料层中材料相同的层在同道工序中形成。
所述半导体器件的制备方法中的步骤S120还包括步骤S130。
步骤S130，自所述第一表面100c形成嵌入所述第一衬底100a内的第一浅沟道隔离区11及所述第二浅沟道隔离区12，自所述第三表面200c形成嵌入所述第二衬底200a内的第三浅沟道隔离区13及第四浅沟道隔离区14，其中，所述第一浅沟道隔离区11的一端与所述第一表面100c平齐，所述第二浅沟道隔离区12的一端与所述第一表面100c平齐，所述第二浅沟道隔离区12与所述第一浅沟道隔离区11相对设置且间隔部分第一衬底100a；所述第三浅沟道隔离区13的一端与所述第三表面200c平齐，所述第四浅沟道隔离区14的一端与所述第三表面200c平齐，所述第四浅沟道隔离区14与所述第三浅沟道隔离区13相对设置且间隔部分第二衬底。
所述平面器件200可以为金属氧化物半导体晶体管300或者为电容400或者为电阻500。当所述平面器件200为金属氧化物半导体晶体管时，所述步骤S120在所述步骤S130之后还包括如下步骤。
步骤S131a，自所述第一表面100c形成嵌入所述第一表面100c内的第一漏区110及第二漏区120，在所述第二表面200c形成嵌入所述第二表面200c 内的第二源区310及第三漏区320；其中，所述第一漏区110的一端与所述第一表面100c平齐，所述第二漏区120的一端与所述第一表面100c平齐，所述第一漏区110与所述第二漏区120相对且通过部分第一衬底100a间隔设置在所述第一浅沟道隔离区11及所述第二浅沟道隔离区12之间，所述第一漏区110与所述第一浅沟道隔离区11接触，所述第二漏区120与所述第二浅沟道隔离区12接触；所述第二源区310的一端与所述第三表面200c平齐，所述第三漏区320的一端与所述第三表面200c平齐，所述第二源区310与所述第三漏区320相对且通过部分第二衬底200a间隔设置在所述第三浅沟道隔离区13及所述第四浅沟道隔离区14之间，所述第二源区310与所述第三浅沟道隔离区13接触，所述第三漏区320与所述第四浅沟道隔离区14接触。。
步骤S132a，形成第一源区130。所述第一源区130凸出设置于所述第一表面100c，且所述第一源区130位于所述第一漏区110和所述第二漏区120之间。
步骤S133a，形成第一绝缘层140。所述第一绝缘层140凸出设置于所述衬底表面，所述第一绝缘层140对称设置于所述第一源区130的两侧，分别连接于所述第一漏区110和所述第一源区130之间以及所述第二漏区120和所述第一源区130之间，且所述第一绝缘层140的厚度小于所述第一源区130的高度。
步骤S134a，形成间隔设置的第一栅电介质层150及第二栅电介质层330。所述第一栅电介质层150对称设置在所述第一源区130两侧且贴合所述第一源区130与所述第一绝缘层140的表面。所述第二栅电介质层330凸出设置于所述衬底20的表面，且所述第二栅电介质层330设置于所述第二源区310及所述第三漏区320之间。
步骤S135a，形成第一栅区160及第二栅区340。所述第一栅区160围绕所述第一栅电介质层150设置。所述第二栅区340设置于所述第二栅电介质层330上，且所述第二栅区340与所述第二栅电介质层330接触。
在一实施方式中，所述第一漏区110、所述第二漏区120、所述第二源区310及所述第三漏区320为对所述总衬底200行第一类型离子重掺杂得到的区域，所述第一源区130为第二类型离子重掺杂区域，其中，所述第一类型离子 重掺杂为N型离子重掺杂，所述第二类型离子重掺杂为P型离子重掺杂；或者所述第一类型离子重掺杂为P型离子重掺杂，所述第二类型离子重掺杂为N型离子重掺杂。
如果所述总衬底20的材料为硅材料，N型离子掺杂时杂质可以是Li、Sb、P、As、Bi、Te、Ti、C、Mg、Se、Cr、Ta、Cs、Ba、S、Mn、Ag、Cd、Pt中的任意一种或者多种；P型离子掺杂时杂质可以是B、Al、Ga、In、Ti、Pd、Na、Be、Zn、Au、Co、V、Ni、MO、Hg、Sr Ge、W、Pb、O、Fe中的任意一种或者多种。如果所述衬底20的材料为锗材料，则N型离子掺杂时的杂质可以时Li、Sb、P、As、S、Se、Te、Cu、Au、Ag中的任意一种或者多种；P型离子掺杂时杂质可以是B、Al、In、Ga、In、Be、Zn、Cr、Cd、Hg、Co、Ni、Mn、Fe、Pt中的任意一种或者多种。当进行P型离子掺杂时，离子掺杂的浓度在1e18～1e21cm-3；当进行N型离子掺杂时，离子掺杂的浓度在1e18～1e20cm-3。
优选地，在所述步骤S131a及所述步骤S132a之间，所述半导体器件的制备方法还包括：对所述总衬底20进行退火处理。对所述总衬底20进行退火处理可以为利用快速退火工艺或者激光退火工艺对所述总衬底20进行处理，以激活所述第一漏区110、所述第二漏区120、所述第二源区310及所述第三漏区320中掺杂的离子。
在本发明的一实施方式中，具体地，所述步骤S131a包括如下步骤。
步骤S131a-I，在所述总衬底20的同个表面依次层叠设置氧化层211及第一硬掩膜层212。请参阅图11。
步骤S131a-II，图案化所述氧化层211及所述第一硬掩膜层212，以保留第一氧化部211a及第一硬掩膜部212a，以及第二氧化部212a及第二硬掩膜部212b，所述第一氧化部211a与所述第一浅沟道隔离区11以及所述第二浅沟道隔离区12间隔设置，所述第一硬掩膜部212a层叠设置在所述第一氧化部211a上，所述第二氧化部212a与所述第三浅沟道隔离区13以及所述第四浅沟道隔离区14间隔设置，所述第二硬掩膜部212b层叠设置在所述第二氧化部212b上。请一并参阅图12。
步骤S131a-III，以所述第一氧化部211a与所述第一硬掩膜部212a以及所 述第二氧化部211b与所述第二硬掩膜部212b为掩膜对所述总衬底20的表面进行第一类型离子重掺杂，形成所述第一漏区110、第二漏区120、所述第二源区310及所述第三漏区320。请一并参阅图13及图14，在本实施方式中以第一类型离子离子重掺杂为N型离子重掺杂为例，在图中以N+表示，其中，图13中示意出了以所述第一氧化部211a与所述第一硬掩膜部212a以及所述第二氧化部211b与所述第二硬掩膜部212b为掩膜对所述衬底20的表面进行第一类型离子重掺杂，图14示意出了形成的所述第一漏区110及所述第二漏区120，以及所述第二源区310及所述第三漏区320。
步骤S131a-IV，剥离所述第一氧化部211a及所述第一硬掩膜部211a以及所述第二氧化部211b及所述第二硬掩膜部212b。请参阅图15。
相应地，所述步骤S132a包括如下步骤。
步骤S132a-I，在所述总衬底20的表面沉积第二类型离子重掺杂半导体层213。请一并参阅图16。所述沉积步骤可以通过低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)或者物理气相沉积(Physical Vapor Deposition PVD)
步骤S132a-II，图案化所述第二类型离子重掺杂半导体层213，以形成所述第一源区130。具体地，所述步骤S132a-II包括以下步骤。
步骤a1，在所述第二类型离子重掺杂半导体层213上沉积第二硬掩膜层214及光刻胶215，请一并参阅图17。
步骤b1，图案化所述第二硬掩膜层214及所述光刻胶215，以保留对应所述所述第一源区110和所述第二源区120中部的第二硬掩膜层214及光刻胶215，请一并参阅图18。
步骤c1，以保留的第二硬掩膜层214及光刻胶215为掩膜对所述第二类型离子重掺杂半导体层213进行蚀刻，以保留被所述第二硬掩膜层214及所述光刻胶215覆盖的第二类型离子重掺杂半导体层213，以形成所述第一源区130，请一并参阅图19。
步骤d1，剥离对应所述第一区域20a中部的光刻胶215，请参阅图20。
相应地，在一实施方式中所述步骤S133a包括如下步骤。
步骤S133a-I，沉积一层绝缘层216，所述绝缘层216的厚度小于所述第 一源区130的高度，请参阅图21。
步骤S133a-II，图案化所述绝缘层216，以保留分别连接于所述第一漏区110和所述第一源区130之间以及所述第二漏区120和所述第一源区130之间的绝缘层216的部分，以形成所述第一绝缘层140，请一并参阅图22。
相应地，在一实施方式中所述步骤S134a包括如下步骤。
步骤S134a-I，沉积整层栅电介质材料层217，请一并参阅图23。
步骤S134a-II，图案化所述栅电介质材料层217，以保留贴合在所述第一绝缘层140及所述第一源区130表面，且对称设置在所述第一源区130两侧的栅电介质材料层217，以及保留设置在所述第二源区310及所述第三漏区320之间且分别与所述第二源区3310及所述第三漏区320接触的栅电介质材料层217，贴合在所述第一绝缘层140及所述第一源区130表面，且对称设置在所述第一源区130两侧的栅电介质材料层217定义为第一栅电介质层150，设置在所述第二源区310及所述第三漏区320之间的栅电介质材料层217定义为第二栅电介质层330，所述第一栅电介质层150包括第一栅电介质部151及第二栅电介质部152，所述第一栅电介质部151层叠设置在所述第一绝缘层140上，所述第二栅电介质部152的一端与所述第一栅电介质部151相连且所述第二栅电介质部152贴合所述第一源区130的表面，请参阅图24。
相应地，在一实施方式中，所述步骤S135a包括如下步骤。
步骤S135a-I，沉积整层的栅极材料层218，请参阅图25。
步骤S135a-II，图案化所述栅极材料层218，以保留围绕所述第一栅电介质层150以及设置在所述第二栅电介质材料层330上的栅极材料层218，设置在所述第一栅电介质材料层150上的栅极材料层218被定义为第一栅区160，设置在所述第二栅电介质层330上的栅极材料层218定义为第二栅区340，所述栅区160包括第一部分161及第二部分162，所述第一部分161层叠设置在所述第一栅电介质层150上，所述第二部分162的一端与所述第一部分161的一端相连且所述第二部分162贴合所述第二栅电介质部152的表面，请参阅图26。
所述半导体器件的制备方法还包括如下步骤。
步骤I，对应所述第一漏区110、所述第二漏区120、所述第一源区130、 所述第一栅区160、所述第二源区310、所述第三漏区320及所述第二栅区340分别形成第一漏极171、第二漏极172、第一源极173、两个第一栅极174、第二源极351、第三漏极352及第二栅极353，所述第一漏极171、所述第二漏极172、所述第一源极173、所述两个第一栅极174、所述第二源极351、所述第三漏极352及所述第二栅极353分别与所述第一漏区110、所述第二漏区120、所述第一源区130、所述第一栅区160的第二部分162、所述第二源区310、所述第三漏区320及所述第二栅区340电连接。
优选地，所述半导体器件的制备方法在所述步骤I之前还包括如下步骤。
步骤S136a，在所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160，以及所述第二源区310、所述第三漏区320及所述第二栅区340上形成绝缘隔离层219，覆盖在所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160上的绝缘隔离层219定义为第一隔离层180，覆盖在所述第二源区310、所述第三漏区320及所述第二栅区340上的绝缘隔离层219定义为第二隔离层360。
步骤S137a，在所述第一隔离层180上开设第一贯孔181、第二贯孔182、第三贯孔183、第四贯孔184及第五贯孔185，所述第四贯孔184及所述第五贯孔185分别设置于所述第三贯孔183的两侧，所述第一贯孔181对应所述第一漏区110设置，所述第一漏极171通过所述第一贯孔181以连接所述第一漏区110，所述第二贯孔182对应所述第二漏区120设置，所述第二漏极172通过所述第二贯孔182以连接所述第二漏区120，所述第三贯孔183对应所述第一源区130设置，所述第一源极173通过所述第三贯孔183以连接所述第一源区130，所述第四贯孔184及所述第五贯孔185分别对应所述第一栅区160的第二部分162设置，所述两个第一栅极174分别通过所述第四贯孔184及所述第五贯孔185连接所述第一栅区160的第二部分162。
步骤S138a，在所述第二隔离层360上开设第七贯孔361、第八贯孔362及第九贯孔363，所述第七贯孔361对应所述第二源区310设置，所述第二源极351通过所述第七贯孔361连接所述第二源区310，所述第八贯孔362对应所述第三漏区320设置，所述第三漏极352通过所述第八贯孔362连接所述第三漏区320，所述第九贯孔363对应所述第二栅区340设置，所述第二栅极353 通过所述第九贯孔363连接所述第二栅区340。上述步骤S136a～步骤S138a请参阅图27。
在一实施方式中，所述半导体器件的制备方法还包括如下步骤中的至少一个步骤。
步骤S139a-I，在所述第一漏极171及所述第一漏区110之间形成第一欧姆接触层181，所述第一漏极171通过所述第一欧姆接触层181连接所述第一漏区110。所述第一欧姆接触层181设置在所述第一漏极171及所述第一漏区110之间，以连接所述第一漏极171及所述第一漏区110，所述第一欧姆接触层181用于减小所述第一漏极171与所述第一漏区110之间的接触电阻。
步骤S139a-II，所述第二漏极172及所述第二漏区120之间形成第二欧姆接触层182，所述第二漏极172通过所述第二欧姆接触层182连接所述第二漏区120。所述第二欧姆接触层182设置在所述第二漏极172与所述第二漏区120之间，以连接所述第二漏极172及所述第二漏区120，所述第二欧姆接触层182用于减小所述第二漏极172与所述第二漏区120之间的接触电阻。
步骤S139a-III，在所述第一源极173及所述第一源区130之间形成第三欧姆接触层183，所述第一源极173通过所述第三欧姆接触层183连接所述第一源区130。所述第三欧姆接触层183设置在所述第一源极173与所述第一源区130之间，以连接所述第一源极173及所述第一源区130，所述第三欧姆接触层183用于减小所述第一源极173与所述第一源区130之间的接触电阻。
步骤S139a-IV，在第一个所述第一栅极174与所述第一栅区160的第二部分162之间形成第四欧姆接触层184，第一个所述第一栅极174通过所述第四欧姆接触层184连接所述第一栅区160的第二部分162。所述第四欧姆接触层184设置在所述第一个第一栅极174与所述第一栅区160的第二部分162之间，以连接所述第一个第一栅极174及所述第一栅区160的第二部分162，所述第四欧姆接触层184用于减小所述第一个第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。
步骤S139a-V，在第二个所述第一栅极174与所述第一栅区160的第二部分162之间形成第五欧姆接触层185，第二个所述第一栅极174通过所述第五欧姆接触185连接所述第一栅区160的第二部分162。所述第五欧姆接触层185 设置在所述第二个第一栅极174与所述第一栅区160的第二部分162之间，以连接所述第二个第一栅极174及所述第一栅区160的第二部分162，所述第五欧姆接触层185用于减小所述第二个第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。
步骤S139a-VI，在所述第二源极351与所述第二源区310之间形成第七欧姆接触层381，所述第二源极351通过所述第七欧姆接触层381连接所述第二源区310。所述第七欧姆接触层381设置在所述第二源极351及所述第二源区310之间，以连接所述第二源极351及所述第二源区310，所述第七欧姆接触层381用于减小所述第二源极351及所述第二源区310之间的接触电阻。
步骤S139a-VII，在所述第三漏极173与所述第三漏区320之间形成第八欧姆接触层382，所述第三漏极173通过所述第八欧姆接触层382连接所述第三漏区320。所述第八欧姆接触层382设置在所述第三漏极173与所述第三漏区320之间，以连接所述第三漏极173及所述第三漏区320，所述第八欧姆接触层382用于减小所述第三漏极173与所述第三漏区320之间的接触电阻。
步骤S139a-VIII，在所述第二栅极353与所述第二栅区340之间形成第九欧姆接触层383，所述第二栅极353通过所述第九欧姆接触层383连接所述第二栅区340。所述第九欧姆接触层383设置在所述第二栅极353与所述第二栅区340之间，以连接所述第二栅极353及所述第二栅区340，所述第九欧姆接触层383用于减小所述第二栅极353及所述第二栅区340之间的接触电阻。
请一并参阅图3，在本发明的一实施方式中，当所述平面器件200为金属氧化物半导体晶体管时，所述步骤S120在所述步骤S130之后包括如下步骤。
步骤a2，在所述第二类型离子重掺杂半导体层213上沉积第二硬掩膜层214及光刻胶215，请参阅图28。
步骤b2，图案化所述第二硬掩膜层214及所述光刻胶215，以保留对应所述第一源区110和所述第二源区120中部的第二硬掩膜层214及光刻胶215，请参阅图29。
步骤c2，以保留的第二硬掩膜层214及光刻胶215为掩膜对所述第二类型离子重掺杂半导体层213进行蚀刻，以保留被所述第二硬掩膜层214及所述光刻胶215覆盖的第二类型离子重掺杂半导体层213，以形成所述第一源区 130，请参阅图30。
步骤d2，剥离对应所述第一区域20a中部的第二硬掩膜层214及光刻胶215，请参阅图31。
相应地，在一实施方式中，所述步骤S134a及所述步骤S135a包括如下步骤。
步骤S134a-I’，沉积整层栅电介质材料层217。
步骤S134a-II’，在整层的栅电介质材料217上沉积整层的栅极材料层218，请参阅图32。
步骤S134a-III’，图案化所述栅电介质材料层217及所述栅极材料层218，以移除覆盖在所述第一漏区110、所述第二漏区120、所述第二源区310及所述第三漏区320上的栅电介质材料层217及栅极材料层218，剩余的栅电介质材料层217为第一栅电介质层150，其中，所述第一栅电介质层150包括第一栅电介质部151、第二栅电介质部152及第三栅电介质部153，所述第一栅电介质部151层叠设置在所述第一绝缘层140上，所述第二栅电介质部152的一端与所述第一栅电介质部151相连且所述第二栅电介质部152贴合所述第一源区130的表面，所述第三电介质部153连接所述第二栅电介质部152远离所述第一栅电介质部151的一端，且所述第三电介质部153覆盖所述第一源区130远离所述衬底20的一端；所述第一栅区160包括第一部分161、第二部分162及第三部分163，其中，所述第一部分161层叠设置在所述第一栅电介质层150上，所述第二部分162的一端与所述第一部分161的一端相连且所述第二部分162贴合所述第二栅电介质部152的表面，所述第三部分163连接所述第二部分162远离所述第一部分161的一端，且所述第三部分163覆盖在所述第三栅电介质部153上，请参阅图33。
所述半导体器件的制备方法还包括如下步骤。
步骤II，对应所述第一漏区110、所述第二漏区120、所述第一源区130、所述第一栅区160、所述第二源区310、所述第三漏区320及所述第二栅区340分别形成第一漏极171、第二漏极172、第一源极173、三个第一栅极174、第二源极351、第三漏极352及第二栅极353，所述第一漏极171、所述第二漏极172、所述第一源极173、所述第二源极351、所述第三漏极352及所述第 二栅极353分别与所述第一漏区110、所述第二漏区120、所述第一源区130、所述第二源区310、所述第三漏区320及所述第二栅区340电连接，其中两个第一栅极174连接第二部分162且分别设置于所述第一源极173的两侧，另外一个第一栅极174连接所述第三部分163。
优选地，所述半导体器件的制备方法在所述步骤II之前还包括如下步骤。
步骤S136b，在所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160，以及所述第二源区310、所述第三漏区320及所述第二栅区340上形成绝缘隔离层219，覆盖在所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160上的绝缘隔离层219定义为第一隔离层180，覆盖在所述第二源区310、所述第三漏区320及所述第二栅区340上的绝缘隔离层219定义为第二隔离层360。
步骤S137b，在所述第一隔离层180上开设第一贯孔181、第二贯孔182、第三贯孔183、第四贯孔184、第五贯孔185及第六贯孔186，所述第四贯孔184及所述第五贯孔185分别设置于所述第三贯孔183的两侧，所述第一贯孔181对应所述第一漏区110设置，所述第一漏极171通过所述第一贯孔181以连接所述第一漏区110，所述第二贯孔182对应所述第二漏区120设置，所述第二漏极172通过所述第二贯孔182以连接所述第二漏区120，所述第三贯孔183对应所述第一源区130设置，所述第一源极173通过所述第三贯孔183以连接所述第一源区130，所述第四贯孔184及所述第五贯孔185分别对应所述第一栅区160的第二部分162设置，所述第六贯孔186对应所述第三部分163设置，其中两个第一栅极174分别通过所述第四贯孔184及所述第五贯孔185连接所述第一栅区160的第二部分162，另外一个第一栅极174通过所述第六贯孔186连接所述第一栅区160的第三部分163。
步骤S138b，在所述第二隔离层360上开设第七贯孔361、第八贯孔362及第九贯孔363，所述第七贯孔361对应所述第二源区310设置，所述第二源极351通过所述第七贯孔361连接所述第二源区310，所述第八贯孔362对应所述第三漏区320设置，所述第三漏极352通过所述第八贯孔362连接所述第三漏区320，所述第九贯孔363对应所述第二栅区340设置，所述第二栅极353通过所述第九贯孔363连接所述第二栅区340。所述步骤S136b～步骤S138b， 请参阅图34。
所述半导体器件的制备方法还包括如下步骤中的至少一个步骤。
步骤S139b-I，在所述第一漏极171及所述第一漏区110之间形成第一欧姆接触层181，所述第一漏极171通过所述第一欧姆接触层181连接所述第一漏区110。所述第一欧姆接触层181设置在所述第一漏极171及所述第一漏区110之间，以连接所述第一漏极171及所述第一漏区110，所述第一欧姆接触层181用于减小所述第一漏极171与所述第一漏区110之间的接触电阻。
步骤S139b-II，所述第二漏极172及所述第二漏区120之间形成第二欧姆接触层182，所述第二漏极172通过所述第二欧姆接触层182连接所述第二漏区120。所述第二欧姆接触层182设置在所述第二漏极172与所述第二漏区120之间，以连接所述第二漏极172及所述第二漏区120，所述第二欧姆接触层182用于减小所述第二漏极172与所述第二漏区120之间的接触电阻。
步骤S139b-III，在所述第一源极173及所述第一源区130之间形成第三欧姆接触层183，所述第一源极173通过所述第三欧姆接触层183连接所述第一源区130。所述第三欧姆接触层183设置在所述第一源极173与所述第一源区130之间，以连接所述第一源极173及所述第一源区130，所述第三欧姆接触层183用于减小所述第一源极173与所述第一源区130之间的接触电阻。
步骤S139b-IV，在第一个所述第一栅极174与所述第一栅区160的第二部分162之间形成第四欧姆接触层184，第一个所述第一栅极174通过所述第四欧姆接触层184连接所述第一栅区160的第二部分162。所述第四欧姆接触层184设置在所述第一个第一栅极174与所述第一栅区160的第二部分162之间，以连接所述第一个第一栅极174及所述第一栅区160的第二部分162，所述第四欧姆接触层184用于减小所述第一个第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。
步骤S139b-V，在第二个所述第一栅极174与所述第一栅区160的第二部分162之间形成第五欧姆接触层185，第二个所述第一栅极174通过所述第五欧姆接触185连接所述第一栅区160的第二部分162。所述第五欧姆接触层185设置在所述第二个第一栅极174与所述第一栅区160的第二部分162之间，以连接所述第二个第一栅极174及所述第一栅区160的第二部分162，所述第五 欧姆接触层185用于减小所述第二个第一栅极174与所述第一栅区160的第二部分162之间的接触电阻。
步骤S139b-VI，在第三个所述第一栅极174与所述第一栅区160的第三部分163之间形成第六欧姆接触层186，第三个所述第一栅极174通过所述第六欧姆接触层186连接所述第一栅区160的第三部分163。
步骤S139b-VII，在所述第二源极351与所述第二源区310之间形成第七欧姆接触层381，所述第二源极351通过所述第七欧姆接触层381连接所述第二源区310。所述第七欧姆接触层381设置在所述第二源极351及所述第二源区310之间，以连接所述第二源极351及所述第二源区310，所述第七欧姆接触层381用于减小所述第二源极351及所述第二源区310之间的接触电阻。
步骤S139b-VIII，在所述第三漏极173与所述第三漏区320之间形成第八欧姆接触层382，所述第三漏极173通过所述第八欧姆接触层382连接所述第三漏区320。所述第八欧姆接触层382设置在所述第三漏极173与所述第三漏区320之间，以连接所述第三漏极173及所述第三漏区320，所述第八欧姆接触层382用于减小所述第三漏极173与所述第三漏区320之间的接触电阻。
步骤S139b-V-IV，在所述第二栅极353与所述第二栅区340之间形成第九欧姆接触层383，所述第二栅极353通过所述第九欧姆接触层383连接所述第二栅区340。所述第九欧姆接触层383设置在所述第二栅极353与所述第二栅区340之间，以连接所述第二栅极353及所述第二栅区340，所述第九欧姆接触层383用于减小所述第二栅极353及所述第二栅区340之间的接触电阻。
相较于现有技术，本发明的半导体器件的制备方法中第一区域20a中的第一漏区110及第二漏区120与所述第二区域20b内金属氧化物半导体晶体管300的第二源区310及第三漏区320的掺杂类型相同，通过一次离子注入便可以实现，减少了制备所述半导体器件的工艺步骤，以及工艺复杂程度，即降低了成本。且本发明的半导体器件的制备工艺斗鱼现有CMOS的标准工艺兼容，没有增加多余复杂的工艺方法。
下面对所述半导体器件中的平面器件为电容时所述半导体器件的制备方法进行介绍。所述步骤S120在所述步骤S130之后还包括如下步骤。
步骤S131c，自所述第一表面100c形成嵌入所述第一表面100c内的第一 漏区110及第二漏区120，在所述第二表面200c形成嵌入所述第二表面200c内的第一掺杂区410；其中，所述第一漏区110的一端与所述第一表面100c平齐，所述第二漏区120的一端与所述第一表面100c平齐，所述第一漏区110与所述第二漏区120相对且通过部分第一衬底100a间隔设置在所述第一浅沟道隔离区11及所述第二浅沟道隔离区12之间，所述第一漏区110与所述第一浅沟道隔离区11接触，所述第二漏区120与所述第二浅沟道隔离区12接触；所述第一掺杂区410的一端与所述第三表面200c平齐，所述第一掺杂区410设置在所述第三浅沟道隔离区13和所述第四浅沟道隔离区14之间，所述第一掺杂区410的一端与所述第三浅沟道隔离区13接触，所述第一掺杂区410的另一端与所述第四浅沟道隔离区14接触。
步骤S132c，形成第一源区130。所述第一源区130凸出设置于所述第一表面100c，且所述第一源区130位于所述第一漏区110和所述第二漏区120之间。
步骤S133c，形成第一绝缘层140及第二绝缘层420。所述第一绝缘层140凸出设置于所述第一衬底表面，所述第一绝缘层140对称设置于所述第一源区130的两侧，分别连接于所述第一漏区110和所述第一源区130之间以及所述第二漏区120和所述第一源区130之间，且所述第一绝缘层140的厚度小于所述第一源区130的高度。所述第二绝缘层420设置于所述第一掺杂区410的中部且所述第二绝缘层420的未覆盖所述第一掺杂区域410的两端，所述第二绝缘层420与所述第一绝缘层140位于同一层。
步骤S134c，形成间隔设置的第一栅电介质层151及第三栅电介质层430。所述第一栅电介质层150对称设置在所述第一源区130两侧且贴合所述第一源区130与所述第一绝缘层140的表面。所述第三栅电介质层430层叠设置于所述第二绝缘层420上。
步骤S135c，形成第一栅区160及第三栅区440。所述第一栅区160围绕所述第一栅电介质层150设置。所述第三栅区440层叠设置于所述第三栅电介质层430上。
具体地，在本实施方式中，所述步骤S131c包括如下步骤。
步骤S131c-I，在所述衬底20的同个表面依次形成层叠设置的氧化层211 及第三硬掩膜层220，请参阅图35。
步骤S131c-II，图案化所述氧化层211及所述第三硬掩膜层220，以移除位于所述第一区域20a的两端以及所述第二区域20b的氧化层211及第三硬掩膜层220，请参阅图36。
步骤S131c-III，以图案化后的氧化层211及第三硬掩膜层220为掩膜对所述衬底20的表面进行第一类型离子重掺杂，以在所述第一区域20a内形成间隔设置的所述第一漏区110及所述第二漏区120，在第二区域20b内形成所述第一掺杂区410，请参阅图37。
步骤S131c-IV，剥离剩余的氧化层211及第三硬掩膜层220，请参阅图38。
优选地，在所述步骤S131b及所述步骤S132b之间，所述半导体器件的制备方法还包括：对所述衬底20进行退火处理。
在本实施方式中，所述步骤S132c具体包括如下步骤。
步骤S132c-I，沉积第二类型离子重掺杂半导体层213，请参阅图39。
步骤S132c-II，图案化所述第二类型离子重掺杂半导体层213，以形成所述第一源区130。
所述步骤S132c-II具体包括如下步骤。
步骤a3，在所述第二类型离子重掺杂半导体层213上沉积第四硬掩膜层221及光刻胶215，请参阅图40。
步骤b3，图案化所述第四硬掩膜层221及所述光刻胶215，以保留对应所述第一源区110和所述第二源区120中部的第四硬掩膜层221及光刻胶215，请参阅图41。
步骤c3，以保留的第四硬掩膜层221及光刻胶215为掩膜对所述第二类型离子重掺杂半导体层213进行蚀刻，以保留被所述第四硬掩膜层221及所述光刻胶215覆盖的第二类型离子重掺杂半导体层213，以形成所述第一源区130，请参阅图42。
步骤d3，剥离对应所述第一区域20a中部的光刻胶215，请参阅图43。
相应地，所述步骤S133c具体包括如下步骤。
步骤S133c-I，沉积一层绝缘层216，所述绝缘层216的厚度小于所述第一源区130的高度，请参阅图44。
步骤S133c-II，图案化所述绝缘层216，以保留围绕所述第一源区130的绝缘层216的部分以及设置在所述第一掺杂区410中部的绝缘层216的部分，其中，围绕所述第一源区130的绝缘层216的部分为所述第一绝缘层140，设置在所述第一掺杂区410中部的绝缘层的部分为第二绝缘层420，请参阅图45。
相应地，所述步骤S134c具体包括如下步骤。
步骤S134c-I，沉积整层栅电介质材料层217，请参阅图46。
步骤S134c-II，图案化所述栅电介质材料层217，以保留贴合在所述第一绝缘层140及所述第一源区130表面，且对称设置在所述第一源区130两侧的栅电介质材料层217，以及保留设置在所述第二绝缘层420上的栅电介质材料层217，贴合在所述第一绝缘层140及所述第一源区130表面，且对称设置在所述第一源区130两侧的栅电介质材料层217定义为第一栅电介质层150，设置在所述第二绝缘层420上的栅电介质材料层217定义为第三栅电介质层430，所述第一栅电介质层150包括第一栅电介质部151及第二栅电介质部152，所述第一栅电介质部151层叠设置在所述第一绝缘层140上，所述第二栅电介质部152的一端与所述第一栅电介质部151相连且所述第二栅电介质部152贴合所述第一源区130的表面，请参阅图47。
相应地，所述步骤S135c具体包括如下步骤。
步骤S135c-I，沉积整层的栅极材料层218，请参阅图48。
步骤S135c-II，图案化所述栅极材料层218，以保留围绕第一栅电介质层150以及设置在所述第三栅电介质层430上的栅极材料层218，设置在所述第一栅电介质层150上的栅极材料层218定义为第一栅区160，设置在所述第三栅电介质层430上的栅极材料层定义为第三栅区440，所述第一栅区160包括第一部分161及第二部分162，所述第一部分161层叠设置在所述第一栅电介质层150上，所述第二部分162的一端与所述第一部分161的一端相连且所述第二部分162贴合所述第二栅电介质部152的表面，请参阅图49。
所述半导体器件的制备方法还包括如下步骤。
步骤III，对应所述第一漏区110、所述第二漏区120、所述第一源区130及第一栅区160分别形成第一漏极171、第二漏极172、第一源极173及两个第一栅极174，及对应所述第一掺杂区410的一端形成第一电极451，对应所 述第一掺杂区410的另一端形成第二电极452，对应所述第三栅区440形成第三电极453。
优选地，在所述步骤III之前，所述半导体器件的制备方法还包括如下步骤。
步骤S136c，在所述第一漏区110、所述第二漏区120、所述第一源区130、所述第一栅区160及所述第三栅区440上形成绝缘隔离层219，覆盖在所述第一漏区110、所述第二漏区120、所述第一源区130、所述第一栅区160的绝缘隔离层219定义为第一隔离层180，覆盖在所述第三栅区440上的绝缘隔离层219定义为第三隔离层460。
步骤S137c，在所述第一隔离层180上开设第一贯孔181、第二贯孔182、第三贯孔183、第四贯孔184及第五贯孔185，所述第四贯孔184及所述第五贯孔185分别设置于所述第三贯孔183的两侧，所述第一贯孔181对应所述第一漏区110设置，所述第一漏极171通过所述第一贯孔181以连接所述第一漏区110，所述第二贯孔182对应所述第二漏区120设置，所述第二漏极172通过所述第二贯孔182以连接所述第二漏区120，所述第三贯孔183对应所述第一源区130设置，所述第一源极173通过所述第三贯孔183以连接所述第一源区130，所述第四贯孔184及所述第五贯孔185分别对应所述第一栅区160的第二部分162设置，所述两个第一栅极174分别通过所述第四贯孔184及所述第五贯孔185连接所述第一栅区160。
步骤S138c，在所述第三隔离层460上开设第十贯孔461、第十一贯孔462及第十二贯孔463，所述第一电极451通过所述第十贯孔461连接所述第一掺杂区410的一端，所述第二电极452通过所述第十一贯孔462连接所述第一掺杂区410的另一端，所述第三电极453通过所述第十二贯孔463连接所述第三栅区440，所述步骤S136c～138c请一并参阅图50。
下面对所述半导体器件10中的平面器件200为电阻500时所述半导体器件10的制备方法进行介绍。当所述平面器件200为电容时，所述步骤S120在所述步骤S130之后还包括如下步骤。
步骤S131d，自所述第一表面100c形成嵌入所述第一表面100c内的第一 漏区110及第二漏区120，在所述第二表面200c形成嵌入所述第二表面200c内的第二掺杂区410；其中，所述第一漏区110的一端与所述第一表面100c平齐，所述第二漏区120的一端与所述第一表面100c平齐，所述第一漏区110与所述第二漏区120相对且通过部分第一衬底100a间隔设置在所述第一浅沟道隔离区11及所述第二浅沟道隔离区12之间，所述第一漏区110与所述第一浅沟道隔离区11接触，所述第二漏区120与所述第二浅沟道隔离区12接触；所述第二掺杂区510的一端与所述第三表面200c平齐，所述第二掺杂区510设置在所述第三浅沟道隔离区13和所述第四浅沟道隔离区14之间，所述第二掺杂区510的一端与所述第三浅沟道隔离区13接触，所述第二掺杂区510的另一端与所述第四浅沟道隔离区14接触。所述第二掺杂区510与所述第一漏区110及所述第二漏区120位于同一层，请参阅图51。
步骤S132d，形成第一源区130。所述第一源区130凸出设置于所述第一衬底20的表面，且所述第一源区130位于所述第一漏区110和所述第二漏区120之间，请一并参阅图52。
步骤S133d，形成第一绝缘层140。所述第一绝缘层140凸出设置于所述第一衬底表面，所述第一绝缘层140对称设置于所述第一源区130的两侧，分别连接于所述第一漏区110和所述第一源区130之间以及所述第二漏区120和所述第一源区130之间，且所述第一绝缘层140的厚度小于所述第一源区130的高度，请一并参阅图53。
步骤S134d，形成第一栅电介质层150。所述第一栅电介质层150对称设置在所述第一源区130两侧且贴合所述第一源区130与所述第一绝缘层140的表面。请一并参阅图54。
步骤S135d，形成第一栅区160，所述第一栅区160围绕所述第一栅电介质层150设置。请一并参阅图55。
所述半导体器件的制备方法还包括如下步骤。
步骤IV，对应所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160分别形成第一漏极171、第二漏极172、第一源极173及两个第一栅极174，及对应所述第二掺杂区510的两端分别形成第四电极520及第五电极530。
优选地，在所述步骤IV之前，所述半导体器件的制备方法还包括如下步骤。
步骤S136d，在所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160，以及所述第二掺杂区510上形成绝缘隔离层219，覆盖在所述第一漏区110、所述第二漏区120、所述第一源区130及所述第一栅区160上的绝缘隔离层219定义为第一隔离层180，覆盖在所述第二掺杂区510上的绝缘隔离层219定义为第四隔离层540。
步骤S137d，在所述第一隔离层180上开设第一贯孔181、第二贯孔182、第三贯孔183、第四贯孔184及第五贯孔185，所述第四贯孔184及所述第五贯孔185分别设置于所述第三贯孔183的两侧，所述第一漏极171通过所述第一贯孔181以连接所述第一漏区110，所述第二漏极172通过所述第二贯孔182以连接所述第二漏区120，所述第一源极173通过所述第三贯孔183以连接所述第一源区130，所述两个第一栅极174分别通过所述第四贯孔184及所述第五贯孔185连接所述第一栅区160。
步骤S138d，在所述第四隔离层540上开设第十二贯孔541及第十三贯孔542，所述第四电极520通过所述第十二贯孔541连接所述第二掺杂区510的一端，所述第五电极530通过所述第十三贯孔542连接所述第二掺杂区510的另一端。所述步骤S136d～步骤S138d请参阅图56。
相较于现有技术，本发明的半导体器件的制备方法中隧穿场效应晶体管中和平面器件中材料相同的层在同道工序中形成，从而减小了所述半导体器件的制备工艺的复杂程度及实现成本。
可以理解地，随着在本发明中的半导体器件10中的所述第一区域20a内设置的器件以隧穿场效应晶体管为例进行介绍，可以理解地，在其他实施方式中，所述半导体器件10中的所述第一区域20a中的器件也可以为漏区设置在底部的其他器件。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (47)

  1. 一种半导体器件，其特征在于，所述半导体器件包括隧穿场效应晶体管及平面器件，所述隧穿场效应晶体管包括第一衬底和第一电气元件，所述第一电气元件形成于所述第一衬底的一侧，所述平面器件包括第二衬底及第二电气元件，所述第二衬底与所述第一衬底为一体式结构并形成一个总衬底，所述第二电气元件形成于所述第二衬底的一侧，且所述第二电气元件与所述第一电气元件设置于所述总衬底的同一侧，其中，所述平面器件包括金属氧化物半导体晶体管、电容、电阻中的任意一种。
  2. 如权利要求1所述的半导体器件，其特征在于，所述第一衬底包括相对设置的第一表面及第二表面，所述第二衬底包括相对设置的第三表面及第四表面，所述第一衬底与所述第二衬底接触，且所述第三表面与所述第一表面平齐，所述第四表面与所述第三表面平齐。
  3. 如权利要求2所述的半导体器件，其特征在于，所述第一电气元件包括第一浅沟道隔离区及第二浅沟道隔离区，所述第一浅沟道隔离区及所述第二浅沟道隔离区自所述第一表面嵌入所述第一衬底，且所述第一浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区与所述第一浅沟道隔离区相对且间隔部分第一衬底。
  4. 如权利要求3所述的半导体器件，其特征在于，所述第一电气元件还包括第一漏区、第二漏区、第一源区、第一绝缘层、第一栅电介质层及第一栅区，所述第一漏区及所述第二漏区自所述第一表面嵌入所述第一衬底内部，且所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第一源区凸出设置于所述第一表面，且所述第一源区位于所述第一漏区和所述第二漏区之 间；所述第一绝缘层凸出设置于所述第一表面；所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的高度小于所述第一源区的高度；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；所述第一栅区围绕所述第一栅电介质层设置。
  5. 如权利要求4所述的半导体器件，其特征在于，所述第一栅电介质层包括第一栅电介质部及第二栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面。
  6. 如权利要求5所述的半导体器件，其特征在于，所述第一栅区包括第一部分及第二部分，所述第一部分层叠设置在所述第一栅电介质部上，所述第二部分的一端与所述第一部分的一端相连且所述第二部分贴合所述第二栅电介质部的表面。
  7. 如权利要求6所述的半导体器件，其特征在于，所述第一栅电介质层还包括第三栅电介质部，所述第三栅电介质部连接所述第二栅电介质部远离所述第一栅电介质部的一端，且所述第三栅电介质部覆盖所述第一源区远离所述衬底的一端，所述第一栅区还包括第三部分，所述第三部分连接所述第二部分远离所述第一部分的一端，且所述第三部分覆盖在所述第三栅电介质部上。
  8. 如权利要求6所述的半导体器件，其特征在于，所述第一电气元件还包括第一漏极、第二漏极、第一源极及两个第一栅极，所述第一漏极、所述第二漏极、所述第一源极及两个所述第一栅极分别对应连接所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区的第二部分，且两个第一栅极分别设置于所述第一源极两侧。
  9. 如权利要求7所述的半导体器件，其特征在于，所述第一电气元件还包括第一漏极、第二漏极、第一源极及三个第一栅极，所述第一漏极、所述第二漏极、所述第一源极及三个第一栅极分别对应连接所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区设置，其中两个第一栅极连接第二部分且分别设置于所述第一源极两侧，另外一个第一栅极连接所述第三部分。
  10. 如权利要求1至9任意一项所述的半导体器件，其特征在于，所述第二电气元件包括第三浅沟道隔离区及第四浅沟道隔离区；所述第三浅沟道隔离区及所述第四浅沟道隔离区自所述第三表面嵌入所述第二衬底内，且所述第三浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区与所述第三浅沟道隔离区相对设置且间隔部分第二衬底。
  11. 如权利要求10所述的半导体器件，其特征在于，当所述平面器件为金属氧化物半导体晶体管时，所述第二电气元件包括第二源区、第三漏区、第二栅电介质层及第二栅区，所述第二源区及所述第三漏区自所述第三表面嵌入所述第二衬底内部，且所述第二源区的一端与所述第三表面平齐，所述第三漏区的一端与所述第三表面平齐，所述第二源区与所述第三漏区相对且通过部分第二衬底间隔设置在所述第三浅沟道隔离区及所述第四浅沟道隔离区之间，所述第二源区与所述第三浅沟道隔离区接触，所述第三漏区与所述第四浅沟道隔离区接触，第二栅电介质层凸出设置于所述第三表面，且所述第二栅电介质层设置于所述第二源区及所述第三漏区之间，所述第二栅区层叠设置于所述第二栅电介质层上，且所述第二栅区与所述第二栅电介质层接触。
  12. 如权利要求11所述的半导体器件，其特征在于，所述第二电气元件还包括第二源极、第三漏极及第二栅极，所述第二源极、所述第三漏极及所述第二栅极分别对应连接所述第二源区、所述第三漏区及所述第二栅区。
  13. 如权利要求12所述的半导体器件，其特征在于，所述第二电气元件还包括第二隔离层，所述第二隔离层与所述第一隔离层位于同一层，所述第二隔离层覆盖所述第二源区、所述第三漏区及所述第二栅区，所述第二隔离层上设置有第七贯孔、第八贯孔及第九贯孔，所述第七贯孔对应所述第二源区设置，所述第二源极通过所述第七贯孔连接所述第二源区，所述第八贯孔对应所述第三漏区设置，所述第三漏极通过所述第八贯孔连接所述第三漏区，所述第九贯孔对应所述第二栅区设置，所述第二栅极通过所述第九贯孔连接所述第二栅区。
  14. 如权利要求11所述的半导体器件，其特征在于，所述第一漏区、所述第二漏区、所述第二源区及所述第三漏区为第一类型离子重掺杂区域，所述第一源区为第二类型离子重掺杂区域，其中，所述第一类型离子重掺杂区域为N型离子重掺杂区域，所述第二类型离子重掺杂区域为P型离子重掺杂区域；或者所述第一类型离子重掺杂区域为P型离子重掺杂区域，所述第二类型离子重掺杂区域为N型离子重掺杂区域。
  15. 如权利要求10任意一项所述的半导体器件，其特征在于，当所述平面器件为电容时，所述第二电气元件包括第一掺杂区、第二绝缘层、第三栅电介质层及第三栅区，所述第一掺杂区自所述第三表面嵌入所述第二衬底内部，所述第一掺杂区的一端与所述第三表面平齐，所述第一掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第一掺杂区的一端与所述第三浅沟道隔离区接触，所述第一掺杂区的另一端与所述第四浅沟道隔离区接触，所述第二绝缘层设置于所述第一掺杂区的中部且所述第二绝缘层未覆盖所述第一掺杂区的两端，所述第三栅电介质层层叠设置于所述第二绝缘层上，所述第三栅区层叠设置于所述第三栅电介质层上。
  16. 如权利要求15所述的半导体器件，其特征在于，所述第二电气元件还包括第一电极、第二电极及第三电极，所述第一电极及所述第二电极分别对应连接所述第一掺杂区的两端，所述第三电极连接所述第三栅区。
  17. 如权利要求10所述的半导体器件，其特征在于，当所述平面器件为电阻时，所述第二电气元件包括第二掺杂区，所述第二掺杂区自所述第三表面嵌入所述第三表面嵌入所述第二衬底内部，所述第二掺杂区的一端与所述第三表面平齐，所述第二掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第二掺杂区的一端与所述第三浅沟道隔离区接触，所述第二掺杂区的另一端与所述第四浅沟道隔离区接触。
  18. 如权利要求17所述的半导体器件，其特征在于，第二电气元件还包括第四电极及第五电极，所述第四电极及所述第五电极分别对应连接所述第二掺杂区的两端。
  19. 一种半导体器件的制备方法，其特征在于，所述半导体器件的制备方法包括：
    S110，提供一总衬底，所述总衬底包括相邻的第一衬底及第二衬底，所述第一衬底包括相对设置的第一表面及第二表面，所述第二衬底包括相对设置的第三表面及第四表面，所述第三表面与所述第一表面平齐，所述第四表面与所述第二表面平齐；
    S120，在所述第一衬底的一侧形成第一电气元件，在所述第二衬底的一侧形成第二电气元件，所述第二电气元件与所述第一电气元件设置于所述总衬底的同一侧，所述第一衬底及所述第一电气元件构成隧穿场效应晶体管，所述第二衬底及所述第二电气元件构成平面器件，其中，所述平面器件包括金属氧化物半导体晶体管、电容、电阻的任意一种。
  20. 如权利要求19所述的半导体器件的制备方法，其特征在于，所述步骤S120包括：
    步骤S130，自所述第一表面形成嵌入所述第一衬底内的第一浅沟道隔离区及所述第二浅沟道隔离区，自所述第三表面形成嵌入所述第二衬底内的第三 浅沟道隔离区及第四浅沟道隔离区，其中，所述第一浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区的一端与所述第一表面平齐，所述第二浅沟道隔离区与所述第一浅沟道隔离区相对设置且间隔部分第一衬底；所述第三浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区的一端与所述第三表面平齐，所述第四浅沟道隔离区与所述第三浅沟道隔离区相对设置且间隔部分第二衬底。
  21. 如权利要求20所述的半导体器件的制备方法，其特征在于，所述步骤S120在所述步骤S130之后还包括：
    步骤S131a，自所述第一表面形成嵌入所述第一表面内的第一漏区及第二漏区，在所述第二表面形成嵌入所述第二表面内的第二源区及第三漏区；其中，所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第二源区的一端与所述第三表面平齐，所述第三漏区的一端与所述第三表面平齐，所述第二源区与所述第三漏区相对且通过部分第二衬底间隔设置在所述第三浅沟道隔离区及所述第四浅沟道隔离区之间，所述第二源区与所述第三浅沟道隔离区接触，所述第三漏区与所述第四浅沟道隔离区接触；
    步骤S132a，形成第一源区，所述第一源区凸出设置于所述第一表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；
    步骤S133a，形成第一绝缘层；所述第一绝缘层凸出设置于所述衬底表面，所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的厚度小于所述第一源区的高度；
    步骤S134a，形成间隔设置的第一栅电介质层及第二栅电介质层；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；所述第二栅电介质层凸出设置于所述衬底的表面，且所述第二栅电介质层设置于所述第二源区及所述第三漏区之间；
    步骤S135a，形成第一栅区及第二栅区；所述第一栅区围绕所述第一栅电介质层设置；所述第二栅区设置于所述第二栅电介质层上，且所述第二栅区与所述第二栅电介质层接触。
  22. 如权利要求21所述的半导体器件的制备方法，其特征在于，所述步骤S131a包括：
    步骤S131a-I，在所述总衬底的同个表面依次层叠设置氧化层及第一硬掩膜层；
    步骤S131a-II，图案化所述氧化层及所述第一硬掩膜层，以保留第一氧化部及第一硬掩膜部，以及第二氧化部及第二硬掩膜部，所述第一氧化部与所述第一浅沟道隔离区以及所述第二浅沟道隔离区间隔设置，所述第一硬掩膜部层叠设置在所述第一氧化部上，所述第二氧化部与所述第三浅沟道隔离区以及所述第四浅沟道隔离区间隔设置，所述第二硬掩膜部层叠设置在所述第二氧化部上；
    步骤S131a-III，以所述第一氧化部与所述第一硬掩膜部以及所述第二氧化部2与所述第二硬掩膜部为掩膜对所述总衬底的表面进行第一类型离子重掺杂，形成间所述第一漏区、第二漏区、所述第二源区及所述第三漏区；
    步骤S131a-IV，剥离所述第一氧化部及所述第一硬掩膜部以及所述第二氧化部及所述第二硬掩膜部。
  23. 如权利要求20所述的半导体器件的制备方法，其特征在于，在所述步骤S132a及所述步骤S133a之间，所述半导体器件的制备方法还包括：
    对所述总衬底进行退火处理。
  24. 如权利要求22所述的半导体器件的制备方法，其特征在于，所述步骤S132a包括：
    步骤S132a-I，在所述总衬底的表面沉积第二类型离子重掺杂半导体层；
    步骤S132a-II，图案化所述第二类型离子重掺杂半导体层，以形成所述第一源区。
  25. 如权利要求24所述的半导体器件的制备方法，其特征在于，所述步骤S132a-II包括：
    步骤a1，在所述第二类型离子重掺杂半导体层上沉积第二硬掩膜层及光刻胶；
    步骤b1，图案化所述第二硬掩膜层及所述光刻胶，以保留对应所述第一源区和所述第二源区中部的第二硬掩膜层及光刻胶；
    步骤c1，以保留的第二硬掩膜层及光刻胶为掩膜对所述第二类型离子重掺杂半导体层进行蚀刻，以保留被所述第二硬掩膜层及所述光刻胶覆盖的第二类型离子重掺杂半导体层，以形成所述第一源区；
    步骤d1，剥离对应所述第一区域中部的光刻胶。
  26. 如权利要求25所述的半导体器件的制备方法，其特征在于，所述步骤S133a包括：
    步骤S133a-I，沉积一层绝缘层，所述绝缘层的厚度小于所述第一源区的高度；
    步骤S133a-II，图案化所述绝缘层，以保留分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间的绝缘层的部分，以形成所述第一绝缘层。
  27. 如权利要求26所述的半导体器件的制备方法，其特征在于，所述步骤S134a包括：
    步骤S134a-I，沉积整层栅电介质材料层；
    步骤S134a-II，图案化所述栅电介质材料层，以保留贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层，以及保留设置在所述第二源区及所述第三漏区之间且分别与所述第二源区及所述第三漏区接触的栅电介质材料层，贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层定义为第一栅电介质层，设置在所述第二源区及所述第三漏区之间的栅电介质材料层定义为第二栅 电介质层，所述第一栅电介质层包括第一栅电介质部及第二栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面。
  28. 如权利要求27所述的半导体器件的制备方法，其特征在于，所述步骤S135a包括：
    步骤S135a-I，沉积整层的栅极材料层；
    步骤S135a-II，图案化所述栅极材料层，以保留围绕所述第一栅电介质层以及设置在所述第二栅电介质层上的栅极材料层，设置在所述第一栅电介质层上的栅极材料层定义为第一栅区，设置在所述第二栅电介质层上的栅极材料层定义为第二栅区，所述栅区包括第一部分及第二部分，所述第一部分层叠设置在所述第一栅电介质层上，所述第二部分的一端与所述第一部分的一端相连且所述第二部分贴合所述第二栅电介质部的表面。
  29. 如权利要求28所述的半导体器件的制备方法，其特征在于，所述半导体器件的制备方法还包括：
    步骤I，对应所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区、所述第二源区、所述第三漏区及所述第二栅区分别形成第一漏极、第二漏极、第一源极、两个第一栅极、第二源极、第三漏极及第二栅极，所述第一漏极、所述第二漏极、所述第一源极、所述两个第一栅极、所述第二源极、所述第三漏极及所述第二栅极分别与所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区的第二部分、所述第二源区、所述第三漏区及所述第二栅区电连接。
  30. 如权利要求25所述的半导体器件的制备方法，其特征在于，所述步骤S120在所述步骤S130还包括：
    步骤a2，在所述第二类型离子重掺杂半导体层上沉积第二硬掩膜层及光刻胶；
    步骤b2，图案化所述第二硬掩膜层及所述光刻胶，以保留对应所述第一源区和所述第二源区中部的第二硬掩膜层及光刻胶；
    步骤c2，以保留的第二硬掩膜层及光刻胶为掩膜对所述第二类型离子重掺杂半导体层进行蚀刻，以保留被所述第二硬掩膜层及所述光刻胶覆盖的第二类型离子重掺杂半导体层，以形成所述第一源区；
    步骤d2，剥离对应所述第一区域中部的第二硬掩膜层及光刻胶。
  31. 如权利要求30所述的半导体器件的制备方法，其特征在于，所述步骤S134a及所述步骤S135a包括：
    步骤S134a-I’，沉积整层栅电介质材料层；
    步骤S134a-II’，整层的栅电介质材料层上沉积栅极材料层；
    步骤S134a-III’，图案化所述栅电介质材料层及所述栅极材料层，以移除覆盖在所述第一漏区、所述第二漏区、所述第二源区及所述第三漏区上的栅电介质材料层及栅极材料层，剩余的栅电介质材料层为第一栅电介质层，其中，所述第一栅电介质层包括第一栅电介质部、第二栅电介质部及第三栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面，所述第三电介质部连接所述第二栅电介质部远离所述第一栅电介质部的一端，且所述第三电介质部覆盖所述第一源区远离所述衬底的一端；所述第一栅区包括第一部分、第二部分及第三部分，其中，所述第一部分层叠设置在所述第一栅电介质层上，所述第二部分的一端与所述第一部分的一端相连且所述第二部分贴合所述第二栅电介质部的表面，所述第三部分连接所述第二部分远离所述第一部分的一端，且所述第三部分覆盖在所述第三栅电介质部上。
  32. 如权利要求31所述的半导体器件的制备方法，其特征在于，所述半导体器件的制备方法还包括：
    步骤II，对应所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区、所述第二源区、所述第三漏区及所述第二栅区分别形成第一漏极、第二漏极、第一源极、三个第一栅极、第二源极、第三漏极及第二栅极，所述第一漏 极、所述第二漏极、所述第一源极、所述第二源极、所述第三漏极及所述第二栅极分别与所述第一漏区、所述第二漏区、所述第一源区、所述第二源区、所述第三漏区及所述第二栅区电连接，其中两个第一栅极连接第二部分且分别设置于所述第一源极的两侧，另外一个第一栅极连接所述第三部分。
  33. 如权利要求32所述的半导体器件的制备方法，其特征在于，在所述步骤II之前，所述半导体器件的制备方法还包括：
    步骤S136b，在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区，以及所述第二源区、所述第三漏区及所述第二栅区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区上的绝缘隔离层定义为第一隔离层，覆盖在所述第二源区、所述第三漏区及所述第二栅区上的绝缘隔离层定义为第二隔离层；
    步骤S137b，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔、第五贯孔及第六贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第一源极通过所述第三贯孔以连接所述第一源区，其中两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区的第二部分，另外一个第一栅极通过所述第六贯孔连接所述第一栅区的第三部分；
    步骤S138b，在所述第二隔离层上开设第七贯孔、第八贯孔及第九贯孔，所述第二源极通过所述第七贯孔连接所述第二源区，所述第三漏极通过所述第八贯孔连接所述第三漏区，所述第二栅极通过所述第九贯孔连接所述第二栅区。
  34. 如权利要求21所述的半导体器件的制备方法，其特征在于，所述第一漏区、所述第二漏区、所述第二源区及所述第三漏区为对所述衬底进行第一类型离子重掺杂得到的区域，所述第一源区为第二类型离子重掺杂区域，其中，所述第一类型离子重掺杂为N型离子重掺杂，所述第二类型离子重掺杂为P 型离子重掺杂；或者所述第一类型离子重掺杂为P型离子重掺杂，所述第二类型离子重掺杂为N型离子重掺杂。
  35. 如权利要求20所述的半导体器件的制备方法，其特征在于，所述步骤S120在所述步骤S130之后包括：
    步骤S131c，自所述第一表面形成嵌入所述第一表面内的第一漏区及第二漏区，在所述第二表面形成嵌入所述第二表面内的第一掺杂区；其中，所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第一掺杂区的一端与所述第三表面平齐，所述第一掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第一掺杂区的一端与所述第三浅沟道隔离区接触，所述第一掺杂区的另一端与所述第四浅沟道隔离区接触；
    步骤S132c，形成第一源区；所述第一源区凸出设置于所述第一衬底的表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；
    步骤S133c，形成第一绝缘层及第二绝缘层；所述第一绝缘层凸出设置于所述衬底表面，所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的厚度小于所述第一源区的高度；
    步骤S134c，形成间隔设置的第一栅电介质层及第三栅电介质层；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；所述第三栅电介质层层叠设置于所述第二绝缘层上；所述第二绝缘层设置于所述第一掺杂区的中部且所述第二绝缘层的未覆盖所述第一掺杂区域的两端，所述第二绝缘层与所述第一绝缘层位于同一层；
    步骤S135c，形成第一栅区及第三栅区；所述第一栅区围绕所述第一栅电介质层设置；所述第三栅区层叠设置于所述第三栅电介质层上。
  36. 如权利要求34所述的半导体器件的制备方法，其特征在于，所述步骤 S131c包括：
    步骤S131c-I，在所述衬底的同个表面依次形成层叠设置的氧化层及第三硬掩膜层；
    步骤S131c-II，图案化所述氧化层及所述第三硬掩膜层，以移除位于所述第一区域的两端以及所述第二区域的氧化层及第三硬掩膜层；
    步骤S131c-III，以图案化后的氧化层及第三硬掩膜层为掩膜对所述衬底的表面进行第一类型离子重掺杂，以在所述第一区域内形成间隔设置的所述第一漏区及所述第二漏区，在第二区域内形成所述第一掺杂区；
    步骤S131c-IV，剥离剩余的氧化层及第三硬掩膜层。
  37. 如权利要求35所述的半导体器件的制备方法，其特征在于，在所述步骤S131c与所述步骤S132c之间，所述半导体器件的制备方法还包括：
    对所述总衬底进行退火处理。
  38. 如权利要求37任意一项所述的半导体器件的制备方法，其特征在于，所述步骤S132c包括：
    步骤S132c-I，沉积第二类型离子重掺杂半导体层；
    步骤S132c-II，图案化所述第二类型离子重掺杂半导体层，以形成所述第一源区。
  39. 如权利要求38所述的半导体器件的制备方法，其特征在于，所述步骤S132c-II包括：
    步骤a3，在所述第二类型离子重掺杂半导体层上沉积第四硬掩膜层及光刻胶；
    步骤b3，图案化所述第四硬掩膜层及所述光刻胶，以保留对应所述第一源区及所述第二源区中部的第四硬掩膜层及光刻胶；
    步骤c3，以保留的第四硬掩膜层及光刻胶为掩膜对所述第二类型离子重掺杂半导体层进行蚀刻，以保留被所述第四硬掩膜层及所述光刻胶覆盖的第二类型离子重掺杂半导体层，以形成所述第一源区；
    步骤d3，剥离对应所述第一区域中部的光刻胶。
  40. 如权利要求39所述的半导体器件的制备方法，其特征在于，所述步骤S133c包括：
    步骤S133c-I，沉积一层绝缘层，所述绝缘层的厚度小于所述第一源区的高度；
    步骤S133c-II，图案化所述绝缘层，以保留围绕所述第一源区的绝缘层的部分以及设置在所述第一掺杂区中部的绝缘层的部分，其中，围绕所述第一源区的绝缘层的部分为所述第一绝缘层，设置在所述第一掺杂区中部的绝缘层的部分为第二绝缘层。
  41. 如权利要求39任意一项所述的半导体器件的制备方法，其特征在于，所述步骤S134c包括：
    步骤S134c-I，沉积整层栅电介质材料层；
    步骤S134c-II，图案化所述栅电介质材料层，以保留贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层，以及保留设置在所述第二绝缘层上的栅电介质材料层，贴合在所述第一绝缘层及所述第一源区表面，且对称设置在所述第一源区两侧的栅电介质材料层定义为第一栅电介质层，设置在所述第二绝缘层上的栅电介质材料层定义为第三栅电介质层，所述第一栅电介质层包括第一栅电介质部及第二栅电介质部，所述第一栅电介质部层叠设置在所述第一绝缘层上，所述第二栅电介质部的一端与所述第一栅电介质部相连且所述第二栅电介质部贴合所述第一源区的表面。
  42. 如权利要求41所述的半导体器件的制备方法，其特征在于，所述步骤S135c包括：
    步骤S135c-I，沉积整层的栅极材料层；
    步骤S135c-II，图案化所述栅极材料层，以保留围绕第一栅电介质层以及设置在所述第三栅电介质层上的栅极材料层，设置在所述第一栅电介质层上的栅极材料层定义为第一栅区，设置在所述第三栅电介质层上的栅极材料层定义 为第三栅区，所述第一栅区包括第一部分及第二部分，所述第一部分层叠设置在所述第一栅电介质层上，所述第二部分的一端与所述第一部分d一端相连且所述第二部分贴合所述第二栅电介质部的表面。
  43. 如权利要求35所述的半导体器件的制备方法，其特征在于，所述半导体器件的制备方法还包括：
    步骤III，对应所述第一漏区、所述第二漏区、所述第一源区及第一栅区分别形成第一漏极、第二漏极、第一源极及第一栅极，及对应所述第一掺杂区的一端形成第一电极，对应所述第一掺杂区的另一端形成第二电极，对应所述第三栅区形成第三电极。
  44. 如权利要求42所述的半导体器件的制备方法，其特征在于，在所述步骤III之前，所述半导体器件的制备方法还包括：
    步骤S136c，在所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区及所述第三栅区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区、所述第一栅区的绝缘隔离层定义为第一隔离层，覆盖在所述第三栅区上的绝缘隔离层定义为第三隔离层；
    步骤S137c，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔及第五贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一贯孔对应所述第一漏区设置，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二贯孔对应所述第二漏区设置，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第三贯孔对应所述第一源区设置,所述第一源极通过所述第三贯孔以连接所述第一源区，所述第四贯孔及所述第五贯孔分别对应所述第一栅区的第二部分设置，所述两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区；
    步骤S138c，在所述第三隔离层上开设第十贯孔、第十一贯孔及第十二贯孔，所述第一电极通过所述第十贯孔连接所述第一掺杂区的一端，所述第二电极通过所述第十一贯孔连接所述第一掺杂区的另一端，所述第三电极通过所述第十二贯孔连接所述第三栅区。
  45. 如权利要求20所述的半导体器件的制备方法，其特征在于，所述步骤S120在所述步骤S130之后还包括：
    步骤S131d，自所述第一表面形成嵌入所述第一表面内的第一漏区及第二漏区，在所述第二表面形成嵌入所述第二表面内的第二掺杂区；其中，所述第一漏区的一端与所述第一表面平齐，所述第二漏区的一端与所述第一表面平齐，所述第一漏区与所述第二漏区相对且通过部分第一衬底间隔设置在所述第一浅沟道隔离区及所述第二浅沟道隔离区之间，所述第一漏区与所述第一浅沟道隔离区接触，所述第二漏区与所述第二浅沟道隔离区接触；所述第二掺杂区的一端与所述第三表面平齐，所述第二掺杂区设置在所述第三浅沟道隔离区和所述第四浅沟道隔离区之间，所述第二掺杂区的一端与所述第三浅沟道隔离区接触，所述第二掺杂区的另一端与所述第四浅沟道隔离区接触；
    步骤S132d，形成第一源区；所述第一源区凸出设置于所述第一衬底的表面，且所述第一源区位于所述第一漏区和所述第二漏区之间；
    步骤S133d，形成第一绝缘层；所述第一绝缘层凸出设置于所述第一衬底表面，所述第一绝缘层对称设置于所述第一源区的两侧，分别连接于所述第一漏区和所述第一源区之间以及所述第二漏区和所述第一源区之间，且所述第一绝缘层的厚度小于所述第一源区的高度；
    步骤S134d，形成第一栅电介质层；所述第一栅电介质层对称设置在所述第一源区两侧且贴合所述第一源区与所述第一绝缘层的表面；
    步骤S135d，形成第一栅区，所述第一栅区围绕所述第一栅电介质层设置。
  46. 如权利要求45所述的半导体器件的制备方法，其特征在于，所述半导体器件的制备方法还包括：
    步骤IV，对应所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区分别形成第一漏极、第二漏极、第一源极及两个第一栅极，及对应所述第二掺杂区的两端分别形成第四电极及第五电极。
  47. 如权利要求46所述的半导体器件的制备方法，其特征在于，在所述步 骤IV之前所述半导体器件的制备方法还包括：
    步骤S136d，在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区，以及所述第二掺杂区上形成绝缘隔离层，覆盖在所述第一漏区、所述第二漏区、所述第一源区及所述第一栅区上的绝缘隔离层定义为第一隔离层，覆盖在所述第二掺杂区上的绝缘隔离层定义为第四隔离层；
    步骤S137d，在所述第一隔离层上开设第一贯孔、第二贯孔、第三贯孔、第四贯孔及第五贯孔，所述第四贯孔及所述第五贯孔分别设置于所述第三贯孔的两侧，所述第一漏极通过所述第一贯孔以连接所述第一漏区，所述第二漏极通过所述第二贯孔以连接所述第二漏区，所述第一源极通过所述第三贯孔以连接所述第一源区，所述两个第一栅极分别通过所述第四贯孔及所述第五贯孔连接所述第一栅区；
    步骤S138d，在所述第四隔离层上开设第十二贯孔及第十三贯孔，所述第四电极通过所述第十二贯孔连接所述第二掺杂区的一端，所述第五电极通过所述第十三贯孔连接所述第二掺杂区的另一端。
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