WO2017107286A1 - 基于ltps半导体薄膜晶体管的goa电路 - Google Patents

基于ltps半导体薄膜晶体管的goa电路 Download PDF

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WO2017107286A1
WO2017107286A1 PCT/CN2016/072427 CN2016072427W WO2017107286A1 WO 2017107286 A1 WO2017107286 A1 WO 2017107286A1 CN 2016072427 W CN2016072427 W CN 2016072427W WO 2017107286 A1 WO2017107286 A1 WO 2017107286A1
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thin film
electrically connected
film transistor
clock signal
node
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French (fr)
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李亚锋
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a GOA circuit based on an LTPS semiconductor thin film transistor.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • GOA technology (Gate Driver on Array) is an array substrate row driving technology.
  • the original array process of the liquid crystal display panel is used to fabricate a horizontal scanning line driving circuit on a substrate around the display area, so that it can replace the external integrated circuit board ( (Integrated Circuit, IC) to complete the horizontal scanning line drive.
  • IC integrated circuit board
  • GOA technology can reduce the bonding process of external ICs, have the opportunity to increase productivity and reduce product cost, and can make LCD panels more suitable for making narrow borders or no borders. Display product.
  • LTPS-TFT liquid crystal displays have attracted more and more attention.
  • LTPS-TFT liquid crystal displays have high resolution, fast response, high brightness and high opening. Rate and other advantages. Since the low-temperature polysilicon has an order of arrangement of amorphous silicon (a-Si), the low-temperature polysilicon semiconductor itself has an ultra-high electron mobility, which is 100 times higher than that of the amorphous silicon semiconductor, and the gate driver can be fabricated by using GOA technology. On the thin film transistor array substrate, the goal of system integration, space saving and cost of driving the IC are achieved.
  • a-Si amorphous silicon
  • a conventional LTPS semiconductor thin film transistor based GOA circuit includes a plurality of cascaded GOA units, wherein n is a positive integer, and the nth stage GOA unit includes: a first thin film transistor T1, the first The gate of a thin film transistor T1 is electrically connected to the Mth clock signal CK(M), and the source is electrically connected to the output terminal G(n-1) of the upper n-1th GOA unit, and the drain is electrically Connected to the third node K(n); the second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and the source is electrically connected to the M+1th The clock signal CK(M+1), the drain is electrically connected to the output terminal G(n); the third thin film transistor T3, the gate of the third thin film transistor T3 is electrically connected to the M+2 clock signal CK (M+2), the drain is electrically connected to the third node K(n), and the source
  • the drain is electrically connected to the second node P(n), the source is electrically connected to the constant voltage low potential VGL; the ninth thin film transistor T9, the gate and the source of the ninth thin film transistor T9 Uniform electricity Connected to the M+1th clock signal CK(M+1), the drain is electrically connected to the second node P(n); the first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q(n), the other end is electrically connected to the output terminal G(n); the second capacitor C2, one end of the second capacitor C2 is electrically connected to the second node P(n), and the other end is electrically connected to the constant Press down the potential VGL.
  • the GOA circuit shown in Figure 1 can be scanned either in the forward direction or in the reverse direction.
  • the working processes of the forward and reverse scans are similar. Please refer to FIG. 1 and FIG. 2, taking forward scanning as an example.
  • the working process is: first, the Mth clock signal CK(M) and the output end G of the n-1th stage GOA unit ( N-1) provides a high potential, the first and fifth thin film transistors T1, T5 are turned on, the first node Q(n) is precharged to a high potential; then, the Mth clock signal CK(M) and the nth-
  • the output terminal G(n-1) of the level 1 GOA unit becomes a low potential, the M+1th clock signal CK(M+1) provides a high potential, and the first node Q(n) is stored by the first capacitor C1.
  • the second thin film transistor T2 is turned on, the output terminal G(n) outputs the high potential of the M+1th clock signal CK(M+1), and causes the first node Q(n) to be raised to a higher level.
  • the eighth thin film transistor T8 is turned on, the second node P(n) is pulled down to the constant voltage low potential VGL, and the sixth and seventh thin film transistors T6, T7 are turned off; next, the M+2 clock signal CK (M+2) and the output terminal G(n+1) of the n+1th GOA unit both provide a high potential, the first node Q(n) is still at a high potential, and the M+1th clock signal CK(M) +1) is lowered to low potential, and the output terminal G(n) outputs the low voltage of the M+1th clock signal CK(M+1) Then, the Mth clock signal CK(M) is again supplied with a high potential, the output terminal G(n-1) of the n-1th stage GOA unit is kept
  • the node Q(n) is low, and the eighth thin film transistor T8 is turned off; then, the M+1th clock signal CK(M+1) provides a high potential, the ninth thin film transistor T9 is turned on, and the second node P(n) is turned After charging to a high potential, the sixth and seventh thin film transistors T6 and T7 are turned on, respectively, and continue to pull down the first node Q(n) and the output terminal G(n) to the constant voltage low potential VGL, and store the second capacitor C2. Next, the second node P(n) continues to protect Holding the high potential, the sixth and seventh thin film transistors T6, T7 are always turned on for one frame time, keeping the low potential of the first node Q(n) and the output terminal G(n).
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each stage GOA unit including an output control module, an output module, a bootstrap capacitor, and a pull-down Module
  • n be a positive integer, in addition to the first and last stage GOA unit circuits, in the nth level GOA unit:
  • the output control module includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to the Mth clock signal, and a source is electrically connected to an output end of the upper n-1th GOA unit
  • the drain is electrically connected to the third node; the third thin film transistor, the gate of the third thin film transistor is electrically connected to the M+2 clock signal, the drain is electrically connected to the third node, and the source is electrically
  • the fifth thin film transistor is electrically connected to the constant voltage high potential, and the source is electrically connected to the third node.
  • the drain is electrically connected to the first node;
  • the output module includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the M+1th clock signal, and a drain is electrically connected to the output end ;
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the pull-down module includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the M+3 clock signal, a drain is electrically connected to the output end, and a source is electrically connected to the constant voltage a sixth thin film transistor, the gate of the sixth thin film transistor is electrically connected to the second node, the drain is electrically connected to the third node, the source is electrically connected to the constant voltage low potential; and the seventh thin film transistor is The gate of the seventh thin film transistor T7 is electrically connected to the second node, the drain is electrically connected to the output end, the source is electrically connected to the constant voltage low potential, and the eighth thin film transistor is the eighth thin film transistor.
  • the gate is electrically connected to the third node, the drain is electrically connected to the second node, and the source is electrically
  • the second thin film transistor is electrically connected to the fourth node, the source is electrically connected to the M+1th clock signal, and the drain is electrically connected to the a second node; a tenth thin film transistor, the gate of the tenth thin film transistor is electrically connected to the third node, the drain is electrically connected to the fourth node, the source is electrically connected to the constant voltage low potential; and the resistor is One end of the resistor is electrically connected to a constant voltage high potential, and the other end is electrically connected to the fourth node.
  • the potential of the second node undergoes the same high and low potential transitions as the M+1th clock signal transitions between high and low potentials.
  • the source of the first thin film transistor is electrically connected to the circuit start signal.
  • the source of the third thin film transistor is electrically connected to the circuit start signal.
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal.
  • the M+2th and the M+3th clock signals are respectively the first clock signal and the second clock signal, when the clock When the signal is the fourth clock signal, the M+1, M+2, and M+3 clock signals are the first clock signal, the second clock signal, and the third clock signal, respectively.
  • the first clock signal and the circuit start signal are first supplied to the first thin film transistor in the first stage GOA unit; in the reverse scan, the third thin film transistor in the last stage GOA unit is first provided.
  • a clock signal and a circuit start signal are first supplied to the first thin film transistor in the first stage GOA unit; in the reverse scan, the third thin film transistor in the last stage GOA unit is first provided.
  • the present invention also provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each stage GOA unit comprising an output control module, an output module, a bootstrap capacitor, and a pull-down module;
  • n be a positive integer, in addition to the first and last stage GOA unit circuits, in the nth level GOA unit:
  • the output control module includes: a first thin film transistor, a gate of the first thin film transistor is electrically connected to the Mth clock signal, and a source is electrically connected to an output end of the upper n-1th GOA unit
  • the drain is electrically connected to the third node; the third thin film transistor, the gate of the third thin film transistor is electrically connected to the M+2 clock signal, the drain is electrically connected to the third node, and the source is electrically
  • the fifth thin film transistor is electrically connected to the constant voltage high potential, and the source is electrically connected to the third node.
  • the drain is electrically connected to the first node;
  • the output module includes: a second thin film transistor, a gate of the second thin film transistor is electrically connected to the first node, a source is electrically connected to the M+1th clock signal, and a drain is electrically connected to the drain Output
  • One end of the bootstrap capacitor is electrically connected to the first node, and the other end is electrically connected to the output end;
  • the pull-down module includes: a fourth thin film transistor, a gate of the fourth thin film transistor is electrically connected to the M+3 clock signal, a drain is electrically connected to the output end, and a source is electrically connected to the constant voltage a sixth thin film transistor, the gate of the sixth thin film transistor is electrically connected to the second node, the drain is electrically connected to the third node, the source is electrically connected to the constant voltage low potential; and the seventh thin film transistor is The gate of the seventh thin film transistor is electrically connected to the second node, the drain is electrically connected to the output end, the source is electrically connected to the constant voltage low potential, and the eighth thin film transistor is connected to the gate of the eighth thin film transistor.
  • the gate is electrically connected to the third node, the drain is electrically connected to the second node, the source is electrically connected to the constant voltage low potential; and the ninth thin film transistor is electrically connected to the fourth gate of the ninth thin film transistor a node, the source is electrically connected to the M+1th clock signal, the drain is electrically connected to the second node, and the tenth thin film transistor is electrically connected to the third node and the drain of the tenth thin film transistor Electrically connected to the fourth node, source electrical Connected to the constant potential down; and a resistor, one end of the resistor is electrically connected to a constant voltage of high potential, the other end is connected electrically to the fourth node;
  • the source of the first thin film transistor is electrically connected to the circuit start signal
  • the clock signal includes four clock signals: a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal;
  • the thin film transistors are all N-type low temperature polysilicon semiconductor thin film transistors.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, which uses a resistor and a tenth thin film transistor to replace the second capacitor in the prior art, and changes the second ninth thin film transistor in the prior art.
  • one end of the resistor is connected to the constant voltage high potential, and the other end is connected to the gate of the ninth thin film transistor, and the potential of the second node can be kept low at the output end, so that the potential of the second node follows the M+1th clock.
  • the signal jumps between high and low potentials and the same high and low potential jump occurs that is, the potential of the second node is pulled down according to a certain frequency, effectively avoiding the second node being at a high potential for a long time, preventing the sixth and the
  • the threshold voltage shift problem caused by the seventh thin film transistor working for a long time improves the stability of the GOA circuit.
  • FIG. 1 is a circuit diagram of a conventional GOA circuit based on an LTPS semiconductor thin film transistor
  • FIG. 2 is a forward scan timing diagram of a conventional LTPS semiconductor thin film transistor-based GOA circuit shown in FIG. 1;
  • FIG. 3 is a circuit diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 4 is a circuit diagram of a first stage GOA unit of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 5 is a circuit diagram of a final stage GOA unit of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention
  • FIG. 6 is a forward scan timing diagram of a GOA circuit based on an LTPS semiconductor thin film transistor of the present invention.
  • the present invention provides a GOA circuit based on an LTPS semiconductor thin film transistor, comprising: a plurality of cascaded GOA units, each stage of the GOA unit including an output control module 100, an output module 200, and a bootstrap capacitor C1. And a pull down module 400.
  • n be a positive integer, in addition to the first and last stage GOA unit circuits, in the nth level GOA unit:
  • the output control module 100 includes a first thin film transistor T1.
  • the gate of the first thin film transistor T1 is electrically connected to the Mth clock signal CK(M), and the source is electrically connected to the first n-th
  • the output terminal G(n-1) of the level-1 GOA unit is electrically connected to the third node K(n); the third thin film transistor T3 is electrically connected to the gate of the third thin film transistor T3.
  • the drain is electrically connected to the third node K(n), and the source is electrically connected to the output terminal G of the n+1th GOA unit of the next stage (n+1)
  • a fifth thin film transistor T5 the gate of the fifth thin film transistor T5 is electrically connected to the constant voltage high potential VGH, the source is electrically connected to the third node K(n), and the drain is electrically connected to the first a node Q(n);
  • the output module 200 includes: a second thin film transistor T2, the gate of the second thin film transistor T2 is electrically connected to the first node Q(n), and the source is electrically connected to the M+1th clock signal CK ( M+1), the drain is electrically connected to the output terminal G(n);
  • the bootstrap capacitor C1 is electrically connected to the first node Q(n), and the other end is electrically connected to the output terminal G(n);
  • the pull-down module 400 includes a fourth thin film transistor T4.
  • the gate of the fourth thin film transistor T4 is electrically connected to the M+3 clock signal CK(M+3), and the drain is electrically connected to the output terminal G. (n), the source is electrically connected to the constant voltage low potential VGL;
  • the sixth thin film transistor T6, the sixth thin The gate of the film transistor T6 is electrically connected to the second node P(n), the drain is electrically connected to the third node K(n), the source is electrically connected to the constant voltage low potential VGL, and the seventh thin film transistor T7 is The gate of the seventh thin film transistor T7 is electrically connected to the second node P(n), the drain is electrically connected to the output terminal G(n), and the source is electrically connected to the constant voltage low potential VGL;
  • the eighth film The transistor T8, the gate of the eighth thin film transistor T8 is electrically connected to the third node K(n), the drain is electrically connected to the second node P(n), and the source is electrically
  • a ninth thin film transistor T9 the gate of the ninth thin film transistor T9 is electrically connected to the fourth node S(n), and the source is electrically connected to the M+1th clock signal CK(M+1), and the drain The gate is electrically connected to the second node P(n); the tenth thin film transistor T10, the gate of the tenth thin film transistor T10 is electrically connected to the third node K(n), and the drain is electrically connected to the fourth node.
  • S (n) the source is electrically connected to the constant voltage low potential VGL; and the resistor R1, one end of the resistor R1 is electrically connected to the constant voltage high potential VGH, and the other end is electrically connected to the fourth node S(n) .
  • the source of the first thin film transistor T1 is electrically connected to the circuit start signal STV, and in the last stage GOA unit, the third thin film transistor T3. The source is electrically connected to the circuit start signal STV.
  • each of the thin film transistors is an N-type low temperature polysilicon semiconductor thin film transistor.
  • the GOA circuit based on the LTPS semiconductor thin film transistor includes four clock signals: a first clock signal CK(1), a second clock signal CK(2), and a third clock signal CK(3). ), and the fourth clock signal CK (4).
  • the Mth clock signal CK(M) is the third clock signal CK(3)
  • the M+2th and the M+3th clock signals CK(M+2), CK(M) +3) respectively a first clock signal CK(1) and a second clock signal CK(2)
  • the clock signal CK(M) is a fourth clock signal CK(4)
  • the M+ One, M+2, and M+3 clock signals CK(M+1), CK(M+2), and CK(M+3) are the first clock signal CK(1), respectively.
  • the GOA circuit based on the LTPS semiconductor thin film transistor of the present invention can perform forward scanning from the first stage to the last stage step by step, or can perform reverse scanning from the last stage to the first stage step by step.
  • the first clock signal CK(1) and the circuit start signal STV are first supplied to the first thin film transistor T1 in the first stage GOA unit; when the reverse scan is performed, the first stage is the first GOA.
  • the third thin film transistor T3 in the cell provides a first clock signal CK(1) and a circuit start signal STV.
  • the GOA circuit based on the LTPS semiconductor thin film transistor can pull down the potential of the second node (P(n)) at a certain frequency whether in forward scanning or reverse scanning.
  • the specific working process is:
  • Stage 1 Mth clock signal CK(M) and output stage G(n-1) of the n-1th stage GOA unit Both provide high potential, and the M+1, M+2, and M+3 clock signals CK(M+1), CK(M+2), and CK(M+3) all provide low potential, nth
  • the output terminal G(n+1) of the +1 level GOA unit also provides a low potential, the first thin film transistor T1 is turned on by the control of the Mth clock signal CK(M), and the fifth thin film transistor T5 is subjected to the constant voltage high potential VGH.
  • the control is always on, the potential of the third node K(n) and the first node Q(n) are always the same, the first node Q(n) is precharged to a high potential, and is controlled by the first node Q(n).
  • the tenth thin film transistors T8, T10 are turned on, the second and fourth nodes P(n), S(n) are pulled down to the constant voltage low potential VGH, and the sixth node controlled by the second node P(n), and
  • the seventh thin film transistors T6, T7 are turned off, and the ninth thin film transistor T9 controlled by the fourth node S(n) is turned off;
  • Phase 2 the Mth clock signal CK(M) and the output terminal G(n-1) of the n-1th stage GOA unit both transition to a low potential, and the M+1th clock signal CK(M+1) provides a high Potential, the M+2 clock signal CK(M+2), the M+3th clock signal CK(M+3), and the output stage G(n+1) of the n+1th GOA unit still provide a low potential
  • the first node Q(n) maintains a potential due to the storage action of the bootstrap capacitor C1, the second thin film transistor T2 is turned on, and the output terminal G(n) outputs a high potential of the M+1th clock signal CK(M+1).
  • the eighth and tenth thin film transistors T8, T10 are still open, and the second and fourth nodes P(n), S(n) are kept at a constant voltage
  • the low potential VGH, the sixth and seventh thin film transistors T6, T7 controlled by the second node P(n) are still turned off, and the ninth thin film transistor T9 controlled by the fourth node S(n) is still turned off;
  • Phase 3 the M+1th clock signal CK(M+1) transitions to a low potential, the M+2th clock signal CK(M+2) and the output end of the n+1th GOA unit G(n+1) Both provide a high potential, and the Mth clock signal CK(M), the M+3th clock signal CK(M+3), and the output terminal G(n-1) of the n-1th stage GOA unit still provide a low potential
  • the third thin film transistor T3 controlled by the M+2 clock signal CK(M+2) is turned on, the first node Q(n) is still at a high potential, and the second node is controlled by the first node Q(n). 8.
  • the tenth and tenth thin film transistors T2, T8, and T10 are still turned on, and the second and fourth nodes P(n) and S(n) still maintain a constant voltage low potential VGH, and are controlled by the second node P(n). 6.
  • the seventh thin film transistors T6 and T7 are still turned off, the ninth thin film transistor T9 controlled by the fourth node S(n) is still turned off, and the output terminal G(n) outputs the M+1th clock signal CK (M+1). Low potential;
  • stage 4 the Mth clock signal CK(M) is again supplied with a high potential, the M+2th clock signal CK(M+2) is turned to a low potential, and the M+1th clock signal CK(M+1),
  • the M+3 clock signal CK(M+3) and the output terminal G(n-1) of the n-1th stage GOA unit still provide a low potential, and the first thin film transistor T1 is controlled by the Mth clock signal CK(M). Turning on, pulling down the first node Q(n) to a low potential, and closing the second, eighth, and tenth thin film transistors T2, T8, and T10 controlled by the first node Q(n);
  • Stage 5 the fourth node S(n) is always at a high potential due to the partial pressure of the resistor R1, the ninth film The transistor T9 is always turned on, and the high and low potentials are alternately supplied with the M+1th clock signal CK(M+1).
  • the M+1th clock signal CK(M+1) is high, the second node P (n) will be charged to a high potential, and the sixth and seventh thin film transistors T6, T7 are turned on.
  • the M+1th clock signal is low, the second node P(n) is pulled low to a low potential.
  • the sixth and seventh thin film transistors T6 and T7 are turned off, and the first node Q(n) and the output terminal G(n) are kept at a low potential, that is, at a stage where the output terminal G(n) is kept at a low potential, the second The potential of the node P(n) undergoes the same high and low potential transitions as the M+1th clock signal CK(M+1) transitions between high and low potentials.
  • the second node P(n) maintains a high potential for a long time, and the sixth and seventh thin film transistors T6, T7 are always turned on within one frame time, in the LTPS thin film transistor-based GOA circuit of the present invention.
  • the second node P(n) is pulled down at a certain frequency, effectively avoiding the second node P(n) being at a high potential for a long time, preventing the sixth and seventh thin film transistors T6 and T7 from being operated for a long time.
  • the threshold voltage offset problem improves the stability of the GOA circuit.
  • the LTPS semiconductor thin film transistor-based GOA circuit of the present invention replaces the second capacitor in the prior art with a resistor and a tenth thin film transistor, and changes the diode connection of the ninth thin film transistor in the prior art.
  • One end of the resistor is connected to the constant voltage high potential, and the other end is connected to the gate of the ninth thin film transistor, and the potential of the second node can be kept low at the output end, so that the potential of the second node is high with the M+1 clock signal.

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Abstract

提供一种基于LTPS半导体薄膜晶体管的GOA电路，采用电阻(R1)与第十薄膜晶体管(T10)取代现有技术中的第二电容，将电阻(R1)的一端接恒压高电位(VGH)，另一端接第九薄膜晶体管(T9)的栅极，能够在输出端(G(n))保持低电位的阶段，使第二节点(P(n))的电位随着第M+1条时钟信号(CK(M+1))在高、低电位之间跳变而发生同样的高、低电位跳变，即按一定频率拉低第二节点(P(n))的电位，有效避免了第二节点(P(n))长时间处于高电位，防止因第六与第七薄膜晶体管(T6、T7)长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。

Description

基于LTPS半导体薄膜晶体管的GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种基于LTPS半导体薄膜晶体管的GOA电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
GOA技术(Gate Driver on Array)即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板((Integrated Circuit，IC)来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接(bonding)工序，有机会提升产能并降低产品成本，而且可以使液晶显示面板更适合制作窄边框或无边框的显示产品。
随着低温多晶硅(Low Temperature Poly-silicon，LTPS)半导体薄膜晶体管的发展，LTPS-TFT液晶显示器也越来越受关注，LTPS-TFT液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点。由于低温多晶硅较非晶硅(a-Si)的排列有次序，低温多晶硅半导体本身具有超高的电子迁移率，比非晶硅半导体相对高100倍以上，可以采用GOA技术将栅极驱动器制作在薄膜晶体管阵列基板上，达到系统整合的目标、节省空间及驱动IC的成本。
请参阅图1，现有的一种基于LTPS半导体薄膜晶体管的GOA电路，包括级联的多个GOA单元，设n为正整数，第n级GOA单元包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点K(n)；第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于输出端G(n)；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于第M+2条时钟信号CK(M+2)，漏极电性连接于第三节点K(n)，源极电性连接于下一级第n+1级GOA单元的输出端 G(n+1)；第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第M+3条时钟信号CK(M+3)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于恒压高电位VGH，源极电性连接于第三节点K(n)，漏极电性连接于第一节点Q(n)；第六薄膜晶体管T6，所述第六薄膜晶体管T6的栅极电性连接于第二节点P(n)，漏极电性连接于第三节点K(n)，源极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第三节点K(n)，漏极电性连接于第二节点P(n)，源极电性连接于恒压低电位VGL；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极与源极均电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于第二节点P(n)；第一电容C1，所述第一电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；第二电容C2，所述第二电容C2的一端电性连接于第二节点P(n)，另一端电性连接于恒压低电位VGL。
图1所示的GOA电路既可以正向扫描也可以反向扫描，正、反向扫描的工作过程类似。请结合图1与图2，以正向扫描为例，在正向扫描时，其工作过程为：首先，第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)均提供高电位，第一、及第五薄膜晶体管T1、T5打开，第一节点Q(n)被预充电至高电位；然后，第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)变为低电位，第M+1条时钟信号CK(M+1)提供高电位，第一节点Q(n)因第一电容C1的存储作用保持高电位，第二薄膜晶体管T2打开，输出端G(n)输出第M+1条时钟信号CK(M+1)的高电位，并使得第一节点Q(n)被抬升至更高的电位，同时第八薄膜晶体管T8打开，第二节点P(n)被拉低至恒压低电位VGL，第六、及第七薄膜晶体管T6、T7关闭；接下来，第M+2条时钟信号CK(M+2)与第n+1级GOA单元的输出端G(n+1)均提供高电位，第一节点Q(n)仍为高电位，第M+1条时钟信号CK(M+1)降低为低电位，输出端G(n)输出第M+1条时钟信号CK(M+1)的低电位；再接下来，第M条时钟信号CK(M)再次提供高电位，第n-1级GOA单元的输出端G(n-1)保持低电位，第一薄膜晶体管T1打开拉低第一节点Q(n)至低电位，第八薄膜晶体管T8关闭；随后，第M+1条时钟信号CK(M+1)提供高电位，第九薄膜晶体管T9打开，第二节点P(n)被充电至高电位，第六、及第七薄膜晶体管T6、T7打开，分别继续拉低第一节点Q(n)与输出端G(n)至恒压低电位VGL，在第二电容C2的存储作用下，第二节点P(n)持续保 持高电位，第六、及第七薄膜晶体管T6、T7在一帧时间内一直打开，保持第一节点Q(n)与输出端G(n)的低电位。
在上述现有的基于LTPS半导体薄膜晶体管的GOA电路中，由于第六、及第七薄膜晶体管T6、T7长时间工作，会造成第六、及第七薄膜晶体管T6、T7的阈值电压发生偏移(Vth Shift)，造成电路的稳定能力下降，从而引起GOA电路输出异常。
发明内容
本发明的目的在于提供一种基于LTPS半导体薄膜晶体管的GOA电路，能够以一定频率拉低第二节点的电位，防止第六与第七薄膜晶体管长时间工作，提升GOA电路的稳定性。
为实现上述目的，本发明提供了一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括输出控制模块、输出模块、自举电容、及下拉模块；
设n为正整数，除第一级与最后一级GOA单元电路以外，在第n级GOA单元中：
所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第M+2条时钟信号，漏极电性连接于第三节点，源极电性连接于下一级第n+1级GOA单元的输出端；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；
所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于输出端；
所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+3条时钟信号，漏极电性连接于输出端，源极电性连接于恒压低电位；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管T7的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第二节点，源极电 性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第M+1条时钟信号，漏极电性连接于第二节点；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第四节点，源极电性连接于恒压低电位；以及电阻，所述电阻的一端电性连接于恒压高电位，另一端电性连接于第四节点。
在输出端保持低电位的阶段，所述第二节点的电位随着第M+1条时钟信号在高、低电位之间跳变而发生同样的高、低电位跳变。
在第一级GOA单元中，第一薄膜晶体管的源极电性连接于电路起始信号。
在最后一级GOA单元中，第三薄膜晶体管的源极电性连接于电路起始信号。
所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号。
当所述第M条时钟信号为第三条时钟信号时，所述第M+2条、及第M+3条时钟信号分别为第一条时钟信号和第二条时钟信号，当所述时钟信号为第四时钟信号时，所述第M+1条、第M+2条、及第M+3条时钟信号分别为第一条时钟信号、第二条时钟信号、及第三条时钟信号。
正向扫描时，首先向第一级GOA单元中的第一薄膜晶体管提供第一条时钟信号和电路起始信号；反向扫描时，首先向最后一级GOA单元中的第三薄膜晶体管提供第一条时钟信号和电路起始信号。
本发明还提供一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括输出控制模块、输出模块、自举电容、及下拉模块；
设n为正整数，除第一级与最后一级GOA单元电路以外，在第n级GOA单元中：
所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第M+2条时钟信号，漏极电性连接于第三节点，源极电性连接于下一级第n+1级GOA单元的输出端；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；
所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于 输出端；
所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+3条时钟信号，漏极电性连接于输出端，源极电性连接于恒压低电位；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第M+1条时钟信号，漏极电性连接于第二节点；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第四节点，源极电性连接于恒压低电位；以及电阻，所述电阻的一端电性连接于恒压高电位，另一端电性连接于第四节点；
其中，在第一级GOA单元中，第一薄膜晶体管的源极电性连接于电路起始信号；
其中，所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号；
其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
本发明的有益效果：本发明提供的一种基于LTPS半导体薄膜晶体管的GOA电路，采用电阻与第十薄膜晶体管取代现有技术中的第二电容，并改变现有技术中第九薄膜晶体管的二极体接法，将电阻的一端接恒压高电位，另一端接第九薄膜晶体管的栅极，能够在输出端保持低电位的阶段，使第二节点的电位随着第M+1条时钟信号在高、低电位之间跳变而发生同样的高、低电位跳变，即按一定频率拉低第二节点的电位，有效避免了第二节点长时间处于高电位，防止因第六与第七薄膜晶体管长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的基于LTPS半导体薄膜晶体管的GOA电路的电路图；
图2为图1所示现有的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图；
图3为本发明的基于LTPS半导体薄膜晶体管的GOA电路的电路图；
图4为本发明的基于LTPS半导体薄膜晶体管的GOA电路第一级GOA单元的电路图；
图5为本发明的基于LTPS半导体薄膜晶体管的GOA电路最后一级GOA单元的电路图；
图6为本发明的基于LTPS半导体薄膜晶体管的GOA电路的正向扫描时序图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括输出控制模块100、输出模块200、自举电容C1、及下拉模块400。
设n为正整数，除第一级与最后一级GOA单元电路以外，在第n级GOA单元中：
所述输出控制模块100包括：第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极电性连接于第M条时钟信号CK(M)，源极电性连接于上一级第n-1级GOA单元的输出端G(n-1)，漏极电性连接于第三节点K(n)；第三薄膜晶体管T3，所述第三薄膜晶体管T3的栅极电性连接于第M+2条时钟信号CK(M+2)，漏极电性连接于第三节点K(n)，源极电性连接于下一级第n+1级GOA单元的输出端G(n+1)；以及第五薄膜晶体管T5，所述第五薄膜晶体管T5的栅极电性连接于恒压高电位VGH，源极电性连接于第三节点K(n)，漏极电性连接于第一节点Q(n)；
所述输出模块200包括：第二薄膜晶体管T2，所述第二薄膜晶体管T2的栅极电性连接于第一节点Q(n)，源极电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于输出端G(n)；
所述自举电容C1的一端电性连接于第一节点Q(n)，另一端电性连接于输出端G(n)；
所述下拉模块400包括：第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极电性连接于第M+3条时钟信号CK(M+3)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第六薄膜晶体管T6，所述第六薄 膜晶体管T6的栅极电性连接于第二节点P(n)，漏极电性连接于第三节点K(n)，源极电性连接于恒压低电位VGL；第七薄膜晶体管T7，所述第七薄膜晶体管T7的栅极电性连接于第二节点P(n)，漏极电性连接于输出端G(n)，源极电性连接于恒压低电位VGL；第八薄膜晶体管T8，所述第八薄膜晶体管T8的栅极电性连接于第三节点K(n)，漏极电性连接于第二节点P(n)，源极电性连接于恒压低电位VGL；第九薄膜晶体管T9，所述第九薄膜晶体管T9的栅极电性连接于第四节点S(n)，源极电性连接于第M+1条时钟信号CK(M+1)，漏极电性连接于第二节点P(n)；第十薄膜晶体管T10，所述第十薄膜晶体管T10的栅极电性连接于第三节点K(n)，漏极电性连接于第四节点S(n)，源极电性连接于恒压低电位VGL；以及电阻R1，所述电阻R1的一端电性连接于恒压高电位VGH，另一端电性连接于第四节点S(n)。
特别地，请参阅图4和图5，在第一级GOA单元中，第一薄膜晶体管T1的源极电性连接于电路起始信号STV，在最后一级GOA单元中，第三薄膜晶体管T3的源极电性连接于电路起始信号STV。
具体地，所述各个薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
结合图3与图6，所述基于LTPS半导体薄膜晶体管的GOA电路包括四条时钟信号：第一条时钟信号CK(1)、第二条时钟信号CK(2)、第三条时钟信号CK(3)、及第四条时钟信号CK(4)。当所述第M条时钟信号CK(M)为第三条时钟信号CK(3)时，所述第M+2条、及第M+3条时钟信号CK(M+2)、CK(M+3)分别为第一条时钟信号CK(1)和第二条时钟信号CK(2)；当所述时钟信号CK(M)为第四时钟信号CK(4)时，所述第M+1条、第M+2条、及第M+3条时钟信号CK(M+1)、CK(M+2)、CK(M+3)分别为第一条时钟信号CK(1)、第二条时钟信号CK(2)、及第三条时钟信号CK(3)。
本发明的基于LTPS半导体薄膜晶体管的GOA电路既可以从第一级向最后一级逐级进行正向扫描，也可以从最后一级向第一级逐级进行反向扫描。其中，在正向扫描时，首先向第一级GOA单元中的第一薄膜晶体管T1提供第一条时钟信号CK(1)和电路起始信号STV；反向扫描时，首先向最后一级GOA单元中的第三薄膜晶体管T3提供第一条时钟信号CK(1)和电路起始信号STV。
需要说明的是，该基于LTPS半导体薄膜晶体管的GOA电路无论是在正向扫描时，还是反向扫描时均能够按一定频率拉低所述第二节点(P(n))的电位，以正向扫描为例，具体的工作过程为：
阶段1、第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1) 均提供高电位，第M+1、第M+2、及第M+3条时钟信号CK(M+1)、CK(M+2)、CK(M+3)均提供低电位，第n+1级GOA单元的输出端G(n+1)也提供低电位，第一薄膜晶体管T1受第M条时钟信号CK(M)的控制打开，第五薄膜晶体管T5受恒压高电位VGH的控制始终打开，第三节点K(n)与第一节点Q(n)的电位始终相同，第一节点Q(n)被预充电至高电位，受第一节点Q(n)控制的第八、及第十薄膜晶体管T8、T10打开，第二、及第四节点P(n)、S(n)被拉低至恒压低电位VGH，受第二节点P(n)控制的第六、及第七薄膜晶体管T6、T7关闭，受第四节点S(n)控制的第九薄膜晶体管T9关闭；
阶段2、第M条时钟信号CK(M)与第n-1级GOA单元的输出端G(n-1)均转变为低电位，第M+1条时钟信号CK(M+1)提供高电位，第M+2条时钟信号CK(M+2)、第M+3条时钟信号CK(M+3)和第n+1级GOA单元的输出端G(n+1)仍提供低电位，第一节点Q(n)因自举电容C1的存储作用保持电位，第二薄膜晶体管T2打开，输出端G(n)输出第M+1条时钟信号CK(M+1)的高电位，并使得第一节点Q(n)被抬升至更高的电位，第八、及第十薄膜晶体管T8、T10仍打开，第二、及第四节点P(n)、S(n)保持恒压低电位VGH，受第二节点P(n)控制的第六、及第七薄膜晶体管T6、T7仍关闭，受第四节点S(n)控制的第九薄膜晶体管T9仍关闭；
阶段3、第M+1条时钟信号CK(M+1)转变为低电位，第M+2条时钟信号CK(M+2)与第n+1级GOA单元的输出端G(n+1)均提供高电位，第M条时钟信号CK(M)、第M+3条时钟信号CK(M+3)及第n-1级GOA单元的输出端G(n-1)仍提供低电位，受第M+2条时钟信号CK(M+2)控制的第三薄膜晶体管T3打开，第一节点Q(n)仍为高电位，受第一节点Q(n)控制的第二、第八、及第十薄膜晶体管T2、T8、T10仍打开，第二、及第四节点P(n)、S(n)仍保持恒压低电位VGH，受第二节点P(n)控制的第六、及第七薄膜晶体管T6、T7仍关闭，受第四节点S(n)控制的第九薄膜晶体管T9仍关闭，输出端G(n)输出第M+1条时钟信号CK(M+1)的低电位；
阶段4，第M条时钟信号CK(M)再次提供高电位，第M+2条时钟信号CK(M+2)转变为低电位，第M+1条时钟信号CK(M+1)、第M+3条时钟信号CK(M+3)和第n-1级GOA单元的输出端G(n-1)仍提供低电位，受第M条时钟信号CK(M)控制第一薄膜晶体管T1打开，拉低第一节点Q(n)至低电位，受第一节点Q(n)控制的第二、第八、及第十薄膜晶体管T2、T8、T10关闭；
阶段5、第四节点S(n)由于电阻R1的分压始终处于高电位，第九薄膜 晶体管T9始终打开，随着第M+1条时钟信号CK(M+1)交替提供高、低电位，当第M+1条时钟信号CK(M+1)为高电位时，第二节点P(n)会被充电到高电位，第六、及第七薄膜晶体管T6、T7打开，当第M+1条时钟信号为低电位时，第二节点P(n)会被拉低到低电位，第六、及第七薄膜晶体管T6、T7关闭，第一节点Q(n)及输出端G(n)保持低电位，即在输出端G(n)保持低电位的阶段，所述第二节点P(n)的电位随着第M+1条时钟信号CK(M+1)在高、低电位之间跳变而发生同样的高、低电位跳变。
相比于现有技术中第二节点P(n)长时间保持高电位，第六、及第七薄膜晶体管T6、T7在一帧时间内一直打开，在本发明的基于LTPS薄膜晶体管的GOA电路在阶段5中第二节点P(n)按一定频率被拉低，有效避免了第二节点P(n)长时间处于高电位，防止因第六与第七薄膜晶体管T6、T7长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
综上所述，本发明的基于LTPS半导体薄膜晶体管的GOA电路，采用电阻与第十薄膜晶体管取代现有技术中的第二电容，并改变现有技术中第九薄膜晶体管的二极体接法，将电阻的一端接恒压高电位，另一端接第九薄膜晶体管的栅极，能够在输出端保持低电位的阶段，使第二节点的电位随着第M+1条时钟信号在高、低电位之间跳变而发生同样的高、低电位跳变，即按一定频率拉低第二节点的电位，有效避免了第二节点长时间处于高电位，防止因第六与第七薄膜晶体管长时间工作引起的阈值电压偏移问题，提升GOA电路的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括输出控制模块、输出模块、自举电容、及下拉模块；
    设n为正整数，除第一级与最后一级GOA单元电路以外，在第n级GOA单元中：
    所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第M+2条时钟信号，漏极电性连接于第三节点，源极电性连接于下一级第n+1级GOA单元的输出端；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于输出端；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+3条时钟信号，漏极电性连接于输出端，源极电性连接于恒压低电位；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第M+1条时钟信号，漏极电性连接于第二节点；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第四节点，源极电性连接于恒压低电位；以及电阻，所述电阻的一端电性连接于恒压高电位，另一端电性连接于第四节点。
  2. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在输出端保持低电位的阶段，所述第二节点的电位随着第M+1条时钟信号在高、低电位之间跳变而发生同样的高、低电位跳变。
  3. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在第一级GOA单元中，第一薄膜晶体管的源极电性连接于电路起始信号。
  4. 如权利要求3所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在最后一级GOA单元中，第三薄膜晶体管的源极电性连接于电路起始信号。
  5. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号。
  6. 如权利要求5所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，当所述第M条时钟信号为第三条时钟信号时，所述第M+2条、及第M+3条时钟信号分别为第一条时钟信号和第二条时钟信号，当所述时钟信号为第四时钟信号时，所述第M+1条、第M+2条、及第M+3条时钟信号分别为第一条时钟信号、第二条时钟信号、及第三条时钟信号。
  7. 如权利要求4所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，正向扫描时，首先向第一级GOA单元中的第一薄膜晶体管提供第一条时钟信号和电路起始信号；反向扫描时，首先向最后一级GOA单元中的第三薄膜晶体管提供第一条时钟信号和电路起始信号。
  8. 如权利要求1所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
  9. 一种基于LTPS半导体薄膜晶体管的GOA电路，包括：级联的多个GOA单元，每一级GOA单元均包括输出控制模块、输出模块、自举电容、及下拉模块；
    设n为正整数，除第一级与最后一级GOA单元电路以外，在第n级GOA单元中：
    所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的栅极电性连接于第M条时钟信号，源极电性连接于上一级第n-1级GOA单元的输出端，漏极电性连接于第三节点；第三薄膜晶体管，所述第三薄膜晶体管的栅极电性连接于第M+2条时钟信号，漏极电性连接于第三节点，源极电性连接于下一级第n+1级GOA单元的输出端；以及第五薄膜晶体管，所述第五薄膜晶体管的栅极电性连接于恒压高电位，源极电性连接于第三节点，漏极电性连接于第一节点；
    所述输出模块包括：第二薄膜晶体管，所述第二薄膜晶体管的栅极电性连接于第一节点，源极电性连接于第M+1条时钟信号，漏极电性连接于 输出端；
    所述自举电容的一端电性连接于第一节点，另一端电性连接于输出端；
    所述下拉模块包括：第四薄膜晶体管，所述第四薄膜晶体管的栅极电性连接于第M+3条时钟信号，漏极电性连接于输出端，源极电性连接于恒压低电位；第六薄膜晶体管，所述第六薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于第三节点，源极电性连接于恒压低电位；第七薄膜晶体管，所述第七薄膜晶体管的栅极电性连接于第二节点，漏极电性连接于输出端，源极电性连接于恒压低电位；第八薄膜晶体管，所述第八薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第二节点，源极电性连接于恒压低电位；第九薄膜晶体管，所述第九薄膜晶体管的栅极电性连接于第四节点，源极电性连接于第M+1条时钟信号，漏极电性连接于第二节点；第十薄膜晶体管，所述第十薄膜晶体管的栅极电性连接于第三节点，漏极电性连接于第四节点，源极电性连接于恒压低电位；以及电阻，所述电阻的一端电性连接于恒压高电位，另一端电性连接于第四节点；
    其中，在第一级GOA单元中，第一薄膜晶体管的源极电性连接于电路起始信号；
    其中，所述时钟信号包括四条时钟信号：第一条时钟信号、第二条时钟信号、第三条时钟信号、及第四条时钟信号；
    其中，所述薄膜晶体管均为N型低温多晶硅半导体薄膜晶体管。
  10. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在输出端保持低电位的阶段，所述第二节点的电位随着第M+1条时钟信号在高、低电位之间跳变而发生同样的高、低电位跳变。
  11. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，在最后一级GOA单元中，第三薄膜晶体管的源极电性连接于电路起始信号。
  12. 如权利要求9所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，当所述第M条时钟信号为第三条时钟信号时，所述第M+2条、及第M+3条时钟信号分别为第一条时钟信号和第二条时钟信号，当所述时钟信号为第四时钟信号时，所述第M+1条、第M+2条、及第M+3条时钟信号分别为第一条时钟信号、第二条时钟信号、及第三条时钟信号。
  13. 如权利要求11所述的基于LTPS半导体薄膜晶体管的GOA电路，其中，正向扫描时，首先向第一级GOA单元中的第一薄膜晶体管提供第一条时钟信号和电路起始信号；反向扫描时，首先向最后一级GOA单元中的第三薄膜晶体管提供第一条时钟信号和电路起始信号。
PCT/CN2016/072427 2015-12-22 2016-01-28 基于ltps半导体薄膜晶体管的goa电路 Ceased WO2017107286A1 (zh)

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