WO2017081727A1 - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

Info

Publication number
WO2017081727A1
WO2017081727A1 PCT/JP2015/081495 JP2015081495W WO2017081727A1 WO 2017081727 A1 WO2017081727 A1 WO 2017081727A1 JP 2015081495 W JP2015081495 W JP 2015081495W WO 2017081727 A1 WO2017081727 A1 WO 2017081727A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
semiconductor layer
gate electrode
hole
forming
Prior art date
Application number
PCT/JP2015/081495
Other languages
English (en)
French (fr)
Inventor
舛岡　富士雄
広記 中村
原田　望
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
舛岡　富士雄
広記 中村
原田　望
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド, 舛岡　富士雄, 広記 中村, 原田　望 filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to PCT/JP2015/081495 priority Critical patent/WO2017081727A1/ja
Priority to JP2016573138A priority patent/JP6294511B2/ja
Publication of WO2017081727A1 publication Critical patent/WO2017081727A1/ja
Priority to US15/849,026 priority patent/US10453941B2/en
Priority to US16/520,892 priority patent/US10483376B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate

Definitions

  • the present invention relates to a semiconductor device.
  • SGT Surrounding Gate Transistor
  • a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate, and the gate surrounds a columnar semiconductor layer (for example, Patent Document 1, Patent Document 2, Patent Document 3).
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2015-188115 A
  • an object of the present invention is to provide a method of manufacturing a semiconductor device in which a columnar semiconductor layer is formed after forming a gate electrode, or a semiconductor device as a result.
  • a first insulating film and a second insulating film are deposited on a planar semiconductor layer formed on a substrate, and a gate electrode is formed on the second insulating film.
  • the first hole is formed, and the gate electrode is formed by embedding the first metal in the first hole, and a third insulating film is formed on the upper surface of the gate electrode and on the side surface of the first hole.
  • a second hole is formed in the gate electrode and the first insulating film by etching using the side wall made of the third insulating film as a mask.
  • a gate insulating film is formed on a side surface, and a first pillar-shaped semiconductor layer is formed by epitaxially growing a semiconductor layer from the planar semiconductor layer in the second hole.
  • the semiconductor device includes a planar semiconductor layer formed on a substrate, a first columnar semiconductor layer formed on the planar semiconductor layer, and a gate insulation surrounding the first columnar semiconductor layer. And a gate electrode surrounding the gate insulating film, and a first insulating film between the gate electrode and the planar semiconductor layer and surrounding the gate insulating film.
  • the present invention it is possible to provide a method for manufacturing a semiconductor device in which a columnar semiconductor layer is formed after forming a gate electrode, or a semiconductor device as a result.
  • first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate forming a first hole for forming a gate electrode in the second insulating film;
  • the gate electrode is formed by embedding a first metal in the first hole, a sidewall made of a third insulating film is formed on the upper surface of the gate electrode and on the side surface of the first hole, and the third electrode
  • a second hole is formed in the gate electrode and the first insulating film by etching using a sidewall made of the insulating film as a mask, a gate insulating film is formed on a side surface of the second hole, and
  • the gate electrode made of metal is covered with the first insulating film, the third insulating film, and the gate insulating film before the first columnar semiconductor layer is epitaxially grown. Metal contamination can be reduced.
  • the gate electrode Since the first insulating film under the gate electrode surrounds the gate insulating film by the structure of the first insulating film between the gate electrode and the planar semiconductor layer and surrounding the gate insulating film, the gate The insulation between the gate electrode and the first columnar semiconductor layer can be ensured at the lower end of the electrode.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
  • FIG. 2A is a plan view of a semiconductor device according to the present invention.
  • FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
  • the semiconductor layer of this embodiment is preferably a silicon layer.
  • the semiconductor layer may be a group IV semiconductor such as Ge or C.
  • the semiconductor layer may be a group III and group IV compound semiconductor.
  • a first insulating film 102 and a second insulating film 103 are deposited on a planar semiconductor layer 101 formed on a substrate 100, and a gate electrode is formed on the second insulating film 103.
  • a resist 104 for forming a first hole for forming the first hole is formed.
  • the resist 104 may be a pattern of a first hole for forming a gate electrode and a gate wiring.
  • the width of the gate wiring is preferably not more than twice the width of the sidewall of the third insulating film later. Further, the diameter of the gate electrode is preferably at least twice the width of the sidewall of the third insulating film later.
  • the first insulating film 102 is preferably a nitride film.
  • the first insulating film may be an oxide film.
  • the second insulating film is preferably an oxide film.
  • a diffusion layer may be formed on the planar semiconductor layer 101. Further, the element isolation insulating film 099 may surround the planar semiconductor layer 101.
  • a first hole 105 for forming a gate electrode is formed in the second insulating film 103.
  • the resist 104 is removed.
  • a first metal 106 is deposited in the first hole 105.
  • the first metal 106 is preferably a metal used for a semiconductor gate.
  • the first metal 106 is preferably titanium nitride or aluminum titanium nitride.
  • the first metal 106 is embedded in the first hole 105, and the gate electrode 106a is formed.
  • the gate wiring 106b may be formed at the same time.
  • a third insulating film 107 is deposited on the upper surface of the gate electrode 106 a and the side surface of the first hole 105.
  • the third insulating film 107 is etched to remain in a sidewall shape, and a sidewall made of the third insulating film 107 is formed on the upper surface of the gate electrode 106a and the side surface of the first hole 105. To do.
  • the second hole 108 is formed in the gate electrode 106a and the first insulating film 102 by etching using the sidewall made of the third insulating film 107 as a mask.
  • a gate insulating film 109 is deposited.
  • the gate insulating film is preferably a high dielectric film.
  • the gate insulating film preferably includes any one of an oxide film, a nitride film, and a high dielectric film.
  • the gate insulating film 109 is etched to form the gate insulating film 109 on the side surface of the second hole 108.
  • the gate electrode 106 a and the gate wiring 106 b made of the first metal 106 are covered with the first insulating film 102, the third insulating film 107, and the gate insulating film 109. Therefore, metal contamination on the first columnar semiconductor layer can be reduced.
  • the first columnar semiconductor layer 110 is formed by epitaxially growing a semiconductor layer from the planar semiconductor layer 101 in the second hole 108.
  • the columnar semiconductor layer can be formed after the gate electrode is formed. Thereafter, a diffusion layer may be formed on the first columnar semiconductor layer.
  • FIG. 11 shows the structure of a semiconductor device according to an embodiment of the present invention.
  • the first insulating film 102 under the gate electrode 106 a has the gate insulating film 109. Since the structure surrounds the gate electrode 106a, the insulation between the gate electrode 106a and the first columnar semiconductor layer 110 can be ensured at the lower end of the gate electrode 106a.
  • the gate wiring 106b may be connected to the gate electrode 106a. Further, the element isolation insulating film 099 may surround the planar semiconductor layer 101.
  • a semiconductor device in which p-type (including p + -type) and n-type (including n + -type) are opposite in conductivity type is naturally included in the technical scope of the present invention. It is.
  • Element isolation insulating film 100 Substrate 101. Planar semiconductor layer 102. First insulating film 103. Second insulating film 104. Resist 105. First hole 106. First metal 106a. Gate electrode 106b. Gate wiring 107. Third insulating film 108. Second hole 109. Gate insulating film 110. First columnar semiconductor layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

ゲート電極を形成後、柱状半導体層を形成する半導体装置の製造方法もしくは、その結果としての半導体装置を提供することを目的とする。　基板上に形成された平面状半導体層上に第１の絶縁膜と第２の絶縁膜を堆積し、前記第２の絶縁膜にゲート電極を形成するための第１の孔を形成し、前記第１の孔に第１の金属を埋め込むことにより前記ゲート電極を形成し、前記ゲート電極の上面且つ前記第１の孔の側面に第３の絶縁膜からなるサイドウォールを形成し、前記第３の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより前記ゲート電極と前記第１の絶縁膜に第２の孔を形成し、前記第２の孔の側面にゲート絶縁膜を形成し、前記第２の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第１の柱状半導体層を形成することを特徴とすることにより上記課題を解決する。

Description

半導体装置の製造方法及び半導体装置
　本発明は半導体装置に関する。
　半導体集積回路、なかでもＭＯＳトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているＭＯＳトランジスタはナノ領域まで微細化が進んでいる。ＭＯＳトランジスタの微細化が進むと、リーク電流の抑制が困難であり、必要な電流量確保の要請から回路の占有面積をなかなか小さくできない、といった問題があった。この様な問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲートが柱状半導体層を取り囲む構造のＳｕｒｒｏｕｎｄｉｎｇ Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒ（ＳＧＴ）が提案された（例えば、特許文献１、特許文献２、特許文献３）。
　柱状半導体層形成後に、ゲート電極を形成することが提案されている。（例えば、特許文献４）。しかしながら、柱状半導体層が細くなったとき、柱状半導体層を立てることができるか不明である。
特開平２－７１５５６号公報 特開平２－１８８９６６号公報 特開平３－１４５７６１号公報 特開２０１５－１８８１１５号公報
　そこで、本発明は、ゲート電極を形成後、柱状半導体層を形成する半導体装置の製造方法もしくは、その結果としての半導体装置を提供することを目的とする。
　本発明の半導体装置の製造方法は、基板上に形成された平面状半導体層上に第１の絶縁膜と第２の絶縁膜を堆積し、前記第２の絶縁膜にゲート電極を形成するための第１の孔を形成し、前記第１の孔に第１の金属を埋め込むことにより前記ゲート電極を形成し、前記ゲート電極の上面且つ前記第１の孔の側面に第３の絶縁膜からなるサイドウォールを形成し、前記第３の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより前記ゲート電極と前記第１の絶縁膜に第２の孔を形成し、前記第２の孔の側面にゲート絶縁膜を形成し、前記第２の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第１の柱状半導体層を形成することを特徴とする。
　また、本発明の半導体装置は、基板上に形成された平面状半導体層と、前記平面状半導体層上に形成された第１の柱状半導体層と、前記第１の柱状半導体層を取り囲むゲート絶縁膜と、前記ゲート絶縁膜を取り囲むゲート電極と、前記ゲート電極と前記平面状半導体層との間にあって前記ゲート絶縁膜を取り囲む第１の絶縁膜と、を有することを特徴とする。
　本発明によれば、ゲート電極を形成後、柱状半導体層を形成する半導体装置の製造方法もしくは、その結果としての半導体装置を提供することができる。
　基板上に形成された平面状半導体層上に第１の絶縁膜と第２の絶縁膜を堆積し、前記第２の絶縁膜にゲート電極を形成するための第１の孔を形成し、前記第１の孔に第１の金属を埋め込むことにより前記ゲート電極を形成し、前記ゲート電極の上面且つ前記第１の孔の側面に第３の絶縁膜からなるサイドウォールを形成し、前記第３の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより前記ゲート電極と前記第１の絶縁膜に第２の孔を形成し、前記第２の孔の側面にゲート絶縁膜を形成し、前記第２の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第１の柱状半導体層を形成することを特徴とすることにより、ゲート電極を形成後、柱状半導体層を形成することができる。
　また、第１の柱状半導体層をエピタキシャル成長させる前に、金属からなるゲート電極は、第１の絶縁膜と第３の絶縁膜とゲート絶縁膜により覆われているため、第１の柱状半導体層に対する金属汚染を低減することができる。
　前記ゲート電極と前記平面状半導体層との間にあって前記ゲート絶縁膜を取り囲む第１の絶縁膜との構造により、ゲート電極下の第１の絶縁膜がゲート絶縁膜を取り囲む構造であるため、ゲート電極下端においてゲート電極と第１の柱状半導体層との絶縁を確かなものとすることができる。
（Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の製造方法の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。 （Ａ）は本発明に係る半導体装置の平面図である。（Ｂ）は（Ａ）のＸ－Ｘ’面での断面図である。
　以下、本発明の実施形態に係る半導体装置の製造方法を、図１～図１１を参照しながら説明する。本実施例の半導体層は、シリコン層であることが好ましい。また、半導体層は、Ｇｅ、ＣといったＩＶ族の半導体としてもよい。また、半導体層はＩＩＩ族とＩＶ族の化合物半導体としてもよい。
　図１に示すように、基板１００上に形成された平面状半導体層１０１上に第１の絶縁膜１０２と第２の絶縁膜１０３を堆積し、第２の絶縁膜１０３上にゲート電極を形成するための第１の孔を形成するためのレジスト１０４を形成する。このとき、レジスト１０４を、ゲート電極とゲート配線を形成するための第１の孔のパターンとしてもよい。ゲート電極とゲート配線を形成するための第１の孔のパターンとするとき、ゲート配線幅は、後の第３の絶縁膜のサイドウォールの幅の二倍以下とすることが好ましい。また、ゲート電極の直径は、後の第３の絶縁膜のサイドウォールの幅の二倍以上とすることが好ましい。また、第１の絶縁膜１０２は窒化膜が好ましい。また、第１の絶縁膜は酸化膜としてもよい。また、第２の絶縁膜は酸化膜であることが好ましい。また、平面状半導体層１０１上部に拡散層を形成しておいてもよい。また、平面状半導体層１０１の周囲を素子分離絶縁膜０９９が取り囲んでいてもよい。
　図２に示すように、第２の絶縁膜１０３にゲート電極を形成するための第１の孔１０５を形成する。
　図３に示すように、レジスト１０４を除去する。
　図４に示すように、第１の孔１０５に第１の金属１０６を堆積する。第１の金属１０６は半導体のゲートに使用される金属であることが好ましい。第１の金属１０６は、窒化チタン、窒化アルミチタンであることが好ましい。
　図５に示すように、第１の金属１０６をエッチバックすることにより、第１の孔１０５に第１の金属１０６が埋め込まれ、ゲート電極１０６ａが形成される。ゲート配線１０６ｂが同時に形成されてもよい。
　図６に示すように、ゲート電極１０６ａの上面且つ第１の孔１０５の側面に第３の絶縁膜１０７を堆積する。
　図７に示すように、第３の絶縁膜１０７をエッチングし、サイドウォール状に残存させゲート電極１０６ａの上面且つ第１の孔１０５の側面に、第３の絶縁膜１０７からなるサイドウォールを形成する。
　図８に示すように、第３の絶縁膜１０７からなるサイドウォールをマスクとしてエッチングをすることによりゲート電極１０６ａと第１の絶縁膜１０２に第２の孔１０８を形成する。
　図９に示すように、ゲート絶縁膜１０９を堆積する。ゲート絶縁膜は、高誘電体膜であることが好ましい。また、ゲート絶縁膜は、酸化膜、窒化膜、高誘電体膜のいずれか一つを含むことが好ましい。
　図１０に示すように、ゲート絶縁膜１０９をエッチングし、第２の孔１０８の側面にゲート絶縁膜１０９を形成する。第１の柱状半導体層をエピタキシャル成長させる前に、第１の金属１０６からなるゲート電極１０６ａとゲート配線１０６ｂは、第１の絶縁膜１０２と第３の絶縁膜１０７とゲート絶縁膜１０９により覆われているため、第１の柱状半導体層に対する金属汚染を低減することができる。
　図１１に示すように、第２の孔１０８に平面状半導体層１０１から半導体層をエピタキシャル成長させることにより第１の柱状半導体層１１０を形成する。以上により、ゲート電極を形成後、柱状半導体層を形成することができる。この後、第１の柱状半導体層上部に拡散層を形成してもよい。
　本発明の実施形態に係る半導体装置の構造を図１１に示す。
　基板１００上に形成された平面状半導体層１０１と、前記平面状半導体層１０１上に形成された第１の柱状半導体層１１０と、前記第１の柱状半導体層１１０を取り囲むゲート絶縁膜１０９と、前記ゲート絶縁膜１０９を取り囲むゲート電極１０６ａと、前記ゲート電極１０６ａと前記平面状半導体層１０１との間にあって前記ゲート絶縁膜１０９を取り囲む第１の絶縁膜１０２と、を有する。
　前記ゲート電極１０６ａと前記平面状半導体層１０１との間にあって前記ゲート絶縁膜１０９を取り囲む第１の絶縁膜１０２との構造により、ゲート電極１０６ａ下の第１の絶縁膜１０２がゲート絶縁膜１０９を取り囲む構造であるため、ゲート電極１０６ａ下端においてゲート電極１０６ａと第１の柱状半導体層１１０との絶縁を確かなものとすることができる。
　また、ゲート電極１０６ａにはゲート配線１０６ｂが接続されていてもよい。また、平面状半導体層１０１の周囲を素子分離絶縁膜０９９が取り囲んでいてもよい。
　なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。
　例えば、上記実施例において、ｐ型（ｐ+型を含む。）とｎ型（ｎ+型を含む。）とをそれぞれ反対の導電型とした半導体装置も当然に本発明の技術的範囲に含まれる。
０９９．素子分離絶縁膜
１００．基板
１０１．平面状半導体層
１０２．第１の絶縁膜
１０３．第２の絶縁膜
１０４．レジスト
１０５．第１の孔
１０６．第１の金属
１０６ａ．ゲート電極
１０６ｂ．ゲート配線
１０７．第３の絶縁膜
１０８．第２の孔
１０９．ゲート絶縁膜
１１０．第１の柱状半導体層

Claims (2)

  1. 　基板上に形成された平面状半導体層上に第１の絶縁膜と第２の絶縁膜を堆積し、
    　前記第２の絶縁膜にゲート電極を形成するための第１の孔を形成し、
    　前記第１の孔に第１の金属を埋め込むことにより前記ゲート電極を形成し、
    　前記ゲート電極の上面且つ前記第１の孔の側面に第３の絶縁膜からなるサイドウォールを形成し、
    　前記第３の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより　前記ゲート電極と前記第１の絶縁膜に第２の孔を形成し、
    　前記第２の孔の側面にゲート絶縁膜を形成し、
    　前記第２の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第１の柱状半導体層を形成することを特徴とする半導体装置の製造方法。
  2. 　基板上に形成された平面状半導体層と、
    　前記平面状半導体層上に形成された第１の柱状半導体層と、
    　前記第１の柱状半導体層を取り囲むゲート絶縁膜と、
    　前記ゲート絶縁膜を取り囲むゲート電極と、
    　前記ゲート電極と前記平面状半導体層との間にあって前記ゲート絶縁膜を取り囲む第１の絶縁膜と、
    を有することを特徴とする半導体装置。
PCT/JP2015/081495 2015-11-09 2015-11-09 半導体装置の製造方法及び半導体装置 WO2017081727A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2015/081495 WO2017081727A1 (ja) 2015-11-09 2015-11-09 半導体装置の製造方法及び半導体装置
JP2016573138A JP6294511B2 (ja) 2015-11-09 2015-11-09 半導体装置の製造方法及び半導体装置
US15/849,026 US10453941B2 (en) 2015-11-09 2017-12-20 Surround gate transistor and method for producing the same
US16/520,892 US10483376B1 (en) 2015-11-09 2019-07-24 Method for producing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/081495 WO2017081727A1 (ja) 2015-11-09 2015-11-09 半導体装置の製造方法及び半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/849,026 Continuation US10453941B2 (en) 2015-11-09 2017-12-20 Surround gate transistor and method for producing the same

Publications (1)

Publication Number Publication Date
WO2017081727A1 true WO2017081727A1 (ja) 2017-05-18

Family

ID=58694918

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/081495 WO2017081727A1 (ja) 2015-11-09 2015-11-09 半導体装置の製造方法及び半導体装置

Country Status (3)

Country Link
US (2) US10453941B2 (ja)
JP (1) JP6294511B2 (ja)
WO (1) WO2017081727A1 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182318A (ja) * 2008-01-29 2009-08-13 Unisantis Electronics Japan Ltd 半導体装置およびその製造方法
WO2013175557A1 (ja) * 2012-05-21 2013-11-28 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0271566A (ja) 1987-10-28 1990-03-12 Kanegafuchi Chem Ind Co Ltd Ｍｏｓ型ｆｅｔゲート駆動用太陽電池アレイ
JP3057661B2 (ja) 1988-09-06 2000-07-04 株式会社東芝 半導体装置
JP2703970B2 (ja) 1989-01-17 1998-01-26 株式会社東芝 Ｍｏｓ型半導体装置
JP2950558B2 (ja) 1989-11-01 1999-09-20 株式会社東芝 半導体装置
JP3229012B2 (ja) * 1992-05-21 2001-11-12 株式会社東芝 半導体装置の製造方法
JP3403231B2 (ja) * 1993-05-12 2003-05-06 三菱電機株式会社 半導体装置およびその製造方法
US8643087B2 (en) * 2006-09-20 2014-02-04 Micron Technology, Inc. Reduced leakage memory cells
JP2009094364A (ja) * 2007-10-10 2009-04-30 Toshiba Corp 半導体装置及びその製造方法
US8598650B2 (en) 2008-01-29 2013-12-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
JP6014726B2 (ja) 2008-02-15 2016-10-25 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置及びその製造方法
KR101417764B1 (ko) * 2008-09-26 2014-07-09 삼성전자주식회사 수직형 반도체 소자 및 이의 제조 방법
JP6361180B2 (ja) * 2014-03-10 2018-07-25 富士通セミコンダクター株式会社 半導体装置の製造方法
JP5903139B2 (ja) * 2014-08-22 2016-04-13 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
JP6427068B2 (ja) * 2015-05-27 2018-11-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182318A (ja) * 2008-01-29 2009-08-13 Unisantis Electronics Japan Ltd 半導体装置およびその製造方法
WO2013175557A1 (ja) * 2012-05-21 2013-11-28 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置

Also Published As

Publication number Publication date
US10483376B1 (en) 2019-11-19
US20180138294A1 (en) 2018-05-17
JP6294511B2 (ja) 2018-03-14
US10453941B2 (en) 2019-10-22
JPWO2017081727A1 (ja) 2017-11-16
US20190348526A1 (en) 2019-11-14

Similar Documents

Publication Publication Date Title
JP5822326B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5752810B2 (ja) 半導体装置
JP5779739B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5775650B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5902868B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5654184B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5680801B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP6294511B2 (ja) 半導体装置の製造方法及び半導体装置
JP6114434B2 (ja) 半導体装置
JP6267369B2 (ja) 半導体装置及び半導体装置の製造方法
JP5833214B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP6154051B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5989197B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5977865B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5926423B2 (ja) 半導体装置
JP6033938B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP6211637B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP6159777B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5861197B2 (ja) 半導体装置の製造方法、及び、半導体装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2016573138

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15908251

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15908251

Country of ref document: EP

Kind code of ref document: A1