WO2017081727A1 - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Definitions
- the present invention relates to a semiconductor device.
- SGT Surrounding Gate Transistor
- a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate, and the gate surrounds a columnar semiconductor layer (for example, Patent Document 1, Patent Document 2, Patent Document 3).
- JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2015-188115 A
- an object of the present invention is to provide a method of manufacturing a semiconductor device in which a columnar semiconductor layer is formed after forming a gate electrode, or a semiconductor device as a result.
- a first insulating film and a second insulating film are deposited on a planar semiconductor layer formed on a substrate, and a gate electrode is formed on the second insulating film.
- the first hole is formed, and the gate electrode is formed by embedding the first metal in the first hole, and a third insulating film is formed on the upper surface of the gate electrode and on the side surface of the first hole.
- a second hole is formed in the gate electrode and the first insulating film by etching using the side wall made of the third insulating film as a mask.
- a gate insulating film is formed on a side surface, and a first pillar-shaped semiconductor layer is formed by epitaxially growing a semiconductor layer from the planar semiconductor layer in the second hole.
- the semiconductor device includes a planar semiconductor layer formed on a substrate, a first columnar semiconductor layer formed on the planar semiconductor layer, and a gate insulation surrounding the first columnar semiconductor layer. And a gate electrode surrounding the gate insulating film, and a first insulating film between the gate electrode and the planar semiconductor layer and surrounding the gate insulating film.
- the present invention it is possible to provide a method for manufacturing a semiconductor device in which a columnar semiconductor layer is formed after forming a gate electrode, or a semiconductor device as a result.
- first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate forming a first hole for forming a gate electrode in the second insulating film;
- the gate electrode is formed by embedding a first metal in the first hole, a sidewall made of a third insulating film is formed on the upper surface of the gate electrode and on the side surface of the first hole, and the third electrode
- a second hole is formed in the gate electrode and the first insulating film by etching using a sidewall made of the insulating film as a mask, a gate insulating film is formed on a side surface of the second hole, and
- the gate electrode made of metal is covered with the first insulating film, the third insulating film, and the gate insulating film before the first columnar semiconductor layer is epitaxially grown. Metal contamination can be reduced.
- the gate electrode Since the first insulating film under the gate electrode surrounds the gate insulating film by the structure of the first insulating film between the gate electrode and the planar semiconductor layer and surrounding the gate insulating film, the gate The insulation between the gate electrode and the first columnar semiconductor layer can be ensured at the lower end of the electrode.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG. (A) is a top view of the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
- FIG. 2A is a plan view of a semiconductor device according to the present invention.
- FIG. 4B is a sectional view taken along the line X-X ′ in FIG.
- the semiconductor layer of this embodiment is preferably a silicon layer.
- the semiconductor layer may be a group IV semiconductor such as Ge or C.
- the semiconductor layer may be a group III and group IV compound semiconductor.
- a first insulating film 102 and a second insulating film 103 are deposited on a planar semiconductor layer 101 formed on a substrate 100, and a gate electrode is formed on the second insulating film 103.
- a resist 104 for forming a first hole for forming the first hole is formed.
- the resist 104 may be a pattern of a first hole for forming a gate electrode and a gate wiring.
- the width of the gate wiring is preferably not more than twice the width of the sidewall of the third insulating film later. Further, the diameter of the gate electrode is preferably at least twice the width of the sidewall of the third insulating film later.
- the first insulating film 102 is preferably a nitride film.
- the first insulating film may be an oxide film.
- the second insulating film is preferably an oxide film.
- a diffusion layer may be formed on the planar semiconductor layer 101. Further, the element isolation insulating film 099 may surround the planar semiconductor layer 101.
- a first hole 105 for forming a gate electrode is formed in the second insulating film 103.
- the resist 104 is removed.
- a first metal 106 is deposited in the first hole 105.
- the first metal 106 is preferably a metal used for a semiconductor gate.
- the first metal 106 is preferably titanium nitride or aluminum titanium nitride.
- the first metal 106 is embedded in the first hole 105, and the gate electrode 106a is formed.
- the gate wiring 106b may be formed at the same time.
- a third insulating film 107 is deposited on the upper surface of the gate electrode 106 a and the side surface of the first hole 105.
- the third insulating film 107 is etched to remain in a sidewall shape, and a sidewall made of the third insulating film 107 is formed on the upper surface of the gate electrode 106a and the side surface of the first hole 105. To do.
- the second hole 108 is formed in the gate electrode 106a and the first insulating film 102 by etching using the sidewall made of the third insulating film 107 as a mask.
- a gate insulating film 109 is deposited.
- the gate insulating film is preferably a high dielectric film.
- the gate insulating film preferably includes any one of an oxide film, a nitride film, and a high dielectric film.
- the gate insulating film 109 is etched to form the gate insulating film 109 on the side surface of the second hole 108.
- the gate electrode 106 a and the gate wiring 106 b made of the first metal 106 are covered with the first insulating film 102, the third insulating film 107, and the gate insulating film 109. Therefore, metal contamination on the first columnar semiconductor layer can be reduced.
- the first columnar semiconductor layer 110 is formed by epitaxially growing a semiconductor layer from the planar semiconductor layer 101 in the second hole 108.
- the columnar semiconductor layer can be formed after the gate electrode is formed. Thereafter, a diffusion layer may be formed on the first columnar semiconductor layer.
- FIG. 11 shows the structure of a semiconductor device according to an embodiment of the present invention.
- the first insulating film 102 under the gate electrode 106 a has the gate insulating film 109. Since the structure surrounds the gate electrode 106a, the insulation between the gate electrode 106a and the first columnar semiconductor layer 110 can be ensured at the lower end of the gate electrode 106a.
- the gate wiring 106b may be connected to the gate electrode 106a. Further, the element isolation insulating film 099 may surround the planar semiconductor layer 101.
- a semiconductor device in which p-type (including p + -type) and n-type (including n + -type) are opposite in conductivity type is naturally included in the technical scope of the present invention. It is.
- Element isolation insulating film 100 Substrate 101. Planar semiconductor layer 102. First insulating film 103. Second insulating film 104. Resist 105. First hole 106. First metal 106a. Gate electrode 106b. Gate wiring 107. Third insulating film 108. Second hole 109. Gate insulating film 110. First columnar semiconductor layer
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Abstract
ゲート電極を形成後、柱状半導体層を形成する半導体装置の製造方法もしくは、その結果としての半導体装置を提供することを目的とする。 基板上に形成された平面状半導体層上に第1の絶縁膜と第2の絶縁膜を堆積し、前記第2の絶縁膜にゲート電極を形成するための第1の孔を形成し、前記第1の孔に第1の金属を埋め込むことにより前記ゲート電極を形成し、前記ゲート電極の上面且つ前記第1の孔の側面に第3の絶縁膜からなるサイドウォールを形成し、前記第3の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより前記ゲート電極と前記第1の絶縁膜に第2の孔を形成し、前記第2の孔の側面にゲート絶縁膜を形成し、前記第2の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第1の柱状半導体層を形成することを特徴とすることにより上記課題を解決する。
Description
本発明は半導体装置に関する。
半導体集積回路、なかでもMOSトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているMOSトランジスタはナノ領域まで微細化が進んでいる。MOSトランジスタの微細化が進むと、リーク電流の抑制が困難であり、必要な電流量確保の要請から回路の占有面積をなかなか小さくできない、といった問題があった。この様な問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲートが柱状半導体層を取り囲む構造のSurrounding Gate Transistor(SGT)が提案された(例えば、特許文献1、特許文献2、特許文献3)。
柱状半導体層形成後に、ゲート電極を形成することが提案されている。(例えば、特許文献4)。しかしながら、柱状半導体層が細くなったとき、柱状半導体層を立てることができるか不明である。
そこで、本発明は、ゲート電極を形成後、柱状半導体層を形成する半導体装置の製造方法もしくは、その結果としての半導体装置を提供することを目的とする。
本発明の半導体装置の製造方法は、基板上に形成された平面状半導体層上に第1の絶縁膜と第2の絶縁膜を堆積し、前記第2の絶縁膜にゲート電極を形成するための第1の孔を形成し、前記第1の孔に第1の金属を埋め込むことにより前記ゲート電極を形成し、前記ゲート電極の上面且つ前記第1の孔の側面に第3の絶縁膜からなるサイドウォールを形成し、前記第3の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより前記ゲート電極と前記第1の絶縁膜に第2の孔を形成し、前記第2の孔の側面にゲート絶縁膜を形成し、前記第2の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第1の柱状半導体層を形成することを特徴とする。
また、本発明の半導体装置は、基板上に形成された平面状半導体層と、前記平面状半導体層上に形成された第1の柱状半導体層と、前記第1の柱状半導体層を取り囲むゲート絶縁膜と、前記ゲート絶縁膜を取り囲むゲート電極と、前記ゲート電極と前記平面状半導体層との間にあって前記ゲート絶縁膜を取り囲む第1の絶縁膜と、を有することを特徴とする。
本発明によれば、ゲート電極を形成後、柱状半導体層を形成する半導体装置の製造方法もしくは、その結果としての半導体装置を提供することができる。
基板上に形成された平面状半導体層上に第1の絶縁膜と第2の絶縁膜を堆積し、前記第2の絶縁膜にゲート電極を形成するための第1の孔を形成し、前記第1の孔に第1の金属を埋め込むことにより前記ゲート電極を形成し、前記ゲート電極の上面且つ前記第1の孔の側面に第3の絶縁膜からなるサイドウォールを形成し、前記第3の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより前記ゲート電極と前記第1の絶縁膜に第2の孔を形成し、前記第2の孔の側面にゲート絶縁膜を形成し、前記第2の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第1の柱状半導体層を形成することを特徴とすることにより、ゲート電極を形成後、柱状半導体層を形成することができる。
また、第1の柱状半導体層をエピタキシャル成長させる前に、金属からなるゲート電極は、第1の絶縁膜と第3の絶縁膜とゲート絶縁膜により覆われているため、第1の柱状半導体層に対する金属汚染を低減することができる。
前記ゲート電極と前記平面状半導体層との間にあって前記ゲート絶縁膜を取り囲む第1の絶縁膜との構造により、ゲート電極下の第1の絶縁膜がゲート絶縁膜を取り囲む構造であるため、ゲート電極下端においてゲート電極と第1の柱状半導体層との絶縁を確かなものとすることができる。
以下、本発明の実施形態に係る半導体装置の製造方法を、図1~図11を参照しながら説明する。本実施例の半導体層は、シリコン層であることが好ましい。また、半導体層は、Ge、CといったIV族の半導体としてもよい。また、半導体層はIII族とIV族の化合物半導体としてもよい。
図1に示すように、基板100上に形成された平面状半導体層101上に第1の絶縁膜102と第2の絶縁膜103を堆積し、第2の絶縁膜103上にゲート電極を形成するための第1の孔を形成するためのレジスト104を形成する。このとき、レジスト104を、ゲート電極とゲート配線を形成するための第1の孔のパターンとしてもよい。ゲート電極とゲート配線を形成するための第1の孔のパターンとするとき、ゲート配線幅は、後の第3の絶縁膜のサイドウォールの幅の二倍以下とすることが好ましい。また、ゲート電極の直径は、後の第3の絶縁膜のサイドウォールの幅の二倍以上とすることが好ましい。また、第1の絶縁膜102は窒化膜が好ましい。また、第1の絶縁膜は酸化膜としてもよい。また、第2の絶縁膜は酸化膜であることが好ましい。また、平面状半導体層101上部に拡散層を形成しておいてもよい。また、平面状半導体層101の周囲を素子分離絶縁膜099が取り囲んでいてもよい。
図2に示すように、第2の絶縁膜103にゲート電極を形成するための第1の孔105を形成する。
図3に示すように、レジスト104を除去する。
図4に示すように、第1の孔105に第1の金属106を堆積する。第1の金属106は半導体のゲートに使用される金属であることが好ましい。第1の金属106は、窒化チタン、窒化アルミチタンであることが好ましい。
図5に示すように、第1の金属106をエッチバックすることにより、第1の孔105に第1の金属106が埋め込まれ、ゲート電極106aが形成される。ゲート配線106bが同時に形成されてもよい。
図6に示すように、ゲート電極106aの上面且つ第1の孔105の側面に第3の絶縁膜107を堆積する。
図7に示すように、第3の絶縁膜107をエッチングし、サイドウォール状に残存させゲート電極106aの上面且つ第1の孔105の側面に、第3の絶縁膜107からなるサイドウォールを形成する。
図8に示すように、第3の絶縁膜107からなるサイドウォールをマスクとしてエッチングをすることによりゲート電極106aと第1の絶縁膜102に第2の孔108を形成する。
図9に示すように、ゲート絶縁膜109を堆積する。ゲート絶縁膜は、高誘電体膜であることが好ましい。また、ゲート絶縁膜は、酸化膜、窒化膜、高誘電体膜のいずれか一つを含むことが好ましい。
図10に示すように、ゲート絶縁膜109をエッチングし、第2の孔108の側面にゲート絶縁膜109を形成する。第1の柱状半導体層をエピタキシャル成長させる前に、第1の金属106からなるゲート電極106aとゲート配線106bは、第1の絶縁膜102と第3の絶縁膜107とゲート絶縁膜109により覆われているため、第1の柱状半導体層に対する金属汚染を低減することができる。
図11に示すように、第2の孔108に平面状半導体層101から半導体層をエピタキシャル成長させることにより第1の柱状半導体層110を形成する。以上により、ゲート電極を形成後、柱状半導体層を形成することができる。この後、第1の柱状半導体層上部に拡散層を形成してもよい。
本発明の実施形態に係る半導体装置の構造を図11に示す。
基板100上に形成された平面状半導体層101と、前記平面状半導体層101上に形成された第1の柱状半導体層110と、前記第1の柱状半導体層110を取り囲むゲート絶縁膜109と、前記ゲート絶縁膜109を取り囲むゲート電極106aと、前記ゲート電極106aと前記平面状半導体層101との間にあって前記ゲート絶縁膜109を取り囲む第1の絶縁膜102と、を有する。
前記ゲート電極106aと前記平面状半導体層101との間にあって前記ゲート絶縁膜109を取り囲む第1の絶縁膜102との構造により、ゲート電極106a下の第1の絶縁膜102がゲート絶縁膜109を取り囲む構造であるため、ゲート電極106a下端においてゲート電極106aと第1の柱状半導体層110との絶縁を確かなものとすることができる。
また、ゲート電極106aにはゲート配線106bが接続されていてもよい。また、平面状半導体層101の周囲を素子分離絶縁膜099が取り囲んでいてもよい。
なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。
例えば、上記実施例において、p型(p+型を含む。)とn型(n+型を含む。)とをそれぞれ反対の導電型とした半導体装置も当然に本発明の技術的範囲に含まれる。
099.素子分離絶縁膜
100.基板
101.平面状半導体層
102.第1の絶縁膜
103.第2の絶縁膜
104.レジスト
105.第1の孔
106.第1の金属
106a.ゲート電極
106b.ゲート配線
107.第3の絶縁膜
108.第2の孔
109.ゲート絶縁膜
110.第1の柱状半導体層
100.基板
101.平面状半導体層
102.第1の絶縁膜
103.第2の絶縁膜
104.レジスト
105.第1の孔
106.第1の金属
106a.ゲート電極
106b.ゲート配線
107.第3の絶縁膜
108.第2の孔
109.ゲート絶縁膜
110.第1の柱状半導体層
Claims (2)
- 基板上に形成された平面状半導体層上に第1の絶縁膜と第2の絶縁膜を堆積し、
前記第2の絶縁膜にゲート電極を形成するための第1の孔を形成し、
前記第1の孔に第1の金属を埋め込むことにより前記ゲート電極を形成し、
前記ゲート電極の上面且つ前記第1の孔の側面に第3の絶縁膜からなるサイドウォールを形成し、
前記第3の絶縁膜からなるサイドウォールをマスクとしてエッチングをすることにより 前記ゲート電極と前記第1の絶縁膜に第2の孔を形成し、
前記第2の孔の側面にゲート絶縁膜を形成し、
前記第2の孔に前記平面状半導体層から半導体層をエピタキシャル成長させることにより第1の柱状半導体層を形成することを特徴とする半導体装置の製造方法。 - 基板上に形成された平面状半導体層と、
前記平面状半導体層上に形成された第1の柱状半導体層と、
前記第1の柱状半導体層を取り囲むゲート絶縁膜と、
前記ゲート絶縁膜を取り囲むゲート電極と、
前記ゲート電極と前記平面状半導体層との間にあって前記ゲート絶縁膜を取り囲む第1の絶縁膜と、
を有することを特徴とする半導体装置。
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