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  • B82—NANOTECHNOLOGY
  • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
  • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
  • B82B3/0009—Forming specific nanostructures
  • B82B3/0038—Manufacturing processes for forming specific nanostructures not provided for in groups B82B3/0014 - B82B3/0033
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  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
  • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
  • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
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  • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
  • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
  • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
  • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
  • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
  • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
  • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
  • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/3065—Plasma etching; Reactive-ion etching
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
  • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y40/00—Manufacture or treatment of nanostructures
• • C—CHEMISTRY; METALLURGY
  • C01—INORGANIC CHEMISTRY
  • C01P—INDEXING SCHEME RELATING TO STRUCTURAL AND PHYSICAL ASPECTS OF SOLID INORGANIC COMPOUNDS
  • C01P2004/00—Particle morphology
  • C01P2004/10—Particle morphology extending in one dimension, e.g. needle-like
  • C01P2004/16—Nanowires or nanorods, i.e. solid nanofibres with two nearly equal dimensions between 1-100 nanometer
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
  • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels

Definitions

• the semiconductor industry has relied on scaling/reducing device feature size in order to boost performance and increase transistor density.
• the continued device performance improvement due to scaling has seen the introduction of unique technologies such as semiconductor on insulator (i.e., SOI, GeOI, etc), and stressor such as SiGe and SiC, to improve mobility at the 90nm node, epitaxial regrowth of source and drain (raised source and drain), high-k metal gate (HKMG) at the 45nm node, and 3D structures such as FinFETs and trigates at the 22nm node.
• semiconductor on insulator i.e., SOI, GeOI, etc
• stressor such as SiGe and SiC
• Nanowires offer scaling of feature size, good short channel control, and enhancement in the device electron mobility, hence enhancement in device speed.
• the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.
• the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle comers, forming a first oxidized surface layer on the plurality of nanowires using a first oxidizing microwave plasma at a first gas pressure, forming a second oxidized surface layer on the plurality of nanowires using a second oxidizing microwave plasma at a second gas pressure that is different than the first gas pressure, removing the first and second oxidized surface layers to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing steps at least once until the plurality of nanowires have a desired trimmed height and rounded corners.
• the first gas pressure can be less or equal to lTorr and the second gas pressure can be greater than lTorr.
• FIGS. 1A-1C schematically show a process flow for forming nanowires according to an embodiment of the invention
• FIGS. 2A-2C schematically show a process flow for forming nanowires according to an embodiment of the invention
• FIGS. 3A-3D schematically show a process flow for forming nanowires according to an embodiment of the invention
• FIG. 4 shows a process flow diagram for a method of processing nanowires according to an embodiment of the invention
• FIGS. 5-8 show cross-sectional transmission electron microscopy (TEM) images of Si nanowires according to an embodiment of the invention.
• FIG. 9 shows a cross-sectional TEM image of a Si nanowire according to an embodiment of the invention.
• FIG. 10 shows a cross-sectional TEM image of a Si nanowire following a process of corner rounding and trimming according to an embodiment of the invention
• FIG. 11 shows a cross-sectional TEM image of a Si nanowire following a process of corner rounding and trimming according to an embodiment of the invention
• FIG. 12 is a schematic diagram of a plasma processing system containing a microwave plasma source for processing a substrate according to an embodiment of the invention
• FIG. 13 is a schematic diagram of another plasma processing system containing a microwave plasma source for processing a substrate according to an embodiment of the invention.
• FIG. 14 illustrates a plan view of a gas supplying unit of the plasma processing system in FIG. 13.
• FIG. 15 illustrates a partial cross-sectional view of an antenna portion of the plasma processing system in FIG. 13.
• Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. Methods for forming the nanowires can result in nanowires that have substantially right angle corners, which can lead to potential device performance degradation such as current crowding.
• the corner rounding and trimming described in the embodiments of the invention reduces an electric field concentration phenomenon that occurs at the corner of a conventional field effect transistor (FET) having a square-shaped nanowire channel.
• FET field effect transistor
• FIGS. 1A-1C schematically show a process flow for forming nanowires according to an embodiment of the invention.
• the process flow includes forming alternating Si films 104, 108 and SiGe films 102, 106 on a substrate 100, as shown in a schematic cross-sectional view in FIG. 1A.
• the process flow further includes, in FIG. IB, performing an anisotropic etch process to form patterned alternating Si features 114, 118 and SiGe features 112, 116 on the substrate 100.
• FIG. IB further shows a recess 120 formed in the substrate 100 by the anisotropic etch process. Thereafter, as depicted in FIG.
• the SiGe features 112, 116 are selectively removed in an isotropic etch process to release the Si features 114, 118 that become Si nanowires 114, 118 that are separated by a void.
• the Si nanowires 114, 118 have at least substantially right angle corners. Only two Si nanowires 114, 118 are depicted in FIG. 1C but embodiments of the invention may be applied to any number of Si nanowires.
• the Si features 114, 118 may be replaced by SiGe features 112, 116 and the SiGe features 112, 116 replaced by Si features 112, 116, and the Si features 112, 116 selectively removing by an isotropic etch process to release the SiGe features 114, 118 to become SiGe nanowires 114, 118.
• FIGS. 2A-2C schematically show a process flow for forming nanowires according to an embodiment of the invention.
• the process flow in FIGS. 2A-2C is similar to the process flow in FIGS. 1A-1C and includes forming alternating Si films 204, 208 and SiGe films 202, 206 on a substrate 200, where the SiGe film 202 is thicker than the Si film 206.
• the process flow further includes, in FIG. 2B, performing an anisotropic etch process to form patterned alternating Si features 214, 218 and SiGe features 212, 216 on the substrate 200.
• FIG. 2B further shows a recess 220 formed in the substrate 200 by the anisotropic etch process. Thereafter, as depicted in FIG.
• the SiGe features 212, 216 are selectively removed in an isotropic etch process to release the Si features 214, 218 that become Si nanowires 214, 218 that are separated by a void.
• the Si features 214, 218 may be replaced by SiGe features 212, 216 and the SiGe features 212, 216 replaced by Si features 214, 218, and the Si features 212, 216 selectively removed by an isotropic etch process to release the SiGe features 214, 218 that become SiGe nanowires 214, 218.
• FIGS. 3A-3D schematically show a process flow for forming nanowires according to an embodiment of the invention.
• the process flow in FIGS. 3A-3D is similar to the process flow in FIG. 2A-2C and includes forming by an anisotropic etch process patterned alternating Si features 314, 318 and SiGe features 312, 316 on the substrate 300, where the SiGe feature 312 is thicker than the SiGe feature 316.
• FIG. 3A which further shows a recess 320 formed in the substrate 300 by the anisotropic etch process.
• a blanket dielectric layer 330 e.g., S1O 2
• the blanket dielectric layer 330 is partially etched to below the Si feature 314, and thereafter the SiGe features 312, 316 are selectively removed in an isotropic etch process to release the Si features 314, 318 that become Si nanowires 314, 318 that are separated by a void.
• the Si features 314, 318 may be replaced by SiGe features 312, 316 and Ihe SiGe features 312, 316 replaced by Si features 314, 318, and the Si features 312, 316 selectively removed by an isotropic etch process to release the SiGe features 314, 318 that become SiGe nanowires 314, 318.
• FIG. 4 shows a process flow diagram 400 for a method of processing nanowires according to an embodiment of the invention.
• the nanowires shown in FIGS. 1C, 2C, and 3D may be processed according to the process flow diagram 400.
• the method includes, in 402, providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners.
• the plurality of nanowires may have a height between about lOnm and about 50nm.
• the plurality of nanowires may, for example, be selected from the group consisting of Si, SiGe, and compound semiconductors.
• the method further includes, in 404, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma that oxidizes the plurality of nanowires.
• the oxidizing microwave plasma includes plasma excited 0 2 gas.
• the oxidizing microwave plasma utilizes a gas pressure of less or equal to lTorr in the process chamber.
• the oxidizing microwave plasma utilizes a gas pressure greater than lTorr in the process chamber.
• the use of the oxidizing microwave plasma provides very precise control over the thickness of the oxidized surface layer and prevents or reduces plasma damage to the nanowires.
• the oxidized surface layer may have a thickness of about 3nm.
• the microwave plasma may be an RLSATM plasma processing system available from Tokyo Electron Limited, Akasaka, Japan.
• the method further includes, in 406, removing the oxidized surface layer from the plurality of nanowires to trim the height and round the corners of the plurality of nanowires.
• the removing includes a chemical oxide removal (COR) process that includes exposing the oxidized surface layer to HF gas and NH 3 gas to form reaction products on the plurality of nanowires, and thereafter heat-treating the plurality of nanowires to desorb the reaction products from the nanowires.
• COR chemical oxide removal
• the COR processing conditions can include a HF gas flow rate of 40sccm, a Nf1 ⁇ 4 gas flow rate of 40sccm, a substrate temperature of about 20-80°C, for example about 30°C, and a process chamber pressure of 40mTorr.
• the heat-treating can include a substrate temperature of about 100-200°C, and aN 2 gas purge.
• a COR process may be performed in a Certas WINGTM, a high throughput gas plasma-free chemical etching system available from Tokyo Electron Limited, Akasaka, Japan.
• steps 404 and 406 may be repeated at least once until the plurality of nanowires have a desired trimmed height and rounded corners. Since each cycle of steps 404 and 406 removes about 3nm of material from each side of the plurality of nanowires, steps 404 and 406 are sequentially repeated a plurality of times, for example three or more times, to fully round the corners of the plurality of nanowires. Thereafter the processed nanowires may be further processed to form a semiconductor device. The further processing can include deposition of a dielectric layer that encapsulates the plurality of nanowires, and deposition of a metal -containing gate electrode layer that fills the remaining voids between the plurality of nanowires.
• the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, and forming a first oxidized surface layer on the plurality of nanowires using a first oxidizing microwave plasma at a first gas pressure.
• the method further includes forming a second oxidized surface layer on the plurality of nanowires using a second oxidizing microwave plasma at a second gas pressure that is different than the first gas pressure, and removing the first and second oxidized surface layers to trim the height and round the corners of the plurality of nanowires.
• first gas pressure is less than the second gas pressure. In one example, the first gas pressure is less or equal to lTorr and the second gas pressure is greater than lTorr.
• FIGS. 5-8 show cross-sectional transmission electron microscopy (TEM) images of Si nanowires according to an embodiment of the invention.
• FIG. 5 shows a cross-sectional TEM of multiple rows of Si nanowires where each row contains three released Si nanowires.
• One row with Si nanowires 501-503 is identified.
• the Si nanowires 501-503 have substantially right angle corners before being subject to the method of corner rounding and trimming according to an embodiment of the invention.
• FIG. 6 shows cross-sectional TEM images of Si nanowires 601-603
• FIGS. 7 and 8 show cross-sectional TEM images of Si nanowire 602 using different magnifications.
• FIG. 9 show a cross-sectional TEM image of a Si nanowire 901
• FIG. 10 shows a cross- sectional TEM image of a Si nanowire 1001 following a process of corner rounding and trimming according to an embodiment of the invention.
• the process included exposing a Si nanowire 1001 having substantially right angle corners to an oxidizing microwave plasma containing plasma excited O2 gas to form an oxidized surface layer on the Si nanowire 1001.
• the process chamber pressure was lTorr and the process gas consisted of 0 2 gas and Ar gas. Thereafter, the oxidized surface layer was removed from the Si nanowire 1001 using a COR process.
• FIG. 10 clearly shows the effectiveness of the inventive process to trim the height and round the comers of the Si nanowire 1001.
• FIG. 11 shows a cross-sectional TEM image of a Si nanowire 1101 following a process of corner rounding and trimming according to an embodiment of the invention.
• the processing included exposing a Si nanowire 1101 having substantially right angle corners to an oxidizing microwave plasma containing plasma excited 0 2 gas at a process chamber pressure of 0. lTorr to form a first oxidized surface layer on the Si nanowire 1101. Thereafter, the Si nanowire 1101 was exposed to an oxidizing microwave plasma containing plasma excited 0 2 gas at a process chamber pressure of 5Torr to form a second oxidized surface layer on the Si nanowire 1101. Thereafter, the first and second oxidized surface layers were removed from the Si nanowire 1101 using a COR process.
• FIG. 11 clearly shows the effectiveness of the inventive process to trim the height and round the corners of the Si nanowire 1101 using a oxidizing microwave plasma and two different process chamber pressures.
• low process chamber pressure i.e., less or equal to lTorr
• high process chamber pressure i.e., greater than 1 Torr
• Oxygen ions in the plasma result in faster oxidation of the nanowires and are believed to have a stronger effect on corner rounding of the nanowires, whereas neutral oxygen radicals are believed to have a stronger effect on trimming the height (thickness) of the nanowires. Therefore, sequential exposures to oxidizing plasmas having different process chamber pressures may be utilized to in order to control the relative thickness and corner rounding of the nanowires.
• FIG. 12 is a schematic diagram of a microwave plasma processing system containing a RLSATM plasma for processing a substrate according to embodiments of the invention.
• the plasma produced in the plasma processing system 510 is characterized by low electron temperature and high plasma density.
• the plasma processing system S 10 contains a plasma processing chamber 550 having an opening portion 551 in the upper portion of the plasma processing chamber 550 that is larger than a substrate 558.
• a cylindrical dielectric top plate 554 made of quartz, aluminum nitride, or aluminum oxide is provided to cover the opening portion 551.
• Gas lines 572 are located in the side wall of the upper portion of plasma processing chamber 550 below the top plate 554.
• the number of gas lines 572 can be 16 (only two of which are shown in FIG. 12).
• a different number of gas lines 572 can be used.
• the gas lines 572 can be circumferentially arranged in the plasma processing chamber 550, but this is not required for the invention.
• a process gas can be evenly and uniformly supplied into the plasma region 559 in plasma processing chamber 550 from the gas lines 572.
• microwave power is provided to the plasma processing chamber 550 through the top plate 554 via a slot antenna 560 having a plurality of slots 560A.
• the slot antenna 560 faces the substrate 558 to be processed and the slot antenna 560 can be made from a metal plate, for example copper.
• a waveguide 563 is disposed on the top plate 554, where the waveguide 563 is connected to a microwave power supply 561 for generating microwaves with a frequency of about 2.45GHz, for example.
• the waveguide 563 contains a flat circular waveguide 563A with a lower end connected to the slot antenna 560, a circular waveguide 563B connected to the upper surface side of the circular waveguide 563A, and a coaxial waveguide converter 563C connected to the upper surface side of the circular waveguide 563B. Furthermore, a rectangular waveguide 563D is connected to the side surface of the coaxial waveguide converter 563C and the microwave power supply 561.
• an axial portion 562 of an electroconductive material is coaxially provided, so that one end of the axial portion 562 is connected to the central (or nearly central) portion of the upper surface of slot antenna 560, and the other end of the axial portion 562 is connected to the upper surface of the circular waveguide 563B, thereby forming a coaxial structure.
• the circular waveguide 563B is constituted so as to function as a coaxial waveguide.
• the microwave power can, for example, be between about 0.5 W/cm 2 and about 4 W/cm 2 . Alternatively, the microwave power can be between about 0.5 W/cm 2 and about 3 W/cm 2 .
• the microwave irradiation may contain a microwave frequency of about 300 MHz to about 10 GHz, for example about 2.45 GHz, and the plasma may contain an electron temperature of less than or equal to 5 eV, including 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5 or 5 eV, or any combination thereof.
• the electron temperature can be below 5eV, below 4.5eV, below 4eV, or even below 3.5eV.
• the electron temperature can be between 3.0 and 3.5 eV, between 3.5eV and 4.0eV, or between 4.0 and 4.5 eV.
• the plasma may have a density of about 1 x 10 n /cm 3 to about 1 x 10 13 /cm 3 , or higher.
• a substrate holder 552 is provided opposite the top plate 554 for supporting and heating a substrate 558 (e.g., a wafer).
• the substrate holder 552 contains a heater 557 to heat the substrate 525, where the heater 557 can be a resistive heater. Alternatively, me heater 557 may be a lamp heater or any other type of heater.
• the plasma processing chamber 550 contains an exhaust line 553 connected to the bottom portion of the plasma processing chamber 550 and to a vacuum pump 555.
• the plasma processing system 510 further contains a substrate bias system 556 configured to bias the substrate holder 552 and the substrate 558 for generating a plasma and/or controlling energy of ions that are drawn to a substrate 558.
• the substrate bias system 556 includes a substrate power source configured couple power to the substrate holder 552.
• the substrate power source contains a RF generator and an impedance match network.
• the substrate power source is configured to couple power to the substrate holder 552 by energizing an electrode in the substrate holder 552.
• a typical frequency for the RF bias can range from about 0.1 MHz to about 100 MHz, and can be 13.56 MHz.
• the RF bias can be less than 1 MHz, for example less than 0.8 MHz, less than 0.6 MHz, less than 0.4 MHz, or even less than 0.2MHz. In one example, the RF bias can be about 0.4 MHz.
• RF power is applied to the electrode at multiple frequencies.
• the substrate bias system 556 is configured for supplying RF bias power can be between 0W and 100W, between 100W and 200W, between 200W and 300W, between 300W and 400W, or between 400W and 500W. In some examples, the RF bias power can be less than 100W, less than 50W, or less than 25W, for example. RF bias systems for plasma processing are well known to those skilled in the art. Further, the substrate bias system 556 includes a DC voltage generator capable of supplying DC bias between -5kV and +5kV to the substrate holder 552.
• the substrate bias system 556 is further configured to optionally provide pulsing of the RF bias power.
• the pulsing frequency can be greater than 1Hz, for example 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, 20Hz, 30Hz, 50Hz, or greater. It is noted that one skilled in the art will appreciate that the power levels of the substrate bias system 556 are related to the size of the substrate being processed. For example, a 300 mm Si wafer requires greater power consumption than a 200 mm wafer during processing.
• a controller 599 is configured for controlling the plasma processing system 510.
• the controller 599 can include a microprocessor, a memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs of the plasma processing system 510 as well as monitor outputs from the plasma processing system 510.
• the controller 599 is coupled to and exchanges information with plasma processing chamber 550, the vacuum pump 555, the heater 557, the substrate bias system 556, and the microwave power supply 561.
• a program stored in the memory is utilized to control the
• controller 599 is a UNIX-based workstation.
• the controller 599 can be implemented as a general-purpose computer, digital signal processing system, etc.
• FIG. 13 is a schematic diagram of a microwave plasma processing system containing a RLSATM plasma for processing a substrate according to another embodiment of the invention.
• the plasma processing system 10 includes a plasma processing chamber 20
• the substrate holder 21 is located centrally on a bottom portion of the plasma processing chamber 20 and serves as a substrate holder for supporting a substrate W. Inside the substrate holder 21, there is provided an insulating member 21a, a cooling jacket 21b, and a temperature control unit (not shown) for controlling the substrate temperature.
• a top portion of the plasma processing chamber 20 is open-ended.
• the plasma gas supply unit 30 is placed opposite to the substrate holder 21 and is attached to the top portion of the plasma processing chamber 20 via sealing members such as O rings (not shown).
• the plasma gas supply unit 30, which may also function as a dielectric window, can be made of materials such as aluminum oxide or quartz and has a planar surface.
• a plurality of gas supply holes 31 are provided opposite the substrate holder 21 on a planar surface of the plasma gas supply unit 30.
• the plurality of gas supply holes 31 communicate with a plasma gas supply port 33 via a gas flow channel 32.
• a plasma gas supply source 34 provides a plasma gas, for example argon (Ar) gas, or other inert gases, into the plasma gas supply port 33.
• the plasma gas is then uniformly supplied into the plasma generation region Rl via the plurality of gas supply holes 31.
• the plasma processing system 10 further includes a process gas supply unit 40, which is centered in the plasma processing chamber 20 between the plasma generation region Rl and the plasma diffusion region R2.
• the process gas supply unit 40 may be made of a conducting material, for example an aluminum alloy that includes magnesium (Mg), or stainless steel. Similar to the plasma gas supply unit 30, a plurality of gas supply holes 41 are provided on a planar surface of the process gas supply unit 40. The planar surface of the process gas supply unit 40 is positioned opposite to the substrate holder 21.
• the plasma processing chamber 20 further includes exhaust lines 26 connected to the bottom portion of the plasma processing chamber 20, a vacuum line 27 connecting the exhaust lines 26 to a pressure controller valve 28 and to a vacuum pump 29.
• the pressure controller valve 28 may be used to achieve a desired gas pressure in the plasma processing chamber 20.
• FIG. 14 A plan view of the process gas supply unit 40 is shown in FIG. 14. As shown in this figure, grid-like gas flow channels 42 are formed within the process gas supply unit 40. The grid-like gas flow channels 42 communicate with an upper-end of the plurality of gas supply holes 41, which are formed in the vertical direction. The lower portion of the plurality of gas supply holes 41 are openings facing the substrate holder 21. The plurality of gas supply holes 41 communicate with a process gas supply port 43 via the grid-patterned gas flow channels 42. [0046] Further, a plurality of openings 44 are formed in the process gas supply unit 40 such that the plurality of openings 44 pass through the process gas supply unit 40 in the vertical direction.
• the plurality of openings 44 introduce the plasma gas, e.g., argon (Ar) gas, helium (He) gas, or other inert gases, into the plasma diffusion region R2 above the substrate holder 21. As shown in FIG. 14, the plurality of openings 44 are formed between adjacent gas flow channels 42.
• the process gas may be supplied from three separate process gas supply sources 45-47 to the process gas supply port 43.
• the process gas supply sources 45-47 may supply H 2 gas, 0 2 gas, and Ar gas. However, other gases may be used.
• the process gas flows through the grid-like gas flow channels 42 and is uniformly supplied into the plasma diffusion region R2 via the plurality of gas supply holes 41.
• the plasma processing system 10 further includes four valves (VI -V4) and four mass flow rate controller (MFC1- MFC4) for controlling a supply of the process gas.
• An external microwave generator 55 provides a microwave of a predetermined frequency, e.g., 2.45 GHz, to the antenna unit 50 via a coaxial waveguide 54.
• the coaxial waveguide 54 may include an inner conductor 54B and an outer conductor 54A.
• the microwave from the microwave generator 55 generates an electric field just below the plasma gas supply unit 30 in the plasma generation region Rl, which in turn causes excitation of the process gas within the plasma processing chamber 20.
• FIG. 15 illustrates a partial cross-sectional view of the antenna unit 50.
• the antenna unit 50 may include a flat antenna main body 51, a radial line slot plate 52, and a dielectric plate 53 to shorten the wavelength of the microwave.
• the flat antenna main body 51 can have a circular shape with an open-ended bottom surface.
• the flat antenna main body 51 and the radial line slot plate 52 can be made of a conductive material.
• a plurality of slots 56 are provided on the radial line slot plate 52 to generate a circularly polarized wave.
• the plurality of slots 56 are arranged in a substantially T-shaped form with a small gap between each slot.
• the plurality of slots 56 are arranged in a concentric circle pattern or a spiral pattern along a circumferential direction. Since the slots 56a and 56b are perpendicular to each other, a circularly polarized wave containing two orthogonal polarized components is radiated, as a plane wave, from the radial line slot plate 52.
• the dielectric plate 53 can be made of a low loss dielectric material, e.g., aluminum oxide (AI 2 O 3 ) or silicon nitride (S1 3 N 4 ), that is located between the radial line slot plate 52 and the flat antenna main body 51.
• the radial line slot plate 52 may be mounted on the plasma processing chamber 20 using sealing members (not shown), such that the radial line slot plate 52 is in close contact with a cover plate 23.
• the cover plate 23 is located on the upper surface of plasma gas supply unit 30 and is formed from a microwave transmissive dielectric material such as aluminum oxide (A1 2 0 3 ).
• An external high-frequency power supply source 22 is electrically connected to the substrate holder 21 via a matching network 25.
• the external high-frequency power supply source 22 generates an RF bias power of a predetermined frequency, e.g. 13.56 MHz, for controlling the energy of ions in the plasma that are drawn to the substrate W.
• the power supply source 22 is further configured to optionally provide pulsing of the RF bias power.
• the pulsing frequency can be greater than lHz, for example 2Hz, 4Hz, 6Hz, 8Hz, 10Hz, 20Hz, 30Hz, 50Hz, or greater.
• the power supply source 22 is configured for supplying RF bias power between 0W and 100W, between 100W and 200W, between 200W and 300W, between 300W and 400W, or between 400W and 500W.
• the plasma processing system 10 further includes DC voltage generator 35 capable of supplying DC voltage bias between -5kV and +5kV to the substrate holder 21.

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• 2016
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