WO2017076158A1 - 像素结构及其制作方法、阵列基板和显示面板 - Google Patents

像素结构及其制作方法、阵列基板和显示面板 Download PDF

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Publication number
WO2017076158A1
WO2017076158A1 PCT/CN2016/102261 CN2016102261W WO2017076158A1 WO 2017076158 A1 WO2017076158 A1 WO 2017076158A1 CN 2016102261 W CN2016102261 W CN 2016102261W WO 2017076158 A1 WO2017076158 A1 WO 2017076158A1
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WIPO (PCT)
Prior art keywords
pixel
common electrode
electrode
comb
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2016/102261
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English (en)
French (fr)
Inventor
贾纬华
马小叶
杨海鹏
尹傛俊
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US15/535,450 priority Critical patent/US20170336681A1/en
Publication of WO2017076158A1 publication Critical patent/WO2017076158A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/124—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode interdigital

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel structure and a method for fabricating the same, an array substrate, and a display panel.
  • the pixel electrode and the common electrode are completely overlapped, and the storage capacitance between the pixel electrode and the common electrode is high.
  • the common electrode 12, the insulating layer 13, and the pixel electrode 14 are sequentially formed on the base substrate 11.
  • the overlapping area between the common electrode 12 and the pixel electrode 14 causes a higher storage capacitance, thereby lowering the charging rate of the pixel.
  • the storage capacitance between the pixel electrode and the common electrode is large, which reduces the charging rate of the pixel.
  • a pixel structure and a method of fabricating the same, an array substrate, and a display panel that are capable of reducing a storage capacitance between a pixel electrode and a common electrode and increasing a charging rate of the pixel.
  • Embodiments of the present invention provide a pixel structure including a plurality of pixel units arranged in a matrix, each pixel unit including a common electrode and a pixel electrode disposed on a different layer of a substrate, the common electrode being on a base substrate
  • the projection on the upper surface and the projection of the pixel electrode on the substrate substrate have no overlapping regions.
  • the common electrode and the pixel electrode disposed in different layers are designed such that the projection on the substrate substrate has no overlapping area, thereby reducing the storage capacitance between the common electrode and the pixel electrode. , increasing the charging rate of the pixel.
  • the pixel electrode and the common electrode are both comb electrodes, and the pixel electrode and the common electrode are arranged in a finger structure.
  • each pixel unit includes a first display area and a second display area.
  • the pixel electrodes in the first display region and the comb electrodes of the common electrode are all arranged in the same extending direction, and the pixel electrodes in the second display region and the comb electrodes of the common electrode are arranged in the same extending direction.
  • the direction in which the comb electrodes in the first display region extend is different from the direction in which the comb electrodes in the second display region extend.
  • the extending directions of the comb electrodes in the first display regions of the plurality of pixel units are the same, and the comb electrodes in the second display regions of the plurality of pixel units The extension directions are the same.
  • the comb electrode in the first display area of each pixel unit and the comb electrode in the second display area are at the intersection of the first display area and the second display area as an axis of symmetry Symmetrical distribution.
  • the extending direction of the comb electrodes in the first display region of one column of pixel units in each adjacent two columns of pixel units is different from the extending direction of the comb electrodes in the first display region of the other column of pixel units.
  • the extending direction of the comb electrodes in the second display region of one column of pixel cells in each adjacent column of pixels is different from the extending direction of the comb electrodes in the second display region of the other column of pixel cells.
  • the comb electrode in the first display area of each pixel unit and the comb electrode in the second display area are at the intersection of the first display area and the second display area as an axis of symmetry Symmetrically distributed, and the comb electrodes in each adjacent two columns of pixel units are symmetrically distributed symmetrically with the gap between the two columns of pixel units.
  • the pixel structure further includes a first common electrode line located at a boundary between the first display area and the second display area of each pixel unit, the first common electrode line connecting adjacent ones a common electrode in the first display area and the second display area.
  • each adjacent two columns of pixel units constitute a pixel unit group, and the pixel units in each pixel unit group are different.
  • the pixel unit in each pixel unit group shares one data line, and each adjacent two pixel unit groups further includes a second common electrode line, and the second common electrode line connection is adjacent to the second common electrode line The common electrode in the two columns of pixel cells.
  • the number of the second common electrode lines is plural, the plurality of second common electrode lines are disposed in the same layer as the gate lines, and pass through the plurality of second common electrodes a plurality of vias near the intersection of the line and the gate line, electrically connecting the plurality of vias A second common electrode line.
  • the embodiment of the invention further provides an array substrate comprising the above pixel structure.
  • the embodiment of the invention further provides a display panel comprising the above array substrate.
  • the embodiment of the present invention further provides a method for fabricating the above pixel structure, the method comprising: forming a common electrode on a substrate by using a patterning process; forming a pixel electrode, and projecting the pixel electrode on the substrate The projection of the common electrode on the substrate substrate has no overlapping area.
  • forming the common electrode on the base substrate by the patterning process includes forming a common electrode by an exposure developing process using a mask plate, the common electrode being a comb electrode.
  • forming the pixel electrode includes: forming a pixel electrode by an exposure and development process using a mask, the pixel electrode is a comb electrode, and the pixel electrode and the common electrode are arranged in a pin structure cloth.
  • the mask is a halftone mask, a gray tone mask or a mask having a slit.
  • the method further includes forming a first common electrode line on the common electrode.
  • the method further includes forming the second common electrode line while forming the first common electrode line.
  • FIG. 1 is a schematic structural view of a pixel structure provided by the prior art
  • FIG. 2 is a schematic structural diagram of a pixel structure according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a pixel electrode and a common electrode according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a comb electrode according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a arrangement direction of a pixel electrode and a common electrode according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of another arrangement direction of a pixel electrode and a common electrode according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a third pixel electrode and a common electrode in an arrangement direction according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a fourth pixel electrode and a common electrode in an arrangement direction according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a fifth pixel electrode and a common electrode in an arrangement direction according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another pixel structure according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic cross-sectional view showing a pixel structure according to an embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of another pixel structure according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic flowchart diagram of a method for fabricating a pixel structure according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a structure obtained by a method for fabricating a pixel structure according to an embodiment of the present invention.
  • FIG. 15 is a second schematic diagram of a structure obtained by a method for fabricating a pixel structure according to an embodiment of the present invention.
  • 16 is a third schematic diagram of a structure obtained by a method for fabricating a pixel structure according to an embodiment of the present invention.
  • FIG. 17 is a fourth schematic diagram of a structure obtained by a method for fabricating a pixel structure according to an embodiment of the present disclosure.
  • FIG. 18 is a fifth schematic diagram of a structure obtained by a method for fabricating a pixel structure according to an embodiment of the present invention.
  • Embodiments of the present invention provide a pixel structure, a method of fabricating the same, an array substrate, and a display panel.
  • an embodiment of the present invention provides a pixel structure, which is arranged in an array. Multiple pixel units. Each of the pixel units includes a common electrode 21 and a pixel electrode 22 which are disposed on a different layer on the base substrate 11. The projection of the common electrode 21 on the base substrate 11 and the projection of the pixel electrode 22 on the base substrate 11 have no overlapping regions.
  • An insulating layer 13 may also be included between the common electrode 21 and the pixel electrode 22.
  • the projection of the common electrode on the substrate and the projection of the pixel electrode on the substrate have no overlapping regions, and are only one of the embodiments of the present invention.
  • the projection of the common electrode on the substrate and the projection of the pixel electrode on the substrate are sufficiently small and the mutual capacitance generated by the overlapping area is sufficiently small, which is also within the scope of protection of the embodiment of the present invention.
  • the pixel electrode and the common electrode are disposed in different layers, and the common electrode and the pixel electrode are designed such that the projection on the substrate substrate has no overlapping area, thereby reducing the common electrode and the pixel.
  • the storage capacitance between the electrodes increases the charging rate of the pixels.
  • the pixel electrode 22 and the common electrode 21 are both comb electrodes, and the pixel electrode 22 and the common electrode 21 are arranged in a finger structure.
  • the comb electrode 10 includes, for example, a strip electrode 101 and a connection electrode 102. There is a gap between two adjacent strip electrodes 101.
  • the connection electrode 102 connects the strip electrodes 101.
  • the structure shown in FIG. 4 can be referred to as a comb electrode.
  • the two comb electrodes are arranged opposite each other, and one strip electrode of the other comb electrode is disposed in the gap between the adjacent two strip electrodes 101 of one comb electrode, so that the two combs The electrodes do not overlap each other.
  • the structural arrangement shown in FIG. 3 can be referred to as a finger arrangement.
  • both the pixel electrode and the common electrode may be designed as a comb electrode, and the pixel electrode and the common electrode are arranged in a finger-finger structure, so that the projection of the pixel electrode and the common electrode on the substrate substrate has no overlapping area. Thereby, the storage capacitance generated between the pixel electrode and the common electrode is reduced, and the charging rate of the pixel is improved.
  • the comb electrodes of the pixel electrode and the common electrode provided in the embodiments of the present invention may be arranged in an interdigitated structure, which enables an electric field to be generated between the pixel electrode and the adjacent common electrode.
  • the pixel electrode and the common electrode can also be designed as comb electrodes, and the common electrode and the pixel electrode are arranged in an interdigitated structure. Thereby, an electric field can be generated between the pixel electrode and the adjacent common electrode, thereby driving the liquid crystal to be deflected for display.
  • the structure of the pixel electrode and the common electrode is equally applicable to the pixel structure in which the common electrode and the pixel electrode are disposed in the same layer.
  • each pixel unit 41 includes a first display area 411 and a second display area 412.
  • the pixel electrodes 22 in the first display region 411 and the comb electrodes of the common electrode 21 are all arranged in the same extending direction, and the pixel electrodes 22 in the second display region 412 and the comb electrodes of the common electrode 21 are all extended along the same direction.
  • Directions are arranged.
  • the direction in which the comb electrodes in the first display region 411 extend is different from the direction in which the comb electrodes in the second display region 412 extend.
  • the pixel unit is divided into two display areas, only to explain that the arrangement directions of the pixel electrode and the common electrode in the two display areas are different.
  • the arrangement direction of the pixel electrode and the common electrode in the pixel unit may be set to the same direction, and the two display areas included in the pixel unit are the same.
  • the area of the first display area and the second display area in the embodiment of the present invention may be the same or different. The present invention is not limited thereto.
  • FIG. 5 is only a schematic structural view showing the comb electrodes of the first display area and the second display area in one pixel unit extending in different directions, but this does not mean that the extension can only be performed in the direction shown in FIG. .
  • the comb electrodes in the first display area and the second display area may also extend in the same direction, which is not specifically limited in the present invention.
  • each pixel unit includes two display areas, that is, a first display area and a second display area, and the extension of the comb electrodes in the first display area and the second display area
  • the direction is different.
  • the extending direction of the comb electrodes of the first display regions of the adjacent two pixel units may be the same or different.
  • the extending direction of the comb electrodes of the second display regions of the adjacent two pixel units may be the same or different.
  • Fig. 5 only shows the extending direction of the comb electrodes of one pixel unit.
  • Fig. 6 shows the extending direction of the comb electrodes of two adjacent pixel units. Although FIG. 6 shows only two adjacent pixel units, a similar structure can be employed for other pixel units.
  • the extending direction of the comb electrode 10 in the first display region 411 of the left pixel unit is different from the extending direction of the comb electrode 10 in the first display region 411 of the right pixel unit, and the pixel unit on the left side Extension of the comb electrode 10 in the second display area 412
  • the extending direction is different from the extending direction of the comb electrodes 10 in the second display region 412 of the pixel unit on the right side, so that the direction of the electric field generated by each pixel unit shown in FIG. 6 is four different directions. Under the driving of the electric field, the deflection directions of the liquid crystals are different, thereby realizing the pixel design of the four-domain structure.
  • each of the pixel units may include two display areas, and the arrangement directions of the pixel electrodes and the common electrodes in each of the display areas are different, so that the display angle of view can be increased, and the color shift can be improved.
  • the pixel electrode 22 in each of the first display regions 411 of the plurality of pixel units and the comb electrodes of the common electrode 21 extend in the same direction, and each of the plurality of pixel units The direction in which the pixel electrodes 22 in the second display region 412 and the comb electrodes of the common electrode 21 extend are the same.
  • the comb electrodes in all the first display regions in the pixel structure extend in the same direction, and the comb electrodes in all the second display regions in the pixel structure extend in the other direction, and the first display region
  • the direction in which the comb electrodes are extended is different from the direction in which the comb electrodes in the second display region extend. Since the pixel structure includes two extending directions of the comb electrodes, an electric field in two directions can be generated to drive the liquid crystal for display.
  • the pixel electrode 22 of the first display region 411 of each pixel unit and the comb electrode of the common electrode 21 and the pixel electrode 22 and the common electrode of the second display region 412 The comb electrode of 21 is symmetrically distributed symmetrically with the intersection of the first display area 411 and the second display area 412.
  • the extending directions of the comb electrodes in the first display region and the second display region of each pixel unit may be distributed in an axisymmetric manner. This can increase the viewing angle and improve the color cast.
  • the pixel structure provided in FIG. 8 is structured in an "eight" shape.
  • a comb-shaped electrode in a first display region of one column of pixel units in each adjacent two columns of pixel units and a comb-shaped electrode in a first display region of another column of pixel units The extending direction is different, and the extending direction of the comb electrodes in the second display region of one column of pixel units in each adjacent two columns of pixel units is different from the extending direction of the comb electrodes in the second display region of the other column of pixel units.
  • the comb electrodes in the first display area of each pixel unit and the comb electrodes in the second display area are symmetrically distributed symmetrically at the intersection of the first display area and the second display area, and each adjacent two columns Pixel unit
  • the comb electrodes of the pixel electrode 22 and the common electrode 21 are symmetrically distributed symmetrically with the gap between the two columns of pixel units.
  • FIG. 9 is a schematic diagram of a pixel structure which is further improved on the basis of FIG. 8. More specifically, the comb electrodes in the first display area of each pixel unit and the comb electrodes in the second display area are symmetrically distributed with the intersection of the first display area and the second display area as symmetry axes, and at the same time The comb electrodes in each adjacent two columns of pixel units are symmetrically distributed symmetrically with the gap between the two columns of pixel units, so that a "m" shape distribution is present in the pixel structure.
  • the pixel structure of FIG. 9 may not be formed on the basis of the pixel structure of FIG. That is, only the comb electrodes in each adjacent two columns of pixel units are symmetrically distributed symmetrically with the gap between the two columns of pixel units.
  • the comb electrodes in each adjacent two columns of pixel units are symmetrically distributed symmetrically with the gap between the two columns of pixel units, which can make the display of the pixel structure more uniform, reduce the color shift, and increase the viewing angle of the display.
  • the pixel structure further includes a first common electrode line 211 at a boundary between the first display area 411 and the second display area 412 of each pixel unit.
  • the first common electrode line 211 connects the common electrode 21 in the adjacent first display region 411 and second display region 412.
  • the first common electrode line may be the same material as the common electrode.
  • the first common electrode line connects the common electrodes in the adjacent first display region and the second display region, thereby reducing the impedance of the common electrode.
  • an electric field may be caused at the boundary between the first display region and the second display region due to the absence of the common electrode. It weakens and appears to show weak areas.
  • the first common electrode line is disposed at the boundary of the first display area and the second display area, thereby alleviating or avoiding the problem of displaying the weak area in the portion.
  • the first common electrode line may be disposed at an edge position of the pixel unit, and the gate line is disposed in the same layer as the first common electrode line.
  • the gate line In order to prevent conduction between the gate line and the first common electrode line, it is necessary to space the first common electrode line and the gate line by a certain distance. This may cause a weak area to be displayed in the middle of each pixel unit, and the aperture ratio of the pixel unit is reduced due to the distance between the first common electrode line and the gate line.
  • the first common electrode line can be disposed in the pixel The junction of the first display area and the second display area of the unit. This can effectively alleviate or avoid the problem that the pixel unit appears to display a weak region, and the design of the pixel unit with respect to the first common electrode line can increase the aperture ratio of the pixel unit.
  • FIG. 11 is a cross-sectional view at the boundary between the first display area and the second display area.
  • the common electrode 21 and the first common electrode line 211 are sequentially disposed on the base substrate 11, and the first common electrode line 211 is located between the adjacent two common electrodes 21 and located adjacent to each other. Above the common electrode 21, the adjacent two common electrodes 21 are connected.
  • the pixel structure further includes an insulating layer 13 between the common electrode 21 and the pixel electrode 22.
  • each adjacent two columns of pixel units 41 constitute a pixel unit group 50, and the pixel units in each pixel unit group are different.
  • the pixel units in each pixel unit group share one data line 51.
  • a second common electrode line 212 is also included between each adjacent two pixel unit groups. The second common electrode line 212 is connected to the common electrode 21 of the two columns of pixel units adjacent to the second common electrode line 212.
  • the pixel structure can be divided into a single-gate arrangement of pixel structures and a dual-gate arrangement of pixel structures.
  • data lines and gate lines may be disposed between respective pixel units of the pixel structure.
  • the gate lines are located between each adjacent two rows of pixel cells, and the data lines are located between each adjacent two columns of pixel cells. That is, when there is a data line between each adjacent two columns of pixel units, the pixel structure is a pixel structure of a single gate arrangement.
  • each data line is used to provide a voltage signal to a pixel cell adjacent to the data line.
  • only the first common electrode line may be disposed.
  • a first common electrode line is disposed at a boundary between the first display area and the second display area in each pixel unit.
  • each adjacent two columns of pixel units constitute a pixel unit group.
  • the pixel structure is a double gated pixel structure.
  • each data line 51 is used to supply a voltage signal to two columns of pixel units 41 adjacent to the data line, but each adjacent two pixel unit groups There is no data line between them.
  • the common electrode of the two columns of pixel cells adjacent to the second common electrode line 212 may be connected through the second common electrode line 212, thereby reducing the resistance of the common electrode.
  • the number of the second common electrode lines may be plural.
  • a plurality of second common electrode lines may be disposed in the same layer as the gate lines. And, through multiple second public A plurality of via holes in the vicinity of the intersection of the common electrode line and the gate line electrically connect the plurality of second common electrode lines.
  • a plurality of second common electrode lines arranged vertically intersect with laterally disposed gate lines in order to prevent conduction between the two, it is possible to set a plurality of insulating layers on the plurality of second common electrode lines.
  • One via. The electrical connection of the plurality of second common electrode lines is achieved across the gate lines through a plurality of vias and a conductive layer (such as a pixel electrode or the like) overlying them.
  • the pixel electrode and the common electrode disposed in different layers are designed such that the projection on the substrate substrate has no overlapping area, thereby reducing the common electrode and the pixel electrode.
  • the storage capacitor between the pixels increases the charging rate of the pixel.
  • the pixel electrode and the common electrode may be designed as comb electrodes and arranged in a finger-finger structure such that projections of the pixel electrode and the common electrode on the substrate substrate have no overlapping regions.
  • Each pixel unit includes, for example, a first display area and a second display area.
  • the first display area includes comb electrodes extending in the same direction
  • the second display area includes comb electrodes extending in the other direction.
  • the pixel structure may further include a first common electrode line connecting the common electrodes in the first display area and the second display area at a boundary between the first display area and the second display area.
  • the first common electrode line alleviates or avoids the problem of displaying a weak zone. Since the first common electrode line is disposed at the boundary, the aperture ratio of the pixel is increased as compared with the case where the first common electrode line is disposed at the pixel edge position.
  • each pixel unit includes, for example, a first display area and a second display area.
  • the first display area includes comb electrodes extending in the same direction
  • the second display area includes comb electrodes extending in the other direction.
  • the pixel structure may further include a first common electrode line connecting the common electrodes in the first display area and the second display area at a boundary between the first display area and the second display area.
  • the first common electrode line alleviates or avoids the problem of displaying a weak zone. Since the first common electrode line is designed at the junction, the aperture ratio of the pixel is increased as compared with the case where the first common electrode line is designed at the pixel edge position.
  • Embodiments of the present invention also provide an array substrate, which may include the above pixel structure.
  • the array substrate in the embodiment of the present invention may also include the same The layer sets the pixel structure of the pixel electrode and the common electrode.
  • the embodiment of the invention further provides a display panel, which may include the above array substrate.
  • an embodiment of the present invention provides a method for fabricating a pixel structure, the method comprising:
  • the common electrode and the pixel electrode are sequentially formed on the base substrate, and the projection of the pixel electrode on the base substrate and the projection of the common electrode on the base substrate have no overlapping region, the common electrode and the pixel are After the electrode is formed, the storage capacitance between the two is reduced, thereby increasing the charging rate of the pixel.
  • forming a common electrode on the base substrate by using a patterning process in S1301 may include forming a common electrode by an exposure developing process using a mask plate, and the common electrode is a comb electrode.
  • the structure of the common electrode provided in the embodiment of the present invention may be the same as that of the common electrode described in Embodiment 1, and both are comb electrodes, and the comb electrodes of the common electrode may be arranged in different directions as described in Embodiment 1. cloth. Since the method of forming the common electrode is known to those skilled in the art, it can be completed by a process such as exposure development, and thus will not be described herein.
  • the pattern of the mask used to form the common electrode of the embodiment of the present invention may be the same pattern as the comb structure.
  • forming the pixel electrode in S1302 may include: forming a pixel electrode by an exposure and development process using a mask, the pixel electrode is a comb electrode, and the pixel electrode and the common electrode are arranged in a finger structure.
  • the structure of the pixel electrode provided in the embodiment of the present invention may be the same as that of the pixel electrode described in Embodiment 1, and each is a comb electrode, and the comb electrodes of the pixel electrode may be arranged in different directions as described in Embodiment 1. cloth. Since the method of forming the pixel electrode is known to those skilled in the art, it can be completed by a process such as exposure development, and thus will not be described herein.
  • the pattern of the mask used to form the pixel electrode of the embodiment of the present invention may be the same pattern as the comb structure.
  • the mask may be a halftone mask, gray tone Mask or mask with slits.
  • the method may further include forming a first common electrode line on the common electrode after forming the common electrode and before forming the pixel electrode.
  • a first common electrode line may be provided to connect the common electrodes extending in different directions, and the first common electrode line is located above the common electrode. Since the materials and methods for forming the first common electrode line can be the same as the materials and methods for forming the common electrode, they are not described herein again.
  • the method may further include forming the second common electrode line while forming the first common electrode line.
  • a second common electrode line may be disposed to connect the common electrode in the two columns of pixel units adjacent to the second common electrode line.
  • the second common electrode line may be formed while forming the first common electrode line.
  • the second common electrode line is disposed in the same layer as the first common electrode line. Since the gate lines are formed after the formation of the common electrode, the second common electrode lines may be disposed in the same layer as the gate lines. For example, each adjacent two columns of pixel units constitute a pixel unit group, and a second common electrode line is located between each adjacent two pixel unit groups.
  • the gate line is located between two adjacent rows of pixel units.
  • the number of the second common electrode lines may be plural.
  • a plurality of via holes may be formed in the insulating layer on the second common electrode line in the vicinity of the intersection of the gate line and the plurality of second common electrode lines.
  • the electrical connection of the plurality of second common electrode lines is achieved across the gate lines through a plurality of vias and a conductive layer (such as a pixel electrode or the like) overlying them.
  • a conductive layer such as a pixel electrode or the like
  • the method for fabricating the pixel structure provided by the embodiment of the present invention is described in detail by taking different layers of the common electrode and the pixel electrode as an example.
  • the method provided by the embodiment of the present invention is also applicable to the pixel structure in which the common electrode and the pixel electrode are disposed in the same layer, and details are not described herein again.
  • the pixel structure of the double gate arrangement is taken as an example to introduce a method for fabricating a pixel structure.
  • the method can include:
  • Step 1 On the glass substrate, a common electrode 21 as shown in FIG. 14 is formed by an exposure and development process using a mask.
  • Step 2 as shown in FIG. 15, a gate layer 53, a gate line 52, a first common electrode line 211, and a second common electrode line 212 are formed on the structure shown in FIG.
  • the first common electrode line 211 and the second common electrode line 212 are overlapped and electrically connected to the common electrode 21, respectively.
  • Step 3 as shown in FIG. 16, a gate insulating layer, an active layer, and a source/drain electrode layer are formed to form a thin film transistor 54.
  • Step 4 As shown in FIG. 17, a passivation layer is formed, and a via 55 is formed in the passivation layer by a dry etching process.
  • the source of the thin film transistor can be electrically connected to the pixel electrode formed later through the via 55.
  • a via 56 can be formed.
  • the electrical connection of the second common electrode lines at different locations can be achieved across the gate lines by a conductive layer (such as a pixel electrode or the like) that is then overlying the vias 56.
  • Step 5 As shown in FIG. 18, the pixel electrode 22 is formed, and the pixel electrode 22 is a comb electrode.
  • the projection of the pixel electrode 22 on the substrate substrate and the projection of the common electrode 21 on the substrate substrate have no overlapping regions.
  • the method for fabricating the above pixel structure provided by the embodiment of the present invention is described by taking a pixel structure of a double gate arrangement as an example. This fabrication method is equally applicable to a single-gate arrangement of pixel structures.
  • the extending direction of the comb electrodes is only described by taking the structure in which the comb electrodes of two adjacent pixel units are arranged in a “m” shape. This method is equally applicable to comb electrodes in other extending directions.
  • a common electrode is formed on the substrate by using a patterning process, and then a pixel electrode is formed, and the projection of the pixel electrode on the substrate and the common electrode are on the substrate.
  • the projection has no overlapping area.
  • the pixel electrode and the common electrode disposed in different layers are designed such that the projection on the substrate substrate has no overlapping area, thereby reducing the common electrode and the pixel electrode.
  • the storage capacitor between the pixels increases the charging rate of the pixel.
  • the pixel electrode and the common electrode may be designed as comb electrodes and arranged in a finger-finger structure such that projections of the pixel electrode and the common electrode on the substrate substrate have no overlapping regions.
  • Each pixel unit includes, for example, a first display area and a second display area.
  • the first display area includes comb electrodes extending in the same direction
  • the second display area includes comb electrodes extending in the other direction.
  • the pixel structure may further include a boundary between the first display area and the second display area, A first common electrode line connecting the common electrodes in the first display area and the second display area.
  • the first common electrode line alleviates or avoids the problem of displaying a weak zone. Since the first common electrode line is disposed at the boundary, the aperture ratio of the pixel is increased as compared with the case where the first common electrode line is disposed at the pixel edge position.

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Abstract

一种像素结构及其制作方法、阵列基板和显示面板，像素结构可以包括呈矩阵排布的多个像素单元，每一像素单元包括位于衬底基板（11）上异层设置的公共电极（21）和像素电极（22），公共电极（21）在衬底基板（11）上的投影和像素电极（22）在衬底基板（11）上的投影无重叠区域。

Description

像素结构及其制作方法、阵列基板和显示面板
相关申请
本申请要求享有2015年11月5日提交的中国发明专利申请No.201510745031.4的优先权，其全部公开内容通过引用并入本文。
技术领域
本发明涉及显示技术领域，尤其涉及一种像素结构及其制作方法、阵列基板和显示面板。
背景技术
在现有的ADS模式的像素结构中，像素电极和公共电极完全重叠，像素电极和公共电极之间的存储电容较高。
具体地，参见图1所示的像素结构。在衬底基板11上依次形成公共电极12、绝缘层13和像素电极14。公共电极12与像素电极14之间的重叠区域造成的存储电容较高，从而降低了像素的充电率。
综上所述，现有技术中的像素结构，像素电极和公共电极之间的存储电容较大，减小了像素的充电率。
发明内容
因此，所期望的是提供一种像素结构及其制作方法、阵列基板和显示面板，其能够减小像素电极和公共电极之间的存储电容，增大像素的充电率。
本发明实施例提供了一种像素结构，包括呈矩阵排布的多个像素单元，每一像素单元包括位于衬底基板上异层设置的公共电极和像素电极，所述公共电极在衬底基板上的投影和所述像素电极在衬底基板上的投影无重叠区域。
在本发明实施例提供的像素结构中，将异层设置的公共电极和像素电极设计为使其在衬底基板上的投影无重叠区域，从而减小了公共电极和像素电极之间的存储电容，增大了像素的充电率。
根据本发明的另一实施例，所述像素电极和公共电极均为梳状电极，且所述像素电极和公共电极呈插指结构排布。
根据本发明的另一实施例，每一像素单元包括第一显示区域和第二显示区域。在第一显示区域中的像素电极和公共电极的梳状电极均沿同一延伸方向排布，在第二显示区域中的像素电极和公共电极的梳状电极均沿同一延伸方向排布。在第一显示区域中的梳状电极的延伸方向与在第二显示区域中的梳状电极的延伸方向不同。
根据本发明的另一实施例，所述多个像素单元的各第一显示区域中的梳状电极的延伸方向均相同，所述多个像素单元的各第二显示区域中的梳状电极的延伸方向均相同。
根据本发明的另一实施例，每个像素单元的第一显示区域中的梳状电极与第二显示区域中的梳状电极以该第一显示区域和第二显示区域的交界处为对称轴对称分布。
根据本发明的另一实施例，每相邻两列像素单元中一列像素单元的第一显示区域中梳状电极的延伸方向与另一列像素单元的第一显示区域中梳状电极的延伸方向不同，每相邻两列像素单元中一列像素单元的第二显示区域中梳状电极的延伸方向与另一列像素单元的第二显示区域中梳状电极的延伸方向不同。
根据本发明的另一实施例，每个像素单元的第一显示区域中的梳状电极与第二显示区域中的梳状电极以该第一显示区域和第二显示区域的交界处为对称轴对称分布，且每相邻两列像素单元中的梳状电极以所述两列像素单元之间的空隙为对称轴对称分布。
根据本发明的另一实施例，所述像素结构还包括位于每个像素单元的第一显示区域和第二显示区域交界处的第一公共电极线，所述第一公共电极线连接相邻的第一显示区域和第二显示区域中的公共电极。
根据本发明的另一实施例，每相邻两列像素单元构成像素单元组，且每一像素单元组中的像素单元不同。每一像素单元组中的像素单元共用一根数据线，每相邻两个像素单元组之间还包括第二公共电极线，所述第二公共电极线连接与该第二公共电极线相邻的两列像素单元中的公共电极。
根据本发明的另一实施例，所述第二公共电极线的数目为多条，所述多条第二公共电极线与栅线同层设置，并且，通过在所述多条第二公共电极线与所述栅线的交叉位置附近的多个过孔，电连接所述多 条第二公共电极线。
本发明实施例还提供了一种阵列基板，包括上述像素结构。
本发明实施例还提供了一种显示面板，包括上述阵列基板。
本发明实施例还提供了一种上述像素结构的制作方法，该方法包括：采用构图工艺在衬底基板上形成公共电极；形成像素电极，且所述像素电极在衬底基板上的投影与所述公共电极在衬底基板上的投影无重叠区域。
根据本发明的另一实施例，采用构图工艺在衬底基板上形成公共电极包括：采用掩膜板通过曝光显影工艺形成公共电极，所述公共电极为梳状电极。
根据本发明的另一实施例，形成像素电极包括：采用掩膜板通过曝光显影工艺形成像素电极，所述像素电极为梳状电极，且所述像素电极与所述公共电极呈插指结构排布。
根据本发明的另一实施例，所述掩膜板为半色调掩膜板、灰色调掩膜板或具有狭缝的掩膜板。
根据本发明的另一实施例，在形成公共电极之后且在形成像素电极之前，该方法还包括：在所述公共电极上形成第一公共电极线。
根据本发明的另一实施例，该方法还包括：在形成第一公共电极线的同时，形成第二公共电极线。
附图说明
图1为现有技术提供的一种像素结构的结构示意图；
图2为本发明实施例提供的一种像素结构的结构示意图；
图3为本发明实施例提供的一种像素电极和公共电极的结构示意图；
图4为本发明实施例提供的一种梳状电极的结构示意图；
图5为本发明实施例提供的一种像素电极和公共电极的排布方向的结构示意图；
图6为本发明实施例提供的另一种像素电极和公共电极的排布方向的结构示意图；
图7为本发明实施例提供的第三种像素电极和公共电极的排布方向的结构示意图；
图8为本发明实施例提供的第四种像素电极和公共电极的排布方向的结构示意图；
图9为本发明实施例提供的第五种像素电极和公共电极的排布方向的结构示意图；
图10为本发明实施例提供的另一种像素结构的结构示意图；
图11为本发明实施例提供的一种像素结构的截面示意图；
图12为本发明实施例提供的另一种像素结构的结构示意图；
图13为本发明实施例提供的一种像素结构的制作方法的流程示意图；
图14为本发明实施例提供的通过像素结构的制作方法得到的结构的示意图之一；
图15为本发明实施例提供的通过像素结构的制作方法得到的结构的示意图之二；
图16为本发明实施例提供的通过像素结构的制作方法得到的结构的示意图之三；
图17为本发明实施例提供的通过像素结构的制作方法得到的结构的示意图之四；
图18为本发明实施例提供的通过像素结构的制作方法得到的结构的示意图之五。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明的实施例作进一步地详细描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
附图中各膜层的厚度和区域的大小形状不反映像素结构和阵列基板各部件的真实比例，目的只是示意说明本发明内容。
本发明实施例提供了一种像素结构及其制作方法、阵列基板和显示面板。
实施例1
参见图2，本发明实施例提供了一种像素结构，包括呈阵列排布的 多个像素单元。每一像素单元包括位于衬底基板11上异层设置的公共电极21和像素电极22。公共电极21在衬底基板11上的投影和像素电极22在衬底基板11上的投影无重叠区域。
公共电极21和像素电极22之间还可以包括绝缘层13。
需要说明的是，公共电极在衬底基板上的投影和像素电极在衬底基板上的投影无重叠区域，仅是本发明的实施例之一。公共电极在衬底基板上的投影和像素电极在衬底基板上的投影足够小且重叠的面积产生的互电容足够小，也属于本发明实施例的保护范围。
在本发明实施例提供的像素结构中，像素电极和公共电极不同层设置，且将公共电极和像素电极设计为使其在衬底基板上的投影无重叠区域，从而减小了公共电极和像素电极之间的存储电容，增大了像素的充电率。
根据本发明的另一实施例，参见图3，像素电极22和公共电极21均为梳状电极，且像素电极22和公共电极21呈插指结构排布。
需要说明的是，参见图4，梳状电极10例如包括条状电极101和连接电极102。相邻两个条状电极101之间存在缝隙。连接电极102将条状电极101进行连接。例如图4所示的结构可以称为梳状电极。再次参见图3，将两个梳状电极相对排列，且在一个梳状电极的相邻两个条状电极101之间的缝隙中设置另一个梳状电极的一个条状电极，使得两个梳状电极相互之间没有重叠。例如图3所示的结构排布方式可以称为插指结构排布。
具体地，可以将像素电极和公共电极均设计为梳状电极，且像素电极和公共电极呈插指结构排布，从而使得像素电极和公共电极在衬底基板上的投影无重叠区域。由此，减少了像素电极和公共电极之间产生的存储电容，提高了像素的充电率。
本发明实施例中提供的像素电极和公共电极的梳状电极，可以呈插指结构排布，这使得像素电极与相邻的公共电极之间能够产生电场。需要强调的是，当像素电极和公共电极为同层设置时，同样可以将像素电极和公共电极设计为梳状电极，且公共电极和像素电极呈插指结构排布。由此，使得像素电极与相邻的公共电极之间能够产生电场，从而驱动液晶偏转以进行显示。
需要说明的是，在下面的实施例中对像素电极和公共电极结构的 改变，以及对梳状电极的延伸方向的改变同样适用于同层设置公共电极和像素电极的像素结构。
根据本发明的另一实施例，参见图5，每一像素单元41包括第一显示区域411和第二显示区域412。在第一显示区域411中的像素电极22和公共电极21的梳状电极均沿同一延伸方向排布，在第二显示区域412中的像素电极22和公共电极21的梳状电极均沿同一延伸方向排布。在第一显示区域411中的梳状电极的延伸方向与在第二显示区域412中的梳状电极的延伸方向不同。
需要说明的是，本发明实施例中将像素单元分为两个显示区域，只是为了说明两个显示区域中的像素电极和公共电极的排布方向不同。当然，也可以将像素单元中的像素电极和公共电极的排布方向设置成同一个方向，则像素单元所包括的两个显示区域均相同。本发明实施例中的第一显示区域和第二显示区域的面积大小可以相同，也可以不相同，本发明不做具体限定。
参见图5，每一像素单元的第一显示区域411中的梳状电极的延伸方向和第二显示区域412中的梳状电极的延伸方向不同，从而使得每一像素单元呈现双畴结构。图5中仅示出了一个像素单元中的第一显示区域和第二显示区域的梳状电极沿着不同方向延伸的结构示意图，但这不代表只能按照图5中所示的方向进行延伸。当然，第一显示区域和第二显示区域中的梳状电极也可以按照相同的方向进行延伸，本发明不做具体限定。
需要说明的是，根据本发明的实施例，每一像素单元包括两个显示区域，即第一显示区域和第二显示区域，且第一显示区域和第二显示区域中的梳状电极的延伸方向不同。相邻的两个像素单元中的第一显示区域的梳状电极的延伸方向可以相同，也可以不同。相邻的两个像素单元中的第二显示区域的梳状电极的延伸方向可以相同，也可以不同。图5仅示出了一个像素单元的梳状电极的延伸方向。图6示出了相邻的两个像素单元的梳状电极的延伸方向。尽管图6仅示出了相邻的两个像素单元，但对于其他的像素单元，可以采用类似的结构。在图6中，左边的像素单元的第一显示区域411中的梳状电极10的延伸方向与右边的像素单元的第一显示区域411中的梳状电极10的延伸方向不同，左边的像素单元的第二显示区域412中的梳状电极10的延 伸方向与右边的像素单元的第二显示区域412中的梳状电极10的延伸方向不同，从而使得图6所示的各像素单元产生的电场的方向为四个不同的方向。在该电场的驱动下，液晶的偏转方向不同，从而实现了四畴结构的像素设计。
根据本发明的另一实施例，每一像素单元可以包括两个显示区域，且每一显示区域中的像素电极和公共电极的排布方向不同，从而能够增大显示视角，改善色偏。
根据本发明的另一实施例，参见图7，多个像素单元的各第一显示区域411中的像素电极22和公共电极21的梳状电极的延伸方向均相同，多个像素单元的各第二显示区域412中的像素电极22和公共电极21的梳状电极的延伸方向均相同。
具体地，像素结构中的所有第一显示区域中的梳状电极均沿同一个方向延伸，像素结构中的所有第二显示区域中的梳状电极均沿另一个方向延伸，且第一显示区域中的梳状电极的延伸方向与第二显示区域中的梳状电极的延伸方向不同。由于像素结构包含了梳状电极的两个延伸方向，因而能够产生两个方向的电场来驱动液晶进行显示。
图7中仅示出了第一显示区域和第二显示区域中的梳状电极的延伸方向不同，但本发明不局限于仅沿着这两个方向进行延伸。
根据本发明的另一实施例，参见图8，每个像素单元的第一显示区域411中的像素电极22和公共电极21的梳状电极与第二显示区域412中的像素电极22和公共电极21的梳状电极以第一显示区域411和第二显示区域412的交界处为对称轴对称分布。
为了使像素结构的显示均匀，可以使每一像素单元的第一显示区域和第二显示区域中的梳状电极的延伸方向成轴对称分布。这可以增加视角，改善色偏。例如，图8中提供的像素结构成“八”字形结构。
根据本发明的另一实施例，参见图9，每相邻两列像素单元中一列像素单元的第一显示区域中梳状电极的延伸方向与另一列像素单元的第一显示区域中梳状电极的延伸方向不同，每相邻两列像素单元中一列像素单元的第二显示区域中梳状电极的延伸方向与另一列像素单元的第二显示区域中梳状电极的延伸方向不同。每个像素单元的第一显示区域中的梳状电极与第二显示区域中的梳状电极以该第一显示区域和第二显示区域的交界处为对称轴对称分布，且每相邻两列像素单元 中的像素电极22和公共电极21的梳状电极以该两列像素单元之间的空隙为对称轴对称分布。
需要说明的是，图9是在图8的基础上进行进一步改进的像素结构示意图。更具体而言，使每一像素单元的第一显示区域中的梳状电极和第二显示区域中的梳状电极以第一显示区域和第二显示区域的交界为对称轴对称分布，同时使每相邻两列像素单元中的梳状电极以该两列像素单元之间的空隙为对称轴对称分布，从而使得像素结构中呈现了“米”字形状分布。
此外，在像素结构的设计中，也可以不在图8的像素结构基础上形成图9的像素结构。即，仅使每相邻两列像素单元中的梳状电极以该两列像素单元之间的空隙为对称轴对称分布。
将每相邻两列像素单元中的梳状电极以该两列像素单元之间的空隙为对称轴对称分布，可以使得像素结构的显示更加均匀，并减少色偏，增大显示的视角。
根据本发明的另一实施例，参见图10，像素结构还包括位于每个像素单元的第一显示区域411和第二显示区域412交界处的第一公共电极线211。第一公共电极线211连接相邻的第一显示区域411和第二显示区域412中的公共电极21。
需要说明的是，第一公共电极线可以与公共电极的材料相同。第一公共电极线连接相邻的第一显示区域和第二显示区域中的公共电极，从而减小了公共电极的阻抗。另外，由于在第一显示区域和第二显示区域中的公共电极的梳状电极的延伸方向不同，因此在第一显示区域和第二显示区域的交界处可能会因为不存在公共电极而导致电场变弱，出现显示弱区。本发明实施例中将第一公共电极线设置在第一显示区域和第二显示区域的交界处，从而减轻或避免在该部分出现显示弱区的问题。
可以将第一公共电极线设置在像素单元的边缘位置，且将栅线与第一公共电极线同层设置。为了防止栅线与第一公共电极线之间导通，需要使第一公共电极线和栅线之间间隔一定距离。这有可能造成每一像素单元中间存在显示弱区，并且由于第一公共电极线与栅线之间的距离而减小了像素单元的开口率。
因此，根据本发明的实施例，可以将第一公共电极线设置在像素 单元的第一显示区域和第二显示区域的交界处。这可以有效地减轻或避免像素单元出现显示弱区的问题，并且相对于第一公共电极线靠近栅线的设计可提高像素单元的开口率。
具体地，为了更加清楚地了解第一公共电极线的位置，参见图11，其为第一显示区域和第二显示区域交界处的截面图。如图11所示，在衬底基板11上依次设置公共电极21和第一公共电极线211，且第一公共电极线211位于相邻的两个公共电极21之间并位于相邻的两个公共电极21之上，用于连接该相邻的两个公共电极21。像素结构还包括在公共电极21和像素电极22之间的绝缘层13。
根据本发明的另一实施例，参见图12，每相邻两列像素单元41构成像素单元组50，且每一像素单元组中的像素单元不同。每一像素单元组中的像素单元共用一根数据线51。每相邻两个像素单元组之间还包括第二公共电极线212。第二公共电极线212连接与第二公共电极线212相邻的两列像素单元中的公共电极21。
一般地，像素结构可以分为单栅极排布的像素结构和双栅极排布的像素结构。具体地，可以在像素结构的各像素单元之间设置数据线和栅线。对于单栅极排布的像素结构，栅线位于每相邻两行像素单元之间，且数据线位于每相邻两列像素单元之间。即，当每相邻两列像素单元之间均存在数据线时，该像素结构为单栅极排布的像素结构。在单栅极排布的像素结构中，每一数据线用于向与该数据线相邻的一个像素单元提供电压信号。在单栅极排布的像素结构中，可以仅设置第一公共电极线。例如，如图10所示，在每一像素单元中的第一显示区域和第二显示区域之间的交界处设置第一公共电极线。而对于双栅极排布的像素结构，例如参见图12。如图12所示，每相邻两列像素单元构成像素单元组。当每一像素单元组50中的像素单元共用一根数据线51时，该像素结构为双栅极排布的像素结构。在图12所示的双栅极排布的像素结构中，每一数据线51用于向与该数据线相邻的两列像素单元41提供电压信号，但每相邻两个像素单元组之间不存在数据线。可以通过第二公共电极线212将与第二公共电极线212相邻的两列像素单元中的公共电极连接，从而减小公共电极的阻值。
根据本发明的另一实施例，第二公共电极线的数目可以为多条。多条第二公共电极线可以与栅线同层设置。并且，通过在多条第二公 共电极线与栅线的交叉位置附近的多个过孔，电连接多条第二公共电极线。
例如，当竖向排布的多条第二公共电极线与横向设置的栅线存在交叉时，为了防止两者之间导通，可以在多条第二公共电极线上的绝缘层中设置多个过孔。通过多个过孔及其上覆盖的导电层(如像素电极等)，跨过栅线实现多条第二公共电极线的电连接。
综上所述，在本发明实施例提供的像素结构中，将异层设置的像素电极和公共电极设计为使其在衬底基板上的投影无重叠区域，从而减小了公共电极和像素电极之间的存储电容，提高了像素的充电率。例如，可以将像素电极和公共电极设计为梳状电极，且呈插指结构排布，使得像素电极和公共电极在衬底基板上的投影无重叠区域。每一像素单元例如包括第一显示区域和第二显示区域。第一显示区域包括沿着同一方向延伸的梳状电极，第二显示区域包括沿着另一方向延伸的梳状电极。由此，能够增加像素单元的显示视角，并改善色偏。另外，像素结构还可以包括位于第一显示区域和第二显示区域交界处的、连接第一显示区域和第二显示区域中的公共电极的第一公共电极线。第一公共电极线减轻或避免了显示弱区的问题。由于第一公共电极线设置在交界处，因此，相比于将第一公共电极线设置在像素边缘位置的情形，增大了像素的开口率。
需要说明的是，当像素电极和公共电极同层设置时，也可以将像素电极和公共电极设计为本发明实施例提供的梳状电极，且像素电极和公共电极呈插指结构排布。具体地，每一像素单元例如包括第一显示区域和第二显示区域。第一显示区域包括沿同一方向延伸的梳状电极，第二显示区域包括沿着另一方向延伸的梳状电极。由此，能够增加像素单元的显示视角，并改善色偏，达到多畴显示的效果。另外，像素结构还可以包括位于第一显示区域和第二显示区域交界处的、连接第一显示区域和第二显示区域中的公共电极的第一公共电极线。第一公共电极线减轻或避免了显示弱区的问题。由于第一公共电极线设计在交界处，因此，相比于将第一公共电极线设计在像素边缘位置的情形，增大了像素的开口率。
本发明实施例还提供了一种阵列基板，其可以包括上述像素结构。
需要说明的是，本发明实施例中的阵列基板，也可以包括其中同 层设置像素电极和公共电极的像素结构。
本发明实施例还提供了一种显示面板，其可以包括上述阵列基板。
实施例2
下面详细描述如何制作根据本发明实施例的像素结构。
参见图13，本发明实施例提供了一种像素结构的制作方法，该方法包括：
S1301、采用构图工艺在衬底基板上形成公共电极；
S1302、形成像素电极，且像素电极在衬底基板上的投影与公共电极在衬底基板上的投影无重叠区域。
需要说明的是，由于在衬底基板上依次形成公共电极和像素电极，且像素电极在衬底基板上的投影和公共电极在衬底基板上的投影无重叠区域，因此，在公共电极和像素电极形成之后，两者之间的存储电容减小，从而提高了像素的充电率。
根据本发明的另一实施例，S1301中采用构图工艺在衬底基板上形成公共电极可以包括：采用掩膜板通过曝光显影工艺形成公共电极，公共电极为梳状电极。
本发明实施例中提供的公共电极的结构可以与实施例1中描述的公共电极的结构相同，均为梳状电极，且公共电极的梳状电极可以如实施例1中所述按照不同方向排布。由于形成公共电极的方法为本领域技术人员已知，可以通过曝光显影等工艺完成，因此此处不再赘述。用于形成本发明实施例的公共电极的掩膜板的图形可以是与梳状结构相同的图形。
根据本发明的另一实施例，S1302中形成像素电极可以包括：采用掩膜板通过曝光显影工艺形成像素电极，像素电极为梳状电极，且像素电极与公共电极呈插指结构排布。
本发明实施例中提供的像素电极的结构可以与实施例1中描述的像素电极的结构相同，均为梳状电极，且像素电极的梳状电极可以如实施例1中所述按照不同方向排布。由于形成像素电极的方法与为本领域技术人员所知，可以通过曝光显影等工艺完成，因此此处不再赘述。用于形成本发明实施例的像素电极的掩膜板的图形可以是与梳状结构相同的图形。
根据本发明的另一实施例，掩膜板可以为半色调掩膜板、灰色调 掩膜板或具有狭缝的掩膜板。
根据本发明的另一实施例，在形成公共电极之后且在形成像素电极之前，该方法还可以包括在公共电极上形成第一公共电极线。
需要说明的是，在公共电极形成之后，沿着两个不同方向延伸的公共电极的梳状电极存在交界处。为了防止公共电极在交界处产生较大的电阻，可以设置第一公共电极线来连接沿不同方向延伸的公共电极，且该第一公共电极线位于公共电极之上。由于形成第一公共电极线的材料和方法可以与形成公共电极的材料和方法相同，因此此处不再赘述。
根据本发明的另一实施例，该方法还可以包括在形成第一公共电极线的同时，形成第二公共电极线。
需要说明的是，对于双栅极排布的像素结构，可以设置第二公共电极线来连接与该第二公共电极线相邻的两列像素单元中的公共电极。可以在形成第一公共电极线的同时，形成第二公共电极线。第二公共电极线与第一公共电极线同层设置。因为在形成公共电极后形成栅线，所以第二公共电极线可以与栅线同层设置。例如，每相邻两列像素单元构成像素单元组，第二公共电极线位于每相邻两个像素单元组之间。栅线位于相邻两行像素单元之间。第二公共电极线的数目可以为多条。可以在栅线与多条第二公共电极线的交叉位置附近，在第二公共电极线上的绝缘层中形成多个过孔。通过多个过孔及其上覆盖的导电层(如像素电极等)，跨过栅线实现多条第二公共电极线的电连接。由此，可以使栅线和第二公共电极线绝缘。
需要说明的是，本发明实施例提供的像素结构的制作方法，只是以公共电极和像素电极不同层设置为例进行详细描述。对于公共电极和像素电极同层设置的像素结构，本发明实施例提供的方法同样适用，此处不再赘述。
为了更加详细地说明本发明实施例提供的像素结构的制作方法，下面通过具体实例进行描述。
下面以双栅极排布的像素结构为例，介绍一种像素结构的制作方法。该方法可以包括：
步骤一、在玻璃基板上，采用掩膜板通过曝光显影工艺形成如图14所示的公共电极21。
步骤二、如图15所示，在图14所示的结构上形成栅极层53、栅线52、第一公共电极线211和第二公共电极线212。第一公共电极线211、第二公共电极线212分别与公共电极21交叠且电连接。
步骤三、如图16所示，形成栅绝缘层、有源层和源漏电极层，以形成薄膜晶体管54。
步骤四、如图17所示，形成钝化层，并采用干刻工艺在钝化层中形成过孔55。可以通过过孔55使薄膜晶体管的源极与之后形成的像素电极电连接。此外，可以形成过孔56。可以通过之后在该过孔56上覆盖的导电层(如像素电极等)，跨过栅线实现不同位置的第二公共电极线的电连接。
步骤五、如图18所示，形成像素电极22，且像素电极22为梳状电极。像素电极22在衬底基板上的投影与公共电极21在衬底基板上的投影无重叠区域。
需要说明的是，本发明实施例提供的上述像素结构的制作方法，仅是以双栅极排布的像素结构为例进行描述的。对于单栅极排布的像素结构，该制作方法同样适用。本发明实施例提供的像素结构中，梳状电极的延伸方向仅是以相邻两个像素单元的梳状电极呈“米”字型排布的结构为例进行描述的。对于其他延伸方向的梳状电极，该制作方法同样适用。
在本发明实施例提供的像素结构的制作方法中，首先采用构图工艺在衬底基板上形成公共电极，之后形成像素电极，且像素电极在衬底基板上的投影与公共电极在衬底基板上的投影无重叠区域。由此，减小了像素电极和公共电极之间的存储电容，提高了像素的充电率。
综上所述，在本发明实施例提供的像素结构中，将异层设置的像素电极和公共电极设计为使其在衬底基板上的投影无重叠区域，从而减小了公共电极和像素电极之间的存储电容，提高了像素的充电率。例如，可以将像素电极和公共电极设计为梳状电极，且呈插指结构排布，使得像素电极和公共电极在衬底基板上的投影无重叠区域。每一像素单元例如包括第一显示区域和第二显示区域。第一显示区域包括沿着同一方向延伸的梳状电极，第二显示区域包括沿着另一方向延伸的梳状电极。由此，能够增加像素单元的显示视角，并改善色偏。另外，像素结构还可以包括位于第一显示区域和第二显示区域交界处的、 连接第一显示区域和第二显示区域中的公共电极的第一公共电极线。第一公共电极线减轻或避免了显示弱区的问题。由于第一公共电极线设置在交界处，因此，相比于将第一公共电极线设置在像素边缘位置的情形，增大了像素的开口率。
显然，本领域的技术人员可以对本发明的实施例进行各种改动和变型而不脱离本发明的精神和范围。因此，倘若对于本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (18)

  1. 一种像素结构，包括呈矩阵排布的多个像素单元，每一像素单元包括位于衬底基板上异层设置的公共电极和像素电极，其中，所述公共电极在衬底基板上的投影和所述像素电极在衬底基板上的投影无重叠区域。
  2. 根据权利要求1所述的像素结构，其中，所述像素电极和所述公共电极均为梳状电极，且所述像素电极和所述公共电极呈插指结构排布。
  3. 根据权利要求2所述的像素结构，其中，每一像素单元包括第一显示区域和第二显示区域；
    在第一显示区域中的像素电极和公共电极的梳状电极均沿同一延伸方向排布，在第二显示区域中的像素电极和公共电极的梳状电极均沿同一延伸方向排布；
    在第一显示区域中的梳状电极的延伸方向与在第二显示区域中的梳状电极的延伸方向不同。
  4. 根据权利要求3所述的像素结构，其中，所述多个像素单元的各第一显示区域中的梳状电极的延伸方向均相同，所述多个像素单元的各第二显示区域中的梳状电极的延伸方向均相同。
  5. 根据权利要求4所述的像素结构，其中，每个像素单元的第一显示区域中的梳状电极与第二显示区域中的梳状电极以该第一显示区域和第二显示区域的交界处为对称轴对称分布。
  6. 根据权利要求3所述的像素结构，其中，每相邻两列像素单元中一列像素单元的第一显示区域中梳状电极的延伸方向与另一列像素单元的第一显示区域中梳状电极的延伸方向不同，每相邻两列像素单元中一列像素单元的第二显示区域中梳状电极的延伸方向与另一列像素单元的第二显示区域中梳状电极的延伸方向不同。
  7. 根据权利要求6所述的像素结构，其中，每个像素单元的第一显示区域中的梳状电极与第二显示区域中的梳状电极以该第一显示区域和第二显示区域的交界处为对称轴对称分布，且每相邻两列像素单元中的梳状电极以所述两列像素单元之间的空隙为对称轴对称分布。
  8. 根据权利要求7所述的像素结构，还包括位于每个像素单元的 第一显示区域和第二显示区域交界处的第一公共电极线，其中，所述第一公共电极线连接相邻的第一显示区域和第二显示区域中的公共电极。
  9. 根据权利要求8所述的像素结构，其中，每相邻两列像素单元构成像素单元组，且每一像素单元组中的像素单元不同，其中，每一像素单元组中的像素单元共用一根数据线，每相邻两个像素单元组之间还包括第二公共电极线，所述第二公共电极线连接与该第二公共电极线相邻的两列像素单元中的公共电极。
  10. 根据权利要求9所述的像素结构，其中，所述第二公共电极线的数目为多条，所述多条第二公共电极线与栅线同层设置，并且，通过在所述多条第二公共电极线与所述栅线的交叉位置附近的多个过孔，电连接所述多条第二公共电极线。
  11. 一种阵列基板，包括如权利要求1-10中任一项所述的像素结构。
  12. 一种显示面板，包括如权利要求11所述的阵列基板。
  13. 一种如权利要求1-10中任一项所述的像素结构的制作方法，包括：
    采用构图工艺在衬底基板上形成公共电极；
    形成像素电极，且所述像素电极在衬底基板上的投影与所述公共电极在衬底基板上的投影无重叠区域。
  14. 根据权利要求13所述的方法，其中，采用构图工艺在衬底基板上形成公共电极包括：
    采用掩膜板通过曝光显影工艺形成公共电极，所述公共电极为梳状电极。
  15. 根据权利要求14所述的方法，其中，形成像素电极包括：
    采用掩膜板通过曝光显影工艺形成像素电极，所述像素电极为梳状电极，且所述像素电极与所述公共电极呈插指结构排布。
  16. 根据权利要求14或15所述的方法，其中，所述掩膜板为半色调掩膜板、灰色调掩膜板或具有狭缝的掩膜板。
  17. 根据权利要求15所述的方法，其中，在形成公共电极之后且在形成像素电极之前，该方法还包括：
    在所述公共电极上形成第一公共电极线。
  18. 根据权利要求17所述的方法，还包括：在形成第一公共电极线的同时，形成第二公共电极线。
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