WO2019085700A1 - 阵列基板及其制造方法和显示装置及其制造方法 - Google Patents

阵列基板及其制造方法和显示装置及其制造方法 Download PDF

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WO2019085700A1
WO2019085700A1 PCT/CN2018/107968 CN2018107968W WO2019085700A1 WO 2019085700 A1 WO2019085700 A1 WO 2019085700A1 CN 2018107968 W CN2018107968 W CN 2018107968W WO 2019085700 A1 WO2019085700 A1 WO 2019085700A1
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sub
line
drain
pixel
drain extension
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PCT/CN2018/107968
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English (en)
French (fr)
Inventor
龙春平
吴新银
乔勇
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京东方科技集团股份有限公司
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Priority to EP18873105.3A priority Critical patent/EP3705935B1/en
Priority to US16/343,964 priority patent/US11314135B2/en
Publication of WO2019085700A1 publication Critical patent/WO2019085700A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present disclosure belongs to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • Display panels have been used extensively as display screens for consumer electronics such as cell phones, notebook computers, personal computers, and personal digital assistants.
  • the display panel includes an active matrix array substrate in which each active component adjusts the beam intensity to display an image.
  • the existing array substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel units electrically connected to the corresponding gate lines and the data lines; each of the pixel units individually controls the light transmittance by the transistors.
  • the liquid crystal display includes twisted nematic (TN), Fringe Field Switching (FFS), In-Plane Switching (IPS), and vertical alignment (VA) modes.
  • TN twisted nematic
  • FFS Fringe Field Switching
  • IPS In-Plane Switching
  • VA vertical alignment
  • the FFS, IPS, and VA modes are wide viewing angle liquid crystal display technologies, and the multi-domain design pixel structure is often used, which is advantageous for increasing the viewing angle.
  • the present disclosure provides an array substrate comprising: a plurality of data lines and a plurality of signal lines disposed in a cross, the signal lines including a first signal line and a second signal line, adjacent first signal lines and adjacent ones
  • the area enclosed by the data line is a pixel area, the pixel area includes a thin film transistor including a drain, each of the sub-pixel units has a sub-pixel electrode, and each sub-pixel electrode and film a drain of the transistor is electrically connected; and a drain extension line is disposed in the pixel region, electrically connected to the drain and located between the sub-pixel units.
  • the drain extension line has via holes, and each of the sub-pixel electrodes is electrically connected to the drain extension line through the via hole.
  • the drain extension line is disposed in parallel with the data line, and the drain extension line has a width of 2-20 microns.
  • one of the first signal line and the second signal line is a scan line, and the other is a common electrode line;
  • a gate of the thin film transistor is connected to a scan line, and a source of the thin film transistor is connected to the data line.
  • the sub-pixel unit further includes a sub-common electrode connected to the common electrode line, wherein the sub-common electrode is disposed in the same layer as the sub-pixel electrode.
  • At least one of the sub-pixel electrode and the sub-common electrode is a comb electrode
  • the comb electrode includes a plurality of strip-shaped comb teeth arranged in parallel, and the comb teeth and the common electrode line The angle between them is greater than 0° and less than 90°.
  • the angle between the comb teeth and the common electrode line is greater than 30° and less than 60°.
  • the comb teeth have the same width and the spacing between the comb teeth is the same.
  • the principle of the drain extension line is that the end projection of the drain overlaps the orthographic projection of the common electrode line.
  • a position of the common electrode line overlapping the orthographic projection of the drain extension line is convex toward the drain.
  • the present disclosure provides a display device including the above array substrate.
  • the present disclosure provides a method of fabricating an array substrate, comprising:
  • the signal lines include a first signal line and a second signal line, and an area surrounded by the adjacent first signal lines and adjacent data lines is a pixel area;
  • the thin film transistor including a drain, each of the sub-pixel units having a sub-pixel electrode, and a sub-pixel electrode of the sub-pixel unit and a thin film transistor Extremely electrical connection;
  • a drain extension line is formed in the sub-pixel region such that the drain extension line is electrically connected to the drain and is located between the sub-pixel units.
  • the step of forming a drain extension line in the sub-pixel region further includes:
  • the drain is formed in the same layer as the drain extension line.
  • the step of forming a drain extension line in the sub-pixel region further includes:
  • the drain and the drain extension are formed in different layers.
  • the step of forming a drain extension line in the sub-pixel region further includes:
  • the sub-pixel electrode is electrically connected to the drain extension line through the via.
  • one of the first signal line and the second signal line is a scan line, and the other is a common electrode line, a gate of the thin film transistor is connected to a scan line, and a source connection of the thin film transistor is The data line, wherein the step of forming a drain extension line in the sub-pixel region further comprises:
  • the drain extension line is formed such that an orthographic projection of the end away from the drain overlaps with an orthographic projection of the common electrode line.
  • the step of forming a plurality of signal lines further includes:
  • the common electrode line is formed to protrude toward the drain at a position overlapping with an orthographic projection of an end of the drain extension line away from the drain.
  • the present disclosure provides a method of manufacturing a display device including the above-described method of fabricating an array substrate.
  • FIG. 1 is a schematic structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 are schematic structural diagrams of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a flow chart of a method of fabricating an array substrate in accordance with an embodiment of the present disclosure.
  • the reference numerals are: 11, the drain; 12, the source; the sub-pixel unit; 21, the sub-pixel electrode; 22, the sub-common electrode; 3, the drain extension line; 31, the first via; , scan line; 42, data line; 43, common electrode line.
  • the electric field at the domain boundary is disordered, and light leakage or an aperture ratio is likely to be lowered.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIG. 1 , including a plurality of intersecting data lines 42 and signal lines, the signal lines including a first signal line and a second signal line, and a second signal line Provided between adjacent first signal lines, an area surrounded by adjacent first signal lines and adjacent data lines is a pixel area, and the pixel area includes two sub-symmetrically arranged about the second signal line a pixel area, each sub-pixel area comprising a thin film transistor and two sub-pixel units 2 arranged side by side;
  • the thin film transistor includes a drain 11; each of the sub-pixel units 2 has a sub-pixel electrode 21; and in each sub-pixel unit, the sub-pixel electrode 21 is electrically connected to a drain 11 of a thin film transistor.
  • the array substrate further includes a drain extension line 3 electrically connected to the drain 11 , and the drain extension line 3 is disposed at a position between adjacent data lines 42 of the pixel region, as shown in FIG. 1 .
  • the drain extension line 3 is provided between the two sub-pixel units 2.
  • the drain extension line may be formed of an opaque conductive material and electrically connected to the drain. Further, the drain extension line can be formed using the same material as the drain.
  • the data lines 42 in the array substrate of the present embodiment are arranged in the longitudinal direction shown in FIG. 1, and the signal lines are arranged in the lateral direction shown in FIG. 1, and the two intersect, and the adjacent first signal lines and adjacent data in the signal lines.
  • the area enclosed by the line is a pixel area; wherein, in this embodiment, the drain 11 of the thin film transistor is extended, that is, extended to the drain extension line 3, wherein the drain extension line 3 is disposed on the adjacent two sub-pixel units 2 At the position between, the light at the boundary of the sub-pixel unit 2 can be blocked, and light leakage caused by the electric field chaos of the sub-pixel unit 2 can be avoided.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIG. 2, including a plurality of intersecting data lines 42 and signal lines, the signal lines including a first signal line and a second signal line, and a second signal
  • the line is disposed between the adjacent first signal lines, the area surrounded by the adjacent first signal line and the adjacent data line is a pixel area, and the pixel area includes two symmetrically arranged with respect to the second signal line a sub-pixel region, each sub-pixel region comprising a thin film transistor and two sub-pixel units 2 arranged side by side; the thin film transistor comprising a drain 11; each of the sub-pixel units 2 having a sub-pixel electrode 21; and in each sub-pixel region
  • the sub-pixel electrode 21 of the sub-pixel unit is electrically connected to the drain 11 of the thin film transistor;
  • the array substrate further includes a drain extension line 3 electrically connected to the drain 11 , the drain extension line 3 It is disposed at a position between two sub-pixel units 21 in the same pixel sub-area.
  • the sub-pixel electrode 21 can be electrically connected to any position of the drain extension line 3, thereby connecting the sub-pixel electrode 21 to the drain 11, which is equivalent to an increase.
  • the contact of the drain 11 enhances the electrical connection between the sub-pixel electrode 21 and the drain 11, wherein the sub-pixel electrode 21 and the drain extension line 3 are different layers. Therefore, by providing the first via 31, the sub-pixel electrode 21 can be disposed.
  • the drain extension line 3 is connected to the first via 31.
  • the array substrate includes a plurality of laterally disposed scan lines 41, a plurality of data lines 42 and a plurality of common electrode lines 43; a gate of the thin film transistor is connected to the scan line 41, and a source of the thin film transistor 12 Connecting the data line 42; a region surrounded by the adjacent common electrode line 43 and the adjacent data line 42 is a pixel region, and the pixel region includes two sub-pixel regions symmetrically arranged with respect to the scan line 41, each of the sub-pixel regions including Two sub-pixel units 2, the drain extension lines 3 are disposed at positions between two sub-pixel units 2 in the same sub-pixel region.
  • the common electrode line 43 is used as the first signal line and the scanning line 41 is used as the second signal line has been described. It can be understood that the scanning line 41 serves as the first signal line and the common electrode line.
  • the second signal line the case where the area surrounded by the common electrode line 43 and the adjacent data line 42 is a pixel area is similar, and details are not described herein again.
  • FIGS. 1-3 A four-domain oriented array substrate in the above embodiment of the present disclosure is shown in FIGS. 1-3.
  • the scan line 41 divides a pixel area into upper and lower parts, and the dotted line frame 5 represents a sub-pixel area, and the dotted line frame 2 Representing one sub-pixel unit 2, that is, the scanning line 41 includes two left and right sub-pixel units 2, the scanning line 41 includes two left and right sub-pixel units 2, and the active region above the scanning line 41 is provided with two thin film transistors, wherein the upper portion One thin film transistor is used to control the two sub-pixel units 2 above, and the lower one is used to control the two sub-pixel units 2 below.
  • the source 12 of the thin film transistor is connected to the data line 42.
  • the drain extension line 3 is an extension of the drain 11.
  • the drain extension lines 3 of the two thin film transistors are elongated through the sub-pixel area.
  • a drain of a thin film transistor extends upwardly at a position between two upper and lower adjacent sub-pixel units 2, and a drain of a lower thin film transistor extends downward, and is disposed at two lower left and right adjacent sub-pixel units 2 between the locations.
  • the width of the drain extension line 3 is between 2 and 20 microns, and the length of the single drain extension line 3 is approximately equal to half the height of the pixel region.
  • the present invention is not limited thereto.
  • the technical solution of the present disclosure is also applicable to a two-domain or more domain-oriented array substrate, and the implementation manner thereof is similar to the embodiment, and details are not described herein again.
  • the drain extension line 3 is disposed in parallel with the data line 42.
  • the drain extension line 3 is shown in parallel with the data line 42 in FIG. 1, that is, the drain extension line 3 is disposed perpendicular to the scan line 41. It can be understood that the drain extension line 3 can also be curved, or other irregular shapes, for example, irregular shapes as shown in FIG. 2, and the specific shapes thereof are not enumerated here, and all can be engraved. The etch process is achieved.
  • one end of the drain extension line 3 away from the drain 11 overlaps with the common electrode line 43, that is, the orthographic projection of the drain extension line 3 on the substrate and the common electrode line 43 on the substrate The orthographic projection overlaps at the end of the drain extension line 3 away from the drain 11.
  • a portion of the drain extension line 3 close to the common electrode line 43 overlaps with a portion of the common electrode line 43, so that the design is such that a storage capacitor can be formed therebetween.
  • the common electrode line 43 protrudes toward the drain 11 at a position overlapping the drain extension line 3.
  • FIG. 3 shows that the middle portion of a common electrode line 43 located above the figure protrudes downward as shown in FIG. 3, which corresponds to an increase in the overlapping area with the drain extension line 3. Therefore, this design The way you can increase the storage capacitance between the two.
  • FIG. 3 also shows that the middle portion of a common electrode line 43 located below in the figure protrudes upward as shown in FIG. 3, which is equivalent to increasing the overlapping area with the drain extension line 3. Thereby increasing the storage capacitance between the two.
  • the sub-pixel unit 2 further includes a sub-common electrode 22 connected to the common electrode line 43 , wherein the sub-common electrode 22 is disposed in the same layer as the sub-pixel electrode 21 .
  • the present embodiment is applicable to an array substrate of a multi-domain oriented IPS mode.
  • the strip-shaped drain extension line 3 is disposed at the domain boundary.
  • the drain extension line 3 can be used as a light-blocking strip on the one hand to prevent the sub-pixel edge electric field. Light leakage caused by chaos; on the other hand, it can cover the middle of the common electrode line 43 to form a storage capacitor.
  • the angle between the sub-common electrode 22 of the sub-pixel unit 2 and the common electrode line 43 also referred to as the interdigital tilt angle
  • the angle between the sub-common electrode 22 of the sub-pixel unit 2 and the common electrode line 43 can be selected according to actual conditions.
  • the sub-pixel electrode 21 and the sub-common electrode 22 are comb electrodes
  • the comb electrode includes a plurality of strip-shaped comb teeth arranged in parallel
  • the comb teeth and the common electrode of the sub-pixel electrode 21 The angle between the lines 43 is ⁇ , the range of ⁇ is 90°> ⁇ >0°, the angle between the comb teeth of the sub-common electrode 22 and the common electrode line 43 is ⁇ , and the range of ⁇ is 90°> ⁇ >0°.
  • the sub-pixel electrode 21 and the sub-common electrode 22 are strip electrodes arranged in the same layer, and the tilt directions of the strip electrodes of the adjacent two sub-pixels in the same pixel region may be the same or different.
  • the alpha ranges from 60° > ⁇ > 30°; the ⁇ ranges from 60° > ⁇ > 30°.
  • the ⁇ ⁇ .
  • the skew angles of the sub-common electrodes 22 and the common electrode lines 22 of the adjacent two sub-pixels in the same sub-pixel region 5 may be the same or different, and the sub-common electrodes of the two sub-pixel units adjacent to each other. 22 and the common electrode line 43 may be axisymmetric with the drain extension line 3 as an axis, or the sub common electrode 22 and the common electrode line 43 of the two sub-pixel units adjacent to each other may be axisymmetric with the scan line 41 as an axis, and Make a selection based on the actual situation.
  • the width of the sub-pixel electrode 21 is the same as the width of the sub-common electrode 22, the spacing between adjacent comb teeth of the sub-pixel electrode 21 is the same, and the adjacent comb teeth of the sub-common electrode The spacing between the two is the same.
  • the sub-pixel electrode 21 may have a comb width of between 2 and 10 microns and a length of between 2 and 50 microns.
  • the sub-common electrode 22 has a comb width of between 2 and 10 microns and a length of between 2 and 50 microns.
  • the comb teeth of the sub-pixel electrode 21 are spaced apart from the comb teeth of the sub-common electrode 22, and the spacing between adjacent comb teeth of the sub-pixel electrode 21 is between 4 and 20 micrometers, and the sub-common electrode 22
  • the spacing between adjacent comb teeth is between 4 and 20 microns, i.e., the spacing between the comb teeth of sub-pixel electrode 21 and the comb teeth of sub-common electrode 22 adjacent thereto is between 2 and 10 microns.
  • the array substrate of the present disclosure is particularly suitable for multi-domain oriented IPS mode array substrates.
  • the present invention is not limited thereto.
  • the technical solution of the present disclosure is also applicable to the case where any one of the sub-pixel electrode 21 and the sub-common electrode 22 is a comb-shaped electrode, and the implementation manner thereof is similar to that of the embodiment, and details are not described herein again.
  • the projected area of each structural layer on the substrate may be the same or different.
  • the like, which is not enumerated here can realize the required projected area of each structural layer by an etching process; meanwhile, the structure shown in the drawing does not limit the geometric shape of each structural layer, for example, may be a rectangle as shown in the drawing. It can also be a trapezoidal shape, or a shape formed by other etching, which can also be achieved by etching.
  • the display device may be any product or component having a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • One embodiment of the present disclosure provides a method 100 of fabricating an array substrate, the method comprising the steps of:
  • S101 forming a plurality of data lines and a plurality of signal lines disposed in a cross, the signal lines include a first signal line and a second signal line, and an area surrounded by the adjacent first signal lines and adjacent data lines is a pixel region;
  • the thin film transistor including a drain, each of the sub-pixel units having a sub-pixel electrode, and a sub-pixel electrode and a thin film transistor of the sub-pixel unit Drain electrical connection;
  • the drain is formed in the same layer as the drain extension line.
  • step S103 further includes:
  • the drain and the drain extension are formed in different layers.
  • step S103 further includes:
  • the sub-pixel electrode is electrically connected to the drain extension line through the via.
  • step S103 further includes:
  • One of the first signal line and the second signal line is a scan line, the other is a common electrode line, a gate of the thin film transistor is connected to a scan line, and a source of the thin film transistor is connected to the data line, wherein
  • the step of forming a drain extension line in the sub-pixel region further includes:
  • the drain extension line is formed such that an orthographic projection of the end away from the drain overlaps with an orthographic projection of the common electrode line.
  • step S103 further includes:
  • the common electrode line is formed to protrude toward the drain at a position overlapping with an orthographic projection of an end of the drain extension line away from the drain.
  • the present disclosure also contemplates a method of fabricating a display device comprising the method of fabricating an array substrate described above.
  • the drain of the thin film transistor is extended by a drain extension line, and the drain extension line is disposed in adjacent sub-pixel units of the pixel region. between.
  • the drain extension line can be used as a light blocking strip to prevent light leakage caused by electric field confusion of the sub-pixel edge; on the other hand, it can also cover the middle portion of the common electrode line to form a storage capacitor.

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Abstract

一种阵列基板及其制造方法和显示装置及其制造方法，属于显示技术领域，阵列基板中将薄膜晶体管的漏极(11)延长形成漏极延长线(3)，其中，漏极延长线(3)布设于像素区域的相邻的子像素单元(2)之间，可以挡住子像素单元(2)边界处的光，避免子像素单元(2)边缘电场混乱引起的漏光。阵列基板适用于多畴取向的IPS模式的阵列基板，一方面漏极延长线(3)可以做为挡光条防止子像素边缘电场混乱引起的漏光；另一方面其还可以覆盖公共电极线(43)的中部形成存储电容。

Description

阵列基板及其制造方法和显示装置及其制造方法
相关申请的交叉引用
本公开要求于2017年11月1日提交的中国专利公开No.201721438535.2的优先权，所公开的内容以引用的方式合并于此。
技术领域
本公开属于显示技术领域，具体涉及一种阵列基板及其制造方法和显示装置。
背景技术
显示面板已被大量地用作于手机、笔记本电脑、个人电脑及个人数字助理等消费电子产品的显示屏幕。显示面板包括有源矩阵阵列基板，其中各个有源元件调节光束强度以显示出影像。现有的阵列基板包括多条栅线、多条数据线以及电性连接至对应的栅线及数据线的多个像素单元；每个像素单元由晶体管单独控制光透过率。液晶显示器包括扭曲向列型(Twisted Nematic，TN)、边缘场开关技术(Fringe Field Switching，FFS)、平面转换(In-Plane Switching，IPS)、垂直排列(vertical alignment，VA)等几种模式，其中FFS、IPS、VA模式都是宽视角液晶显示技术，经常采用多畴设计的像素结构，有利于增大视角。
发明内容
本公开提供了一种阵列基板，包括：交叉设置的多条数据线和多条信号线，所述信号线包括第一信号线和第二信号线，相邻的第一信号线和相邻的数据线围成的区域为像素区域，所述像素区域包括薄膜晶体管和多个子像素单元，所述薄膜晶体管包括漏极，每个所述子像素单元具有子像素电极，并且各子像素电极与薄膜晶体管的漏极电连接；和漏极延长线，其设于像素区域内， 与所述漏极电连接且位于子像素单元之间。
在一个具体实施方式中，所述漏极延长线具有过孔，各所述子像素电极通过所述过孔与所述漏极延长线电连接。
在一个具体实施方式中，所述漏极延长线与数据线平行设置，所述漏极延长线的宽度为2-20微米。
在一个具体实施方式中，所述第一信号线和第二信号线中一个为扫描线，另一个为公共电极线；
所述薄膜晶体管的栅极连接扫描线，所述薄膜晶体管的源极连接所述数据线。
在一个具体实施方式中，所述子像素单元还包括子公共电极，所述子公共电极与公共电极线连接，其中，子公共电极与子像素电极同层设置。
在一个具体实施方式中，所述子像素电极和子公共电极中的至少一个为梳状电极，所述梳状电极包括多个平行布置的条状梳齿，且所述梳齿与公共电极线之间的夹角大于0°且小于90°。
在一个具体实施方式中，所述梳齿与公共电极线之间的夹角大于30°且小于60°。
在一个具体实施方式中，所述梳齿的宽度相同，且各梳齿之间的间距相同。
在一个具体实施方式中，所述漏极延长线的原理所述漏极的端部正投影与所述公共电极线的正投影重叠。
在一个具体实施方式中，所述公共电极线的与所述漏极延长线的正投影重叠的位置处朝向所述漏极凸出。
本公开提供了一种显示装置，包括上述的阵列基板。
本公开提供了一种制造阵列基板的方法，包括：
形成交叉设置的多条数据线和多条信号线，所述信号线包括第一信号线和第二信号线，相邻的第一信号线和相邻的数据线围成的区域为像素区域；
在所述像素区域内形成薄膜晶体管和多个子像素单元，所述薄膜晶体管包括漏极，每个所述子像素单元具有子像素电极，并 且所述子像素单元的子像素电极与薄膜晶体管的漏极电连接；以及
在子像素区域中形成漏极延长线，使得所述漏极延长线与所述漏极电连接且位于子像素单元之间。
在一个具体实施方式中，在子像素区域中形成漏极延长线的步骤进一步包括：
使所述漏极与所述漏极延长线同层形成。
在一个具体实施方式中，在子像素区域中形成漏极延长线的步骤进一步包括：
使所述漏极与所述漏极延长线形成在不同层中。
在一个具体实施方式中，在子像素区域中形成漏极延长线的步骤进一步包括：
在所述漏极延长线中形成过孔；以及
通过所述过孔将所述子像素电极与所述漏极延长线电连接。
在一个具体实施方式中，所述第一信号线和第二信号线中一个为扫描线，另一个为公共电极线，所述薄膜晶体管的栅极连接扫描线，所述薄膜晶体管的源极连接所述数据线，其中，在子像素区域中形成漏极延长线的步骤进一步包括：
将所述漏极延长线形成为其远离所述漏极的端部正投影与所述公共电极线的正投影重叠。
在一个具体实施方式中，形成多条信号线的步骤进一步包括：
将所述公共电极线形成为其与所述漏极延长线的远离所述漏极的端部正投影重叠的位置处朝向所述漏极凸出。
本公开提供一种制造显示装置的方法，包括上述的制造阵列基板的方法。
附图说明
图1为本公开一个实施例的阵列基板的结构示意图；
图2-图3为本公开一个实施例的阵列基板的结构示意图；
图4为本公开一个实施例的制造阵列基板的方法的流程图。
其中，附图标记为：11、漏极；12、源极；2、子像素单元；21、子像素电极；22、子公共电极；3、漏极延长线；31、第一过孔；41、扫描线；42、数据线；43、公共电极线。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
现有的VA、FFS、IPS模式的液晶显示装置的多畴设计中，在畴边界的电场较混乱，容易造成漏光或者开口率的下降。
本公开的一个实施例提供一种阵列基板，如图1所示，包括多条交叉设置的数据线42和信号线，所述信号线包括第一信号线和第二信号线，第二信号线设置在相邻的第一信号线之间，相邻的第一信号线和相邻的数据线围成的区域为像素区域，所述像素区域包括关于所述第二信号线对称布置的两个子像素区域，每个子像素区域包括薄膜晶体管和并排布置的两个子像素单元2；
所述薄膜晶体管包括漏极11；每个所述子像素单元2具有子像素电极21；并且在每个子像素单元中，子像素电极21与薄膜晶体管的漏极11电连接。所述阵列基板还包括与所述漏极11电连接的漏极延长线3，所述漏极延长线3设于像素区域的相邻数据线42之间的位置处，如图1所示，漏极延长线3设于两个子像素单元2之间。所述漏极延长线可以由不透明导电材料形成，且与所述漏极电连接。进一步地，漏极延长线可以利用与漏极相同的材料形成。
本实施例的阵列基板中数据线42沿图1所示的纵向布置，信号线沿图1所示的横向布置，二者交叉，且信号线中相邻的第一信号线与相邻的数据线围成的区域为像素区域；其中，本实施例将薄膜晶体管的漏极11延长，即延长为漏极延长线3，其中，漏极延长线3布设于相邻的两个子像素单元2之间的位置处，可以挡住子像素单元2边界处的光，避免子像素单元2边缘电场混乱引起的漏光。
本公开的一个实施例提供了一种阵列基板，如图2所示，包括多条交叉设置的数据线42和信号线，所述信号线包括第一信号线和第二信号线，第二信号线设置在相邻的第一信号线之间，相邻的第一信号线和相邻的数据线围成的区域为像素区域，所述像素区域包括关于所述第二信号线对称布置的两个子像素区域，每个子像素区域包括薄膜晶体管和并排布置的两个子像素单元2；所述薄膜晶体管包括漏极11；每个所述子像素单元2具有子像素电极21；并且在每个子像素区域中，所述子像素单元的子像素电极21与薄膜晶体管的漏极11电连接；所述阵列基板还包括与所述漏极11电连接的漏极延长线3，所述漏极延长线3设于同一个像素子区域中的两个子像素单元21之间的位置处。此外，所述漏极延长线3具有第一过孔31，所述子像素电极21通过所述第一过孔31与漏极11电连接。
本实施例中的阵列基板由于漏极11被延长，因此，子像素电极21可与漏极延长线3的任意位置电连接，从而将子像素电极21连接至漏极11，这样相当于增加了漏极11的可接点，增强子像素电极21与漏极11的电连接性，其中子像素电极21与漏极延长线3不同层，因此通过设置第一过孔31，可以将子像素电极21与漏极延长线3通过第一过孔31连接。
在一个具体实施方式中，所述阵列基板包括多条横向设置的扫描线41、多条数据线42和多条公共电极线43；薄膜晶体管的栅极连接扫描线41，薄膜晶体管的源极12连接数据线42；相邻的公共电极线43与相邻的数据线42围成的区域为像素区域，所述像素区域内包括关于扫描线41对称布置的两个子像素区域，每个子像素区域包括两个子像素单元2，所述漏极延长线3设于同一子像素区域内的两个子像素单元2之间的位置处。
需要说明的是，附图中以公共电极线43作为第一信号线，扫描线41作为第二信号线的情况进行了说明，可以理解的是，扫描线41作为第一信号线，共电极线43作为第二信号线的情况，即公共电极线43与相邻的数据线42围成的区域为像素区域的情况 与之类似，在此不再赘述。
图1-图3中显示了本公开的上述实施例中的一种四畴取向的阵列基板，扫描线41把一个像素区域分为上下两部分，虚线框5代表一个子像素区域，虚线框2代表一个子像素单元2，即扫描线41上方包括左右两个子像素单元2，扫描线41下方包括左右两个子像素单元2，在扫描线41上方的有源区设有两个薄膜晶体管，其中上方的一个薄膜晶体管用于控制上方的两个子像素单元2，下方的一个薄膜晶体管用于控制下方的两个子像素单元2。具体的，薄膜晶体管的源极12与数据线42连接，其中漏极延长线3为漏极11的延伸，两个薄膜晶体管的漏极延长线3均呈长条状贯穿子像素区域，上方的一个薄膜晶体管的漏极向上延伸，设于上部左右两个相邻子像素单元2之间的位置处，下方的一个薄膜晶体管的漏极向下延伸，设于下部左右两个相邻子像素单元2之间的位置处。具体的，漏极延长线3的宽度在2～20微米之间，单根漏极延长线3的长度大约等于像素区域高度的一半。
需要注意的是，虽然本实施例中参照图1至图3以四畴取向的阵列基板为例进行了说明，但是本发明不限于此。例如，本公开的技术方案还适用于二畴或者更多畴取向的阵列基板，其实现方式与本实施例相似，在此不再赘述。
在一个具体实施方式中，所述漏极延长线3与数据线42平行设置。
图1中显示了漏极延长线3与数据线42平行设置，即漏极延长线3与扫描线41垂直设置。可以理解的是，漏极延长线3也可以是弯曲的，或者其它不规则的形状，例如，如图2所示的不规则形状，其具体形状此处不再一一列举，均可以通过刻蚀工艺实现。
在一个具体实施方式中，所述漏极延长线3远离漏极11的一端与公共电极线43重叠，即，所述漏极延长线3在基底上的正投影与公共电极线43在基底上的正投影在漏极延长线3远离漏极11的一端处重叠。
也就是说，漏极延长线3靠近公共电极线43点一段与公共电极线43的一部分重叠，这样设计的作用是：二者之间可以形成存储电容。
在一个具体实施方式中，所述公共电极线43在与漏极延长线3重叠的位置处朝向漏极11凸出。
如图3所示，位于图中上方的一根公共电极线43的中部向图3所示的下方凸出，这样相当于增加了其与漏极延长线3的重叠面积，因此，这种设计方式可以更多的增加二者之间的存储电容。同理，附图3中还示出了图中位于下方的一根公共电极线43的中部向图3所示的上方凸出，同样相当于增加了其与漏极延长线3的重叠面积，从而增加二者之间的存储电容。
在一个具体实施方式中，所述子像素单元2还包括子公共电极22，所述子公共电极22与公共电极线43连接，其中，子公共电极22与子像素电极21同层设置。
也就是说，本实施例适用于多畴取向的IPS模式的阵列基板。从附图中可以看出，在畴边界设置条状漏极延长线3，在增大了视角的情况下，漏极延长线3一方面可以在畴边界做为挡光条防止子像素边缘电场混乱引起的漏光；另一方面其可以覆盖公共电极线43的中部形成存储电容。可以理解的是，子像素单元2的子公共电极22与公共电极线43的夹角(也称叉指倾斜角)可以根据实际情况进行选择。
在一个具体实施方式中，所述子像素电极21和子公共电极22均为梳状电极，所述梳状电极包括多个平行布置的条状梳齿，且子像素电极21的梳齿与公共电极线43之间的夹角为α，所述α的范围为90°＞α＞0°，子公共电极22的梳齿与公共电极线43之间的夹角为β，所述β的范围为90°＞β＞0°。
具体的，子像素电极21和子公共电极22均为同层设置的条状电极，同一个像素区域中的相邻的两个子像素的条状电极的倾斜方向可以相同也可以不同。
在一个具体实施方式中，所述α的范围为60°＞α＞30°；所述 β的范围为60°＞β＞30°。
在一个具体实施方式中，所述α＝β。
参见附图，同一个子像素区域5中的相邻的两个子像素的子公共电极22与公共电极线22的叉指倾斜角可以相同也可以不同，左右相邻的两个子像素单元的子公共电极22与公共电极线43可以以漏极延长线3为轴呈轴对称，或者上下相邻的两个子像素单元的子公共电极22与公共电极线43可以以扫描线41为轴呈轴对称，可以根据实际情况进行选择。
在一个具体实施方式中，所述子像素电极21的宽度与子公共电极22的宽度相同，子像素电极21的相邻的梳齿之间的间距相同，子公共电极的相邻的梳齿之间的间距相同。
具体的，子像素电极21的梳齿宽度可以在2至10微米之间，长度在2至50微米之间。子公共电极22的梳齿宽度在2至10微米之间，长度在2至50微米之间。更具体的，子像素电极21的梳齿与子公共电极22的梳齿间隔排布，子像素电极21的相邻的梳齿之间的间距在4至20微米之间，子公共电极22的相邻的梳齿之间的间距在4至20微米之间，即子像素电极21的梳齿和与之相邻的子公共电极22的梳齿之间的间距在2至10微米之间。
本公开的阵列基板尤其适用于多畴取向的IPS模式的阵列基板。
需要注意的是，虽然本实施例中参照图1至图3以子像素电极21和子公共电极22均为梳状电极为例进行了说明，但是本发明不限于此。例如，本公开的技术方案还适用于子像素电极21和子公共电极22中的任意一个为梳状电极的情况，其实现方式与本实施例相似，在此不再赘述。
附图所示各结构的大小、厚度等仅为示意。在工艺实现中，各结构层在衬底上的投影面积可以相同，也可以不同。诸如此类，此处不再列举，可以通过刻蚀工艺实现所需的各结构层投影面积；同时，附图所示结构也不限定各结构层的几何形状，例如可以是附图所示的矩形，还可以是梯形，或其它刻蚀所形成的形状，同 样可通过刻蚀实现。
本实施例提供一种显示装置，包括上述的阵列基板。所述显示装置可以为：液晶显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的一个实施例提供了一种制造阵列基板的方法100，该方法包括步骤：
S101，形成交叉设置的多条数据线和多条信号线，所述信号线包括第一信号线和第二信号线，相邻的第一信号线和相邻的数据线围成的区域为像素区域；
S102，在所述像素区域内形成薄膜晶体管和多个子像素单元，所述薄膜晶体管包括漏极，每个所述子像素单元具有子像素电极，并且所述子像素单元的子像素电极与薄膜晶体管的漏极电连接；以及
S103，在子像素区域中形成漏极延长线，使得所述漏极延长线与所述漏极电连接且位于子像素单元之间。
使所述漏极与所述漏极延长线同层形成。
在一个具体实施方式中，步骤S103进一步包括：
使所述漏极与所述漏极延长线形成在不同层中。
在一个具体实施方式中，步骤S103进一步包括：
在所述漏极延长线中形成过孔；以及
通过所述过孔将所述子像素电极与所述漏极延长线电连接。
在一个具体实施方式中，步骤S103进一步包括：
所述第一信号线和第二信号线中一个为扫描线，另一个为公共电极线，所述薄膜晶体管的栅极连接扫描线，所述薄膜晶体管的源极连接所述数据线，其中，在子像素区域中形成漏极延长线的步骤进一步包括：
将所述漏极延长线形成为其远离所述漏极的端部正投影与所述公共电极线的正投影重叠。
在一个具体实施方式中，步骤S103进一步包括：
将所述公共电极线形成为其与所述漏极延长线的远离所述漏极的端部正投影重叠的位置处朝向所述漏极凸出。
本公开还体用了一种制造显示装置的方法，包括上述所述的制造阵列基板的方法。
在本公开的上述阵列基版及其制造方法及显示装置及其制造方法中，利用漏极延长线将薄膜晶体管的漏极延长，并且将漏极延长线布设在像素区域的相邻子像素单元之间。一方面漏极延长线可以做为挡光条防止子像素边缘电场混乱引起的漏光；另一方面其还可以覆盖公共电极线的中部形成存储电容。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种阵列基板，其特征在于，包括：
    交叉设置的多条数据线和多条信号线，所述信号线包括第一信号线和第二信号线，相邻的第一信号线和相邻的数据线围成的区域为像素区域，所述像素区域包括薄膜晶体管和多个子像素单元，所述薄膜晶体管包括漏极，每个所述子像素单元具有子像素电极，并且各子像素电极与薄膜晶体管的漏极电连接；和
    漏极延长线，其设于像素区域内，与所述漏极电连接且位于子像素单元之间。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述漏极延长线具有过孔，各所述子像素电极通过所述过孔与所述漏极延长线电连接。
  3. 根据权利要求1-2中任一项所述的阵列基板，其特征在于，所述漏极延长线与数据线平行设置，所述漏极延长线的宽度为2-20微米。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述第一信号线和第二信号线中一个为扫描线，另一个为公共电极线；
    所述薄膜晶体管的栅极连接扫描线，所述薄膜晶体管的源极连接所述数据线。
  5. 根据权利要求4所述的阵列基板，其特征在于，所述子像素单元还包括子公共电极，所述子公共电极与公共电极线连接，其中，子公共电极与子像素电极同层设置。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述子像素电极和子公共电极中的至少一个为梳状电极，所述梳状电极包 括多个平行布置的条状梳齿，且所述梳齿与公共电极线之间的夹角大于0°且小于90°。
  7. 根据权利要求6所述的阵列基板，其特征在于，所述梳齿与公共电极线之间的夹角大于30°且小于60°。
  8. 根据权利要求6所述的阵列基板，其特征在于，所述梳齿的宽度相同，且各梳齿之间的间距相同。
  9. 根据权利要求4所述的阵列基板，其特征在于，所述漏极延长线的原理所述漏极的端部正投影与所述公共电极线的正投影重叠。
  10. 根据权利要求9所述的阵列基板，其特征在于，所述公共电极线的与所述漏极延长线的正投影重叠的位置处朝向所述漏极凸出。
  11. 一种显示装置，其特征在于，包括权利要求1-10中任一项所述的阵列基板。
  12. 一种制造阵列基板的方法，其特征在于，包括：
    形成交叉设置的多条数据线和多条信号线，所述信号线包括第一信号线和第二信号线，相邻的第一信号线和相邻的数据线围成的区域为像素区域；
    在所述像素区域内形成薄膜晶体管和多个子像素单元，所述薄膜晶体管包括漏极，每个所述子像素单元具有子像素电极，并且所述子像素单元的子像素电极与薄膜晶体管的漏极电连接；以及
    在子像素区域中形成漏极延长线，使得所述漏极延长线与所述漏极电连接且位于子像素单元之间。
  13. 根据权利要求12所述的方法，其特征在于，在子像素区域中形成漏极延长线的步骤进一步包括：
    使所述漏极与所述漏极延长线同层形成。
  14. 根据权利要求12所述的方法，其特征在于，在子像素区域中形成漏极延长线的步骤进一步包括：
    使所述漏极与所述漏极延长线形成在不同层中。
  15. 根据权利要求12-14中任一项所述的方法，其特征在于，在子像素区域中形成漏极延长线的步骤进一步包括：
    在所述漏极延长线中形成过孔；以及
    通过所述过孔将所述子像素电极与所述漏极延长线电连接。
  16. 根据权利要求15所述的方法，其特征在于，所述第一信号线和第二信号线中一个为扫描线，另一个为公共电极线，所述薄膜晶体管的栅极连接扫描线，所述薄膜晶体管的源极连接所述数据线，其中，在子像素区域中形成漏极延长线的步骤进一步包括：
    将所述漏极延长线形成为其远离所述漏极的端部正投影与所述公共电极线的正投影重叠。
  17. 根据权利要求16所述的方法，其特征在于，形成多条信号线的步骤进一步包括：
    将所述公共电极线形成为其与所述漏极延长线的远离所述漏极的端部正投影重叠的位置处朝向所述漏极凸出。
  18. 一种制造显示装置的方法，包括权利要求12-17中任一项所述的制造阵列基板的方法。
PCT/CN2018/107968 2017-11-01 2018-09-27 阵列基板及其制造方法和显示装置及其制造方法 WO2019085700A1 (zh)

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