WO2017071405A1 - 薄膜晶体管的制作方法、阵列基板的制作方法、显示面板以及显示装置 - Google Patents

薄膜晶体管的制作方法、阵列基板的制作方法、显示面板以及显示装置 Download PDF

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WO2017071405A1
WO2017071405A1 PCT/CN2016/098168 CN2016098168W WO2017071405A1 WO 2017071405 A1 WO2017071405 A1 WO 2017071405A1 CN 2016098168 W CN2016098168 W CN 2016098168W WO 2017071405 A1 WO2017071405 A1 WO 2017071405A1
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layer
region
dissolution
drain
source
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PCT/CN2016/098168
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English (en)
French (fr)
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苏同上
杜生平
刘宁
王东方
袁广才
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京东方科技集团股份有限公司
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Priority to EP16845355.3A priority Critical patent/EP3370261A4/en
Priority to US15/512,981 priority patent/US10475906B2/en
Publication of WO2017071405A1 publication Critical patent/WO2017071405A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a method of fabricating a thin film transistor, a method of fabricating an array substrate, a display panel, and a display device.
  • the oxide thin film transistor array substrate includes a back channel etched TFT (Thin Film Transistor) array substrate, a coplanar TFT array substrate, an etch barrier TFT array substrate, and the like, wherein the back channel etch TFT Array substrates and coplanar TFT array substrates have been widely used due to their simple structure.
  • TFT Thin Film Transistor
  • the structure of the back channel etch type TFT array substrate is to sequentially form a gate electrode, a gate insulating layer, an oxide active layer, a source, a drain, a passivation layer, and a pixel electrode on the base substrate.
  • a source/drain layer is first deposited on the oxide active layer, and then the source and drain are formed by one patterning process.
  • the structure of the coplanar TFT array substrate is such that a gate electrode, a gate insulating layer, a source, a drain, an oxide active layer, a passivation layer, and a pixel electrode are sequentially formed on the base substrate.
  • a metal oxide layer is first deposited on the source, the gate insulating layer, and the drain, and an oxide active layer is formed by one patterning process.
  • a method of fabricating a thin film transistor includes forming a gate of a thin film transistor, a gate insulating layer, and an oxide active layer by a patterning process, the gate insulating layer being located between the gate electrode and the oxide active layer; a dissolution layer having an inverted trapezoidal cross section formed on the active layer, the inverted trapezoidal dissolution layer being soluble in an organic solvent; on the oxide active layer, the gate insulating layer, and the inverted trapezoidal dissolution layer Forming a source/drain layer, a thickness of the inverted trapezoidal dissolution layer being greater than a thickness of the source/drain layer; and dissolving the dissolved layer of the inverted trapezoid using an organic solvent and removing the layer located on the dissolved layer of the inverted trapezoid
  • the source and drain layers form a source and a drain.
  • the source/drain layer formed over the dissolved layer of the inverted trapezoid is disconnected from the source and drain layers formed outside the dissolved layer of the inverted trapezoid.
  • the forming an inverted trapezoidal dissolution layer on the oxide active layer includes: forming a dissolution layer on the oxide active layer; masking a dissolution layer in the first region to cause the The dissolution layer in the first region generates an acidic substance for enhancing the crosslinking reaction, the first region is located on the oxide active layer, and the dissolution layer is subjected to reverse drying and pan exposure. And developing treatment to remove the dissolved layer in the region other than the first region and to convert the dissolved layer in the first region into a dissolved layer of the inverted trapezoid.
  • the portion of the dissolution layer in the first region that is further away from the oxide active layer is exposed to a stronger intensity of the mask, so that the first region is The more acidic layer the dissolved layer is from the oxide active layer, the more acidic material is produced.
  • the dissolving layer is subjected to reverse drying, pan exposure, and development processing to remove a dissolution layer in other regions than the first region and to convert a dissolved layer in the first region into
  • the inverted trapezoidal dissolution layer comprises: inverting and drying the thin film transistor, the dissolution layer undergoes a crosslinking reaction during the reverse drying process, and the dissolved layer in the first region is in the acidic substance
  • the strength of the crosslinking reaction occurs stronger than the dissolution layer in the other regions, and the molecular density and hardness of the dissolution layer in the first region after inversion drying are higher than the other regions.
  • Dissolving layer performing over-exposure on the thin film transistor after reverse drying, the molecular chain of the dissolved layer in the other region is broken during the pan exposure; developing the dissolved layer after the overexposure The treatment is such that the dissolution layer of the other region is dissolved in the developer and the dissolution layer in the first region becomes a dissolution layer of the inverted trapezoid.
  • the portion of the dissolution layer in the first region that is further away from the oxide active layer under the action of an acidic substance in the dissolution layer in the first region The stronger the intensity of the cross-linking reaction that occurs, the higher the molecular density and hardness of the portion of the first region that is further away from the oxide active layer; during the overexposure process, The molecular density and the lower the hardness of the dissolution layer in the first region, the more easily the molecular chain breaks, and the portion of the dissolution layer in the first region that is further away from the oxide active layer
  • the method before performing the mask exposure on the dissolved layer in the first region, the method further comprises: pre-baking the dissolving layer, and removing the solvent in the dissolving layer by the pre-bake.
  • a method of fabricating an array substrate includes: forming a gate and a gate line, a gate insulating layer, and an oxide active layer on a base substrate, the gate insulating layer being located between the gate and the oxide active layer; a dissolution layer having an inverted trapezoidal cross section formed on the oxide active layer, the inverted trapezoidal dissolution layer being soluble in an organic solvent; and dissolving in the oxide active layer, the gate insulating layer, and the inverted trapezoid Forming a source/drain layer on the layer, the thickness of the inverted trapezoidal dissolution layer being greater than the thickness of the source/drain layer, dissolving the dissolved layer of the inverted trapezoid using an organic solvent, and removing the layer located on the dissolved layer of the inverted trapezoid a source drain layer, a source and a data line and a drain are formed; a passivation layer is formed on the source, the oxide active layer, and the
  • the forming an inverted trapezoidal dissolution layer on the oxide active layer includes: forming a dissolution layer on the oxide active layer; masking a dissolution layer in the first region to cause the The dissolution layer in the first region generates an acidic substance for enhancing the crosslinking reaction, the first region is located on the oxide active layer; and the dissolution layer is subjected to reverse drying and pan exposure And developing treatment to remove the dissolved layer in the region other than the first region and to convert the dissolved layer in the first region into a dissolved layer of the inverted trapezoid.
  • a display panel includes an array substrate formed by the method described above.
  • a display device includes a display panel as described above.
  • a method of fabricating a thin film transistor includes: forming a gate of a thin film transistor, a gate insulating layer, a source and a drain by a patterning process, the source and the drain are located in a same layer, and the gate insulating layer is located at the source and the Between the drain and the gate; forming a dissolved layer having an inverted trapezoidal cross section on the source and the drain, the inverted trapezoidal dissolved layer being soluble in an organic solvent; at the source, Forming a metal oxide active layer on the drain, the gate insulating layer, and the inverted trapezoidal dissolved layer, the inverted trapezoidal dissolved layer having a thickness greater than a thickness of the metal oxide active layer; and using The organic solvent dissolves to remove the dissolved layer of the inverted trapezoid and removes the metal oxide active layer on the dissolved layer of the inverted trapezoid to form an oxide active layer.
  • the metal oxide active layer formed over the dissolved layer of the inverted trapezoid is disconnected from the metal oxide active layer formed outside the dissolved layer of the inverted trapezoid.
  • the dissolving layer forming an inverted trapezoid on the source and the drain includes: forming a dissolving layer on the source and the drain; and dissolving layers in the second and third regions; Performing a mask exposure to cause an acidic substance in the second and third regions to be used for enhancing an crosslinking reaction, the second region being located on the source, the third a region is located on the drain; performing reverse drying, pan exposure, and development processing on the dissolution layer to remove a dissolution layer of the region other than the second region and the third region and The dissolved layer in the second region and the third region is transformed into a dissolved layer of an inverted trapezoid.
  • the portion of the dissolution layer in the second region that is further away from the source is exposed to a stronger intensity of the mask, such that the dissolution layer in the second region The more acidic the substance is generated from the portion farther from the source; the portion of the dissolution layer in the third region that is further away from the drain is exposed to the stronger the intensity of the mask, so that the third region The more acidic the inner layer of the dissolved layer is from the drain, the more acidic material is produced.
  • the dissolving layer is subjected to reverse drying, pan exposure, and development processing to remove a dissolving layer other than the second region and the third region and to remove the second region And converting the dissolution layer in the third region into an inverted trapezoidal dissolution layer, comprising: performing reverse drying on the thin film transistor, and the dissolution layer undergoes a crosslinking reaction during the reverse drying process, and the The dissolution layer in the second region and the third region undergoes a crosslinking reaction under the action of the acidic substance to be stronger than the dissolution layer in the other region, and the second region after the reverse drying And a molecular layer density and hardness of the dissolution layer in the third region are higher than a dissolution layer of the other region; the thin film transistor after the reverse drying is subjected to a flood exposure, and the other is in the process of the flood exposure The molecular chain of the dissolution layer in the region is broken; the dissolution layer after the flood exposure is developed, the dissolution layer of the other region is dissolved in the developer,
  • the dissolved layer in the second region is separated from the source under the action of an acidic substance in the second region and the dissolved layer in the third region
  • the stronger the strength of the cross-linking reaction occurring in the farther portion the higher the molecular density and hardness of the portion of the second region in which the dissolution layer is further from the source, and the dissolution layer in the third region.
  • the stronger the intensity of the crosslinking reaction occurring in the portion farther from the drain, the more the dissolution layer in the third region is away from the drain The higher the molecular density and hardness of the far portion; the lower the molecular density and hardness of the dissolved layer in the second region and the third region, the more likely the molecules are to occur during the overexposure process
  • the molecular chain is broken, such that the further the molecular layer in the second region is separated from the source and the molecular layer in the third region is further away from the drain Less; during the development, the portion of the dissolution layer in the second region and the third region where the molecular chain is broken is less soluble in the developer, so that the second region is The further the dissolution layer is from the source and the portion of the dissolution layer in the third region that is further away from the drain, the more difficult it is to dissolve in the developer.
  • the method before performing the mask exposure on the dissolution layer in the second region and the third region, the method further comprises: pre-baking the dissolution layer, and removing the solvent in the dissolution layer by the pre-baking.
  • a method of fabricating an array substrate includes: forming a gate and a gate line, a gate insulating layer, a source, and a data line and a drain on the base substrate, The source and the drain are located in the same layer, the gate insulating layer is located between the source, the drain and the gate; forming an inverted trapezoidal cross section on the source and the drain a reverse trapezoidal dissolution layer, the inverted trapezoidal dissolution layer being soluble in an organic solvent; forming a metal oxide layer on the source, the drain, the gate insulating layer, and the inverted trapezoidal dissolved layer a thickness of the inverted trapezoidal dissolution layer is greater than a thickness of the metal oxide layer; dissolving the dissolved layer of the inverted trapezoid using an organic solvent and removing the metal oxide on the dissolved layer of the inverted trapezoid a source layer, an oxide active layer is formed; a passivation layer is formed on the
  • forming an inverted trapezoidal dissolution layer on the source and the drain includes: forming a dissolution layer on the source and the drain; masking a dissolution layer in the second region and the third region The film is exposed such that the dissolved layer in the second and third regions generates an acidic substance for enhancing the crosslinking reaction, the second region is located on the source, and the third region is located On the drain; performing reverse drying, pan exposure, and development processing on the dissolving layer to remove a dissolving layer other than the second region and the third region and to The dissolved layer in the two regions and the third region is transformed into a dissolved layer of an inverted trapezoid.
  • a display panel includes an array substrate formed by the method described above.
  • a display device includes a display panel as described above.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor according to Embodiment 1 of the present invention
  • FIG. 2 to FIG. 5 are schematic diagrams showing a method of fabricating a thin film transistor according to Embodiment 1 of the present invention.
  • FIG. 6 is a flow chart of a method for forming an inverted trapezoidal dissolution layer according to Embodiment 1 of the present invention.
  • FIG. 7-8 are schematic views showing a manufacturing method of forming an inverted trapezoidal dissolution layer according to Embodiment 1 of the present invention.
  • FIG. 9 is a flow chart of a method for forming an inverted trapezoidal dissolution layer according to Embodiment 1 of the present invention.
  • FIG. 10 is a flowchart of a method for fabricating an array substrate according to Embodiment 1 of the present invention.
  • FIG. 11 is a schematic structural diagram of an array substrate according to Embodiment 1 of the present invention.
  • FIG. 12 to FIG. 13 are schematic diagrams showing a method of fabricating an array substrate according to Embodiment 1 of the present invention.
  • FIG. 14 to FIG. 18 are schematic diagrams showing a method of fabricating an array substrate when forming different numbers of inverted trapezoidal dissolution layers according to Embodiment 1 of the present invention.
  • FIG. 19 is a flow chart of a method for fabricating a thin film transistor according to Embodiment 2 of the present invention.
  • FIG. 23 are schematic diagrams showing a method of fabricating a thin film transistor according to Embodiment 2 of the present invention.
  • 24 is a flow chart of a method for forming an inverted trapezoidal dissolution layer according to a second embodiment of the present invention.
  • FIG. 26 are schematic views showing a manufacturing method of forming an inverted trapezoidal dissolution layer according to Embodiment 2 of the present invention.
  • Figure 27 is a flow chart showing a method of forming an inverted trapezoidal dissolution layer according to a second embodiment of the present invention.
  • FIG. 29 to FIG. 30 are schematic diagrams showing a method of fabricating an array substrate according to Embodiment 2 of the present invention.
  • the inventors have found that the back channel etch type TFT array substrate and the coplanar TFT array substrate have at least the following problems.
  • the etching liquid or the etching gas destroys the characteristics of the oxide active layer, so that the leakage current of the back channel etching type TFT array substrate is increased, and the back channel etching is reduced. The performance of a TFT array substrate.
  • an embodiment of the present invention provides a method for fabricating a thin film transistor, including:
  • Step 101 forming a gate electrode 1 of the thin film transistor, a gate insulating layer 2, and an oxide active layer 3 by a patterning process, and the gate insulating layer 2 is located between the gate electrode 1 and the oxide active layer 3;
  • a gate electrode 1 is formed by a patterning process, a gate insulating layer 2 is deposited on the gate electrode 1, and an oxide active layer 3 is formed on the gate insulating layer 2 by a patterning process.
  • Step 102 As shown in FIG. 3, a dissolution layer A having an inverted trapezoidal cross section is formed on the oxide active layer 3, and the inverted trapezoidal dissolution layer A is soluble in an organic solvent;
  • the organic solvent is acetone or chlorobenzene.
  • Step 103 depositing a source/drain layer 4 on the oxide active layer 3, the gate insulating layer 2, and the inverted trapezoidal dissolution layer A, the thickness of the inverted trapezoidal dissolution layer A being greater than the thickness of the source/drain layer 4;
  • the thickness of the inverted trapezoidal dissolution layer A is larger than the thickness of the source/drain layer 4, so the source/drain layer 4 deposited on the inverted trapezoidal dissolution layer A and the deposition layer A deposited on the inverted trapezoidal layer are excluded. Part of the source and drain layers 4 do not touch each other.
  • the difference between the thickness of the inverted trapezoidal dissolution layer A and the thickness of the source/drain layer 4 is greater than or equal to 2 micrometers.
  • Step 104 Dissolving the inverted trapezoidal dissolution layer A using an organic solvent and removing the source/drain layer 4 on the dissolution layer A of the inverted trapezoid to form the source 5 and the drain 6.
  • the dissolved layer A of the inverted trapezoid is removed by dissolving with an organic solvent, and the source/drain layer 4 deposited on the dissolved layer A of the inverted trapezoid is removed together with the dissolved layer A of the inverted trapezoid, and deposited in the trapezoidal shape.
  • the source/drain layer 4 of the portion other than the dissolution layer A remains, and the source 5 and the drain 6 are formed.
  • the other portions of the source and drain layers 4 except the source 5 and the drain 6 are deposited on the inverted trapezoidal dissolution layer A, and the thickness of the inverted trapezoidal dissolution layer A is greater than the thickness of the source/drain layer 4, Then, the dissolved layer A of the inverted trapezoid and the source/drain layer 4 thereon are removed by using an organic solvent, thereby forming the source 5 and the drain 6, effectively solving the process of forming the source 5 and the drain 6 by using an etching process.
  • an embodiment of the present invention provides a method for forming an inverted trapezoidal dissolved layer A on an oxide active layer 3, including:
  • Step 201 depositing a dissolution layer 7 on the oxide active layer 3, the thickness of the dissolution layer 7 being greater than the thickness of the source/drain layer 4;
  • a dissolution layer 7 is deposited on the oxide active layer 3, and the dissolution layer 7 is dissolved in an organic solvent.
  • Step 202 As shown in FIG. 8, the dissolution layer 7 in the first region B is subjected to mask exposure, so that the acidic layer is generated by the dissolution layer 7 in the first region B, and the acidic substance is used to enhance the crosslinking reaction.
  • the region B is located on the oxide active layer 3;
  • the mask exposure process of the dissolution layer 7 in the first region B is performed by using a mask having a pattern such that only the dissolution layer 7 in the first region B is exposed except for the first region B.
  • the dissolution layer 7 of the region is not exposed.
  • the first region B is located on the oxide active layer 3, and the dissolution layer 7 in the first region B is mask exposed. If the material of the dissolving layer 7 is selected from a photoresist, the corresponding photoresist in the first region B after the mask exposure produces a carboxylic acid, and the carboxylic acid can enhance the crosslinking reaction. Since the portion of the photoresist in the first region B that is farther away from the oxide active layer 3 is exposed to the mask during the mask exposure, the intensity of the mask exposure is stronger, so that the photoresist in the first region B is separated from the oxide.
  • the gum produces the least amount of carboxylic acid.
  • the mask exposure time is greater than or equal to 5 s and less than or equal to 6 s.
  • Step 203 Perform reverse drying on the dissolution layer 7.
  • inverting the thin film transistor and then injecting the photoresist into the reversed thin film transistor Drying For example, inverting the thin film transistor and then injecting the photoresist into the reversed thin film transistor Drying.
  • the photoresist undergoes a crosslinking reaction
  • the photoresist in the first region B undergoes a cross-linking reaction under the action of the carboxylic acid, which is stronger than the photoresist in other regions, and is in the opposite direction.
  • the photoresist in the first region B after the transfer drying has higher molecular density and hardness than the photoresist in other regions.
  • the photoresist of the upper surface portion of the first region B has the highest molecular density and hardness, and the photoresist in the first region B which is in contact with the oxide active layer 3 has the lowest molecular density and hardness.
  • the time of reverse drying is greater than or equal to 10 min and less than or equal to 12 min.
  • the temperature of the reverse drying is greater than or equal to 80 ° C and less than or equal to 100 ° C.
  • the photoresist can be sufficiently cross-linked.
  • Step 204 performing a flood exposure on the dissolution layer 7 after the reverse drying, in which the molecular chain of the dissolution layer 7 in other regions except the first region B is broken during the pan exposure;
  • the dissolution layer 7 in the first region B and the dissolution layer 7 in other regions than the first region B are exposed.
  • the over-exposure of the photoresist after the reverse drying is performed because the photoresist in the first region B undergoes a cross-linking reaction under the action of the carboxylic acid to be stronger than the photoresist in other regions of the dissolving layer 7.
  • the molecular density and hardness of the photoresist in the first region B are higher than those of the other regions, so the flood exposure process causes the photoresist molecules in other regions except the first region B.
  • the chain is broken, and at the same time, the molecular density of the photoresist in the first region B and the partial molecular chain having a lower hardness are broken, so that the farther away from the oxide active layer 3 in the first region B, the molecular chain breaks. The fewer molecules that are opened.
  • the time of the pan exposure is greater than or equal to 5 s and less than or equal to 6 s.
  • the light of the overexposure is greater than or equal to 30 mJ/cm 2 and less than or equal to 60 mJ/cm 2 .
  • the light intensity and time of the overexposure are controlled within a reasonable range, so that the photoresist is sufficiently exposed to prepare for the next step of developing the inverted trapezoidal dissolution layer A.
  • Step 205 Developing the dissolution layer 7 after the overexposure to dissolve the dissolution layer 7 in the other region in the developer and the dissolution layer 7 in the first region B into the inverted trapezoidal dissolution layer A.
  • the photoresist after the overexposure is subjected to photolithography, and since the molecular chain of the photoresist other than the first region B is broken after the flood exposure process, photolithography of other regions outside the first region B is performed.
  • the gum is dissolved in the developer. Since the portion of the photoresist in the first region B is farther away from the oxide active layer 3, the higher the density and hardness, the more distant the portion of the photoresist in the first region B from the oxide active layer 3 is. Dissolving in the developer, the photoresist of the upper surface portion of the first region B is dissolved in the developer at the slowest speed, and the photoresist in the first region B in contact with the oxide active layer 3 is dissolved in the developer. The fastest, finally the photoresist in the first region B will have an inverted trapezoidal shape, as shown in Figure 3;
  • the development time is greater than or equal to 60 s and less than or equal to 90 s.
  • the photoresist in other regions other than the first region B can be dissolved, and the cross section of the photoresist in the first region B can be inverted trapezoidal.
  • the method before performing mask exposure on the first region B of the dissolution layer 7, the method further includes:
  • the dissolving layer 7 is pre-baked, and the solvent in the dissolving layer 7 is removed by pre-baking.
  • the solvent in the film can be volatilized during the pre-baking process to fix the characteristics of the photoresist and increase the adhesion of the photoresist.
  • the pre-bake time is greater than or equal to 10 min and less than or equal to 12 min.
  • the pre-bake temperature is greater than or equal to 80 ° C and less than or equal to 100 ° C.
  • the dissolution layer 7 is deposited on the oxide active layer 3 of the thin film transistor, and the mask layer exposure process, the reverse drying process, the flood exposure process, and the development process are performed on the dissolution layer 7 so that The dissolving layer 7 is formed in an inverted trapezoidal shape, and the other portions of the source/drain layer 4 except the source 5 and the drain 6 are deposited on the inverted trapezoidal dissolving layer A, and the thickness of the dissolving layer 7 is greater than the thickness of the source/drain layer 4, and then The dissolved layer A of the inverted trapezoid and the source/drain layer 4 thereon are removed by using an organic solvent, thereby forming the source 5 and the drain 6, effectively solving the problem of dry gas engraving when the source 5 and the drain 6 are formed by an etching process.
  • the etching solution destroys the problem of the oxide active layer 3.
  • an embodiment of the present invention provides a method for fabricating an array substrate, including:
  • Step 301 As shown in FIG. 11, and referring to FIG. 2, a gate electrode 1 and a gate line C, a gate insulating layer 2, and an oxide active layer 3 are formed on the base substrate 8, and the gate insulating layer 2 is located at the gate electrode 1 and Between the oxide active layers 3;
  • a gate layer is deposited on the base substrate 8
  • a gate electrode 1 and a gate line C are formed by one patterning process
  • a gate insulating layer 2 is deposited on the gate electrode 1 at the gate.
  • An oxide active layer 3 is formed on the insulating layer 2 by one patterning process, and the gate insulating layer 2 is located between the gate electrode 1 and the oxide active layer 3.
  • Step 302 forming an inverted trapezoidal dissolution layer A on the oxide active layer 3, and dissolving the trapezoidal dissolved layer A in an organic solvent;
  • a dissolution layer 7 is deposited on the oxide active layer 3;
  • the dissolution layer 7 of the first region B on the dissolution layer 7 is subjected to mask exposure, so that the dissolution layer 7 of the first region B generates an acidic substance, and the acidic substance is used to enhance the crosslinking reaction.
  • a region B is located on the oxide active layer 3;
  • dissolution layer 7 is subjected to reverse drying, flood exposure, and development processing to remove the dissolution layer 7 of the region other than the first region B and to convert the dissolution layer 7 in the first region B into an inverted trapezoidal shape.
  • Dissolve layer A as shown in Figure 3.
  • Step 303 depositing a source/drain layer 4 on the oxide active layer 3, the gate insulating layer 2, and the inverted trapezoidal dissolution layer A.
  • the thickness of the inverted trapezoidal dissolution layer A is greater than the thickness of the source/drain layer 4, and is removed by using an organic solvent.
  • source and drain layers 4 other than the source 5 and the drain 6 are deposited on the inverted trapezoidal dissolution layer A; as shown in FIG. 5, and see FIG.
  • the organic solvent removes the inverted trapezoidal dissolution layer A and the source and drain layers 4 thereon, forming the source 5 and the data line D and the drain 6;
  • the difference between the thickness of the inverted trapezoidal dissolution layer A and the thickness of the source/drain layer 4 is greater than or equal to 2 micrometers.
  • Step 304 forming a passivation layer 9 on the source 5, the oxide active layer 3 and the drain 6;
  • a passivation layer 9 is formed on the source 5, the oxide active layer 3 and the drain 6;
  • Step 305 Forming the pixel electrode 10 on the passivation layer 9.
  • a pixel electrode layer is deposited on the passivation layer 9, and the pixel electrode 10 is formed by one patterning process.
  • the dissolution layer 7 may form a plurality of inverted trapezoidal dissolution layers A;
  • the dissolved layer A of the inverted trapezoid and the source/drain layer 4 thereon are dissolved by using an organic solvent to form the source 5 and the drain 6. Removing excess source and drain layer 4, as shown in FIG. 17;
  • a passivation layer 9 is deposited, and a pixel electrode layer is deposited on the passivation layer to form a pixel electrode.
  • the pixel electrode of the embodiment of the present invention may be any one of a liquid crystal pixel electrode, a common electrode, and an anode or a cathode in the OLED backplane, which is not limited herein.
  • the dissolution layer 7 is deposited on the oxide active layer 3 of the array substrate, and the mask layer exposure process, the reverse drying process, the flood exposure process, and the development process are performed on the dissolution layer 7 to make
  • the dissolving layer 7 is formed in an inverted trapezoidal shape, and the other portions of the source/drain layer 4 except the source 5 and the drain 6 are deposited on the inverted trapezoidal dissolving layer A, and the thickness of the dissolving layer 7 is greater than the thickness of the source/drain layer 4, and then
  • the dissolved layer A of the inverted trapezoid and the source/drain layer 4 thereon are removed by using an organic solvent, thereby forming the source 5 and the drain 6, effectively solving the problem of dry gas engraving when the source 5 and the drain 6 are formed by an etching process.
  • the etching solution destroys the problem of the oxide active layer 3.
  • Embodiments of the present invention provide a display panel including an array substrate formed using the method described above.
  • Embodiments of the present invention provide a display device including the display panel as described above.
  • an embodiment of the present invention provides a method for fabricating a thin film transistor, including:
  • Step 401 Form a gate electrode 1, a gate insulating layer 2, a source 5 and a drain 6 of the thin film transistor by a patterning process, the source 5 and the drain 6 are located in the same layer, and the gate insulating layer 2 is located at the source 5 and the drain 6. Between and the gate 1;
  • a gate electrode 1 is formed by a patterning process, a gate insulating layer 2 is deposited on the gate electrode 1, and a source electrode 5 and a drain electrode 6 are formed on the gate insulating layer 2 by a patterning process.
  • Step 402 As shown in FIG. 21, an inverted trapezoidal dissolution layer A is formed on the source 5 and the drain 6, and the inverted trapezoidal dissolution layer A is dissolved in an organic solvent;
  • the organic solvent is acetone or chlorobenzene.
  • Step 403 depositing a metal oxide active layer 11 on the source 5, the drain 6, the gate insulating layer 2, and the inverted trapezoidal dissolution layer A.
  • the thickness of the inverted trapezoidal dissolution layer A is greater than that of the metal oxide active layer 11. thickness;
  • the thickness of the inverted trapezoidal dissolution layer A is larger than the thickness of the metal oxide active layer 11, so that the metal oxide active layer 11 deposited on the inverted trapezoidal dissolution layer A is deposited on the inverted trapezoidal shape.
  • the metal oxide active layers 11 other than the dissolution layer A do not contact each other.
  • the difference between the thickness of the inverted trapezoidal dissolution layer A and the thickness of the metal oxide active layer 11 is greater than Or equal to 2 microns.
  • Step 404 Dissolving the insoluble trapezoidal dissolving layer A and the metal oxide active layer 11 thereon by using an organic solvent to form the oxide active layer 3.
  • the dissolved layer A of the inverted trapezoid is removed by dissolving with an organic solvent, and the metal oxide active layer 11 deposited on the dissolved layer A of the inverted trapezoid is removed together with the dissolved layer A of the inverted trapezoid to form an oxidation.
  • the active layer 3 is as shown in FIG.
  • the other portion of the metal oxide active layer 11 excluding the oxide active layer 3 is deposited by forming an inverted trapezoidal dissolution layer A on the source 5 and the drain 6 of the thin film transistor.
  • the thickness of the inverted trapezoidal dissolution layer A is larger than the thickness of the metal oxide layer 11, and the inverted trapezoidal dissolution layer A and the metal oxide layer 11 thereon are removed using an organic solvent to form an oxidation.
  • the active layer 3 effectively solves the problem that the acidic etching solution corrodes the metal wiring of the source 5 and the drain 6 when the oxide active layer 3 is formed by a wet etching process.
  • an embodiment of the present invention provides a method for forming an inverted trapezoidal dissolution layer A on a source 5 and a drain 6, which includes:
  • Step 501 depositing a dissolution layer 7 on the source 5 and the drain 6, the thickness of the dissolution layer 7 being greater than the thickness of the metal oxide active layer 11;
  • a dissolution layer 7 is deposited on the source 5 and the drain 6, and the dissolution layer 7 is dissolved in an organic solvent.
  • Step 502 performing mask exposure on the dissolution layer 7 in the second region E and the third region F as shown in FIG. 26, so that the dissolution layer 7 in the second region E and the third region F generates an acidic substance, an acidic substance.
  • the second region E is located on the source 5
  • the third region F is located on the drain 6;
  • the process of masking the dissolution layer 7 in the second region E and the third region F is: using a mask, only the dissolution layer 7 in the second region E and the third region F is masked; The dissolution layer 7 except the second region E and the third region F is exposed.
  • the second region E is located on the source 5, and the third region F is located on the drain 6, and the dissolution layer 7 in the second region E and the third region F is mask exposed.
  • the material of the dissolving layer 7 is selected as a photoresist, the photoresist in the second region E and the third region F is subjected to mask exposure to the second region E and the third region F of the photoresist, and a carboxylic acid is generated.
  • the carboxylic acid can enhance the crosslinking reaction.
  • the portion of the photoresist in the second region E that is farther away from the source 5 is exposed to the mask during the mask exposure, the stronger the exposure of the mask, the farther the photoresist in the second region E is from the source 5 The more carboxylic acid that is partially produced.
  • the photoresist of the upper surface portion of the second region E produces the most carboxylic acid, and the photoresist in contact with the source 5 in the second region E produces the least carboxylic acid.
  • the portion of the photoresist in the third region F that is further away from the drain 6 is exposed to the stronger the intensity of the mask, so the portion of the photoresist in the third region F that is farther from the drain 6 generates more carboxylic acid.
  • the photoresist of the upper surface portion of the third region F generates the most carboxylic acid, and the photoresist in contact with the drain 6 in the third region generates the least carboxylic acid.
  • the mask exposure time is greater than or equal to 5 s and less than or equal to 6 s.
  • the light exposed by the mask is greater than or equal to 30 mJ/cm 2 and less than or equal to 60 mJ/cm 2 .
  • Step 503 Perform reverse drying on the dissolution layer 7.
  • the thin film transistor is inverted, and then the photoresist of the inverted thin film transistor is dried, and the photoresist undergoes a crosslinking reaction during the reverse drying process, and the second region E and the third region F
  • the photoresist in the photoresist is stronger under the action of the carboxylic acid than the photoresist in the other regions, and the molecules of the photoresist in the second region E and the third region F after the reverse drying are performed.
  • the density and hardness are higher than those of other regions.
  • the portion of the photoresist in the second region E that is farther from the source 5 generates more carboxylic acid
  • the portion of the photoresist in the third region F that is farther from the drain 6 generates more carboxylic acid, so
  • the portion of the second region E that is farther from the source 5 and the portion of the third region F that is farther from the drain 6 have a stronger cross-linking reaction, and the second region E is farther from the source 5
  • the portion of the photoresist and the portion of the third region F that is further away from the drain 6 have a higher molecular density and hardness.
  • the photoresist of the upper surface portion of the second region E has the highest molecular density and hardness, and the photoresist in the second region E which is in contact with the source 5 has the lowest molecular density and hardness.
  • the photoresist of the upper surface portion of the third region F has the highest molecular density and hardness, and the photoresist in contact with the drain electrode 6 in the third region F has the lowest molecular density and hardness.
  • the time of reverse drying is greater than or equal to 10 min and less than or equal to 12 min.
  • the temperature of the reverse drying is greater than or equal to 80 ° C and less than or equal to 100 ° C.
  • the photoresist can be sufficiently cross-linked.
  • Step 504 performing a flood exposure on the dissolution layer 7 after the reverse drying, in which the molecular chains of the dissolution layer 7 in the regions other than the second region E and the third region F are broken during the pan exposure;
  • the dissolution layer 7 in the second region E and the third region F and The dissolution layers 7 of the other regions other than the second region E and the third region F are exposed.
  • the over-exposure of the photoresist of the reverse-transferred thin film transistor is performed, because the photoresist in the second region E and the third region F undergoes a crosslinking reaction under the action of the carboxylic acid, and the intensity of the crosslinking reaction is stronger than that of other regions.
  • the molecular density and hardness of the photoresist in the second region E and the third region F after inversion drying are higher than those in other regions, so the pan exposure process will remove the second region E and the first The molecular chains of the photoresist in other regions outside the three regions F are broken, and the molecular density of the photoresist in the second region E and the third region F is broken, and the molecular chain of the lower hardness is broken, so that the second The farther away the photoresist in the region E is from the source 5 and the further the photoresist in the third region F is from the drain 6, the less molecules are broken by the molecular chain.
  • the time of the pan exposure is greater than or equal to 5 s and less than or equal to 6 s.
  • the light of the overexposure is greater than or equal to 30 mJ/cm 2 and less than or equal to 60 mJ/cm 2 .
  • the light intensity and time of the overexposure are controlled within a reasonable range, so that the photoresist is sufficiently exposed to prepare for the next step of developing the inverted trapezoidal dissolution layer A.
  • Step 505 developing the dissolving layer 7 after the overexposure, so that the dissolving layer 7 in the other regions is dissolved in the developing solution and the dissolving layer 7 in the second region E and the third region F is turned into an inverted trapezoidal dissolving layer.
  • the second region E and the third region The photoresist of other regions outside the region F is dissolved in the developer due to the density of the photoresist in the portion of the second region E farther from the source 5 and the portion of the third region F farther from the drain 6
  • the photoresist of the surface portion is the slowest to dissolve in the developer, and the photoresist in contact with the source 5 in the second region E is dissolved in the developer at the fastest speed, and the photoresist on the upper surface portion of the third region F is photolithographically.
  • the glue dissolves in the developer at the slowest speed, and the photoresist in the third region F that is in contact with the drain 6 dissolves in the developer at the fastest speed, and finally the photoresist in the second region E and the third region F Presenting an inverted trapezoidal shape as shown in FIG. 21;
  • the development time is greater than or equal to 60 s and less than or equal to 90 s.
  • the photoresist of the other regions other than the second region E and the third region F can be dissolved, and the cross section of the photoresist in the second region E and the third region F can be made. Form an inverted trapezoid.
  • the method further comprises: pre-baking the dissolution layer 7, and pre-baking to remove the solvent in the dissolution layer 7.
  • the solvent in the film can be volatilized during the pre-baking process to fix the characteristics of the photoresist and increase the adhesion of the photoresist.
  • the pre-bake time is greater than or equal to 10 min and less than or equal to 12 min.
  • the pre-bake temperature is greater than or equal to 80 ° C and less than or equal to 100 ° C.
  • a dissolution layer 7 is deposited on the source 5 and the drain 6 of the thin film transistor, and the mask layer is subjected to a mask exposure process, an inversion drying process, a pan exposure process, and a development process.
  • the dissolution layer 7 is formed into an inverted trapezoidal shape, and the other portion of the oxide active layer 11 of the metal oxide active layer 11 is deposited on the inverted trapezoidal dissolution layer A, and the thickness of the dissolution layer 7 is larger than that of the metal oxide layer 11.
  • the thickness of the layer is further removed by using an organic solvent to remove the inverted trapezoidal dissolved layer A and the metal oxide active layer 11 thereon, thereby forming the oxide active layer 3, which effectively solves the problem of forming an oxide active using a wet etching process.
  • the acidic etchant etches the problem of metal wiring of source 5 and drain 6 .
  • an embodiment of the present invention provides a method for fabricating an array substrate, including:
  • Step 601 As shown in FIG. 11, and referring to FIG. 20, a gate electrode 1 and a gate line C, a gate insulating layer 2, a source 5, and a data line D and a drain 6 are formed on the base substrate 8, and the source 5 and The data line D and the drain 6 are located in the same layer, and the gate insulating layer 2 is located between the source 5, the drain 6 and the gate 1;
  • a gate layer is deposited on the base substrate 8
  • a gate electrode 1 and a gate line C are formed by one patterning process
  • a gate insulating layer 2 is deposited on the gate electrode 1 at the gate.
  • the source 5 and the data line D and the drain 6 are formed on the insulating layer 2 by one patterning process, and the gate insulating layer 2 is located between the source 5, the drain 6, and the gate 1.
  • Step 602 forming an inverted trapezoidal dissolution layer A on the source 5 and the drain 6, and dissolving the trapezoidal dissolved layer A in an organic solvent;
  • a deposition layer 7 is deposited on the source 5 and the drain 6;
  • the second layer E on the dissolution layer 7 and the dissolution layer 7 in the third region F are mask exposed to cause the dissolution of the dissolution layer 7 in the second region E and the third region F.
  • a substance, an acidic substance is used to enhance the crosslinking reaction, and the second region E and the third region F are located on the oxide active layer 3;
  • the dissolution layer 7 is subjected to reverse drying, pan exposure, and development processing to remove the second region.
  • the dissolution layer 7 of the regions other than E and the third region F is removed and the dissolution layer 7 in the second region E and the third region F is converted into the dissolution layer A of the inverted trapezoid as shown in FIG.
  • Step 603 depositing a metal oxide active layer 11 on the source 5, the drain 6, the gate insulating layer 2, and the inverted trapezoidal dissolution layer A.
  • the thickness of the inverted trapezoidal dissolution layer A is greater than that of the metal oxide active layer 11. Thickness, using an organic solvent to dissolve and remove the inverted trapezoidal dissolved layer A and the metal oxide active layer 11 thereon, forming an oxide active layer 3;
  • a metal oxide active layer 11 other than the oxide active layer 3 is deposited on the inverted trapezoidal dissolution layer A, and the inverted trapezoid is removed using an organic solvent. Dissolving layer A and metal oxide active layer 11 thereon, forming oxide active layer 3, as shown in FIG. 23;
  • the difference between the thickness of the inverted trapezoidal dissolution layer A and the thickness of the metal oxide layer 11 is greater than or equal to 2 micrometers.
  • Step 604 forming a passivation layer 9 on the source 5, the oxide active layer 3 and the drain 6;
  • a passivation layer 9 is formed on the source 5, the oxide active layer 3 and the drain 6;
  • Step 605 Forming the pixel electrode 10 on the passivation layer 9.
  • a pixel electrode layer is deposited on the passivation layer 9, and the pixel electrode 10 is formed by one patterning process.
  • the pixel electrode in the embodiment of the present invention may be one of a liquid crystal pixel electrode, a common electrode, and an anode or a cathode in the OLED backplane, which is not limited herein.
  • the dissolving layer 7 is deposited on the source 5 and the drain 6 of the array substrate, and the masking exposure process, the reverse drying process, the pan exposure process, and the development process are performed on the dissolving layer 7 .
  • the dissolution layer 7 is formed into an inverted trapezoidal shape, and the other portion of the oxide active layer 11 of the metal oxide active layer 11 is deposited on the inverted trapezoidal dissolution layer A, and the thickness of the dissolution layer 7 is greater than that of the metal oxide.
  • the thickness of the layer 11 is further removed by using an organic solvent to remove the inverted trapezoidal dissolved layer A and the metal oxide active layer 11 thereon, thereby forming the oxide active layer 3, which effectively solves the formation of an oxide using a wet etching process.
  • the acidic etching solution erodes the problem of the metal wiring of the source 5 and the drain 6.
  • Embodiments of the present invention provide a display panel including an array substrate formed using the method described above.
  • Embodiments of the present invention provide a display device including the display panel as described above.

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Abstract

薄膜晶体管的制作方法、阵列基板的制作方法、显示面板以及显示装置。该薄膜晶体管的制作方法包括：通过构图工艺形成薄膜晶体管的栅极(1)、栅绝缘层(2)和氧化物有源层(3)，栅绝缘层(2)位于所述栅极(1)和氧化物有源层(3)之间；在氧化物有源层(3)上形成截面为倒梯形的溶解层(7)，倒梯形的溶解层(7)能溶于有机溶剂；在氧化物有源层(3)、栅绝缘层(2)和倒梯形的溶解层(7)上形成源漏层(4)，倒梯形的溶解层(7)的厚度大于源漏层(4)的厚度；以及使用有机溶剂溶解去除倒梯形的溶解层(7)并去除位于倒梯形的溶解层(7)上的源漏层(4)，形成源极(5)和漏极(6)。有效解决了使用刻蚀工艺形成源极和漏极的过程中而导致氧化物有源层受到破坏的问题。

Description

薄膜晶体管的制作方法、阵列基板的制作方法、显示面板以及显示装置 技术领域
本发明的实施例涉及薄膜晶体管的制作方法、阵列基板的制作方法、显示面板以及显示装置。
背景技术
氧化物薄膜晶体管阵列基板包括背沟道刻蚀型TFT(Thin film transistor，薄膜晶体管)阵列基板、共面型TFT阵列基板和刻蚀阻挡型TFT阵列基板等，其中，背沟道刻蚀型TFT阵列基板和共面型TFT阵列基板因其结构简单而受到了广泛的应用。
背沟道刻蚀型TFT阵列基板的结构为依次在衬底基板上形成栅极、栅绝缘层、氧化物有源层、源极、漏极、钝化层和像素电极。形成源极和漏极时，先在氧化物有源层上沉积源漏层，然后通过一次构图工艺形成源极和漏极。
共面型TFT阵列基板的结构为依次在衬底基板上形成栅极、栅绝缘层、源极、漏极、氧化物有源层、钝化层和像素电极。形成氧化物有源层时，先在源极、栅绝缘层和漏极上沉积金属氧化物层，通过一次构图工艺形成氧化物有源层。
发明内容
根据本发明的实施例，提供一种薄膜晶体管的制作方法。所述方法包括：通过构图工艺形成薄膜晶体管的栅极、栅绝缘层和氧化物有源层，所述栅绝缘层位于所述栅极和所述氧化物有源层之间；在所述氧化物有源层上形成截面为倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；在所述氧化物有源层、所述栅绝缘层和所述倒梯形的溶解层上形成源漏层，所述倒梯形的溶解层的厚度大于所述源漏层的厚度；以及使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述源漏层，形成源极和漏极。
例如，形成在所述倒梯形的溶解层之上的所述源漏层与形成在所述倒梯形的溶解层之外的所述源漏层断开。
例如，所述在所述氧化物有源层上形成倒梯形的溶解层包括：在所述氧化物有源层上形成溶解层；对第一区域内的溶解层进行掩膜曝光，使所述第一区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第一区域位于所述氧化物有源层上，对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第一区域以外的其他区域的溶解层去除以及将所述第一区域内的溶解层变换成倒梯形的溶解层。
例如，在所述掩膜曝光的过程中，所述第一区域内的溶解层离所述氧化物有源层越远的部分受到的掩膜曝光的强度越强，使得所述第一区域内的溶解层离所述氧化物有源层越远的部分产生的酸性物质越多。
例如，所述对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第一区域以外的其他区域的溶解层去除以及将所述第一区域内的溶解层变换成倒梯形的溶解层，包括：对所述薄膜晶体管进行反转烘干，在反转烘干过程中所述溶解层发生交联反应，且所述第一区域内的溶解层在所述酸性物质的作用下发生所述交联反应的强度强于所述其他区域内的溶解层，且在反转烘干后所述第一区域内的溶解层的分子密度和硬度都高于所述其他区域的溶解层；对反转烘干后的所述薄膜晶体管进行泛曝光，在泛曝光的过程中所述其它区域内的溶解层的分子链断开；对泛曝光后的所述溶解层进行显影处理，使所述其他区域的溶解层溶于显影液内以及使所述第一区域内的溶解层变成倒梯形的溶解层。
例如，在所述反转烘干过程中，在所述第一区域内的溶解层中的酸性物质作用下，所述第一区域内的溶解层离所述氧化物有源层越远的部分发生的交联反应的强度越强，使所述第一区域内的溶解层离所述氧化物有源层越远的部分的分子密度和硬度越高；在所述泛曝光的过程中，所述第一区域内的溶解层的分子密度和硬度越低的部分的分子越容易发生分子链断开，使所述第一区域内的溶解层的离所述氧化物有源层越远的部分发生分子链断开的分子越少；在所述显影的过程中，所述第一区域内的溶解层的发生分子链断开越少的部分越难溶解于显影液，使所述第一区域内的溶解层的离所述氧化物有源层越远的部分越难溶于所述显影液。
例如，所述对第一区域内的溶解层进行掩膜曝光之前还包括：对所述溶解层进行前烘，所述前烘去除所述溶解层中的溶剂。
根据本发明的实施例，提供一种阵列基板的制作方法。所述方法包括：在衬底基板上形成栅极及栅线、栅绝缘层和氧化物有源层，所述栅绝缘层位于所述栅极和所述氧化物有源层之间；在所述氧化物有源层上形成截面为倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；在所述氧化物有源层、所述栅绝缘层和所述倒梯形的溶解层上形成源漏层，所述倒梯形的溶解层的厚度大于所述源漏层的厚度，使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述源漏层，形成源极及数据线和漏极；在所述源极、所述氧化物有源层和所述漏极上形成钝化层；在所述钝化层上形成像素电极。
例如，所述在所述氧化物有源层上形成倒梯形的溶解层包括：在所述氧化物有源层上形成溶解层；对第一区域内的溶解层进行掩膜曝光，使所述第一区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第一区域位于所述氧化物有源层上；对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第一区域以外的其他区域的溶解层去除以及将所述第一区域内的溶解层变换成倒梯形的溶解层。
根据本发明的实施例，提供一种显示面板。所述显示面板包括如上所述的方法形成的阵列基板。
根据本发明的实施例，提供一种显示装置。所述显示装置包括如上所述的显示面板。
根据本发明的实施例，提供一种薄膜晶体管的制作方法。所述方法包括：通过构图工艺形成薄膜晶体管的栅极、栅绝缘层、源极和漏极，所述源极和所述漏极位于同一层，所述栅绝缘层位于所述源极、所述漏极和所述栅极之间；在所述源极和所述漏极上形成截面为倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；在所述源极、所述漏极、所述栅绝缘层和所述倒梯形的溶解层上形成金属氧化物有源层，所述倒梯形的溶解层的厚度大于所述金属氧化物有源层的厚度；以及使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述金属氧化物有源层，形成氧化物有源层。
例如，形成在所述倒梯形的溶解层之上的所述金属氧化物有源层与形成在所述倒梯形的溶解层之外的所述金属氧化物有源层断开。
例如，所述在所述源极和所述漏极上形成倒梯形的溶解层包括：在所述源极和所述漏极上形成溶解层；对第二区域和第三区域内的溶解层进行掩膜曝光，使所述第二区域和第三区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第二区域位于所述源极上，所述第三区域位于所述漏极上；对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第二区域和所述第三区域以外的其他区域的溶解层去除以及将所述第二区域和所述第三区域内的溶解层变换成倒梯形的溶解层。
例如，在所述掩膜曝光的过程中，所述第二区域内的溶解层离所述源极越远的部分受到的掩膜曝光的强度越强，使得所述第二区域内的溶解层离所述源极越远的部分产生的酸性物质越多；所述第三区域内的溶解层离所述漏极越远的部分受到的掩膜曝光的强度越强，使得所述第三区域内的溶解层离所述漏极越远的部分产生的酸性物质越多。
例如，所述对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第二区域和所述第三区域以外的其他区域的溶解层去除以及将所述第二区域和所述第三区域内的溶解层变换成倒梯形的溶解层，包括：对所述薄膜晶体管进行反转烘干，在反转烘干过程中所述溶解层发生交联反应，且所述第二区域和所述第三区域内的溶解层在所述酸性物质的作用下发生交联反应的强度强于所述其他区域内的溶解层，且在反转烘干后所述第二区域和所述第三区域内的溶解层的分子密度和硬度都高于所述其他区域的溶解层；对反转烘干后的所述薄膜晶体管进行泛曝光，在泛曝光的过程中所述其它区域内的溶解层的分子链断开；对泛曝光后的所述溶解层进行显影处理，使所述其他区域的溶解层溶于显影液内以及使所述第二区域和所述第三区域内的溶解层变成倒梯形的溶解层。
例如，在所述反转烘干过程中，在所述第二区域内和所述第三区域内的溶解层中的酸性物质作用下，所述第二区域内的溶解层离所述源极越远的部分发生的交联反应的强度越强，使所述第二区域内的溶解层离所述源极越远的部分的分子密度和硬度越高，所述第三区域内的溶解层离所述漏极越远的部分发生的交联反应的强度越强，使所述第三区域内的溶解层离所述漏极越 远的部分的分子密度和硬度越高；在所述泛曝光的过程中，所述第二区域内和所述第三区域内的溶解层的分子密度和硬度越低的部分的分子越容易发生分子链断开，使所述第二区域内的溶解层离所述源极越远的和所述第三区域内的溶解层离所述漏极越远的部分发生分子链断开的分子越少；在所述显影的过程中，所述第二区域内和所述第三区域内的溶解层的发生分子链断开越少的部分越难溶于显影液，使所述第二区域内的溶解层离所述源极越远的和所述第三区域内的溶解层离所述漏极越远的部分越难溶于所述显影液。
例如，所述对第二区域和第三区域内的溶解层进行掩膜曝光之前还包括：对所述溶解层进行前烘，所述前烘去除所述溶解层中的溶剂。
根据本发明的实施例，提供一种阵列基板的制作方法，其中，所述方法包括：在衬底基板上形成栅极及栅线、栅绝缘层、源极及数据线和漏极，所述源极和所述漏极位于同一层，所述栅绝缘层位于所述源极、所述漏极和所述栅极之间；在所述源极和所述漏极上形成截面为倒梯形的倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；在所述源极、所述漏极、所述栅绝缘层和所述倒梯形的溶解层上形成金属氧化物层，所述倒梯形的溶解层的厚度大于所述金属氧化物层的厚度；使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述金属氧化物有源层，形成氧化物有源层；在所述源极、所述氧化物有源层和所述漏极上形成钝化层；在所述钝化层上形成像素电极。
例如，在所述源极和所述漏极上形成倒梯形的溶解层包括：在所述源极和所述漏极上形成溶解层；对第二区域和第三区域内的溶解层进行掩膜曝光，使所述第二区域和第三区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第二区域位于所述源极上，所述第三区域位于所述漏极上；对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第二区域和所述第三区域以外的其他区域的溶解层去除以及将所述第二区域和所述第三区域内的溶解层变换成倒梯形的溶解层。
根据本发明的实施例，提供一种显示面板。所述显示面板包括如上所述的方法形成的阵列基板。
根据本发明的实施例，提供一种显示装置。所述显示装置包括如上所述的显示面板。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例一提供的制作薄膜晶体管的方法流程图；
图2-图5是本发明实施例一提供的薄膜晶体管的制作方法示意图；
图6是本发明实施例一提供的形成倒梯形的溶解层的方法流程图；
图7-图8是本发明实施例一提供的形成倒梯形的溶解层的制作方法示意图；
图9是本发明实施例一提供的形成倒梯形的溶解层的方法流程图；
图10是本发明实施例一提供的制作阵列基板的方法流程图；
图11是本发明实施例一提供的阵列基板的结构示意图；
图12-图13是本发明实施例一提供的阵列基板的制作方法示意图；
图14-图18是本发明实施例一提供的形成不同数量的倒梯形的溶解层时阵列基板的制作方法示意图；
图19是本发明实施例二提供的制作薄膜晶体管的方法流程图；
图20-图23是本发明实施例二提供的薄膜晶体管的制作方法示意图；
图24是本发明实施例二提供的形成倒梯形的溶解层的方法流程图；
图25-图26是本发明实施例二提供的形成倒梯形的溶解层的制作方法示意图；
图27是本发明实施例二提供的形成倒梯形的溶解层的方法流程图；
图28是本发明实施例二提供的制作阵列基板的方法流程图；
图29-图30是本发明实施例二提供的阵列基板的制作方法示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
发明人发现背沟道刻蚀型TFT阵列基板和共面型TFT阵列基板至少存在以下问题。
在背沟道刻蚀型TFT阵列基板形成源极和漏极的构图工艺过程中，需要将源漏层的除源极和漏极所在区的其它的部分刻蚀掉，刻蚀的过程会使用到刻蚀液或者刻蚀气体，而刻蚀液或者刻蚀气体会破坏氧化物有源层的特性，使背沟道刻蚀型TFT阵列基板的漏电流增大，降低了背沟道刻蚀型TFT阵列基板的性能。
在共面型TFT阵列基板形成氧化物有源层的构图工艺过程中，需要将金属氧化物层的除氧化物有源层所在区的其他部分刻蚀掉，采用湿法刻蚀的过程中会使用到酸性刻蚀液，酸性刻蚀液会腐蚀源极和漏极图案的金属布线，导致信号的传输时间延长。
实施例一
如图1所示，本发明实施例提供了一种薄膜晶体管的制作方法，包括：
步骤101：通过构图工艺形成薄膜晶体管的栅极1、栅绝缘层2和氧化物有源层3，栅绝缘层2位于栅极1和氧化物有源层3之间；
如图2所示，通过构图工艺形成栅极1，在栅极1上沉积栅绝缘层2，通过构图工艺在栅绝缘层2上形成氧化物有源层3。
步骤102：如图3所示，在氧化物有源层3上形成截面为倒梯形的溶解层A，倒梯形的溶解层A能溶于有机溶剂；
例如，有机溶剂为丙酮或者氯苯。
步骤103：在氧化物有源层3、栅绝缘层2和倒梯形的溶解层A上沉积源漏层4，倒梯形的溶解层A的厚度大于源漏层4的厚度；
如图4所示，倒梯形的溶解层A的厚度大于源漏层4的厚度，所以沉积在倒梯形的溶解层A上的源漏层4与沉积在除倒梯形的溶解层A以外的其它部分的源漏层4不会互相接触。
例如，倒梯形的溶解层A的厚度与源漏层4的厚度差大于或等于2微米。
步骤104：使用有机溶剂溶解去除倒梯形的溶解层A并去除位于倒梯形的溶解层A上的源漏层4，形成源极5和漏极6。
如图5所示，使用有机溶剂溶解去除倒梯形的溶解层A，沉积在倒梯形的溶解层A上的源漏层4随着倒梯形的溶解层A一起被去除，沉积在除倒梯形的溶解层A以外的其它部分的源漏层4保留，形成源极5和漏极6。
在本发明的实施例中，通过在薄膜晶体管的氧化物有源层3上形成倒梯 形的溶解层A，将源漏层4的除源极5和漏极6的其它的部分沉积在倒梯形的溶解层A上，倒梯形的溶解层A的厚度大于源漏层4的厚度，再使用有机溶剂将倒梯形的溶解层A及其上的源漏层4去除，从而形成源极5和漏极6，有效解决了使用刻蚀工艺形成源极5和漏极6的过程中干刻气体或者刻蚀液破坏氧化物有源层3的问题。
进一步地，如图6所示，本发明实施例提供了一种在氧化物有源层3上形成倒梯形的溶解层A的方法，包括：
步骤201：在氧化物有源层3上沉积溶解层7，溶解层7的厚度大于源漏层4的厚度；
例如，如图7所示，在氧化物有源层3上沉积一层溶解层7，该溶解层7溶于有机溶剂。
步骤202：如图8所示，对第一区域B内的溶解层7进行掩膜曝光，使第一区域B内的溶解层7的产生酸性物质，酸性物质用于增强交联反应，第一区域B位于氧化物有源层3上；
例如，对第一区域B内的溶解层7进行掩膜曝光的过程为：采用具有图案的掩模板，使得仅第一区域B内的溶解层7被曝光而除第一区域B之外的其他区域的溶解层7不被曝光。
如图8所示，第一区域B位于氧化物有源层3上，对第一区域B内的溶解层7进行掩膜曝光。若溶解层7的材料选择光刻胶，则在进行掩膜曝光后第一区域B内对应的光刻胶会产生羧酸，羧酸可以增强交联反应。由于掩膜曝光过程中第一区域B内的光刻胶离氧化物有源层3越远的部分受到的掩膜曝光的强度越强，使得第一区域B内的光刻胶离氧化物有源层3越远的部分产生的羧酸越多，所以第一区域B的上表面部分的光刻胶产生的羧酸最多，第一区域B内的与氧化物有源层3接触的光刻胶产生的羧酸最少。
例如，掩膜曝光的时间大于或等于5s且小于或等于6s。
例如，掩膜曝光的光强大于或等于30mJ/cm2且小于或等于60mJ/cm2。
合理的控制掩膜曝光的光强和时间可以使第一区域B内的光刻胶得到适当的曝光，产生适量的羧酸。
步骤203：对溶解层7进行反转烘干。
例如，将薄膜晶体管进行反转，然后对反转后的薄膜晶体管的光刻胶进 行烘干。在反转烘干过程中光刻胶发生交联反应，且第一区域B内的光刻胶在羧酸的作用下发生交联反应的强度强于其他区域内的光刻胶，且在反转烘干后第一区域B内的光刻胶的分子密度和硬度都高于其他区域的光刻胶。由于第一区域B内的光刻胶离氧化物有源层3越远的部分产生的羧酸越多，所以第一区域B内的光刻胶离氧化物有源层3越远的部分产生的交联反应越强，导致第一区域B内的光刻胶离氧化物有源层3越远的部分的分子密度和硬度越高。所以第一区域B的上表面部分的光刻胶的分子密度和硬度最高，第一区域B内的与氧化物有源层3接触的光刻胶的分子密度和硬度最低。
例如，反转烘干的时间大于或等于10min且小于或等于12min。
例如，反转烘干的温度大于或等于80℃且小于或等于100℃。
将反转烘干的温度和时间控制在合理的范围内，可使光刻胶充分的发生交联反应。
步骤204：对反转烘干后的溶解层7进行泛曝光，在泛曝光的过程中除第一区域B外的其它区域内的溶解层7的分子链断开；
例如，泛曝光的过程中，第一区域B内的溶解层7以及除第一区域B之外的其他区域的溶解层7均被曝光。
对反转烘干后的光刻胶进行泛曝光，由于第一区域B内的光刻胶在羧酸的作用下发生交联反应的强度强于溶解层7的其他区域的光刻胶，在反转烘干后第一区域B内的光刻胶的分子密度和硬度都高于其他区域的光刻胶，所以泛曝光过程会使除第一区域B外的其他区域的光刻胶的分子链断开，同时第一区域B内的光刻胶分子密度和硬度较低的部分分子链断开，使第一区域B内的光刻胶离氧化物有源层3越远发生分子链断开的分子越少。
例如，泛曝光的时间为大于或等于5s且小于或等于6s。
例如，泛曝光的光强大于或等于30mJ/cm2且小于或等于60mJ/cm2。
将泛曝光的光强和时间控制在合理的范围内，使光刻胶得到充分的曝光，为下一步显影形成倒梯形的溶解层A做准备。
步骤205：对泛曝光后的溶解层7进行显影处理，使其他区域的溶解层7溶于显影液内以及使第一区域B内的溶解层7变成倒梯形的溶解层A。
对泛曝光后的光刻胶进行显影处理，由于在泛曝光过程后除第一区域B外的其他区域的光刻胶的分子链断开，所以第一区域B外的其他区域的光刻 胶溶于显影液。由于第一区域B内的光刻胶离氧化物有源层3越远的部分密度和硬度越高，所以第一区域B内的光刻胶离氧化物有源层3越远的部分越难溶于显影液，使第一区域B的上表面部分的光刻胶溶于显影液的速度最慢，第一区域B内与氧化物有源层3接触的光刻胶溶于显影液的速度最快，最终第一区域B内的光刻胶会呈现倒梯形的形状，如图3所示；
例如，显影的时间大于或等于60s且小于或等于90s。
将显影的时间控制在合理的范围内，可使第一区域B以外的其它区域的光刻胶溶解，并使第一区域B内的光刻胶的截面形成倒梯形。
例如，如图9所示，对溶解层7的第一区域B进行掩膜曝光之前还包括：
对溶解层7进行前烘，前烘去除溶解层7中的溶剂。
若选择光刻胶作为溶解层7，前烘过程中可以使胶膜里的溶剂挥发出来，使光刻胶的特性固定，增加光刻胶的粘附性。
例如，前烘的时间大于或等于10min且小于或等于12min。
例如，前烘的温度大于或等于80℃且小于或等于100℃。
合理的控制前烘的温度和时间，使光刻胶里的溶剂得到充分的挥发。
在本发明的实施例中，在薄膜晶体管的氧化物有源层3上沉积溶解层7，通过对溶解层7进行掩膜曝光工艺、反转烘干工艺、泛曝光工艺和显影工艺处理，使得溶解层7形成倒梯形的形状，将源漏层4的除源极5和漏极6的其它部分沉积在倒梯形的溶解层A上，溶解层7的厚度大于源漏层4的厚度，再使用有机溶剂将倒梯形的溶解层A及其上的源漏层4去除，从而形成源极5和漏极6，有效解决了使用刻蚀工艺形成源极5和漏极6时干刻气体或者刻蚀液破坏氧化物有源层3的问题。
如图10所示，本发明实施例提供了一种阵列基板的制作方法，包括：
步骤301：如图11所示，且参见图2，在衬底基板8上形成栅极1及栅线C、栅绝缘层2和氧化物有源层3，栅绝缘层2位于栅极1和氧化物有源层3之间；
例如，如图11所示，且参见图2，在衬底基板8上沉积栅极层，通过一次构图工艺形成栅极1及栅线C，在栅极1上沉积栅绝缘层2，在栅绝缘层2上通过一次构图工艺形成氧化物有源层3，栅绝缘层2位于栅极1和氧化物有源层3之间。
步骤302：在氧化物有源层3上形成倒梯形的溶解层A，倒梯形的溶解层A溶于有机溶剂；
例如，如图7所示，首先，在氧化物有源层3上沉积溶解层7；
之后，如图8所示，对溶解层7上的第一区域B的溶解层7进行掩膜曝光，使第一区域B的溶解层7产生酸性物质，酸性物质用于增强交联反应，第一区域B位于氧化物有源层3上；
之后，对溶解层7进行反转烘干、泛曝光和显影处理，以将除第一区域B以外的其他区域的溶解层7去除以及将第一区域B内的溶解层7变换成倒梯形的溶解层A，如图3所示。
步骤303：在氧化物有源层3、栅绝缘层2和倒梯形的溶解层A上沉积源漏层4，倒梯形的溶解层A的厚度大于源漏层4的厚度，使用有机溶剂溶解去除倒梯形的溶解层A以及其上的源漏层4，形成源极5及数据线D和漏极6；
如图4所示，沉积源漏层4时，除源极5和漏极6以外的其它源漏层4沉积在倒梯形的溶解层A上；如图5所示，且参见图11，使用有机溶剂去除倒梯形的溶解层A以及其上的源漏层4，形成源极5及数据线D和漏极6；
例如，倒梯形的溶解层A的厚度与源漏层4的厚度差大于或者等于2微米。
步骤304：在源极5、氧化物有源层3和漏极6上形成钝化层9；
如图12所示，在源极5、氧化物有源层3和漏极6上形成钝化层9；
步骤305：在钝化层9上形成像素电极10。
如图13所示，在钝化层9上沉积像素电极层，通过一次构图工艺形成像素电极10。
例如，如图14所示，在形成倒梯形的溶解层A的过程中，可以将溶解层7形成多个倒梯形的溶解层A；
如图15所示，在氧化物有源层3、栅绝缘层2和倒梯形的溶解层A上沉积源漏层4；
如图16所示，使用有机溶剂溶解去除倒梯形的溶解层A以及其上的源漏层4，形成源极5和漏极6。去除多余的源漏层4，如图17所示；
如图18所示，沉积钝化层9，在钝化层上沉积像素电极层，形成像素电 极10。本发明实施例的像素电极可以为液晶像素电极、公共电极、OLED背板中的阳极或阴极中的任意一种，在此不做限定。
在本发明的实施例中，在阵列基板的氧化物有源层3上沉积溶解层7，通过对溶解层7进行掩膜曝光工艺、反转烘干工艺、泛曝光工艺和显影工艺处理，使得溶解层7形成倒梯形的形状，将源漏层4的除源极5和漏极6的其它部分沉积在倒梯形的溶解层A上，溶解层7的厚度大于源漏层4的厚度，再使用有机溶剂将倒梯形的溶解层A及其上的源漏层4去除，从而形成源极5和漏极6，有效解决了使用刻蚀工艺形成源极5和漏极6时干刻气体或者刻蚀液破坏氧化物有源层3的问题。
本发明实施例提供了一种显示面板，该显示面板包括使用如上所述的方法形成的阵列基板。
本发明实施例提供了一种显示装置，该显示装置包括如上所述的显示面板。
实施例二
如图19所示，本发明实施例提供了一种薄膜晶体管的制作方法，包括：
步骤401：通过构图工艺形成薄膜晶体管的栅极1、栅绝缘层2、源极5和漏极6，源极5和漏极6位于同一层，栅绝缘层2位于源极5、漏极6和栅极1之间；
如图20所示，通过构图工艺形成栅极1，在栅极1上沉积栅绝缘层2，通过构图工艺在栅绝缘层2上形成源极5和漏极6。
步骤402：如图21所示，在源极5和漏极6上形成倒梯形的溶解层A，倒梯形的溶解层A溶于有机溶剂；
例如，有机溶剂为丙酮或者氯苯。
步骤403：在源极5、漏极6、栅绝缘层2和倒梯形的溶解层A上沉积金属氧化物有源层11，倒梯形的溶解层A的厚度大于金属氧化物有源层11的厚度；
如图22所示，倒梯形的溶解层A的厚度大于金属氧化物有源层11的厚度，所以沉积在倒梯形的溶解层A上的金属氧化物有源层11与沉积在除倒梯形的溶解层A以外的其它部分的金属氧化物有源层11不会互相接触。
例如，倒梯形的溶解层A的厚度与金属氧化物有源层11的厚度差大于 或等于2微米。
步骤404：使用有机溶剂溶解去除倒梯形的溶解层A以及其上的金属氧化物有源层11，形成氧化物有源层3。
如图22所示，使用有机溶剂溶解去除倒梯形的溶解层A，沉积在倒梯形的溶解层A上的金属氧化物有源层11随着倒梯形的溶解层A一并被去除，形成氧化物有源层3，如图23所示。
在本发明的实施例中，通过在薄膜晶体管的源极5和漏极6上形成倒梯形的溶解层A，将金属氧化物有源层11的除氧化物有源层3的其它部分沉积在倒梯形的溶解层A上，倒梯形的溶解层A的厚度大于金属氧化物层11的厚度，再使用有机溶剂将倒梯形的溶解层A及其上的金属氧化物层11去除，从而形成氧化物有源层3，有效解决了使用湿法刻蚀工艺形成氧化物有源层3时酸性刻蚀液腐蚀源极5和漏极6金属布线的问题。
如图24所示，本发明实施例提供了一种在源极5和漏极6上形成倒梯形的溶解层A的方法，包括：
步骤501：在源极5和漏极6上沉积溶解层7，溶解层7的厚度大于金属氧化物有源层11的厚度；
例如，如图25所示，在源极5和漏极6上沉积一层溶解层7，该溶解层7溶于有机溶剂。
步骤502：如图26所示，对第二区域E和第三区域F内的溶解层7进行掩膜曝光，使第二区域E和第三区域F内的溶解层7产生酸性物质，酸性物质用于增强交联反应，第二区域E位于源极5上，第三区域F位于漏极6上；
例如，对第二区域E和第三区域F内的溶解层7进行掩膜曝光的过程为：采用掩模板，仅对第二区域E和第三区域F内的溶解层7进行掩膜而不对除第二区域E和第三区域F外的溶解层7曝光。
如图26所示，第二区域E位于源极5上，第三区域F位于漏极6上，对第二区域E和第三区域F内的溶解层7进行掩膜曝光。若溶解层7的材料选择光刻胶，则对光刻胶的第二区域E和第三区域F进行掩膜曝光后第二区域E和第三区域F内的光刻胶会产生羧酸，羧酸可以增强交联反应。由于掩膜曝光过程中第二区域E内的光刻胶离源极5越远的部分受到的掩膜曝光的强度越强，所以第二区域E内的光刻胶离源极5越远的部分产生的羧酸越多， 第二区域E的上表面部分的光刻胶产生的羧酸最多，第二区域E内与源极5接触的光刻胶产生的羧酸最少。第三区域F内光刻胶离漏极6越远的部分受到的掩膜曝光的强度越强，所以第三区域F内的光刻胶离漏极6越远的部分产生的羧酸越多，第三区域F的上表面部分的光刻胶产生的羧酸最多，第三区域内的与漏极6接触的光刻胶产生的羧酸最少。
例如，掩膜曝光的时间大于或等于5s且小于或等于6s。
例如，掩膜曝光的光强大于或等于30mJ/cm2且小于或等于60mJ/cm2。
合理的控制掩膜曝光的光强和时间可以使第二区域E和第三区域F内的光刻胶得到适当的曝光，产生适量的羧酸。
步骤503：对溶解层7进行反转烘干。
例如，将薄膜晶体管进行反转，然后对反转后的薄膜晶体管的光刻胶进行烘干，在反转烘干过程中光刻胶发生交联反应，且第二区域E和第三区域F内的光刻胶在羧酸的作用下发生交联反应的强度强于其他区域内的光刻胶，且在反转烘干后第二区域E和第三区域F内的光刻胶的分子密度和硬度都高于其他区域的光刻胶。由于第二区域E内的光刻胶离源极5越远的部分产生的羧酸越多，第三区域F内的光刻胶离漏极6越远的部分产生的羧酸越多，所以第二区域E内离源极5越远的部分和第三区域F内离漏极6越远的部分的光刻胶产生的交联反应越强，第二区域E内离源极5越远的部分和第三区域F内离漏极6越远的部分的光刻胶的分子密度和硬度越高。第二区域E的上表面部分的光刻胶的分子密度和硬度最高，第二区域E内与源极5接触的光刻胶的分子密度和硬度最低。第三区域F的上表面部分的光刻胶的分子密度和硬度最高，第三区域F内与漏极6接触的光刻胶的分子密度和硬度最低。
例如，反转烘干的时间大于或等于10min且小于或等于12min。
例如，反转烘干的温度大于或等于80℃且小于或等于100℃。
将反转烘干的温度和时间控制在合理的范围内，可使光刻胶充分的发生交联反应。
步骤504：对反转烘干后的溶解层7进行泛曝光，在泛曝光的过程中除第二区域E和第三区域F外的其它区域内的溶解层7的分子链断开；
例如，泛曝光的过程中，第二区域E和第三区域F内的溶解层7以及除 第二区域E和第三区域F内之外的其他区域的溶解层7均被曝光。
对反转烘干后的薄膜晶体管的光刻胶进行泛曝光，由于第二区域E和第三区域F内的光刻胶在羧酸的作用下发生交联反应的强度强于其他区域的光刻胶，在反转烘干后第二区域E和第三区域F内的光刻胶的分子密度和硬度都高于其他区域的光刻胶，所以泛曝光过程会除第二区域E和第三区域F外的其他区域的光刻胶的分子链断开，同时第二区域E内和第三区域F内的光刻胶的分子密度和硬度较低的部分分子链断开，使第二区域E内的光刻胶离源极5越远的和第三区域F内的光刻胶离漏极6越远的部分发生分子链断开的分子越少。
例如，泛曝光的时间为大于或等于5s且小于或等于6s。
例如，泛曝光的光强大于或等于30mJ/cm2且小于或等于60mJ/cm2。
将泛曝光的光强和时间控制在合理的范围内，使光刻胶得到充分的曝光，为下一步显影形成倒梯形的溶解层A做准备。
步骤505：对泛曝光后的溶解层7进行显影处理，使其他区域的溶解层7溶于显影液内以及使第二区域E和第三区域F内的溶解层7变成倒梯形的溶解层A。
对泛曝光后的光刻胶进行显影处理，由于在泛曝光过程后除第二区域E和第三区域F外的其他区域的光刻胶的分子链断开，所以第二区域E和第三区域F外的其他区域的光刻胶溶于显影液，由于第二区域E内离源极5越远的部分和第三区域F内离漏极6越远的部分的光刻胶的密度和硬度越高，所以第二区域E内离源极5越远的部分和第三区域F内离漏极6越远的部分的光刻胶越难溶于显影液，使第二区域E的上表面部分的光刻胶溶于显影液的速度最慢，第二区域E内的与源极5接触的光刻胶溶于显影液的速度最快，第三区域F的上表面部分的光刻胶溶于显影液的速度最慢，第三区域F内的与漏极6接触的光刻胶溶于显影液的速度最快，最终第二区域E和第三区域F内的光刻胶会呈现倒梯形的形状，如图21所示；
例如，显影的时间大于或等于60s且小于或等于90s。
将显影的时间控制在合理的范围内，可使第二区域E和第三区域F以外的其它区域的光刻胶溶解，并使第二区域E和第三区域F内的光刻胶的截面形成倒梯形。
例如，如图27所示，对溶解层7的第二区域E和第三区域F进行掩膜曝光之前还包括：对溶解层7进行前烘，前烘去除溶解层7中的溶剂。
若选择光刻胶作为溶解层7，前烘过程中可以使胶膜里的溶剂挥发出来，使光刻胶的特性固定，增加光刻胶的粘附性。
例如，前烘的时间大于或等于10min且小于或等于12min。
例如，前烘的温度大于或等于80℃且小于或等于100℃。
合理的控制前烘的温度和时间，使光刻胶里的溶剂得到充分的挥发。
在本发明的实施例中，在薄膜晶体管的源极5和漏极6上沉积溶解层7，通过对溶解层7进行掩膜曝光工艺、反转烘干工艺、泛曝光工艺和显影工艺处理，使得溶解层7形成倒梯形的形状，将金属氧化物有源层11的除氧化物有源层3的其它部分沉积在倒梯形的溶解层A上，溶解层7的厚度大于金属氧化物层11的厚度，再使用有机溶剂将倒梯形的溶解层A及其上的金属氧化物有源层11去除，从而形成氧化物有源层3，有效解决了使用湿法刻蚀工艺形成氧化物有源层3时酸性刻蚀液腐蚀源极5和漏极6金属布线的问题。
如图28所示，本发明实施例提供了一种阵列基板的制作方法，包括：
步骤601：如图11所示，且参见图20，在衬底基板8上形成栅极1及栅线C、栅绝缘层2、源极5及数据线D和漏极6，源极5及数据线D和漏极6位于同一层，栅绝缘层2位于源极5、漏极6和栅极1之间；
例如，如图11所示，且参见图20，在衬底基板8上沉积栅极层，通过一次构图工艺形成栅极1及栅线C，在栅极1上沉积栅绝缘层2，在栅绝缘层2上通过一次构图工艺形成源极5及数据线D和漏极6，栅绝缘层2位于源极5、漏极6和栅极1之间。
步骤602：在源极5和漏极6上形成倒梯形的溶解层A，倒梯形的溶解层A溶于有机溶剂；
例如，如图25所示，首先，在源极5和漏极6上沉积溶解层7；
之后，如图26所示，对溶解层7上的第二区域E和第三区域F内的溶解层7进行掩膜曝光，使第二区域E和第三区域F内的溶解层7产生酸性物质，酸性物质用于增强交联反应，第二区域E和第三区域F位于氧化物有源层3上；
之后，对溶解层7进行反转烘干、泛曝光和显影处理，以将除第二区域 E和第三区域F以外的其他区域的溶解层7去除以及将第二区域E和第三区域F内的溶解层7变换成倒梯形的溶解层A，如图21所示。
步骤603：在源极5、漏极6、栅绝缘层2和倒梯形的溶解层A上沉积金属氧化物有源层11，倒梯形的溶解层A的厚度大于金属氧化物有源层11的厚度，使用有机溶剂溶解去除倒梯形的溶解层A以及其上的金属氧化物有源层11，形成氧化物有源层3；
如图22所示，在沉积金属氧化物有源层11时，除氧化物有源层3以外的其它金属氧化物有源层11沉积在倒梯形的溶解层A上，使用有机溶剂去除倒梯形的溶解层A以及其上的金属氧化物有源层11，形成氧化物有源层3，如图23所示；
例如，倒梯形的溶解层A的厚度与金属氧化物层11的厚度差大于或者等于2微米。
步骤604：在源极5、氧化物有源层3和漏极6上形成钝化层9；
如图29所示，在源极5、氧化物有源层3和漏极6上形成钝化层9；
步骤605：在钝化层9上形成像素电极10。
如图30所示，在钝化层9上沉积像素电极层，通过一次构图工艺形成像素电极10。本发明实施例像素电极可以为液晶像素电极、公共电极、OLED背板中的阳极或阴极中的一种，在此不做限定。
在本发明的实施例中，在阵列基板的源极5和漏极6上沉积溶解层7，通过对溶解层7进行掩膜曝光工艺、反转烘干工艺、泛曝光工艺和显影工艺处理，使得溶解层7形成倒梯形的形状，将金属氧化物有源层11的除氧化物有源层3的其它部分沉积在倒梯形的溶解层A上，溶解层7的厚度大于金属氧化物有源层11的厚度，再使用有机溶剂将倒梯形的溶解层A及其上的金属氧化物有源层11去除，从而形成氧化物有源层3，有效解决了使用湿法刻蚀工艺形成氧化物有源层3时酸性刻蚀液腐蚀源极5和漏极6金属布线的问题。
本发明实施例提供了一种显示面板，该显示面板中包括使用如上所述的方法形成的阵列基板。
本发明实施例提供了一种显示装置，该显示装置包括如上所述的显示面板。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年10月29日递交的第201510718317.3号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (22)

  1. 一种薄膜晶体管的制作方法，其中，所述方法包括：
    通过构图工艺形成薄膜晶体管的栅极、栅绝缘层和氧化物有源层，所述栅绝缘层位于所述栅极和所述氧化物有源层之间；
    在所述氧化物有源层上形成截面为倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；
    在所述氧化物有源层、所述栅绝缘层和所述倒梯形的溶解层上形成源漏层，所述倒梯形的溶解层的厚度大于所述源漏层的厚度；以及
    使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述源漏层，形成源极和漏极。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中，形成在所述倒梯形的溶解层之上的所述源漏层与形成在所述倒梯形的溶解层之外的所述源漏层断开。
  3. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述在所述氧化物有源层上形成倒梯形的溶解层包括：
    在所述氧化物有源层上形成溶解层；
    对第一区域内的溶解层进行掩膜曝光，使所述第一区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第一区域位于所述氧化物有源层上，
    对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第一区域以外的其他区域的溶解层去除以及将所述第一区域内的溶解层变换成倒梯形的溶解层。
  4. 根据权利要求3所述的薄膜晶体管的制作方法，其中，在所述掩膜曝光的过程中，
    所述第一区域内的溶解层离所述氧化物有源层越远的部分受到的掩膜曝光的强度越强，使得所述第一区域内的溶解层离所述氧化物有源层越远的部分产生的酸性物质越多。
  5. 根据权利要求3所述的薄膜晶体管的制作方法，其中，所述对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第一区域以外的其他区 域的溶解层去除以及将所述第一区域内的溶解层变换成倒梯形的溶解层，包括：
    对所述薄膜晶体管进行反转烘干，在反转烘干过程中所述溶解层发生交联反应，且所述第一区域内的溶解层在所述酸性物质的作用下发生所述交联反应的强度强于所述其他区域内的溶解层，且在反转烘干后所述第一区域内的溶解层的分子密度和硬度都高于所述其他区域的溶解层；
    对反转烘干后的所述薄膜晶体管进行泛曝光，在泛曝光的过程中所述其它区域内的溶解层的分子链断开；
    对泛曝光后的所述溶解层进行显影处理，使所述其他区域的溶解层溶于显影液内以及使所述第一区域内的溶解层变成倒梯形的溶解层。
  6. 根据权利要求5所述的薄膜晶体管的制作方法，其中，
    在所述反转烘干过程中，在所述第一区域内的溶解层中的酸性物质作用下，所述第一区域内的溶解层离所述氧化物有源层越远的部分发生的交联反应的强度越强，使所述第一区域内的溶解层离所述氧化物有源层越远的部分的分子密度和硬度越高；
    在所述泛曝光的过程中，所述第一区域内的溶解层的分子密度和硬度越低的部分的分子越容易发生分子链断开，使所述第一区域内的溶解层的离所述氧化物有源层越远的部分发生分子链断开的分子越少；
    在所述显影的过程中，所述第一区域内的溶解层的发生分子链断开越少的部分越难溶解于显影液，使所述第一区域内的溶解层的离所述氧化物有源层越远的部分越难溶于所述显影液。
  7. 根据权利要求3所述的薄膜晶体管的制作方法，其中，所述对第一区域内的溶解层进行掩膜曝光之前还包括：
    对所述溶解层进行前烘，所述前烘去除所述溶解层中的溶剂。
  8. 一种阵列基板的制作方法，其中，所述方法包括：
    在衬底基板上形成栅极及栅线、栅绝缘层和氧化物有源层，所述栅绝缘层位于所述栅极和所述氧化物有源层之间；
    在所述氧化物有源层上形成截面为倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；
    在所述氧化物有源层、所述栅绝缘层和所述倒梯形的溶解层上形成源漏 层，所述倒梯形的溶解层的厚度大于所述源漏层的厚度，使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述源漏层，形成源极及数据线和漏极；
    在所述源极、所述氧化物有源层和所述漏极上形成钝化层；
    在所述钝化层上形成像素电极。
  9. 根据权利要求8所述的阵列基板的制作方法，其中，所述在所述氧化物有源层上形成倒梯形的溶解层包括：
    在所述氧化物有源层上形成溶解层；
    对第一区域内的溶解层进行掩膜曝光，使所述第一区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第一区域位于所述氧化物有源层上；
    对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第一区域以外的其他区域的溶解层去除以及将所述第一区域内的溶解层变换成倒梯形的溶解层。
  10. 一种显示面板，其中，所述显示面板包括如权利要求8-9中任一项权利要求所述的方法形成的阵列基板。
  11. 一种显示装置，其中，所述显示装置包括权利要求10所述的显示面板。
  12. 一种薄膜晶体管的制作方法，其中，所述方法包括：
    通过构图工艺形成薄膜晶体管的栅极、栅绝缘层、源极和漏极，所述源极和所述漏极位于同一层，所述栅绝缘层位于所述源极、所述漏极和所述栅极之间；
    在所述源极和所述漏极上形成截面为倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；
    在所述源极、所述漏极、所述栅绝缘层和所述倒梯形的溶解层上形成金属氧化物有源层，所述倒梯形的溶解层的厚度大于所述金属氧化物有源层的厚度；以及
    使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述金属氧化物有源层，形成氧化物有源层。
  13. 根据权利要求12所述的薄膜晶体管的制作方法，其中，形成在所述 倒梯形的溶解层之上的所述金属氧化物有源层与形成在所述倒梯形的溶解层之外的所述金属氧化物有源层断开。
  14. 根据权利要求12所述的薄膜晶体管的制作方法，其中，所述在所述源极和所述漏极上形成倒梯形的溶解层包括：
    在所述源极和所述漏极上形成溶解层；
    对第二区域和第三区域内的溶解层进行掩膜曝光，使所述第二区域和第三区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第二区域位于所述源极上，所述第三区域位于所述漏极上；
    对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第二区域和所述第三区域以外的其他区域的溶解层去除以及将所述第二区域和所述第三区域内的溶解层变换成倒梯形的溶解层。
  15. 根据权利要求14所述的薄膜晶体管的制作方法，其中，
    在所述掩膜曝光的过程中，所述第二区域内的溶解层离所述源极越远的部分受到的掩膜曝光的强度越强，使得所述第二区域内的溶解层离所述源极越远的部分产生的酸性物质越多；
    所述第三区域内的溶解层离所述漏极越远的部分受到的掩膜曝光的强度越强，使得所述第三区域内的溶解层离所述漏极越远的部分产生的酸性物质越多。
  16. 根据权利要求14所述的薄膜晶体管的制作方法，其中，所述对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第二区域和所述第三区域以外的其他区域的溶解层去除以及将所述第二区域和所述第三区域内的溶解层变换成倒梯形的溶解层，包括：
    对所述薄膜晶体管进行反转烘干，在反转烘干过程中所述溶解层发生交联反应，且所述第二区域和所述第三区域内的溶解层在所述酸性物质的作用下发生交联反应的强度强于所述其他区域内的溶解层，且在反转烘干后所述第二区域和所述第三区域内的溶解层的分子密度和硬度都高于所述其他区域的溶解层；
    对反转烘干后的所述薄膜晶体管进行泛曝光，在泛曝光的过程中所述其它区域内的溶解层的分子链断开；
    对泛曝光后的所述溶解层进行显影处理，使所述其他区域的溶解层溶于 显影液内以及使所述第二区域和所述第三区域内的溶解层变成倒梯形的溶解层。
  17. 根据权利要求16所述的薄膜晶体管的制作方法，其中，
    在所述反转烘干过程中，在所述第二区域内和所述第三区域内的溶解层中的酸性物质作用下，所述第二区域内的溶解层离所述源极越远的部分发生的交联反应的强度越强，使所述第二区域内的溶解层离所述源极越远的部分的分子密度和硬度越高，所述第三区域内的溶解层离所述漏极越远的部分发生的交联反应的强度越强，使所述第三区域内的溶解层离所述漏极越远的部分的分子密度和硬度越高；
    在所述泛曝光的过程中，所述第二区域内和所述第三区域内的溶解层的分子密度和硬度越低的部分的分子越容易发生分子链断开，使所述第二区域内的溶解层离所述源极越远的和所述第三区域内的溶解层离所述漏极越远的部分发生分子链断开的分子越少；
    在所述显影的过程中，所述第二区域内和所述第三区域内的溶解层的发生分子链断开越少的部分越难溶于显影液，使所述第二区域内的溶解层离所述源极越远的和所述第三区域内的溶解层离所述漏极越远的部分越难溶于所述显影液。
  18. 根据权利要求12所述的薄膜晶体管的制作方法，其中，所述对第二区域和第三区域内的溶解层进行掩膜曝光之前还包括：
    对所述溶解层进行前烘，所述前烘去除所述溶解层中的溶剂。
  19. 一种阵列基板的制作方法，其中，所述方法包括：
    在衬底基板上形成栅极及栅线、栅绝缘层、源极及数据线和漏极，所述源极和所述漏极位于同一层，所述栅绝缘层位于所述源极、所述漏极和所述栅极之间；
    在所述源极和所述漏极上形成截面为倒梯形的倒梯形的溶解层，所述倒梯形的溶解层能溶于有机溶剂；
    在所述源极、所述漏极、所述栅绝缘层和所述倒梯形的溶解层上形成金属氧化物层，所述倒梯形的溶解层的厚度大于所述金属氧化物层的厚度；
    使用有机溶剂溶解去除所述倒梯形的溶解层并去除位于所述倒梯形的溶解层上的所述金属氧化物有源层，形成氧化物有源层；
    在所述源极、所述氧化物有源层和所述漏极上形成钝化层；
    在所述钝化层上形成像素电极。
  20. 根据权利要求19所述的阵列基板的制作方法，其中，在所述源极和所述漏极上形成倒梯形的溶解层包括：
    在所述源极和所述漏极上形成溶解层；
    对第二区域和第三区域内的溶解层进行掩膜曝光，使所述第二区域和第三区域内的溶解层产生酸性物质，所述酸性物质用于增强交联反应，所述第二区域位于所述源极上，所述第三区域位于所述漏极上；
    对所述溶解层进行反转烘干、泛曝光和显影处理，以将除所述第二区域和所述第三区域以外的其他区域的溶解层去除以及将所述第二区域和所述第三区域内的溶解层变换成倒梯形的溶解层。
  21. 一种显示面板，其中，所述显示面板包括如权利要求19-20中任一项权利要求所述的方法形成的阵列基板。
  22. 一种显示装置，其中，所述显示装置包括权利要求21所述的显示面板。
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