WO2017059607A1 - 一种阵列基板及其制作方法 - Google Patents

一种阵列基板及其制作方法 Download PDF

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Publication number
WO2017059607A1
WO2017059607A1 PCT/CN2015/092357 CN2015092357W WO2017059607A1 WO 2017059607 A1 WO2017059607 A1 WO 2017059607A1 CN 2015092357 W CN2015092357 W CN 2015092357W WO 2017059607 A1 WO2017059607 A1 WO 2017059607A1
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Prior art keywords
conductor
layer
channel region
semiconductor layer
gate insulating
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PCT/CN2015/092357
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English (en)
French (fr)
Inventor
石龙强
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to JP2018518458A priority Critical patent/JP6555843B2/ja
Priority to US14/890,654 priority patent/US9905470B2/en
Priority to KR1020187012296A priority patent/KR102097226B1/ko
Priority to DE112015007014.1T priority patent/DE112015007014B4/de
Priority to GB1805502.0A priority patent/GB2558114B/en
Publication of WO2017059607A1 publication Critical patent/WO2017059607A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/403—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials for lift-off processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/15—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on an electrochromic effect
    • G02F1/163—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor
    • G02F2001/1635—Operation of electrochromic cells, e.g. electrodeposition cells; Circuit arrangements therefor the pixel comprises active switching elements, e.g. TFT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present invention relates to the field of liquid crystals, and in particular to an array substrate and a method of fabricating the same.
  • AMLCD Active Matrix Liquid Crystal Display
  • AMOLED Active-matrix organic light emitting diode
  • the Gate Driver on Array (GOA) technology is generally used to realize the narrow border effect of the display.
  • the array substrate needs to design two layers of metal layers at intervals during the production process, and at the same time, the two metal layers need to be bridged across the gate insulating layer of the array substrate, so how to do it in a relatively simple manner Achieving bridging of two metal layers to improve the production efficiency of the array substrate is an urgent problem to be solved.
  • the array substrate requires two different masks in the production process to respectively pattern the semiconductor layer and the gate insulating layer, thereby increasing the production cost of the array substrate.
  • the technical problem to be solved by the present invention is to provide an array substrate and a manufacturing method thereof, which can pattern a semiconductor layer and a gate insulating layer by using a photomask, thereby reducing the production cost of the array substrate, and can be realized in a relatively simple manner.
  • the bridging of two metal layers in the array substrate improves the production efficiency of the array substrate.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, the method comprising: providing a substrate, depositing a first metal layer on the substrate, and patterning through the first mask a first metal layer to form a gate and a first conductor; a gate insulating layer deposited on the gate and the first conductor; a semiconductor layer deposited on the gate insulating layer; and a semiconductor patterned by the second mask a layer and a gate insulating layer to form a via hole exposing the first conductor; patterning the semiconductor layer through the gate electrode and the first conductor to form a first channel region and a second channel region which are spaced apart, wherein a channel region correspondingly above the gate, a second channel region corresponding to the first conductor; a second metal layer deposited on the first channel region and the second channel region, and passing through the third mask pattern Forming a second metal layer to form spaced apart source, drain and second conductors, wherein the source and the drain are
  • the step of depositing a gate insulating layer on the gate and the first conductor is specifically: depositing a gate insulating layer by plasma enhanced chemical vapor deposition on the gate and the first conductor; depositing a semiconductor layer on the gate insulating layer
  • the step is specifically: depositing a semiconductor layer by physical vapor deposition on the gate insulating layer.
  • the material of the semiconductor layer is indium gallium zinc oxide.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, the method comprising: providing a substrate, depositing a first metal layer on the substrate, and passing the first mask pattern Forming a first metal layer to form spaced gates and a first conductor; depositing a gate insulating layer on the gate and the first conductor; depositing a semiconductor layer on the gate insulating layer, and patterning through the second mask a semiconductor layer and a gate insulating layer to form a via hole exposing the first conductor; patterning the semiconductor layer through the gate electrode and the first conductor to form a first channel region and a second channel region which are spaced apart, wherein The first channel region is correspondingly located above the gate, the second channel region is correspondingly located above the first conductor; the second metal layer is deposited on the first channel region and the second channel region, and passes through the third mask Patterning the second metal layer to form spaced apart source, drain and second conductors, wherein the source and the drain are
  • the step of depositing a gate insulating layer on the gate and the first conductor is specifically: depositing a gate insulating layer by plasma enhanced chemical vapor deposition on the gate and the first conductor; depositing a semiconductor layer on the gate insulating layer
  • the step is specifically: depositing a semiconductor layer by physical vapor deposition on the gate insulating layer.
  • the step of patterning the semiconductor layer and the gate insulating layer by the second mask to form the through hole exposing the first conductor is specifically: coating the first photoresist layer on the semiconductor layer; and passing the second mask a photoresist layer is subjected to front side exposure and development; the developed first photoresist layer, the semiconductor layer and the gate insulating layer are wet-etched; and the wet-etched first photoresist layer is stripped to be in the semiconductor layer and the gate
  • the insulating layer forms a via hole exposing the first conductor.
  • the step of forming the first channel region and the second channel region by patterning the semiconductor layer through the gate and the first conductor is specifically: coating a second photoresist layer on the semiconductor layer; passing the gate and the first conductor Performing back exposure and development on the second photoresist layer; performing wet etching on the developed second photoresist layer and the semiconductor layer; and stripping the wet-etched second photoresist layer to form a first channel region in the semiconductor layer And a second channel region.
  • the material of the semiconductor layer is indium gallium zinc oxide.
  • an array substrate including a substrate, a first metal layer, a gate insulating layer, a semiconductor layer, and a second layer, which are sequentially disposed from bottom to top.
  • a metal layer the first metal layer includes spaced gates and a first conductor;
  • the semiconductor layer includes spaced apart first and second channel regions; and
  • the second metal layer includes spaced apart sources, drains, and Second conductor
  • the first channel region is correspondingly located above the gate, and the second channel region is located above the first conductor;
  • the source and the drain are respectively in contact with the first channel region, and the second conductor is in contact with the second channel region and is in contact with the first conductor through the through hole;
  • the gate insulating layer and the semiconductor layer are patterned by using a photomask.
  • the second channel region includes a first channel portion and a second channel portion, the first channel portion and the second channel portion are disposed on both sides of the through hole; wherein the second conductor covers the first channel portion a through hole and a second channel portion.
  • the material of the first metal layer and the second metal layer is copper, aluminum or molybdenum.
  • the material of the gate insulating layer is silicon oxide or silicon nitride.
  • the material of the semiconductor layer is indium gallium zinc oxide.
  • the beneficial effects of the present invention are: the array substrate of the present invention and the manufacturing method thereof, the first metal layer is patterned by the first mask to form the gate electrode and the first conductor; and the semiconductor layer is patterned by the second mask And a gate insulating layer to form a via hole exposing the first conductor; patterning the semiconductor layer through the gate electrode and the first conductor to form the first channel region and the second channel region which are spaced apart; through the third light
  • the cover patterns the second metal layer to form spaced apart source, drain and second conductors; wherein the second conductor is in contact with the first conductor through the via.
  • the present invention uses a reticle to pattern the semiconductor layer and the gate insulating layer, thereby reducing the production cost of the array substrate.
  • the present invention achieves the bridging of the first conductor and the second conductor in a relatively simple manner, and further The production efficiency of the array substrate is improved.
  • FIG. 1 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 2A-2G are schematic structural views of an array substrate in the manufacturing process of the manufacturing method shown in FIG. 1;
  • FIG. 3 is a schematic structural view of an array substrate prepared by the manufacturing method shown in FIG. 1.
  • FIG. 1 is a schematic flow chart of a method of fabricating an array substrate according to an embodiment of the present invention.
  • 2A-2G are schematic structural views of an array substrate in the manufacturing process of the manufacturing method shown in FIG. 1. It should be noted that the method of the present invention is not limited to the sequence of the flow shown in FIG. 1 if substantially the same result is obtained. As shown in FIG. 1, the method includes the following steps:
  • Step S101 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer through the first mask to form spaced gates and first conductors.
  • the substrate is preferably a glass substrate, and the material of the first metal layer is preferably copper, aluminum or molybdenum.
  • FIG. 2A is a schematic cross-sectional view of the gate electrode 21 and the first conductor 22 obtained after the first mask is deposited on the first metal layer of the substrate 10.
  • Step S102 depositing a gate insulating layer on the gate and the first conductor.
  • step S102 the step of depositing a gate insulating layer on the gate and the first conductor is specifically: plasma enhanced chemical vapor deposition on the gate and the first conductor (Plasma) Enhanced Chemical Vapor Deposition (PECVD) deposits a gate insulating layer.
  • the material of the gate insulating layer is silicon oxide or silicon nitride.
  • Step S103 depositing a semiconductor layer on the gate insulating layer, and patterning the semiconductor layer and the gate insulating layer through the second mask to form a via hole exposing the first conductor.
  • step S103 the step of depositing a semiconductor layer on the gate insulating layer is specifically: physical vapor deposition on the gate insulating layer (Physical) Vapor Deposition, PVD) deposits a semiconductor layer.
  • the material of the semiconductor layer is indium gallium zinc oxide (Indium Gallium Zinc) Oxide, IGZO).
  • the step of patterning the semiconductor layer and the gate insulating layer by the second mask to form the through hole exposing the first conductor is specifically: coating the first photoresist layer on the semiconductor layer; and passing the second mask a photoresist layer is subjected to front side exposure and development; the developed first photoresist layer, the semiconductor layer and the gate insulating layer are wet-etched; and the wet-etched first photoresist layer is stripped to be in the semiconductor layer and the gate
  • the insulating layer forms a via hole exposing the first conductor.
  • FIG. 2B is a cross-sectional structure of the substrate 10, the gate electrode 21, the first conductor 22, the gate insulating layer 30, and the semiconductor layer 40 coated with the first photoresist layer 41.
  • schematic diagram. 2C is a front side exposure of the first photoresist layer 41 by the second photomask, and the substrate 10, the gate electrode 21, the first conductor 22, the gate insulating layer 30, the semiconductor layer 40, and the first photoresist layer 41 after development. Schematic diagram of the section structure.
  • 2D is a cross-sectional view of the first photoresist layer 41 after the wet etching of the substrate 10, the gate 21, the first conductor 22, the gate insulating layer 30, the semiconductor layer 40, and the via 23 exposing the first conductor 22.
  • Step S104 patterning the semiconductor layer through the gate and the first conductor to form a first channel region and a second channel region which are disposed at intervals.
  • step S104 the step of forming the first channel region and the second channel region by patterning the semiconductor layer through the gate and the first conductor is specifically: coating a second photoresist layer on the semiconductor layer; The first conductive layer performs back exposure and development on the second photoresist layer; wet etching the developed second photoresist layer and the semiconductor layer; and peeling off the wet etching second photoresist layer to form a first layer in the semiconductor layer a channel region and a second channel region.
  • the gate and the first conductor are used as a mask, which reduces the use of the mask during the production of the array substrate, and reduces the production cost of the array substrate.
  • first channel region is above the gate and the second channel region is above the first conductor.
  • FIG. 2E is a cross-sectional structure of the substrate 10, the gate electrode 21, the first conductor 22, the gate insulating layer 30, and the semiconductor layer 40 coated with the second photoresist layer 42.
  • schematic diagram. 2F is a back exposure of the second photoresist layer 42 through the gate and the first conductor, and the substrate 10, the gate 21, the first conductor 22, the gate insulating layer 30, the semiconductor layer 40, and the second photoresist layer after development.
  • 2G is a cross-sectional structure of the rear substrate 10, the gate electrode 21, the first conductor 22, the gate insulating layer 30, the first channel region 43, and the second channel region 44 after the second photoresist layer 42 is stripped of the wet etching.
  • Step S105 depositing a second metal layer on the first channel region and the second channel region, and patterning the second metal layer through the third mask to form spaced apart source, drain and second conductors, The second conductor is in contact with the first conductor through the through hole.
  • step S105 the step of depositing the second metal layer on the first channel region and the second channel region is specifically: depositing the second metal by physical vapor deposition on the first channel region and the second channel region Floor.
  • the material of the second metal layer is copper, aluminum or molybdenum.
  • the material of the first metal layer and the material of the second metal layer are different. In other embodiments, the material of the first metal layer may also be the same as the material of the second metal layer.
  • the source and the drain are respectively in contact with the first channel region, and the second conductor is in contact with the second channel region.
  • the first channel region may be present, and the second conductor is in direct contact with the first conductor through the via.
  • FIG. 3 is a schematic structural view of the array substrate prepared by the manufacturing method shown in FIG. As shown in FIG. 3, the entire column substrate includes a substrate 10, a first metal layer, a gate insulating layer 30, a semiconductor layer, and a second metal layer which are disposed in this order from bottom to top.
  • the first metal layer comprises a gate electrode 21 and a first conductor 22 which are arranged at intervals.
  • the semiconductor layer includes a first channel region 43 and a second channel region 44 that are spaced apart.
  • the second metal layer includes a source 51, a drain 52, and a second conductor 53 that are spaced apart.
  • the first channel region 43 is located above the gate 21
  • the second channel region 44 is located above the first conductor 22 .
  • the source 51 and the drain 52 are respectively in contact with the first channel region 43
  • the second conductor 53 is in contact with the second channel region 44 and is in contact with the first conductor 22 through the through hole.
  • the through hole 23 is made of a reticle patterned gate insulating layer 30 and a semiconductor layer.
  • the gate insulating layer 30 and the semiconductor layer are patterned by using a photomask.
  • the second channel region 44 includes a first channel portion 441 and a second channel portion 442, and the first channel portion 441 and the second channel portion 442 are disposed on both sides of the through hole 23, and the second conductor 53 The first channel portion 441, the through hole 23, and the second channel portion 442 are covered.
  • the material of the gate electrode 21 and the first conductor 22 of the first metal layer and the source electrode 51, the drain electrode 52 and the second conductor 53 of the second metal layer are copper, aluminum or molybdenum.
  • the material of the gate insulating layer 30 is silicon oxide or silicon nitride.
  • the material of the first channel region 43 and the second channel region 44 of the semiconductor layer is indium gallium zinc oxide.
  • the beneficial effects of the present invention are: the array substrate of the present invention and the manufacturing method thereof, the first metal layer is patterned by the first mask to form the gate electrode and the first conductor; and the semiconductor layer is patterned by the second mask And a gate insulating layer to form a via hole exposing the first conductor; patterning the semiconductor layer through the gate electrode and the first conductor to form the first channel region and the second channel region which are spaced apart; through the third light
  • the cover patterns the second metal layer to form spaced apart source, drain and second conductors; wherein the second conductor is in contact with the first conductor through the via.
  • the present invention uses a reticle to pattern the semiconductor layer and the gate insulating layer, thereby reducing the production cost of the array substrate.
  • the present invention can bridge the first conductor and the second conductor in a relatively simple manner, thereby Improve the production efficiency of the array substrate.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板及其制作方法，该方法包括：通过第一道光罩图案化第一金属层，以形成间隔设置的栅极（21）和第一导体（22）；通过第二道光罩图案化半导体层（40）和栅极绝缘层（30），以形成暴露出第一导体（22）的通孔（23）；通过栅极（21）和第一导体（22）图案化半导体层（40），以形成间隔设置的第一沟道区（43）和第二沟道区（44）；通过第三道光罩图案化第二金属层，以形成间隔设置的源极（51）、漏极（52）和第二导体（53）；其中，第二导体（53）通过通孔（23）与第一导体（22）相接触。该阵列基板的制造方法通过一道光罩图案化半导体层（40）和栅极绝缘层（30），降低了阵列基板的生产成本，且以相对简单的方式实现第一导体（22）和第二导体（53）的桥接，进而提高阵列基板的生产效率。

Description

一种阵列基板及其制作方法
【技术领域】
本发明涉及液晶领域，特别是涉及一种阵列基板及其制作方法。
【背景技术】
在主动式矩阵显示器（Active Matrix Liquid Crystal Display，AMLCD）或有源矩阵有机发光二极体（Active-matrix organic light emitting diode，AMOLED）显示器中，一般采用阵列基板行驱动（Gate Driver on Array，GOA）技术来实现显示器的窄边框效果。
其中，在GOA技术中，阵列基板在生产的过程中需要设计间隔设置的两层金属层，同时，两层金属层需要跨越阵列基板的栅极绝缘层进行桥接，因此，如何以相对简单的方式实现两层金属层的桥接以提高阵列基板的生产效率是一个亟待解决的问题。另外，为了实现两层金属层的桥接，阵列基板在生产的过程中需要两道不同的光罩分别对半导体层和栅极绝缘层进行图案化，增加了阵列基板的生产成本。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及其制作方法，能够采用一道光罩图案化半导体层和栅极绝缘层，从而降低阵列基板的生产成本，另外，能够以相对简单的方式实现阵列基板中两层金属层的桥接，从而提高阵列基板的生产效率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制作方法，该方法包括：提供一基板，在基板上沉积第一金属层，并通过第一道光罩图案化第一金属层，以形成间隔设置的栅极和第一导体；在栅极和第一导体上沉积栅极绝缘层；在栅极绝缘层上沉积半导体层，并通过第二道光罩图案化半导体层和栅极绝缘层，以形成暴露出第一导体的通孔；通过栅极和第一导体图案化半导体层，以形成间隔设置的第一沟道区和第二沟道区，其中，第一沟道区对应位于栅极的上方，第二沟道区对应位于第一导体的上方；在第一沟道区和第二沟道区上沉积第二金属层，并通过第三道光罩图案化第二金属层，以形成间隔设置的源极、漏极和第二导体，其中，源极、漏极分别与第一沟道区相接触，第二导体与第二沟道区相接触并通过通孔与第一导体相接触；其中，通过第二道光罩图案化半导体层和栅极绝缘层，形成暴露出第一导体的通孔的步骤具体为：在半导体层上涂布第一光阻层；通过第二道光罩对第一光阻层进行正面曝光、显影；对显影后的第一光阻层、半导体层、栅极绝缘层进行湿法蚀刻；剥离湿法蚀刻后的第一光阻层以在半导体层、栅极绝缘层形成暴露出第一导体的通孔；通过栅极和第一导体图案化半导体层，形成第一沟道区和第二沟道区的步骤具体为：在半导体层上涂布第二光阻层；通过栅极和第一导体对第二光阻层进行背面曝光、显影；对显影后的第二光阻层、半导体层进行湿法蚀刻；剥离湿法蚀刻后的第二光阻层以在半导体层形成第一沟道区和第二沟道区。
其中，在栅极和第一导体上沉积栅极绝缘层的步骤具体为：在栅极和第一导体上通过等离子增强化学气相沉积法沉积栅极绝缘层；在栅极绝缘层上沉积半导体层的步骤具体为：在栅极绝缘层上通过物理气相沉积法沉积半导体层。
其中，半导体层的材料为铟镓锌氧化物。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，该方法包括：提供一基板，在基板上沉积第一金属层，并通过第一道光罩图案化第一金属层，以形成间隔设置的栅极和第一导体；在栅极和第一导体上沉积栅极绝缘层；在栅极绝缘层上沉积半导体层，并通过第二道光罩图案化半导体层和栅极绝缘层，以形成暴露出第一导体的通孔；通过栅极和第一导体图案化半导体层，以形成间隔设置的第一沟道区和第二沟道区，其中，第一沟道区对应位于栅极的上方，第二沟道区对应位于第一导体的上方；在第一沟道区和第二沟道区上沉积第二金属层，并通过第三道光罩图案化第二金属层，以形成间隔设置的源极、漏极和第二导体，其中，源极、漏极分别与第一沟道区相接触，第二导体与第二沟道区相接触并通过通孔与第一导体相接触。
其中，在栅极和第一导体上沉积栅极绝缘层的步骤具体为：在栅极和第一导体上通过等离子增强化学气相沉积法沉积栅极绝缘层；在栅极绝缘层上沉积半导体层的步骤具体为：在栅极绝缘层上通过物理气相沉积法沉积半导体层。
其中，通过第二道光罩图案化半导体层和栅极绝缘层，形成暴露出第一导体的通孔的步骤具体为：在半导体层上涂布第一光阻层；通过第二道光罩对第一光阻层进行正面曝光、显影；对显影后的第一光阻层、半导体层、栅极绝缘层进行湿法蚀刻；剥离湿法蚀刻后的第一光阻层以在半导体层、栅极绝缘层形成暴露出第一导体的通孔。
其中，通过栅极和第一导体图案化半导体层，形成第一沟道区和第二沟道区的步骤具体为：在半导体层上涂布第二光阻层；通过栅极和第一导体对第二光阻层进行背面曝光、显影；对显影后的第二光阻层、半导体层进行湿法蚀刻；剥离湿法蚀刻后的第二光阻层以在半导体层形成第一沟道区和第二沟道区。
其中，半导体层的材料为铟镓锌氧化物。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种阵列基板，该阵列基板包括从下到上依次设置的基板、第一金属层、栅极绝缘层、半导体层和第二金属层；第一金属层包括间隔设置的栅极和第一导体；半导体层包括间隔设置的第一沟道区和第二沟道区；第二金属层包括间隔设置的源极、漏极和第二导体；
其中，第一沟道区对应位于栅极的上方，第二沟道区对应位于第一导体的上方；
其中，源极、漏极分别与第一沟道区相接触，第二导体与第二沟道区相接触并通过通孔与第一导体相接触；
其中，所述栅极绝缘层和所述半导体层采用一道光罩进行图案化。
其中，第二沟道区包括第一沟道部和第二沟道部，第一沟道部和第二沟道部设置在通孔的两侧；其中，第二导体覆盖第一沟道部、通孔和第二沟道部。
其中，第一金属层和第二金属层的材料为铜、铝或钼。
其中，栅极绝缘层的材料为氧化硅或氮化硅。
其中，半导体层的材料为铟镓锌氧化物。
本发明的有益效果是：本发明的阵列基板及其制造方法通过第一道光罩图案化第一金属层，以形成间隔设置的栅极和第一导体；通过第二道光罩图案化半导体层和栅极绝缘层，以形成暴露出第一导体的通孔；通过栅极和第一导体图案化半导体层，以形成间隔设置的第一沟道区和第二沟道区；通过第三道光罩图案化第二金属层，以形成间隔设置的源极、漏极和第二导体；其中，第二导体通过通孔与第一导体相接触。通过上述方式，本发明采用一道光罩图案化半导体层和栅极绝缘层，降低了阵列基板的生产成本，另外，本发明以相对简单的方式实现了第一导体和第二导体的桥接，进而提高了阵列基板的生产效率。
【附图说明】
图1是本发明实施例的阵列基板的制作方法的流程示意图；
图2A-2G是图1所示制作方法在制作过程中的阵列基板的结构示意图；
图3是图1所示制作方法制得的阵列基板的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图1是本发明实施例的阵列基板的制作方法的流程示意图。图2A-2G是图1所示制作方法在制作过程中的阵列基板的结构示意图。需注意的是，若有实质上相同的结果，本发明的方法并不以图1所示的流程顺序为限。如图1所示，该方法包括如下步骤：
步骤S101：提供一基板，在基板上沉积第一金属层，并通过第一道光罩图案化第一金属层，以形成间隔设置的栅极和第一导体。
在步骤S101中，基板优选为玻璃基板，第一金属层的材料优选为铜、铝或钼。
请一并参考图2A，图2A为对沉积于基板10的第一金属层进行第一道光罩后得到的栅极21和第一导体22的剖面结构示意图。
步骤S102：在栅极和第一导体上沉积栅极绝缘层。
在步骤S102中，在栅极和第一导体上沉积栅极绝缘层的步骤具体为：在栅极和第一导体上通过等离子增强化学气相沉积法（Plasma Enhanced Chemical Vapor Deposition，PECVD）沉积栅极绝缘层。优选地，栅极绝缘层的材料为氧化硅或氮化硅。
步骤S103：在栅极绝缘层上沉积半导体层，并通过第二道光罩图案化半导体层和栅极绝缘层，以形成暴露出第一导体的通孔。
在步骤S103中，在栅极绝缘层上沉积半导体层的步骤具体为：在栅极绝缘层上通过物理气相沉积法（Physical Vapor Deposition，PVD）沉积半导体层。优选地，半导体层的材料为铟镓锌氧化物（Indium Gallium Zinc Oxide，IGZO）。
其中，通过第二道光罩图案化半导体层和栅极绝缘层，形成暴露出第一导体的通孔的步骤具体为：在半导体层上涂布第一光阻层；通过第二道光罩对第一光阻层进行正面曝光、显影；对显影后的第一光阻层、半导体层、栅极绝缘层进行湿法蚀刻；剥离湿法蚀刻后的第一光阻层以在半导体层、栅极绝缘层形成暴露出第一导体的通孔。
请一并参考图2B、2C、2D，其中，图2B为涂布了第一光阻层41的基板10、栅极21、第一导体22、栅极绝缘层30、半导体层40的剖面结构示意图。图2C为通过第二道光罩对第一光阻层41进行正面曝光、显影后基板10、栅极21、第一导体22、栅极绝缘层30、半导体层40和第一光阻层41的剖面结构示意图。图2D为剥离湿法蚀刻后的第一光阻层41后基板10、栅极21、第一导体22、栅极绝缘层30、半导体层40和暴露出第一导体22的通孔23的剖面结构示意图。
步骤S104：通过栅极和第一导体图案化半导体层，以形成间隔设置的第一沟道区和第二沟道区。
在步骤S104中，通过栅极和第一导体图案化半导体层，形成第一沟道区和第二沟道区的步骤具体为：在半导体层上涂布第二光阻层；通过栅极和第一导体对第二光阻层进行背面曝光、显影；对显影后的第二光阻层、半导体层进行湿法蚀刻；剥离湿法蚀刻后的第二光阻层以在半导体层形成第一沟道区和第二沟道区。本领域的技术人员可以理解，在步骤S104中，以栅极和第一导体作为一道光罩，减少了阵列基板生产过程中光罩的使用，降低了阵列基板的生产成本。
其中，第一沟道区位于栅极的上方，第二沟道区位于第一导体的上方。
请一并参考图2E、2F、2G，其中，图2E为涂布了第二光阻层42的基板10、栅极21、第一导体22、栅极绝缘层30、半导体层40的剖面结构示意图。图2F为通过栅极和第一导体对第二光阻层42进行背面曝光、显影后基板10、栅极21、第一导体22、栅极绝缘层30、半导体层40和第二光阻层42的剖面结构示意图。图2G为剥离湿法蚀刻后的第二光阻层42后基板10、栅极21、第一导体22、栅极绝缘层30、第一沟道区43、第二沟道区44的剖面结构示意图。
步骤S105：在第一沟道区和第二沟道区上沉积第二金属层，并通过第三道光罩图案化第二金属层，以形成间隔设置的源极、漏极和第二导体，其中，第二导体通过通孔与第一导体相接触。
在步骤S105中，在第一沟道区和第二沟道区上沉积第二金属层的步骤具体为：在第一沟道区和第二沟道区上通过物理气相沉积法沉积第二金属层。优选地，第二金属层的材料为铜、铝或钼。
在本实施例中，第一金属层的材料和第二金属层的材料不相同，在其它实施例中，第一金属层的材料也可与第二金属层的材料相同。
在本实施例中，源极、漏极分别与第一沟道区相接触，第二导体与第二沟道区相接触。在其它实施例中，也可以仅存在第一沟道区，第二导体直接通过通孔与第一导体相接触。
请一并参考图3，图3是图1所示制作方法制得的阵列基板的结构示意图。如图3所示，整列基板包括从下到上依次设置的基板10、第一金属层、栅极绝缘层30、半导体层和第二金属层。
其中，第一金属层包括间隔设置的栅极21和第一导体22。半导体层包括间隔设置的第一沟道区43和第二沟道区44。第二金属层包括间隔设置的源极51、漏极52和第二导体53。
其中，第一沟道区43对应位于栅极21的上方，第二沟道区44对应位于第一导体22的上方。源极51、漏极52分别与第一沟道区43相接触，第二导体53与第二沟道区44相接触并通过通孔与第一导体22相接触。
其中，通孔23由一道光罩图案化栅极绝缘层30和半导体层制得。
其中，栅极绝缘层30和半导体层采用一道光罩进行图案化。
优选地，第二沟道区44包括第一沟道部441和第二沟道部442，第一沟道部441和第二沟道部442设置在通孔23的两侧，第二导体53覆盖第一沟道部441、通孔23和第二沟道部442。
优选地，位于第一金属层的栅极21和第一导体22以及位于和第二金属层的源极51、漏极52和第二导体53的材料为铜、铝或钼。
优选地，栅极绝缘层30的材料为氧化硅或氮化硅。
优选地，位于半导体层的第一沟道区43和第二沟道区44的材料为铟镓锌氧化物。
本发明的有益效果是：本发明的阵列基板及其制造方法通过第一道光罩图案化第一金属层，以形成间隔设置的栅极和第一导体；通过第二道光罩图案化半导体层和栅极绝缘层，以形成暴露出第一导体的通孔；通过栅极和第一导体图案化半导体层，以形成间隔设置的第一沟道区和第二沟道区；通过第三道光罩图案化第二金属层，以形成间隔设置的源极、漏极和第二导体；其中，第二导体通过通孔与第一导体相接触。通过上述方式，本发明采用一道光罩图案化半导体层和栅极绝缘层，降低了阵列基板的生产成本，另外，本发明能够以相对简单的方式实现第一导体和第二导体的桥接，从而提高阵列基板的生产效率。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板的制作方法，其中，所述方法包括：
    提供一基板，在所述基板上沉积第一金属层，并通过第一道光罩图案化所述第一金属层，以形成间隔设置的栅极和第一导体；
    在所述栅极和所述第一导体上沉积栅极绝缘层；
    在所述栅极绝缘层上沉积半导体层，并通过第二道光罩图案化所述半导体层和栅极绝缘层，以形成暴露出所述第一导体的通孔；
    通过所述栅极和所述第一导体图案化所述半导体层，以形成间隔设置的第一沟道区和第二沟道区，其中，所述第一沟道区对应位于所述栅极的上方，所述第二沟道区对应位于所述第一导体的上方；
    在所述第一沟道区和所述第二沟道区上沉积第二金属层，并通过第三道光罩图案化所述第二金属层，以形成间隔设置的源极、漏极和第二导体，其中，所述源极、漏极分别与所述第一沟道区相接触，所述第二导体与所述第二沟道区相接触并通过所述通孔与所述第一导体相接触；
    其中，所述通过第二道光罩图案化所述半导体层和栅极绝缘层，形成暴露出所述第一导体的通孔的步骤具体为：
    在所述半导体层上涂布第一光阻层；
    通过第二道光罩对所述第一光阻层进行正面曝光、显影；
    对显影后的所述第一光阻层、半导体层、栅极绝缘层进行湿法蚀刻；
    剥离湿法蚀刻后的所述第一光阻层以在所述半导体层、栅极绝缘层形成暴露出所述第一导体的通孔；
    其中，所述通过所述栅极和所述第一导体图案化所述半导体层，形成第一沟道区和第二沟道区的步骤具体为：
    在所述半导体层上涂布第二光阻层；
    通过所述栅极和所述第一导体对所述第二光阻层进行背面曝光、显影；
    对显影后的所述第二光阻层、半导体层进行湿法蚀刻；
    剥离湿法蚀刻后的所述第二光阻层以在所述半导体层形成第一沟道区和第二沟道区。
  2. 根据权利要求1所述的方法，其中，
    所述在所述栅极和所述第一导体上沉积栅极绝缘层的步骤具体为：
    在所述栅极和所述第一导体上通过等离子增强化学气相沉积法沉积栅极绝缘层；
    所述在所述栅极绝缘层上沉积半导体层的步骤具体为：
    在所述栅极绝缘层上通过物理气相沉积法沉积半导体层。
  3. 根据权利要求1所述的方法，其中，所述半导体层的材料为铟镓锌氧化物。
  4. 一种阵列基板的制作方法，其中，所述方法包括：
    提供一基板，在所述基板上沉积第一金属层，并通过第一道光罩图案化所述第一金属层，以形成间隔设置的栅极和第一导体；
    在所述栅极和所述第一导体上沉积栅极绝缘层；
    在所述栅极绝缘层上沉积半导体层，并通过第二道光罩图案化所述半导体层和栅极绝缘层，以形成暴露出所述第一导体的通孔；
    通过所述栅极和所述第一导体图案化所述半导体层，以形成间隔设置的第一沟道区和第二沟道区，其中，所述第一沟道区对应位于所述栅极的上方，所述第二沟道区对应位于所述第一导体的上方；
    在所述第一沟道区和所述第二沟道区上沉积第二金属层，并通过第三道光罩图案化所述第二金属层，以形成间隔设置的源极、漏极和第二导体，其中，所述源极、漏极分别与所述第一沟道区相接触，所述第二导体与所述第二沟道区相接触并通过所述通孔与所述第一导体相接触。
  5. 根据权利要求4所述的方法，其中，
    所述在所述栅极和所述第一导体上沉积栅极绝缘层的步骤具体为：
    在所述栅极和所述第一导体上通过等离子增强化学气相沉积法沉积栅极绝缘层；
    所述在所述栅极绝缘层上沉积半导体层的步骤具体为：
    在所述栅极绝缘层上通过物理气相沉积法沉积半导体层。
  6. 根据权利要求4所述的方法，其中，所述通过第二道光罩图案化所述半导体层和栅极绝缘层，形成暴露出所述第一导体的通孔的步骤具体为：
    在所述半导体层上涂布第一光阻层；
    通过第二道光罩对所述第一光阻层进行正面曝光、显影；
    对显影后的所述第一光阻层、半导体层、栅极绝缘层进行湿法蚀刻；
    剥离湿法蚀刻后的所述第一光阻层以在所述半导体层、栅极绝缘层形成暴露出所述第一导体的通孔。
  7. 根据权利要求4所述的方法，其中，所述通过所述栅极和所述第一导体图案化所述半导体层，形成第一沟道区和第二沟道区的步骤具体为：
    在所述半导体层上涂布第二光阻层；
    通过所述栅极和所述第一导体对所述第二光阻层进行背面曝光、显影；
    对显影后的所述第二光阻层、半导体层进行湿法蚀刻；
    剥离湿法蚀刻后的所述第二光阻层以在所述半导体层形成第一沟道区和第二沟道区。
  8. 根据权利要求4所述的方法，其中，所述半导体层的材料为铟镓锌氧化物。
  9. 一种阵列基板，其中，所述阵列基板包括从下到上依次设置的基板、第一金属层、栅极绝缘层、半导体层和第二金属层；所述第一金属层包括间隔设置的栅极和第一导体；所述半导体层包括间隔设置的第一沟道区和第二沟道区；所述第二金属层包括间隔设置的源极、漏极和第二导体；
    其中，所述第一沟道区对应位于所述栅极的上方，所述第二沟道区对应位于所述第一导体的上方；
    其中，所述源极、漏极分别与所述第一沟道区相接触，所述第二导体与所述第二沟道区相接触并通过所述通孔与所述第一导体相接触；
    其中，所述栅极绝缘层和所述半导体层采用一道光罩进行图案化。
  10. 根据权利要求9所述的阵列基板，所述第二沟道区包括第一沟道部和第二沟道部，所述第一沟道部和所述第二沟道部设置在所述通孔的两侧；其中，所述第二导体覆盖所述第一沟道部、通孔和第二沟道部。
  11. 根据权利要求9所述的阵列基板，其中，所述第一金属层和第二金属层的材料为铜、铝或钼。
  12. 根据权利要求9所述的阵列基板，其中，所述栅极绝缘层的材料为氧化硅或氮化硅。
  13. 根据权利要求9所述的阵列基板，其中，所述半导体层的材料为铟镓锌氧化物。
PCT/CN2015/092357 2015-10-10 2015-10-21 一种阵列基板及其制作方法 Ceased WO2017059607A1 (zh)

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