Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/022—Mountings; Housings
  • H01S5/0235—Method for mounting laser chips
  • H01S5/02355—Fixing laser chips on mounts
  • H01S5/0237—Fixing laser chips on mounts by soldering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/022—Mountings; Housings
  • H01S5/0235—Method for mounting laser chips
  • H01S5/02375—Positioning of the laser chips
  • H01S5/0238—Positioning of the laser chips using marks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
  • H01S5/024—Arrangements for thermal management
  • H01S5/02461—Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
  • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
  • H10H20/018—Bonding of wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/858—Means for heat extraction or cooling
  • H10H20/8582—Means for heat extraction or cooling characterised by their shape
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
  • H10H20/036—Manufacture or treatment of packages
  • H10H20/0364—Manufacture or treatment of packages of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
  • H10H20/036—Manufacture or treatment of packages
  • H10H20/0365—Manufacture or treatment of packages of means for heat extraction or cooling
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/858—Means for heat extraction or cooling
  • H10H20/8581—Means for heat extraction or cooling characterised by their material

Definitions

• the present invention relates to a method for herstel ⁇ len an optoelectronic component according to claim. 1
• An object of the present invention is to provide a method for producing an optoelectronic component. This object is achieved by a method having the features of claim 1. In the dependent Ansprü ⁇ Chen various developments are given.
• a method for producing an optoelectronic component comprises steps for providing a carrier with an upper side, for applying a region, which is recessed to a mounting region of the upper side, on the upper side of the carrier, wherein a step is formed between the mounting region and the recessed region, for arranging a Metallization on the upper side of the carrier extending over the mounting region and the recessed region, for applying a separation trace in the metallization, the metallization in the assembly region at least in sections is completely severed and is at least not completely severed in the recessed area, and for Anord ⁇ nen an optoelectronic semiconductor chip over the mounting area of the top, wherein the optoelectronic semiconductor chip is aligned with the separation track.
• an interpreting ⁇ Licher optical contrast between the exposed area in the separation trace in the assembly area and the material of the carrier is not completely severed in the region of the separation trace in the recessed area metallization.
• a high-contrast adjustment mark is formed. This allows reliable automated positioning of the optoelectronic rule ⁇ semiconductor chip to the mounting area of the top of the carrier.
• the method of the opto-electro ⁇ African semiconductor chip on the stage is disposed above standing.
• this risk is reduced that the over standing arranged part of the optoelectronic semiconductor ⁇ semiconductor chip is contaminated during the placement of the optoelectronic semiconductor chip on the mounting portion of the upper surface of the support by a for connecting the optoelectronic semiconductor chip used with the carrier joining material.
• the alignment on the separation track comprises an optical detection of a position of a boundary between the at least partially completely severed severed metallization in the assembly area and the at least not completely severed metallization in the recessed area.
• the material of the carrier exposed in the region of the at least partially completely severed metallization in the mounting area and the at least incompletely severed metallization in the recessed area arise in this method Range a pronounced optical contrast, which can be detected reliably automated, for example by means of an optical image recognition system. This allows precise detection of the position of the boundary.
• the position of this boundary is precisely defined by the separating track, so that overall precise alignment of the opto ⁇ electronic semiconductor chip with only slight inaccuracies is made possible.
• the separation track is applied in a straight line and perpendicular to the step.
• this allows a particularly simple and precise from ⁇ direction of the optoelectronic semiconductor chips.
• a straight-line application of the separating track is advantageously particularly easy.
• the carrier is provided in a carrier composite. After applying the separation track, the carrier composite is divided to separate the carrier. In this case, an outer edge of the carrier is formed by the dicing. The recessed portion is adjacent to the outer edge of so that the stage is usernamet parallel to the outer edge ⁇ ori.
• the method thereby enables a parallel production of a plurality of carriers in common operations. This reduces the manufacturing cost per carrier and the time required to make a carrier.
• a further advantage is that the process steps taken on the carrier assembly can be carried out more simply and with higher accuracy because of the larger dimensions of the carrier assembly.
• the recessed area adjoining the outer edge of the carrier advantageously ensures that the carrier has no burrs on its upper side in the region of the outer edge which make it difficult or prevent precise alignment and mounting of the optoelectronic semiconductor chip.
• the application of the separation track by sawing or by means of a laser. ⁇ advantageous way legally allow this method, a rapid, simple and reproducible ⁇ ches and applying the separating track with precisely defined groove depth and track width.
• the separation track is applied so that the metallization in the recessed area is not severed.
• a clear contrast between the at least partially completely severed in the assembly area metallization ⁇ tion and the non-severed in the recessed area metallization on the track separation is achieved.
• a solder is arranged on the metal ⁇ capitalization on the mounting portion of the top prior to placing the optoelectronic semiconductor chip. Then, the optoelectronic semiconductor chip is arranged on the solder. The solder can serve for mechanical attachment of the optoelectronic semiconductor chip and for electrical contacting of the optoelectronic semiconductor chip.
• the optoelectronic ⁇ African semiconductor chip is a laser chip.
• the optoelectronic component is then a laser component.
• the laser chip is arranged such that an emission facet of the laser chip protrudes beyond the step.
• ⁇ game as solder ge reached ⁇ on the emission facet of the laser chip.
• an anode contact of the laser chip faces the top side of the carrier.
• One Emission range of the laser chip can thereby be arranged particularly close to the top of the carrier, whereby an effective cooling of the laser chip can be achieved.
• FIG. 1 shows a plan view of an upper side of a carrier arranged in a carrier composite
• Figure 2 is a sectional side view of the carrier
• FIG. 3 shows a sectional side view of an optoelectronic component comprising the carrier and an optoelectronic semiconductor chip.
• FIG. 1 shows a schematic representation of a plan view of a carrier 200.
• FIG. 2 shows a sectional side view of the carrier 200. The sectional plane on which the carrier 200 is cut in the representation of FIG. 2 is shown in FIG. 1
• the carrier 200 can also be submount ⁇ records.
• the carrier 200 is formed as a substantially flat disc with an upper side 201.
• the carrier 200 may comprise an electrically insulating material, for example silicon or a ceramic.
• the carrier 200 may be provided in a carrier assembly 300.
• the carrier assembly 300 is indicated in the illustration of FIG.
• the carrier assembly 300 comprises a plurality of similar carriers 200, which are in a plane next to each other arranged and integrally connected to each other verbun ⁇ are.
• the individual carrier 200 may, for example, depending ⁇ wells have a rectangular shape and be disposed within the carrier assembly 300 in a rectangular grid.
• the carrier assembly 300 enables a parallel production of a plurality of carriers 200 in common operations. Only after completion of the common processing steps the individual carriers 200 are separated by dividing the carrier composite 300 along separating planes 310. The cutting ⁇ share of the carrier composite 300 along the parting lines 310 can be done for example by a sawing process.
• the top surface 201 of the carrier 200 includes a mounting portion 210 and against the mounting portion 210 recessed portion 220. At the boundary between the recessed portion 220 and the mounting portion 210 is a step ge ⁇ forms 230 on which the height of the top side 201 of the carrier 200 changes.
• the recessed area 220 of the upper side 201 of the carrier 200 is arranged so that the recessed area 220 adjoins the parting lines 310 after dividing the carrier assembly 300 against an outer edge 240 of the carrier 200 formed on a parting plane. This means that the recessed Be rich ⁇ 220 in an edge region of the top 201 of the carrier
• the recessed area 220 may be made by machining the top
• the recessed portions 220 may be a plurality of carriers 200 of the carrier assembly 300 applied wor ⁇ be simultaneous. It is also possible for a plurality of recessed regions 220 to have been applied per carrier 200, for example on opposite outer edges of the respective carrier 200, as shown in the example of FIGS. 1 and 2.
• a metallization 250 has been arranged on the upper side 201 of the carrier 200.
• the metallization 250 extends over both the recessed area 220 and the mounting area 210 of the top 201 of the carrier 200.
• the metallization 250 may include, for example, titanium, platinum, and / or gold.
• the metallization 250 has a thickness that is perpendicular to the upper surface 201 of the carrier 200, which is less than the depth of the recessed region 220.
• the metallization 250 may have a thickness of 1 ⁇ m.
• the separating track 270 is rectilinear and extends perpendicular to the step 230 between the recessed area 220 and the mounting area 210 and thus also perpendicular to the outer edge 240 of the carrier 200 formed during the division of the carrier composite 300. In this case, the separating track 270 extends over both the mounting area 210 as well as over the recessed area 220 of the top 201 of the carrier 200th
• the metallization 250 in the region of the separating track 270 is completely severed at least in sections so that the material of the carrier 200 is at least partially exposed in the region of the separating track 270 in the assembly region 210.
• the metal ⁇ tion 250 in the separation track 270 is at least not completely severed.
• the material of the carrier 200 is not exposed, but is further covered by the metallization 250.
• separation track 270 it is possible to apply the separation track 270 in such a way that the metallization 250 in the recessed area 220 of the upper side 201 of the carrier 200 is not severed at all by the separation track 270.
• the separating track 270 thus points towards the top 201 of the carrier
• the 200 vertical direction expediently has a depth that is greater than the thickness of the metallization 250, but less than the sum of the thickness of the metallization 250 and the depth by which the recessed portion 220 is recessed relative to the mounting portion 210.
• the separator 270 may track play, have a depth of several ym at ⁇ .
• the separation track 270 may have been created, for example, by sawing or by means of a laser. If the separation track 270 has been applied by sawing, the separation track 270 may also be referred to as a saw track.
• a solder 260 has been arranged on the metallization 250 on the upper side 201 of the carrier 200.
• the placement of the solder 260 may be done before or after applying the separation trace 270.
• the solder 260 extends over part of the mounting portion 210 of the top 201 of the carrier 200 and can also extend over a part of the recessed portion 220 of the top 201 of the Trä ⁇ gers 200th However, the solder 260 does not extend beyond that part of the upper side 201 of the carrier 200 in which the separating track 270 extends.
• FIG. 3 shows a schematic sectional side view of the carrier 200 in one of the representation of Figures 1 and 2 temporally subsequent processing status.
• An optoelectronic semiconductor chip 110 has been arranged above the upper side 201 of the carrier 200.
• the carrier 200 and the optoelectronic semiconductor chip 110 together form an optoelectronic component 100.
• the optoelectronic semiconductor chip 110 can be, for example, a laser chip.
• the optoelectronic component 100 is a laser component.
• the optoelectronic semiconductor chip 110 has been placed over the Monta ⁇ give 210 reaching the top surface 201 of the carrier 200th In this case, the optoelectronic semiconductor chip 110 was aligned on the separation track 270 in order to determine the position and / or orientation of the optoelectronic semiconductor chip 110 on the upper side 201 of the carrier 200.
• Contrast between the metallization 250 and the exposed Material of the carrier 200 is formed, which is well suited for op ⁇ table detection and whose position relative to the step 230 at the top 201 of the carrier 200 is precisely fest ⁇ laid.
• the optoelectronic semiconductor chip 110 has been arranged above the upper side 201 of the carrier 200 in such a way that it projects beyond the step 230.
• the length of the supernatant could be precisely determined by the alignment at the separation track 270, in particular by the alignment at the boundary 280.
• the optoelectronic semiconductor chip 110 has an upper side
• the optoelectronic semiconductor chip 110 is disposed ⁇ art over the top 201 of the carrier 200, the top 111 of the optoelectronic semiconductor chip faces 110 of the top 201 of the carrier 200th
• the opto-electronic ⁇ semiconductor chip 110 is disposed is arranged on the in Montagebe ⁇ reaching the top 210 of the carrier 201 200 Lot 260, and fixed by means of the solder 260th It is possible to dispense with disposing the solder 260 at the top 201 of the carrier 200 and instead, for example, arrange a solder on the top side 111 of the optoelectronic semiconductor chip 110 before it is placed over the top 201 of the carrier 200.
• the solder 260 may for fastening of the optoelectronic semiconductor chip 110 and an adhesive, for example an electrically conductive adhesive, or using another fastening material ⁇ the.
• An electrical contact of the optoelectronic semiconductor chip 110 may be at the top 111 of the optoelectronic semiconductor chip 110 is formed, for example, an anode contact 120.
• the anode contact 120 is in this case with ⁇ means of the solder 260 electrically conductively connected to the metallization 250 of the carrier 200 connected.
• the optoelectronic semiconductor chip 110 is a laser chip, thus forming the 200 supernatant sides ⁇ surface of the optoelectronic semiconductor chip 110, a emis- sionsfacette at the top 201 of the carrier over the step 230 between the recessed portion 220 and the mounting portion 210 130 of the optoelectronic semiconductor chip 110.
• the optoelectronic semiconductor chips 110 emit ⁇ advantage of this a laser beam at the emission facet 130 in the emission facet 130 perpendicular direction. In this case, the exit point of the laser beam can be close to the upper side 111 of the optoelectronic semiconductor chip 110.
• the projection of the emission facet 130 via the step 230 on the upper side 201 of the carrier 200 prevents solder 260 from reaching the emission facet 130 during the attachment of the optoelectronic semiconductor chip 110 to the upper side 201 of the carrier 200 and contaminating it.
• the voltage applied to the upper surface 201 of the carrier 200 recessed Be ⁇ rich 220 ensures that no edge during dicing of the carrier assembly 300 on the outside 240 of the carrier 200 burrs formed are present in the region of the step 230 that the attachment and orientation of the could affect optoelectronic semiconductor chip 110.

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Optics & Photonics (AREA)
• Semiconductor Lasers (AREA)
• Led Device Packages (AREA)

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• 2015
  • 2015-09-23 DE DE102015116092.7A patent/DE102015116092B4/de active Active
• 2016
  • 2016-09-15 US US15/761,585 patent/US10454240B2/en active Active
  • 2016-09-15 WO PCT/EP2016/071847 patent/WO2017050636A1/de not_active Ceased
  • 2016-09-15 JP JP2018514853A patent/JP6779283B2/ja active Active

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