WO2017045220A1 - 一种goa电路及液晶显示器 - Google Patents

一种goa电路及液晶显示器 Download PDF

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Publication number
WO2017045220A1
WO2017045220A1 PCT/CN2015/090352 CN2015090352W WO2017045220A1 WO 2017045220 A1 WO2017045220 A1 WO 2017045220A1 CN 2015090352 W CN2015090352 W CN 2015090352W WO 2017045220 A1 WO2017045220 A1 WO 2017045220A1
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WIPO (PCT)
Prior art keywords
transistor
signal
gate
nth
nth stage
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Ceased
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PCT/CN2015/090352
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English (en)
French (fr)
Inventor
曹尚操
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/786,088 priority Critical patent/US9721520B2/en
Publication of WO2017045220A1 publication Critical patent/WO2017045220A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystals, and in particular to a GOA circuit and a liquid crystal display.
  • an indium gallium zinc oxide thin film transistor (IGZO) is usually used.
  • TFT to implement a Gate Driver On Array (GOA). Due to IGZO
  • Vth negative turn-on voltage
  • SS Subthreshold Swing
  • Vgs potential difference between the gate and the source
  • the technical problem mainly solved by the present invention is to provide a GOA circuit and a liquid crystal display capable of blocking IGZO in a GOA circuit.
  • the leakage path of the TFT enhances the stability of the GOA circuit.
  • a technical solution adopted by the present invention is to provide a GOA circuit for a liquid crystal display, wherein the GOA circuit includes a plurality of cascaded GOA units, wherein the Nth level GOA unit includes: Pulling control module, downlink module, pull-up module, pull-down maintaining module and leakage control module; the pull-up control module comprises a first transistor, and the gate of the first transistor is connected with the N-1th-level down signal, the first transistor The drain is connected to the first leakage control signal, the source of the first transistor is connected to the Nth gate signal; the downstream module comprises a second transistor, the gate of the second transistor is connected to the Nth gate signal, and the second The drain of the transistor is connected to the Nth clock signal line, the source of the second transistor outputs the Nth stage down signal, the pullup module includes a third transistor, and the gate of the third transistor is connected to the Nth stage gate signal.
  • the drain of the third transistor is connected to the Nth clock signal line, the source of the third transistor outputs the Nth scan signal;
  • the pull-down sustaining module includes the fifth transistor and the eighth transistor, and the gate of the fifth transistor Connected to the Nth stage common signal, the drain of the fifth transistor is connected to the Nth stage down signal, the source of the fifth transistor is connected to the first DC low voltage, and the gate of the eighth transistor and the Nth stage common signal Connected, the source of the eighth transistor is connected to the first DC low voltage, the drain of the eighth transistor is connected to the signal of the Nth gate; and the leakage control module is connected in series between the Nth gate signal and the eighth transistor And/or between the Nth stage down signal and the fifth transistor, for blocking the leakage path of the Nth stage gate signal through the eighth transistor by the second leakage control signal during the effective period of the Nth stage scan signal Or the Nth stage downlink signal passes through the leakage path of the fifth transistor; wherein the leakage control module includes a fourth transistor and a seventh transistor,
  • the second leakage control signal is an Nth stage downlink signal.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein the Nth-level GOA unit includes: a pull-up control module, a downlink module, a pull-up module, a pull-down maintenance module, and a leakage control module;
  • the pull-up control module includes a first transistor, and a gate of the first transistor is connected to a N-1th-level down signal, the first transistor The drain is connected to the first leakage control signal, the source of the first transistor is connected to the Nth gate signal;
  • the downstream module comprises a second transistor, and the gate of the second transistor is connected to the Nth gate signal, The drain of the two transistors is connected to the Nth clock signal line, the source of the second transistor outputs the Nth stage down signal,
  • the pullup module includes the third transistor, and the gate of the third transistor is connected to the Nth stage gate signal a drain of the third transistor is connected to
  • the leakage control module includes a fourth transistor and a seventh transistor.
  • the gate of the fourth transistor is connected to the second leakage control signal
  • the drain of the fourth transistor is connected to the DC signal source
  • the source and the eighth transistor of the fourth transistor are connected.
  • a drain connection the seventh transistor is connected in series between the Nth stage gate signal and the drain of the eighth transistor
  • the gate of the seventh transistor is connected to the Nth stage common signal
  • the drain of the seventh transistor is the Nth
  • the gate signal is connected, and the source of the seventh transistor is connected to the drain of the eighth transistor to block the leakage path of the Nth gate signal through the eighth transistor during the period of the Nth scan signal.
  • the second leakage control signal is an Nth stage downlink signal.
  • the second leakage control signal is an N-1th stage gate signal.
  • the leakage control module further includes a sixth transistor connected in series between the Nth stage down signal and the drain of the fifth transistor, the gate of the sixth transistor being connected to the Nth stage common signal, and the sixth transistor
  • the drain is connected to the Nth stage down signal
  • the source of the sixth transistor is connected to the drain of the fifth transistor and the source of the fourth transistor to block the Nth stage downlink during the period of the Nth scan signal being valid.
  • the signal passes through the leakage path of the fifth transistor.
  • the first leakage control signal is an N-1th stage gate signal to block the leakage path of the Nth stage gate signal through the first transistor during the effective period of the Nth stage scan signal.
  • the Nth stage GOA unit further includes a pull-down module including a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a gate of the ninth transistor
  • the Nth stage downlink signal connection the source of the ninth transistor is connected to the second DC low voltage, the drain of the ninth transistor is connected to the Nth stage common signal, and the gate of the tenth transistor is transmitted to the N-1th stage.
  • the source of the tenth transistor is connected to the second DC low voltage
  • the drain of the tenth transistor is connected to the common signal of the Nth stage
  • the gate of the eleventh transistor is connected with the signal of the N-1th stage
  • the source of the eleven transistor is connected to the second DC low voltage
  • the drain of the eleventh transistor is connected to the source of the twelfth transistor
  • the gate of the twelfth transistor is connected to the N-1th clock signal line
  • the drain of the twelve transistor is connected to the gate of the thirteenth transistor
  • the source of the fourteenth transistor is connected to the common signal of the Nth stage
  • the drain of the thirteenth transistor and the fourteenth transistor Pole and DC signal source Then, N + 2 and the second gate clock bar signal lines fourteenth transistor.
  • the potential of the first DC low voltage is less than the potential of the second DC low voltage
  • the low potential of the N-1th stage and the Nth stage down signal is smaller than the potential of the second DC low voltage, so that the N level scan signal is invalid.
  • the leakage path of the Nth common signal through the ninth transistor, the tenth transistor, and the eleventh transistor is blocked during the period.
  • the Nth stage GOA unit receives the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, and the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are in one operation.
  • the cycle is time-dependent and effective.
  • the Nth clock signal line is the first clock signal
  • the N+2th clock signal line is the third clock signal
  • the N-1th clock signal line is the fourth clock signal.
  • a liquid crystal display including a GOA circuit including a plurality of cascaded GOA units, wherein the Nth stage GOA unit includes: a pull-up control a module, a downlink module, a pull-up module, a pull-down maintenance module, and a leakage control module;
  • the pull-up control module includes a first transistor, and a gate of the first transistor is connected to a N-1th-level downlink signal, and a drain of the first transistor Connected to the first leakage control signal, the source of the first transistor is connected to the Nth stage gate signal;
  • the downstream module includes a second transistor, the gate of the second transistor is connected to the Nth stage gate signal, and the second transistor is The drain is connected to the Nth clock signal line, the source of the second transistor outputs the Nth stage down signal;
  • the pull-up module includes a third transistor, the gate of the third transistor is connected to the Nth-level gate signal, and the third The drain of the
  • the source of the eighth transistor is connected to the first DC low voltage
  • the drain of the eighth transistor is connected to the signal of the Nth gate
  • the leakage control module is connected in series between the Nth gate signal and the eighth transistor and/ Or between the Nth stage down signal and the fifth transistor, for blocking the leakage path of the Nth stage gate signal through the eighth transistor and/or the second leakage control signal during the effective period of the Nth stage scan signal
  • the N-stage downlink signal passes through the leakage path of the fifth transistor.
  • the leakage control module includes a fourth transistor and a seventh transistor.
  • the gate of the fourth transistor is connected to the second leakage control signal
  • the drain of the fourth transistor is connected to the DC signal source
  • the source and the eighth transistor of the fourth transistor are connected.
  • a drain connection the seventh transistor is connected in series between the Nth stage gate signal and the drain of the eighth transistor
  • the gate of the seventh transistor is connected to the Nth stage common signal
  • the drain of the seventh transistor is the Nth
  • the gate signal is connected, and the source of the seventh transistor is connected to the drain of the eighth transistor to block the leakage path of the Nth gate signal through the eighth transistor during the period of the Nth scan signal.
  • the second leakage control signal is an Nth stage downlink signal.
  • the second leakage control signal is an N-1th stage gate signal.
  • the leakage control module further includes a sixth transistor connected in series between the Nth stage down signal and the drain of the fifth transistor, the gate of the sixth transistor being connected to the Nth stage common signal, and the sixth transistor
  • the drain is connected to the Nth stage down signal
  • the source of the sixth transistor is connected to the drain of the fifth transistor and the source of the fourth transistor to block the Nth stage downlink during the period of the Nth scan signal being valid.
  • the signal passes through the leakage path of the fifth transistor.
  • the first leakage control signal is an N-1th stage gate signal to block the leakage path of the Nth stage gate signal through the first transistor during the effective period of the Nth stage scan signal.
  • the Nth stage GOA unit further includes a pull-down module including a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a gate of the ninth transistor
  • the Nth stage downlink signal connection the source of the ninth transistor is connected to the second DC low voltage, the drain of the ninth transistor is connected to the Nth stage common signal, and the gate of the tenth transistor is transmitted to the N-1th stage.
  • the source of the tenth transistor is connected to the second DC low voltage
  • the drain of the tenth transistor is connected to the common signal of the Nth stage
  • the gate of the eleventh transistor is connected with the signal of the N-1th stage
  • the source of the eleven transistor is connected to the second DC low voltage
  • the drain of the eleventh transistor is connected to the source of the twelfth transistor
  • the gate of the twelfth transistor is connected to the N-1th clock signal line
  • the drain of the twelve transistor is connected to the gate of the thirteenth transistor
  • the source of the fourteenth transistor is connected to the common signal of the Nth stage
  • the drain of the thirteenth transistor and the fourteenth transistor Pole and DC signal source Then, N + 2 and the second gate clock bar signal lines fourteenth transistor.
  • the potential of the first DC low voltage is less than the potential of the second DC low voltage
  • the low potential of the N-1th stage and the Nth stage down signal is smaller than the potential of the second DC low voltage, so that the N level scan signal is invalid.
  • the leakage path of the Nth common signal through the ninth transistor, the tenth transistor, and the eleventh transistor is blocked during the period.
  • the Nth stage GOA unit receives the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal, and the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are in one operation.
  • the cycle is time-dependent and effective.
  • the Nth clock signal line is the first clock signal
  • the N+2th clock signal line is the third clock signal
  • the N-1th clock signal line is the fourth clock signal.
  • the invention has the beneficial effects that the GOA circuit and the liquid crystal display of the present invention are connected between the Nth stage gate signal and the eighth transistor and/or in series between the Nth stage down signal and the fifth transistor.
  • Leakage control module thereby enhancing the leakage path of the Nth stage gate signal through the eighth transistor and/or the leakage path of the Nth stage down signal through the fifth transistor during the effective period of the Nth stage scan signal, thereby enhancing The stability of the GOA circuit.
  • FIG. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention.
  • Figure 2 is a circuit schematic diagram of a first embodiment of a GOA unit in the GOA circuit of Figure 1;
  • FIG 3 is a timing chart showing the operation of the first embodiment of the GOA unit in the GOA circuit shown in Figure 1;
  • Figure 4 is a circuit schematic diagram of a second embodiment of a GOA unit in the GOA circuit of Figure 1;
  • FIG. 5 is a schematic structural view of a liquid crystal display device according to an embodiment of the present invention.
  • the GOA circuit 10 includes a plurality of cascaded GOA units 11.
  • the Nth stage GOA unit 11 is configured to output a scan under the control of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4, and the downlink signal ST(N-1).
  • the signal G(N) charges the corresponding Nth horizontal scan line in the display area.
  • the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are sequentially time-divided in one working cycle of the GOA circuit, that is, sequentially time-divided into a high potential.
  • the transistor in the GOA circuit is IGZO TFT.
  • FIG. 2 is a circuit schematic diagram of a first embodiment of a GOA unit in the GOA circuit of Figure 1.
  • the Nth stage GOA unit 11 includes a pull-up control module 100, a downlink module 200, a pull-up module 300, a pull-down maintenance module 400, a leakage control module 500, and a pull-down module 600.
  • the pull-up control module 100 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the N-1th-stage downlink signal ST(N-1), and the drain of the first transistor T1 is connected to the first leakage control signal.
  • the source of the first transistor T1 is coupled to the Nth stage gate signal Q(N).
  • the first leakage control signal is the N-1th stage gate signal Q(N-1).
  • the N-1th-level gate signal Q(N-1) is at a high potential such that the drain of the first transistor T1 is at a high potential, thereby causing the first transistor T1 to Vgs is less than 0, thereby blocking the leakage path of the Nth stage gate signal Q(N) through the first transistor T1.
  • the downstream module 200 includes a second transistor T2, the gate of the second transistor T2 is connected to the Nth stage gate signal Q(N), and the drain of the second transistor T2 is connected to the Nth clock signal line CKn, the second transistor The source of T2 outputs the Nth stage downlink signal ST(N).
  • the pull-up module 300 includes a third transistor T3, the gate of the third transistor T3 is connected to the N-th gate signal Q(N), the drain of the third transistor T3 is connected to the N-th clock signal line CKn, and the third transistor The source of T3 outputs an Nth-order scan signal G(N).
  • the pull-down maintaining module 400 includes a fifth transistor T5 and an eighth transistor T8.
  • the gate of the fifth transistor T5 is connected to the Nth common signal P(N), and the drain of the fifth transistor T5 and the Nth stage downlink signal ST ( N) connected, the source of the fifth transistor T5 is connected to the first DC low voltage VGL1, the gate of the eighth transistor T8 is connected to the Nth common signal P(N), and the source of the eighth transistor T8 is first The DC low voltage VGL1 is connected, and the drain of the eighth transistor T8 is connected to the Nth stage gate signal Q(N).
  • the Nth stage down signal ST(N) leaks through the fifth transistor T5, so that the Nth stage down signal ST (N) The high potential cannot be reached.
  • the Vgs of the eighth transistor T8 is equal to 0, the Nth gate signal Q(N) is leaked through the eighth transistor T8, so that the Nth gate signal Q(N) Unable to reach high potential.
  • the leakage control module 500 is connected in series between the pull-down maintaining module 400 and the Nth stage downlink signal ST(N) and the Nth stage gate signal Q(N) to block by the second leakage control signal.
  • the Nth stage gate signal Q(N) passes through the leakage path of the eighth transistor T8 and the Nth stage down signal ST(N) through the leakage path of the fifth transistor T5.
  • the leakage control module 500 includes a fourth transistor T4, a sixth transistor T6, and a seventh transistor T7.
  • the gate of the fourth transistor T4 is connected to the second leakage control signal, and the drain and DC signal source of the fourth transistor T4.
  • VGL is connected
  • the source of the fourth transistor T4 is connected to the drain of the eighth transistor T8, and the sixth transistor T6 is connected in series between the Nth stage down signal ST(N) and the drain of the fifth transistor T5, sixth
  • the gate of the transistor T6 is connected to the Nth common signal P(N)
  • the drain of the sixth transistor T6 is connected to the Nth stage down signal ST(N)
  • the drain and the source of the fourth transistor T4 are connected
  • the seventh transistor T7 is connected in series between the Nth stage gate signal Q(N) and the drain of the eighth transistor T8, and the gate of the seventh transistor T7 and the Nth
  • the stage common signal P(N) is connected
  • the Nth clock signal line CKn transitions from a low potential to a high potential during the period in which the Nth scan signal G(N) is active, and the Nth stage down signal ST(N) and the Nth stage gate signal Q(N)
  • the output high potential, the drains of the sixth transistor T6 and the seventh transistor T7 become high under the action of the fourth transistor T4, so that the Vgs of the sixth transistor T6 and the seventh transistor T7 are less than 0, thereby blocking the first
  • the N-stage gate signal Q(N) passes through the leakage path of the eighth transistor T8 and the N-th stage down-conversion signal ST(N) through the leakage path of the fifth transistor T5.
  • the leakage control module 500 includes the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7, thereby blocking the Nth stage gate signal Q(N).
  • the leakage path of the eight transistor T8 and the Nth stage down signal ST(N) pass through the leakage path of the fifth transistor T5.
  • the leakage control module 500 may also include only the fourth transistor T4 and the sixth transistor T6 to block the leakage path of the Nth stage down signal ST(N) through the fifth transistor T5.
  • the leakage control module 500 may also include only the fourth transistor T4 and the seventh transistor T7 to block the leakage path of the Nth stage gate signal Q(N) through the eighth transistor T8.
  • the pull-down module 600 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.
  • the gate of the ninth transistor T9 is connected to the Nth stage down signal ST(N)
  • the source of the ninth transistor T9 is connected to the second DC low voltage VGL2
  • the drain of the ninth transistor and the Nth stage common signal are connected.
  • the gate of the tenth transistor T10 is connected to the N-1th down signal ST(N-1)
  • the source of the tenth transistor T10 is connected to the second DC low voltage VGL2
  • the tenth transistor is The drain is connected to the Nth common signal P(N)
  • the gate of the eleventh transistor T11 is connected to the N-1th down signal ST(N-1)
  • the source and the second of the eleventh transistor T11 are connected.
  • the DC low voltage VGL2 is connected, the drain of the eleventh transistor T11 is connected to the source of the twelfth transistor T12, and the gate of the twelfth transistor T12 is connected to the N-1th clock signal line CKn-1, the twelfth
  • the drain of the transistor T12 is connected to the gate of the thirteenth transistor T13 and the source of the fourteenth transistor T14, and the source of the thirteenth transistor T13 is connected to the Nth common signal P(N), and the thirteenth transistor T13
  • the drain of the fourteenth transistor T14 is connected to the DC signal source VGL, and the gate of the fourteenth transistor T14 and the N+2th clock signal line CK n+2 connection.
  • the potential of the first DC low voltage VGL1 is less than the potential of the second DC low voltage VGL2, and the N-1th stage downlink signal ST(N-1) and the Nth stage downlink signal ST(N)
  • the low potential is smaller than the potential of the second DC low voltage VGL2, so that during the period in which the N-th scan signal G(N) is inactive, that is, the N-th common signal P(N) is at a high potential, the ninth transistor T9, the tenth The transistor T10, the Vgs of the eleventh transistor T11 is less than 0, thereby blocking the leakage path of the Nth stage common signal P(N) through the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11, ensuring the Nth The stage common signal P(N) is maintained at a high potential.
  • the Nth clock signal line CKn is the first clock signal CK1
  • the N+2th clock signal line CKn+2 is the third clock signal CK3
  • the N-1th clock signal line CKn- 1 is the fourth clock signal CK4.
  • the Nth stage GOA unit 11 further includes a filter capacitor C1 and a bootstrap capacitor C2.
  • One end of the filter capacitor C1 is connected to the Nth common signal P(N), and the other end of the filter capacitor C1 is connected to the second DC low voltage VGL2.
  • One end of the bootstrap capacitor C2 is connected to the Nth stage gate signal Q(N), and the other end of the bootstrap capacitor C2 is connected to the Nth stage down signal ST(N).
  • FIG. 3 is a timing diagram of the operation of the GOA unit in the GOA circuit shown in FIG. 1.
  • the working process of the Nth-level GOA unit includes:
  • the N-1th downlink signal ST(N-1) and the N-1th gate signal Q(N-1) are at a high potential, and the first transistor T1, the second transistor T2, and the third transistor T3 is turned on, so that the Nth-level gate signal Q(N) becomes a high potential.
  • the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the thirteenth transistor T13 is turned off, so that the Nth-order common signal P(N) becomes a low potential.
  • the Nth stage down signal ST(N) outputs a high potential to drive the N+1th GOA unit.
  • the Nth stage gate signal Q(N) outputs a high potential to charge the corresponding Nth horizontal scanning line in the display area.
  • the N-1th stage gate signal Q(N-1) input to the drain of the first transistor T1 is at a high potential, so that the Vgs of the first transistor T1 is less than 0, thereby blocking the Nth stage gate.
  • the signal Q(N) passes through the leakage path of the first transistor T1.
  • the drains of the sixth transistor T6 and the seventh transistor T7 are high, such that the Vgs of the sixth transistor T6 and the seventh transistor T7 are less than 0, thereby blocking the Nth gate signal Q(N) through the eighth transistor T8.
  • the leakage path and the Nth stage down signal ST(N) pass through the leakage path of the fifth transistor T5.
  • the Nth clock signal line CKn that is, the first clock signal CK1
  • the Nth stage gate signal Q(N) remains at a high potential
  • the Nth stage common signal P (N) Keep it low.
  • the potential of the first DC low voltage VGL1 is smaller than the potential of the second DC low voltage VGL2, the N-1th stage down signal ST(N-1) and the Nth stage down signal ST(N) are low.
  • the potential is less than the potential of the second DC low voltage VGL2, such that the Vgs of the ninth transistor T9, the tenth transistor T10, and the eleventh transistor T11 are less than 0, thereby blocking the Nth common signal P(N) through the ninth transistor T9.
  • FIG. 4 is a circuit schematic diagram of a second embodiment of a GOA unit in the GOA circuit of FIG. 1.
  • the second embodiment shown in FIG. 4 differs from the first embodiment shown in FIG. 2 in that the gate of the fourth transistor T4 and the N-1th gate signal shown in FIG. Q (N-1) is connected, and the gate of the fourth transistor T4 shown in FIG. 2 is connected to the Nth stage down signal ST(N).
  • the Vgs of the seventh transistor is smaller than 0, which in turn causes the Nth stage gate signal Q(N) to go high to block the leakage path of the Nth stage gate signal Q(N) through the eighth transistor T8.
  • FIG. 5 is a schematic structural view of a liquid crystal display device according to an embodiment of the present invention. As shown in FIG. 5, the liquid crystal display 1 includes the above-described GOA circuit 10.
  • the invention has the beneficial effects that the GOA circuit and the liquid crystal display of the present invention are connected between the Nth stage gate signal and the eighth transistor and/or in series between the Nth stage down signal and the fifth transistor.
  • Leakage control module thereby enhancing the leakage path of the Nth stage gate signal through the eighth transistor and/or the leakage path of the Nth stage down signal through the fifth transistor during the effective period of the Nth stage scan signal, thereby enhancing The stability of the GOA circuit.

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Abstract

一种GOA电路及液晶显示器。该GOA电路包括级联的多个GOA单元，第N级GOA单元包括下拉维持模块（400）和漏电控制模块（500），其中，下拉维持模块（400）包括第五晶体管（T5）和第八晶体管（T8），第五晶体管（T5）的漏极与第N级下传信号（ST(N)）连接，第八晶体管（T8）的漏极与第N级栅极信号（Q(N)）连接。漏电控制模块（500）串接于第N级栅极信号（Q(N)）与第八晶体管（T8）之间和/或串接于第N级下传信号（ST(N)）与第五晶体管（T5）之间，以在第N级扫描信号（G(N)）有效期间，阻断第N级栅极信号（Q(N)）经第八晶体管（T8）的漏电途径和/或第N级下传信号（ST(N)）经第五晶体管（T5）的漏电途径，从而增强GOA电路的稳定性。

Description

一种GOA电路及液晶显示器
【技术领域】
本发明涉及液晶领域，特别是涉及一种GOA电路及液晶显示器。
【背景技术】
目前，为了实现液晶显示屏的窄边框或无边框，通常采用铟镓锌氧化物薄膜晶体管（IGZO TFT）来实现栅极驱动电路（Gate Driver On Array，GOA）。由于IGZO TFT具有较负的开启电压（Vth）和较小的亚阈值摆幅（Subthreshold Swing，SS），在栅极与源极的电位差（Vgs）等于0的情况下，IGZO TFT仍然无法正常关闭，存在较大的漏电，从而降低了GOA电路的稳定性、增加了GOA电路的功耗。
【发明内容】
本发明主要解决的技术问题是提供一种GOA电路及液晶显示器，能够阻断GOA电路中IGZO TFT的漏电途径，从而增强GOA电路的稳定性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA电路，用于液晶显示器，其中，该GOA电路包括级联的多个GOA单元，其中，第N级GOA单元包括：上拉控制模块、下传模块、上拉模块、下拉维持模块和漏电控制模块；上拉控制模块包括第一晶体管，第一晶体管的栅极与第N-1级下传信号连接，第一晶体管的漏极与第一漏电控制信号连接，第一晶体管的源极与第N级栅极信号连接；下传模块包括第二晶体管，第二晶体管的栅极与第N级栅极信号连接，第二晶体管的漏极与第N条时钟信号线连接，第二晶体管的源极输出第N级下传信号；上拉模块包括第三晶体管，第三晶体管的栅极与第N级栅极信号连接，第三晶体管的漏极与第N条时钟信号线连接，第三晶体管的源极输出第N级扫描信号；下拉维持模块包括第五晶体管和第八晶体管，第五晶体管的栅极与第N级公共信号连接，第五晶体管的漏极与第N级下传信号连接，第五晶体管的源极与第一直流低电压连接，第八晶体管的栅极与第N级公共信号连接，第八晶体管的源极与第一直流低电压连接，第八晶体管的漏极与第N级栅极信号连接；漏电控制模块串接于第N级栅极信号与第八晶体管之间和/或第N级下传信号与第五晶体管之间，用于在第N级扫描信号有效期间，通过第二漏电控制信号阻断第N级栅极信号经第八晶体管的漏电途径和/或第N级下传信号经第五晶体管的漏电途径；其中，漏电控制模块包括第四晶体管和第七晶体管，第四晶体管的栅极与第二漏电控制信号连接，第四晶体管的漏极与直流信号源连接，第四晶体管的源极与第八晶体管的漏极连接，第七晶体管串接于第N级栅极信号和第八晶体管的漏极之间，第七晶体管的栅极与第N级公共信号连接，第七晶体管的漏极与第N级栅极信号连接，第七晶体管的源极与第八晶体管的漏极连接，以在第N级扫描信号有效期间阻断第N级栅极信号经第八晶体管的漏电途径；其中，第一漏电控制信号为第N-1级栅极信号，以在第N级扫描信号有效期间阻断第N级栅极信号经第一晶体管的漏电途径。
其中，第二漏电控制信号为第N级下传信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种GOA电路，用于液晶显示器，其中，该GOA电路包括级联的多个GOA单元，其中，第N级GOA单元包括：上拉控制模块、下传模块、上拉模块、下拉维持模块和漏电控制模块；上拉控制模块包括第一晶体管，第一晶体管的栅极与第N-1级下传信号连接，第一晶体管的漏极与第一漏电控制信号连接，第一晶体管的源极与第N级栅极信号连接；下传模块包括第二晶体管，第二晶体管的栅极与第N级栅极信号连接，第二晶体管的漏极与第N条时钟信号线连接，第二晶体管的源极输出第N级下传信号；上拉模块包括第三晶体管，第三晶体管的栅极与第N级栅极信号连接，第三晶体管的漏极与第N条时钟信号线连接，第三晶体管的源极输出第N级扫描信号；下拉维持模块包括第五晶体管和第八晶体管，第五晶体管的栅极与第N级公共信号连接，第五晶体管的漏极与第N级下传信号连接，第五晶体管的源极与第一直流低电压连接，第八晶体管的栅极与第N级公共信号连接，第八晶体管的源极与第一直流低电压连接，第八晶体管的漏极与第N级栅极信号连接；漏电控制模块串接于第N级栅极信号与第八晶体管之间和/或第N级下传信号与第五晶体管之间，用于在第N级扫描信号有效期间，通过第二漏电控制信号阻断第N级栅极信号经第八晶体管的漏电途径和/或第N级下传信号经第五晶体管的漏电途径。
其中，漏电控制模块包括第四晶体管和第七晶体管，第四晶体管的栅极与第二漏电控制信号连接，第四晶体管的漏极与直流信号源连接，第四晶体管的源极与第八晶体管的漏极连接，第七晶体管串接于第N级栅极信号和第八晶体管的漏极之间，第七晶体管的栅极与第N级公共信号连接，第七晶体管的漏极与第N级栅极信号连接，第七晶体管的源极与第八晶体管的漏极连接，以在第N级扫描信号有效期间阻断第N级栅极信号经第八晶体管的漏电途径。
其中，第二漏电控制信号为第N级下传信号。
其中，第二漏电控制信号为第N-1级栅极信号。
其中，漏电控制模块进一步包括第六晶体管，第六晶体管串接于第N级下传信号和第五晶体管的漏极之间，第六晶体管的栅极与第N级公共信号连接，第六晶体管的漏极与第N级下传信号连接，第六晶体管的源极与第五晶体管的漏极、第四晶体管的源极连接，以在第N级扫描信号有效期间阻断第N级下传信号经第五晶体管的漏电途径。
其中，第一漏电控制信号为第N-1级栅极信号，以在第N级扫描信号有效期间阻断第N级栅极信号经第一晶体管的漏电途径。
其中，第N级GOA单元进一步包括下拉模块，下拉模块包括第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管，第九晶体管的栅极与第N级下传信号连接，第九晶体管的源极与第二直流低电压连接，第九晶体管的漏极与第N级公共信号连接，第十晶体管的栅极与第N-1级下传信号连接，第十晶体管的源极与第二直流低电压连接，第十晶体管的漏极与第N级公共信号连接，第十一晶体管的栅极与第N-1级下传信号连接，第十一晶体管的源极与第二直流低电压连接，第十一晶体管的漏极与第十二晶体管的源极连接，第十二晶体管的栅极与第N-1条时钟信号线连接，第十二晶体管的漏极与第十三晶体管的栅极、第十四晶体管的源极连接，第十三晶体管的源极与第N级公共信号连接，第十三晶体管、第十四晶体管的漏极与直流信号源连接，第十四晶体管的栅极与第N+2条时钟信号线连接。
其中，第一直流低电压的电位小于第二直流低电压的电位，第N-1级、第N级下传信号的低电位小于第二直流低电压的电位，以在N级扫描信号无效期间阻断第N级公共信号经第九晶体管、第十晶体管、第十一晶体管的漏电途径。
其中，第N级GOA单元接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在一个工作周期依次分时有效，其中，当第N条时钟信号线为第一时钟信号时，第N+2条时钟信号线为第三时钟信号，第N-1条时钟信号线为第四时钟信号。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示器，包括GOA电路，该GOA电路包括级联的多个GOA单元，其中，第N级GOA单元包括：上拉控制模块、下传模块、上拉模块、下拉维持模块和漏电控制模块；上拉控制模块包括第一晶体管，第一晶体管的栅极与第N-1级下传信号连接，第一晶体管的漏极与第一漏电控制信号连接，第一晶体管的源极与第N级栅极信号连接；下传模块包括第二晶体管，第二晶体管的栅极与第N级栅极信号连接，第二晶体管的漏极与第N条时钟信号线连接，第二晶体管的源极输出第N级下传信号；上拉模块包括第三晶体管，第三晶体管的栅极与第N级栅极信号连接，第三晶体管的漏极与第N条时钟信号线连接，第三晶体管的源极输出第N级扫描信号；下拉维持模块包括第五晶体管和第八晶体管，第五晶体管的栅极与第N级公共信号连接，第五晶体管的漏极与第N级下传信号连接，第五晶体管的源极与第一直流低电压连接，第八晶体管的栅极与第N级公共信号连接，第八晶体管的源极与第一直流低电压连接，第八晶体管的漏极与第N级栅极信号连接；漏电控制模块串接于第N级栅极信号与第八晶体管之间和/或第N级下传信号与第五晶体管之间，用于在第N级扫描信号有效期间，通过第二漏电控制信号阻断第N级栅极信号经第八晶体管的漏电途径和/或第N级下传信号经第五晶体管的漏电途径。
其中，漏电控制模块包括第四晶体管和第七晶体管，第四晶体管的栅极与第二漏电控制信号连接，第四晶体管的漏极与直流信号源连接，第四晶体管的源极与第八晶体管的漏极连接，第七晶体管串接于第N级栅极信号和第八晶体管的漏极之间，第七晶体管的栅极与第N级公共信号连接，第七晶体管的漏极与第N级栅极信号连接，第七晶体管的源极与第八晶体管的漏极连接，以在第N级扫描信号有效期间阻断第N级栅极信号经第八晶体管的漏电途径。
其中，第二漏电控制信号为第N级下传信号。
其中，第二漏电控制信号为第N-1级栅极信号。
其中，漏电控制模块进一步包括第六晶体管，第六晶体管串接于第N级下传信号和第五晶体管的漏极之间，第六晶体管的栅极与第N级公共信号连接，第六晶体管的漏极与第N级下传信号连接，第六晶体管的源极与第五晶体管的漏极、第四晶体管的源极连接，以在第N级扫描信号有效期间阻断第N级下传信号经第五晶体管的漏电途径。
其中，第一漏电控制信号为第N-1级栅极信号，以在第N级扫描信号有效期间阻断第N级栅极信号经第一晶体管的漏电途径。
其中，第N级GOA单元进一步包括下拉模块，下拉模块包括第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管，第九晶体管的栅极与第N级下传信号连接，第九晶体管的源极与第二直流低电压连接，第九晶体管的漏极与第N级公共信号连接，第十晶体管的栅极与第N-1级下传信号连接，第十晶体管的源极与第二直流低电压连接，第十晶体管的漏极与第N级公共信号连接，第十一晶体管的栅极与第N-1级下传信号连接，第十一晶体管的源极与第二直流低电压连接，第十一晶体管的漏极与第十二晶体管的源极连接，第十二晶体管的栅极与第N-1条时钟信号线连接，第十二晶体管的漏极与第十三晶体管的栅极、第十四晶体管的源极连接，第十三晶体管的源极与第N级公共信号连接，第十三晶体管、第十四晶体管的漏极与直流信号源连接，第十四晶体管的栅极与第N+2条时钟信号线连接。
其中，第一直流低电压的电位小于第二直流低电压的电位，第N-1级、第N级下传信号的低电位小于第二直流低电压的电位，以在N级扫描信号无效期间阻断第N级公共信号经第九晶体管、第十晶体管、第十一晶体管的漏电途径。
其中，第N级GOA单元接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在一个工作周期依次分时有效，其中，当第N条时钟信号线为第一时钟信号时，第N+2条时钟信号线为第三时钟信号，第N-1条时钟信号线为第四时钟信号。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过增加串接于第N级栅极信号与第八晶体管之间和/或串接于第N级下传信号与第五晶体管之间的漏电控制模块，从而实现了在第N级扫描信号有效期间阻断第N级栅极信号经第八晶体管的漏电途径和/或第N级下传信号经第五晶体管的漏电途径，进而增强了GOA电路的稳定性。
【附图说明】
图1是本发明实施例的GOA电路的结构示意图；
图2是图1所示GOA电路中GOA单元的第一实施例的电路原理图；
图3是图1所示GOA电路中GOA单元的第一实施例的工作时序图；
图4是图1所示GOA电路中GOA单元的第二实施例的电路原理图；
图5是本发明实施例的液晶显示器的结构示意图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图1是本发明实施例的GOA电路的结构示意图。如图1所示，GOA电路10包括级联的多个GOA单元11。其中，第N级GOA单元11用于在第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4、下传信号ST（N-1）的控制下，输出扫描信号G（N）以对显示区域中对应的第N条水平扫描线进行充电。其中，第一时钟信号CK1、第二时钟信号CK2、第三时钟信号CK3、第四时钟信号CK4在GOA电路的一个工作周期依次分时有效也即依次分时为高电位。其中，GOA电路中的晶体管为IGZO TFT。
图2是图1所示GOA电路中GOA单元的第一实施例的电路原理图。如图2所示，第N级GOA单元11包括上拉控制模块100、下传模块200、上拉模块300、下拉维持模块400、漏电控制模块500和下拉模块600。
上拉控制模块100包括第一晶体管T1，第一晶体管T1的栅极与第N-1级下传信号ST（N-1）连接，第一晶体管T1的漏极与第一漏电控制信号连接，第一晶体管T1的源极与第N级栅极信号Q（N）连接。在本实施例中，第一漏电控制信号为第N-1级栅极信号Q（N-1）。其中，在第N级扫描信号G（N）有效期间，第N-1级栅极信号Q（N-1）为高电位使得第一晶体管T1的漏极为高电位，进而使得第一晶体管T1的Vgs小于0，从而阻断了第N级栅极信号Q（N）经第一晶体管T1的漏电途径。
下传模块200包括第二晶体管T2，第二晶体管T2的栅极与第N级栅极信号Q（N）连接，第二晶体管T2的漏极与第N条时钟信号线CKn连接，第二晶体管T2的源极输出第N级下传信号ST（N）。
上拉模块300包括第三晶体管T3，第三晶体管T3的栅极与第N级栅极信号Q（N）连接，第三晶体管T3的漏极与第N条时钟信号线CKn连接，第三晶体管T3的源极输出第N级扫描信号G（N）。
下拉维持模块400包括第五晶体管T5和第八晶体管T8，第五晶体管T5的栅极与第N级公共信号P（N）连接，第五晶体管T5的漏极与第N级下传信号ST（N）连接，第五晶体管T5的源极与第一直流低电压VGL1连接，第八晶体管T8的栅极与第N级公共信号P（N）连接，第八晶体管T8的源极与第一直流低电压VGL1连接，第八晶体管T8的漏极与第N级栅极信号Q（N）连接。
其中，在第N级扫描信号G（N）有效期间，由于第五晶体管T5的Vgs等于0，第N级下传信号ST（N）通过第五晶体管T5漏电，使得第N级下传信号ST（N）无法达到高电位，与此同时，由于第八晶体管T8的Vgs等于0，第N级栅极信号Q（N）通过第八晶体管T8漏电，使得第N级栅极信号Q（N）无法达到高电位。
为解决上述问题，在下拉维持模块400与第N级下传信号ST（N）、第N级栅极信号Q（N）之间串接漏电控制模块500，以通过第二漏电控制信号阻断第N级栅极信号Q（N）经第八晶体管T8的漏电途径和第N级下传信号ST（N）经第五晶体管T5的漏电途径。
具体来说，漏电控制模块500包括第四晶体管T4、第六晶体管T6和第七晶体管T7，第四晶体管T4的栅极与第二漏电控制信号连接，第四晶体管T4的漏极与直流信号源VGL连接，第四晶体管T4的源极与第八晶体管T8的漏极连接，第六晶体管T6串接于第N级下传信号ST（N）和第五晶体管T5的漏极之间，第六晶体管T6的栅极与第N级公共信号P（N）连接，第六晶体管T6的漏极与第N级下传信号ST（N）连接，第六晶体管T6的源极与第五晶体管T5的漏极、第四晶体管T4的源极连接，第七晶体管T7串接于第N级栅极信号Q（N）和第八晶体管T8的漏极之间，第七晶体管T7的栅极与第N级公共信号P（N）连接，第七晶体管T7的漏极与第N级栅极信号Q（N）连接，第七晶体管T7的源极与第八晶体管T8的漏极连接。在本实施例中，第二漏电控制信号为第N级下传信号ST（N）。
其中，在第N级扫描信号G（N）有效期间，第N条时钟信号线CKn从低电位转为高电位，第N级下传信号ST（N）和第N级栅极信号Q（N）输出高电位，第六晶体管T6和第七晶体管T7的漏极在第四晶体管T4的作用下变为高电位，使得第六晶体管T6和第七晶体管T7的Vgs小于0，从而阻断了第N级栅极信号Q（N）经第八晶体管T8的漏电途径和第N级下传信号ST（N）经第五晶体管T5的漏电途径。
本领域的技术人员可以理解，在本实施例中，漏电控制模块500包括第四晶体管T4、第六晶体管T6和第七晶体管T7，从而阻断了第N级栅极信号Q（N）经第八晶体管T8的漏电途径和第N级下传信号ST（N）经第五晶体管T5的漏电途径。在其它实施例中，漏电控制模块500也可以仅仅包括第四晶体管T4和第六晶体管T6以阻断第N级下传信号ST（N）经第五晶体管T5的漏电途径。另外漏电控制模块500也可以仅仅包括第四晶体管T4和第七晶体管T7以阻断第N级栅极信号Q（N）经第八晶体管T8的漏电途径。
下拉模块600包括第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14。其中，第九晶体管T9的栅极与第N级下传信号ST（N）连接，第九晶体管T9的源极与第二直流低电压VGL2连接，第九晶体管的漏极与第N级公共信号P（N）连接，第十晶体管T10的栅极与第N-1级下传信号ST（N-1）连接，第十晶体管T10的源极与第二直流低电压VGL2连接，第十晶体管的漏极与第N级公共信号P（N）连接，第十一晶体管T11的栅极与第N-1级下传信号ST（N-1）连接，第十一晶体管T11的源极与第二直流低电压VGL2连接，第十一晶体管T11的漏极与第十二晶体管T12的源极连接，第十二晶体管T12的栅极与第N-1条时钟信号线CKn-1连接，第十二晶体管T12的漏极与第十三晶体管T13的栅极、第十四晶体管T14的源极连接，第十三晶体管T13的源极与第N级公共信号P（N）连接，第十三晶体管T13、第十四晶体管T14的漏极与直流信号源VGL连接，第十四晶体管T14的栅极与第N+2条时钟信号线CKn+2连接。
在本实施例中，第一直流低电压VGL1的电位小于第二直流低电压VGL2的电位，第N-1级下传信号ST（N-1）、第N级下传信号ST（N）的低电位小于第二直流低电压VGL2的电位，从而使得在N级扫描信号G（N）无效期间也即第N级公共信号P（N）处于高电位的期间，第九晶体管T9、第十晶体管T10，第十一晶体管T11的Vgs小于0，从而阻断了第N级公共信号P（N）经第九晶体管T9、第十晶体管T10、第十一晶体管T11的漏电途径，保证了第N级公共信号P（N）维持在高电位。
在本实施例中，当第N条时钟信号线CKn为第一时钟信号CK1时，第N+2条时钟信号线CKn+2为第三时钟信号CK3，第N-1条时钟信号线CKn-1为第四时钟信号CK4。
优选地，第N级GOA单元11进一步包括滤波电容C1和自举电容C2。滤波电容C1的一端与第N级公共信号P（N）连接，滤波电容C1的另一端与第二直流低电压VGL2连接。自举电容C2的一端与第N级栅极信号Q（N）连接，自举电容C2的另一端与第N级下传信号ST（N）连接。
请一并参考图3，图3是图1所示GOA电路中GOA单元的工作时序图。如图3所示，第N级GOA单元的工作过程包括：
在T1阶段，第N-1级下传信号ST（N-1）和第N-1级栅极信号Q（N-1）为高电位，第一晶体管T1、第二晶体管T2和第三晶体管T3打开，从而使得第N级栅极信号Q（N）变为高电位。第十晶体管T10、第十一晶体管T11、第十二晶体管T12打开，第十三晶体管T13关闭，从而使得第N级公共信号P（N）变为低电位。
在T2阶段，第N条时钟信号线CKn也即第一时钟信号CK1从低电位变为高电位时，第N级下传信号ST（N）输出高电位以驱动第N+1级GOA单元，第N级栅极信号Q（N）输出高电位以对显示区域中对应的第N条水平扫描线进行充电。此时，第一晶体管T1的漏极所输入的第N-1级栅极信号Q（N-1）为高电位，使得第一晶体管T1的Vgs小于0，从而阻断了第N级栅极信号Q（N）经第一晶体管T1的漏电途径。第六晶体管T6、第七晶体管T7的漏极为高电位，使得第六晶体管T6、第七晶体管T7的Vgs小于0，从而阻断了第N级栅极信号Q（N）经第八晶体管T8的漏电途径和第N级下传信号ST（N）经第五晶体管T5的漏电途径。
在T3阶段，第N条时钟信号线CKn也即第一时钟信号CK1从高电位变为低电位时，此时，第N级栅极信号Q（N）保持高电位，第N级公共信号P（N）保持低电位。
在T4阶段，第N+2条时钟信号线CKn+2也即第三时钟信号CK3为高电位，第十三晶体管T13、第十四晶体管T14打开，第N级公共信号P（N）变为高电位，第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8打开，第N级下传信号ST（N）和第N级栅极信号Q（N）变为低电位。此时，由于第一直流低电压VGL1的电位小于第二直流低电压VGL2的电位，第N-1级下传信号ST（N-1）、第N级下传信号ST（N）的低电位小于第二直流低电压VGL2的电位，使得第九晶体管T9、第十晶体管T10，第十一晶体管T11的Vgs小于0，从而阻断了第N级公共信号P（N）经第九晶体管T9、第十晶体管T10、第十一晶体管T11的漏电途径。
图4是图1所示GOA电路中GOA单元的第二实施例的电路原理图。如图4所示，图4所示的第二实施例与图2所示的第一实施例的区别在于：图4所示的第四晶体管T4的栅极与第N-1级栅极信号Q（N-1）连接，而图2所示的第四晶体管T4的栅极与第N级下传信号ST（N）连接。
其中，在图3所示的T1阶段，由于图4中第四晶体管T4的栅极所连接的第N-1级栅极信号Q（N-1）为高电位，使得第七晶体管的Vgs小于0，进而使得第N级栅极信号Q（N）变为高电平时阻断了第N级栅极信号Q（N）经第八晶体管T8的漏电途径。
图5是本发明实施例的液晶显示器的结构示意图。如图5所示，液晶显示器1包括了上述GOA电路10。
本发明的有益效果是：本发明的GOA电路及液晶显示器通过增加串接于第N级栅极信号与第八晶体管之间和/或串接于第N级下传信号与第五晶体管之间的漏电控制模块，从而实现了在第N级扫描信号有效期间阻断第N级栅极信号经第八晶体管的漏电途径和/或第N级下传信号经第五晶体管的漏电途径，进而增强了GOA电路的稳定性。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，其中，第N级GOA单元包括：上拉控制模块、下传模块、上拉模块、下拉维持模块和漏电控制模块；
    所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极与第N-1级下传信号连接，所述第一晶体管的漏极与第一漏电控制信号连接，所述第一晶体管的源极与第N级栅极信号连接；
    所述下传模块包括第二晶体管，所述第二晶体管的栅极与第N级栅极信号连接，所述第二晶体管的漏极与第N条时钟信号线连接，所述第二晶体管的源极输出第N级下传信号；
    所述上拉模块包括第三晶体管，所述第三晶体管的栅极与第N级栅极信号连接，所述第三晶体管的漏极与第N条时钟信号线连接，所述第三晶体管的源极输出第N级扫描信号；
    所述下拉维持模块包括第五晶体管和第八晶体管，所述第五晶体管的栅极与第N级公共信号连接，所述第五晶体管的漏极与第N级下传信号连接，所述第五晶体管的源极与第一直流低电压连接，所述第八晶体管的栅极与第N级公共信号连接，所述第八晶体管的源极与所述第一直流低电压连接，所述第八晶体管的漏极与第N级栅极信号连接；
    所述漏电控制模块串接于第N级栅极信号与所述第八晶体管之间和/或第N级下传信号与所述第五晶体管之间，用于在第N级扫描信号有效期间，通过第二漏电控制信号阻断第N级栅极信号经所述第八晶体管的漏电途径和/或第N级下传信号经所述第五晶体管的漏电途径；
    所述漏电控制模块包括第四晶体管和第七晶体管，所述第四晶体管的栅极与所述第二漏电控制信号连接，所述第四晶体管的漏极与直流信号源连接，所述第四晶体管的源极与所述第八晶体管的漏极连接，所述第七晶体管串接于第N级栅极信号和所述第八晶体管的漏极之间，所述第七晶体管的栅极与所述第N级公共信号连接，所述第七晶体管的漏极与第N级栅极信号连接，所述第七晶体管的源极与所述第八晶体管的漏极连接，以在第N级扫描信号有效期间阻断第N级栅极信号经所述第八晶体管的漏电途径；
    所述第一漏电控制信号为第N-1级栅极信号，以在第N级扫描信号有效期间阻断第N级栅极信号经所述第一晶体管的漏电途径。
  2. 根据权利要求2所述的GOA电路，其中，所述第二漏电控制信号为第N级下传信号。
  3. 一种GOA电路，用于液晶显示器，其中，所述GOA电路包括级联的多个GOA单元，其中，第N级GOA单元包括：上拉控制模块、下传模块、上拉模块、下拉维持模块和漏电控制模块；
    所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极与第N-1级下传信号连接，所述第一晶体管的漏极与第一漏电控制信号连接，所述第一晶体管的源极与第N级栅极信号连接；
    所述下传模块包括第二晶体管，所述第二晶体管的栅极与第N级栅极信号连接，所述第二晶体管的漏极与第N条时钟信号线连接，所述第二晶体管的源极输出第N级下传信号；
    所述上拉模块包括第三晶体管，所述第三晶体管的栅极与第N级栅极信号连接，所述第三晶体管的漏极与第N条时钟信号线连接，所述第三晶体管的源极输出第N级扫描信号；
    所述下拉维持模块包括第五晶体管和第八晶体管，所述第五晶体管的栅极与第N级公共信号连接，所述第五晶体管的漏极与第N级下传信号连接，所述第五晶体管的源极与第一直流低电压连接，所述第八晶体管的栅极与第N级公共信号连接，所述第八晶体管的源极与所述第一直流低电压连接，所述第八晶体管的漏极与第N级栅极信号连接；
    所述漏电控制模块串接于第N级栅极信号与所述第八晶体管之间和/或第N级下传信号与所述第五晶体管之间，用于在第N级扫描信号有效期间，通过第二漏电控制信号阻断第N级栅极信号经所述第八晶体管的漏电途径和/或第N级下传信号经所述第五晶体管的漏电途径。
  4. 根据权利要求3所述的GOA电路，其中，所述漏电控制模块包括第四晶体管和第七晶体管，所述第四晶体管的栅极与所述第二漏电控制信号连接，所述第四晶体管的漏极与直流信号源连接，所述第四晶体管的源极与所述第八晶体管的漏极连接，所述第七晶体管串接于第N级栅极信号和所述第八晶体管的漏极之间，所述第七晶体管的栅极与所述第N级公共信号连接，所述第七晶体管的漏极与第N级栅极信号连接，所述第七晶体管的源极与所述第八晶体管的漏极连接，以在第N级扫描信号有效期间阻断第N级栅极信号经所述第八晶体管的漏电途径。
  5. 根据权利要求4所述的GOA电路，其中，所述第二漏电控制信号为第N级下传信号。
  6. 根据权利要求4所述的GOA电路，其中，所述第二漏电控制信号为第N-1级栅极信号。
  7. 根据权利要求4所述的GOA电路，其中，所述漏电控制模块进一步包括第六晶体管，所述第六晶体管串接于第N级下传信号和所述第五晶体管的漏极之间，所述第六晶体管的栅极与所述第N级公共信号连接，所述第六晶体管的漏极与第N级下传信号连接，所述第六晶体管的源极与所述第五晶体管的漏极、所述第四晶体管的源极连接，以在第N级扫描信号有效期间阻断第N级下传信号经所述第五晶体管的漏电途径。
  8. 根据权利要求3所述的GOA电路，其中，所述第一漏电控制信号为第N-1级栅极信号，以在第N级扫描信号有效期间阻断第N级栅极信号经所述第一晶体管的漏电途径。
  9. 根据权利要求3所述的GOA电路，其中，第N级GOA单元进一步包括下拉模块，所述下拉模块包括第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管，所述第九晶体管的栅极与第N级下传信号连接，所述第九晶体管的源极与第二直流低电压连接，所述第九晶体管的漏极与第N级公共信号连接，所述第十晶体管的栅极与第N-1级下传信号连接，所述第十晶体管的源极与所述第二直流低电压连接，所述第十晶体管的漏极与第N级公共信号连接，所述第十一晶体管的栅极与第N-1级下传信号连接，所述第十一晶体管的源极与所述第二直流低电压连接，所述第十一晶体管的漏极与所述第十二晶体管的源极连接，所述第十二晶体管的栅极与第N-1条时钟信号线连接，所述第十二晶体管的漏极与所述第十三晶体管的栅极、所述第十四晶体管的源极连接，所述第十三晶体管的源极与所述第N级公共信号连接，所述第十三晶体管、第十四晶体管的漏极与所述直流信号源连接，所述第十四晶体管的栅极与第N+2条时钟信号线连接。
  10. 根据权利要求9所述的GOA电路，其中，所述第一直流低电压的电位小于所述第二直流低电压的电位，第N-1级、第N级下传信号的低电位小于所述第二直流低电压的电位，以在N级扫描信号无效期间阻断第N级公共信号经所述第九晶体管、第十晶体管、第十一晶体管的漏电途径。
  11. 根据权利要求9所述的GOA电路，其中，第N级GOA单元接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，所述第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在一个工作周期依次分时有效，其中，当第N条时钟信号线为所述第一时钟信号时，所述第N+2条时钟信号线为所述第三时钟信号，所述第N-1条时钟信号线为所述第四时钟信号。
  12. 一种液晶显示器，其中，包括GOA电路，所述GOA电路包括级联的多个GOA单元，其中，第N级GOA单元包括：上拉控制模块、下传模块、上拉模块、下拉维持模块和漏电控制模块；
    所述上拉控制模块包括第一晶体管，所述第一晶体管的栅极与第N-1级下传信号连接，所述第一晶体管的漏极与第一漏电控制信号连接，所述第一晶体管的源极与第N级栅极信号连接；
    所述下传模块包括第二晶体管，所述第二晶体管的栅极与第N级栅极信号连接，所述第二晶体管的漏极与第N条时钟信号线连接，所述第二晶体管的源极输出第N级下传信号；
    所述上拉模块包括第三晶体管，所述第三晶体管的栅极与第N级栅极信号连接，所述第三晶体管的漏极与第N条时钟信号线连接，所述第三晶体管的源极输出第N级扫描信号；
    所述下拉维持模块包括第五晶体管和第八晶体管，所述第五晶体管的栅极与第N级公共信号连接，所述第五晶体管的漏极与第N级下传信号连接，所述第五晶体管的源极与第一直流低电压连接，所述第八晶体管的栅极与第N级公共信号连接，所述第八晶体管的源极与所述第一直流低电压连接，所述第八晶体管的漏极与第N级栅极信号连接；
    所述漏电控制模块串接于第N级栅极信号与所述第八晶体管之间和/或第N级下传信号与所述第五晶体管之间，用于在第N级扫描信号有效期间，通过第二漏电控制信号阻断第N级栅极信号经所述第八晶体管的漏电途径和/或第N级下传信号经所述第五晶体管的漏电途径。
  13. 根据权利要求12所述的液晶显示器，其中，所述漏电控制模块包括第四晶体管和第七晶体管，所述第四晶体管的栅极与所述第二漏电控制信号连接，所述第四晶体管的漏极与直流信号源连接，所述第四晶体管的源极与所述第八晶体管的漏极连接，所述第七晶体管串接于第N级栅极信号和所述第八晶体管的漏极之间，所述第七晶体管的栅极与所述第N级公共信号连接，所述第七晶体管的漏极与第N级栅极信号连接，所述第七晶体管的源极与所述第八晶体管的漏极连接，以在第N级扫描信号有效期间阻断第N级栅极信号经所述第八晶体管的漏电途径。
  14. 根据权利要求13所述的液晶显示器，其中，所述第二漏电控制信号为第N级下传信号。
  15. 根据权利要求13所述的液晶显示器，其中，所述第二漏电控制信号为第N-1级栅极信号。
  16. 根据权利要求13所述的液晶显示器，其中，所述漏电控制模块进一步包括第六晶体管，所述第六晶体管串接于第N级下传信号和所述第五晶体管的漏极之间，所述第六晶体管的栅极与所述第N级公共信号连接，所述第六晶体管的漏极与第N级下传信号连接，所述第六晶体管的源极与所述第五晶体管的漏极、所述第四晶体管的源极连接，以在第N级扫描信号有效期间阻断第N级下传信号经所述第五晶体管的漏电途径。
  17. 根据权利要求12所述的液晶显示器，其中，所述第一漏电控制信号为第N-1级栅极信号，以在第N级扫描信号有效期间阻断第N级栅极信号经所述第一晶体管的漏电途径。
  18. 根据权利要求12所述的液晶显示器，其中，第N级GOA单元进一步包括下拉模块，所述下拉模块包括第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管，所述第九晶体管的栅极与第N级下传信号连接，所述第九晶体管的源极与第二直流低电压连接，所述第九晶体管的漏极与第N级公共信号连接，所述第十晶体管的栅极与第N-1级下传信号连接，所述第十晶体管的源极与所述第二直流低电压连接，所述第十晶体管的漏极与第N级公共信号连接，所述第十一晶体管的栅极与第N-1级下传信号连接，所述第十一晶体管的源极与所述第二直流低电压连接，所述第十一晶体管的漏极与所述第十二晶体管的源极连接，所述第十二晶体管的栅极与第N-1条时钟信号线连接，所述第十二晶体管的漏极与所述第十三晶体管的栅极、所述第十四晶体管的源极连接，所述第十三晶体管的源极与所述第N级公共信号连接，所述第十三晶体管、第十四晶体管的漏极与所述直流信号源连接，所述第十四晶体管的栅极与第N+2条时钟信号线连接。
  19. 根据权利要求18所述的液晶显示器，其中，所述第一直流低电压的电位小于所述第二直流低电压的电位，第N-1级、第N级下传信号的低电位小于所述第二直流低电压的电位，以在N级扫描信号无效期间阻断第N级公共信号经所述第九晶体管、第十晶体管、第十一晶体管的漏电途径。
  20. 根据权利要求18所述的液晶显示器，其中，第N级GOA单元接收第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号，所述第一时钟信号、第二时钟信号、第三时钟信号、第四时钟信号在一个工作周期依次分时有效，其中，当第N条时钟信号线为所述第一时钟信号时，所述第N+2条时钟信号线为所述第三时钟信号，所述第N-1条时钟信号线为所述第四时钟信号。
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