WO2017041363A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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WO2017041363A1
WO2017041363A1 PCT/CN2015/095251 CN2015095251W WO2017041363A1 WO 2017041363 A1 WO2017041363 A1 WO 2017041363A1 CN 2015095251 W CN2015095251 W CN 2015095251W WO 2017041363 A1 WO2017041363 A1 WO 2017041363A1
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layer
substrate
vertical channel
gate
common source
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PCT/CN2015/095251
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English (en)
French (fr)
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霍宗亮
叶甜春
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中国科学院微电子研究所
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Priority to US15/758,292 priority Critical patent/US10504916B2/en
Publication of WO2017041363A1 publication Critical patent/WO2017041363A1/zh

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    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Definitions

  • the present invention relates to the field of semiconductor devices and methods of fabricating the same, and in particular to a three-dimensional memory device and a method of fabricating the same.
  • the process and structure for forming a three-dimensional memory device are faced with many challenges in view of the continued scaling down of the feature size of the semiconductor process.
  • the lower selection tube (BSG) 21 is composed of an L-type SEG (selective epitaxial growth) transistor, including two trench lengths L1 and L2.
  • the width of the gate electrode needs to be reduced, and the aperture is further reduced, but the high-temperature process in the preparation process of the memory device causes undesired diffusion of the implantation of the common source region 22, as shown by the dotted line in FIG.
  • the N+ region under the channel hole 23 tends to be pinched off, so that it is difficult to perform hole body erasing of the substrate 24.
  • the invention provides a novel three-dimensional memory device and a manufacturing method thereof, which adopts a method of forming an isolation structure between a common source region and a substrate, and overcomes the storage operation caused by the diffusion of the common source region existing in the prior art. The problem of failure.
  • the present invention provides a method of fabricating a semiconductor device for fabricating a three-dimensional memory device, comprising the steps of:
  • a semiconductor material is grown by an epitaxial or deposition process to completely cover the isolation structure and planarize;
  • the isolating structural material is silicon dioxide having an L-shaped structure.
  • the gate structure layer is a gate layer using a gate-first process; or a gate gate layer is a dummy gate layer.
  • the gate dielectric layer comprises a tunneling layer, a storage layer and a barrier layer, wherein the tunneling layer material is formed of SiO 2 , SiON, Si 3 N 4 or high K material, having a single layer or Multilayer structure; the storage layer material is a material having charge trapping ability, including Si 3 N 4 , SiON, HfO 2 , Al 2 O 3 , AlN, having a single layer or a multilayer structure; the barrier layer material is SiO 2 , Al 2 O 3 , HfO 2 , has a single layer or a multilayer structure.
  • the tunneling layer material is formed of SiO 2 , SiON, Si 3 N 4 or high K material, having a single layer or Multilayer structure
  • the storage layer material is a material having charge trapping ability, including Si 3 N 4 , SiON, HfO 2 , Al 2 O 3 , AlN, having a single layer or a multilayer structure
  • the barrier layer material is SiO 2 , Al 2 O 3 , HfO 2
  • the material of the vertical channel layer is a-Si, PolySi, SiGe.
  • the gate layer is a polysilicon, a silicide, a metal or a metal nitride, having a multilayer or a single layer structure.
  • the formation of the vertical channel region is a core-shell structure filled with a columnar, hollow ring, hollow ring and insulating layer.
  • the present invention also provides a semiconductor device, including a three-dimensional memory device, which specifically includes:
  • a multilayer dielectric film comprising alternating layers of silicon dioxide and a gate structure layer
  • a vertical channel region located in the multilayer dielectric film, a bottom portion of the vertical channel region exposing a semiconductor material, wherein at least a portion of the vertical channel region directly under the substrate is not Isolated by the isolation structure;
  • a common source region located in the substrate, at least partially separated from the substrate directly under the common source region by the isolation structure;
  • the gate dielectric layer among the vertical channel regions is linear or L-shaped.
  • the invention has the advantages that an isolation structure is embedded between the common source region and the substrate under it, which can suppress undesired diffusion of impurities during the common source implantation, and avoid operation failure due to excessive diffusion of impurities. .
  • an isolation structure is embedded between the common source region and the substrate under it, which can suppress undesired diffusion of impurities during the common source implantation, and avoid operation failure due to excessive diffusion of impurities. .
  • electrons flow from the common source region to the bit line, and when erasing, holes are injected from the substrate. Due to the existence of the isolation structure, the three-dimensional memory device needs to be programmed/erased. The spatial separation of electrons and holes enhances the efficiency of erasing and also improves integration.
  • FIG. 1-12 are schematic flow charts of a semiconductor manufacturing method provided by the present invention and a schematic structural view of a semiconductor device;
  • Figure 13 is a schematic view of the prior art.
  • the present invention provides a semiconductor device and a method of fabricating the same, and, in particular, to a three-dimensional memory device and a method of fabricating the same.
  • a method of manufacturing a semiconductor device provided by the present invention will be described in detail with reference to the accompanying drawings.
  • a substrate 1 is provided on which a first mask layer 2 is formed.
  • the semiconductor substrate 1 can be reasonably selected according to the needs of the device, including but not limited to a bulk silicon substrate, an SOI substrate, a germanium substrate, a germanium-silicon (SiGe) substrate, a compound semiconductor material such as gallium nitride (GaN), Gallium arsenide (GaAs), indium phosphide (InP), and the like.
  • the semiconductor substrate 1 in the present embodiment preferably employs a bulk silicon substrate such as a P-type silicon substrate.
  • the first mask layer may be used 2 SiON, Si 3 N 4 and other materials.
  • a semiconductor material is grown by an epitaxial or deposition process to completely cover the isolation structure 3 and planarize.
  • a single crystal silicon, SiGe, or the like may be grown by an epitaxial method, or a semiconductor material such as polycrystalline silicon may be deposited by a deposition method.
  • the semiconductor material formed in this step is used to form a common source region, a horizontal channel region, and the like in a subsequent process. Since both of the substrate and the substrate are of a semiconductor material and have the same function, no boundary is drawn in the drawing, and no new reference numerals are given to the epitaxial semiconductor material.
  • a silicon dioxide layer and a gate structure layer are alternately deposited a plurality of times to form a multilayer dielectric film 4; then, a vertical trench is formed in the multilayer dielectric film 4 by a photolithography and etching process.
  • the track region 5, the bottom portion of the vertical channel region is exposed to grow semiconductor material by epitaxial or deposition processes, and at least a portion of the vertical channel region 5 directly under the substrate 1 is not isolated by the isolation structure 3.
  • the multilayer dielectric film 4 is a laminate formed by alternately laminating a silicon dioxide layer and a gate structure layer, and the portion of the multilayer dielectric film 4 close to the substrate 1 is a silicon dioxide layer. If a gate first process is used, the gate structure layer in the multilayer dielectric film 4 is the gate layer of the final memory device, and the material of the gate layer is polysilicon, silicide, metal or metal nitride, for example. Tungsten (W), TaN, etc. may also include a metal barrier layer such as tungsten nitride (WN), and the gate layer may be formed of a plurality of layers or a single layer structure from these materials.
  • WN tungsten nitride
  • the gate structure layer in the multilayer dielectric film 4 is a dummy gate layer, for example, a SiON, Si 3 N 4 layer, which is removed in a subsequent process.
  • a back gate process is employed, and the subsequent process is also performed based on a back gate process, while in an alternative embodiment, a gate first process may be employed.
  • the shape of the vertical channel region 5 includes, but is not limited to, a columnar shape, a strip shape, a rhombic column shape, a semi-cylindrical shape, or the like, or a core-shell structure filled with a hollow ring shape, a hollow ring shape, and an insulating layer, which is determined according to specific device requirements. .
  • the gate dielectric layer 6 further includes a tunneling layer, a storage layer, and a barrier layer (both of which are not given reference numerals).
  • the tunneling layer material is formed of SiO 2 , SiON, or high-k materials such as HfO 2 and Al 2 O 3 , and may have a single layer or a multi-layer structure
  • the storage layer material is a material having charge trapping ability, such as Si 3 N 4 , SiON, HfO 2 , Al 2 O 3 , AlN, etc., may also have a single layer or a multilayer structure
  • the barrier layer material is a dielectric material such as SiO 2 , Al 2 O 3 , HfO 2 , and has a single layer or a multilayer structure.
  • the material of the vertical channel layer 7 is amorphous Si, polycrystalline Si, SiGe, etc.
  • the channel isolation layer 8 is SiO 2 , Si 3 N 4 , air gap, SiGe, and the like.
  • SEG selective epitaxial growth
  • each layer can be etched back and filled with the bit line contact region 10, such as amorphous Si, polycrystalline Si, SiGe or metal. material.
  • the multilayer dielectric film 4 is etched by a mask to grow a semiconductor material by epitaxial or deposition process, and implanted to form a common source region 11, directly under the common source region 11 and the substrate 1 At least partially isolated by the isolation structure 3.
  • the substrate of the semiconductor material is exposed by etching, that is, the position of the common source region 11 is required to be formed; meanwhile, in the present embodiment, after the etching process, multiple The dummy gate layer forms a space for accommodating the subsequent gate layer.
  • the impurity type of the common source region 11 is N+ type.
  • the invention embeds the isolation structure 3, in particular the L-shaped isolation structure 3, between the common source region 11 and the substrate below it, and can suppress the undesired diffusion of impurities when performing the common source region implantation, and better
  • the impurities are controlled in the common source region, avoiding operational failure due to excessive diffusion of impurities, for example, causing the void body to be erased.
  • the isolation structure 3 realizes spatial separation of the N-type region and the P-type region, and specifically to the present embodiment, is the separation of the P-type substrate from the N+-type common source region.
  • the gate-last process of the present embodiment referring to FIG. 9, after the common source region is formed, filling of the gate electrode is performed, for example, using TiN, W, or the like, to form respective gate electrodes including the lower selection transistor gate 12.
  • a gate dielectric layer of the lower selection transistor gate 12 corresponding to its vertical direction channel is preferentially formed, for example, using an oxidation process.
  • the silicon dioxide material in the multilayer dielectric film 4 may also be removed first before the dummy gate layer is removed, and after the dummy gate layer is removed, the entire gate dielectric layer 6 or a portion of the gate dielectric Layer 6 can be filled by deposition after the dummy gate layer is removed, and then the gate electrode is filled.
  • the formation of the gate electrode and the gate dielectric layer in the back gate process can be set at a suitable position in the process flow after etching the common source region according to specific needs.
  • a spacer dielectric is deposited to form an isolation spacer, and then a metal material such as W or the like is deposited to form respective electrode extractions 14 including the common source regions and the bit lines 13, thereby completing the manufacturing process of the three-dimensional memory device.
  • a metal material such as W or the like is deposited to form respective electrode extractions 14 including the common source regions and the bit lines 13, thereby completing the manufacturing process of the three-dimensional memory device.
  • electrons flow from the common source region 11 through the horizontal and vertical channels toward the bit line, as shown by the L-shaped dotted arrow in FIG. 10, and when erasing, the hole is lining.
  • the bottom injection is as shown by the straight dotted arrow in FIG. 10, so that due to the existence of the isolation structure, the three-dimensional memory device realizes the spatial separation of electrons and holes required during programming/erasing, and improves the erasing. Efficiency also helps to increase integration.
  • the gate dielectric layer 6 of the vertical channel region 5 is formed in an L shape; or, referring to FIG. 12, the bottom of the vertical channel region 5 is not subjected to the SEG epitaxial semiconductor region 9.
  • the process, that is, the lower selection transistor does not include the channel in the vertical direction, and only the channel in the horizontal direction exists.
  • the present invention also provides a semiconductor device comprising a three-dimensional memory device, specifically comprising: a substrate 1; an isolation structure 3 located in the substrate; and a multilayer dielectric film 4 comprising alternating layers of silicon dioxide And a gate structure layer; a vertical channel region 5, located in the multilayer dielectric film 4, the bottom of the vertical channel region 5 exposing a semiconductor material, wherein At least a portion of the straight channel region 5 directly under the substrate 1 is not isolated by the isolation structure 3; the gate dielectric layer 6, the vertical channel layer 7, the channel isolation layer 8 located in the vertical channel region 5;
  • the common source region 11 is located in the substrate 1, and is directly separated from the substrate 1 directly under the common source region 11 by the isolation structure 3; the isolation sidewalls and the respective electrode extraction terminals 14 and the bit lines 13.
  • the substrate 1 comprises an epitaxial semiconductor material layer over the substrate 1.
  • the gate dielectric layer 6 located in the vertical channel region 5 is linear (see FIG. 10) or L-shaped (see FIG. 11); therefore, in an alternative embodiment, The lower select transistor may have an epitaxial channel portion 9 or an epitaxial channel portion in the vertical channel direction (see Figure 12).
  • an isolation structure is embedded between the common source region and the substrate under it, which is capable of suppressing undesired diffusion of impurities during the common source implantation, and avoiding operation due to excessive diffusion of impurities. Invalid.
  • the three-dimensional memory device electrons flow from the common source region to the bit line, and when erasing, holes are injected from the substrate. Due to the existence of the isolation structure, the three-dimensional memory device needs to be programmed/erased. The spatial separation of electrons and holes enhances the efficiency of erasing and also improves integration.

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Abstract

一种三维存储器件及其制造方法，在共源区（11）与其下方的衬底（1）之间嵌入了隔离结构（3），其能够在进行共源区（11）注入时抑制杂质产生不期望的扩散，避免了由于杂质过度扩散而引起的操作失效。在三维存储器件编程和读取状态的时候，电子从共源区（11）向位线（13）流动，而在擦除时，空穴从衬底（1）注入，由于隔离结构（3）的存在，三维存储器件实现了编程/擦除时候需要的电子和空穴在空间上的分离，提高了擦写的效率，也有利于提高集成度。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体器件及其制造方法领域，具体而言，涉及一种三维存储器件及其制造方法。
背景技术
随着时代的进步和社会的发展，半导体存储器件在人类社会中所起到的作用越来越重要，与此同时，人们对半导体存储器性能、成本等的要求也越来越高。由于半导体技术和工艺的发展，具有垂直沟道晶体管的半导体存储器被开发出并成功用于产业之中，这样的存储器件通常会被称为三维存储器件。与之前仅仅具有平面沟道晶体管的存储器件相比，三维存储器件可以在相同芯片面积上获得更多的存储节点，从而增加存储器件的集成度，降低成本。
考虑到半导体工艺特征尺寸的持续等比例缩小，形成三维存储器件的工艺和结构面临着很多挑战。其中一个值得注意的问题是，参见图13，在图示的三维存储结构中，下选择管(BSG)21由L型SEG(选择性外延生长)晶体管构成，包括两段沟长L1和L2。高密度集成过程中需要减小栅电极的宽度，同时孔径会进一步缩小，但存储器件制备过程中的高温工艺会使得共源区22的注入存在不期望的扩散，如图13中虚线部分，从而导致在沟道孔23下面的N+区域趋向夹断，这样很难进行衬底24的空穴体擦除。
因此，需要提供一种新的三维存储器件及其制造方法，以克服现有技术的上述缺陷。
发明内容
本发明提出了一种新的三维存储器件及其制造方法，采用了在共源区与衬底之间形成隔离结构的方式，克服了现有技术中存在的共源区扩散而引起的存储操作失效的问题。
本发明提供了一种半导体器件的制造方法，用于制造三维存储器件，其包括如下步骤：
提供衬底，在所述衬底上形成图案化的第一掩模层，利用所述第一掩模层对衬底进行刻蚀；
在刻蚀暴露出的衬底之上形成隔离结构；
去除图案化的第一掩模层；
利用外延或者沉积工艺生长半导体材料以完全覆盖所述隔离结构并进行平坦化处理；
多次交替沉积二氧化硅层和栅极结构层，形成多层介质膜；
通过光刻和刻蚀工艺，在所述多层介质膜中形成垂直沟道区域，所述垂直沟道区域的底部暴露出所述通过外延或者沉积工艺生长半导体材料，其中，所述垂直沟道区域的正下方与所述衬底之间至少一部分不被所述隔离结构所隔离；
在垂直沟道区域形成栅介质层、垂直沟道层、沟道隔离层；
刻蚀所述多层介质膜至所述通过外延或者沉积工艺生长半导体材料，并进行注入，形成共源区，所述共源区的正下方与所述衬底之间至少部分被所述隔离结构所隔离；
形成隔离侧墙以及各个电极引出和位线。
根据本发明的一个方面，所述隔离结构材料为二氧化硅，其具有L形结构。
根据本发明的一个方面，采用先栅工艺，所述栅极结构层为栅极层；或者，采用后栅工艺，所述栅极结构层为伪栅极层。
根据本发明的一个方面，所述栅极介质层包括隧穿层、存储层和阻挡层，其中，隧穿层材料为SiO2，SiON，Si3N4或者高K材料形成，具有单层或多层结构；存储层材料为具有电荷俘获能力的材料，包括Si3N4，SiON，HfO2，Al2O3,AlN，具有单层或多层结构；阻挡层材料为SiO2，Al2O3，HfO2，具有单层或多层结构。
根据本发明的一个方面，所述垂直沟道层的材料为a-Si，PolySi，SiGe。
根据本发明的一个方面，所述栅极层为多晶硅，硅化物，金属或者金属的氮化物，具有多层或者单层结构。
根据本发明的一个方面，所述垂直沟道区域的形成是柱状、空心环状、空心环状与绝缘层填充的核心-外壳结构。
本发明还提供一种半导体器件，包括三维存储器件，其具体包括：
衬底；
隔离结构层，位于所述衬底之中；
多层介质膜，包括交替层叠的二氧化硅层和栅极结构层；
垂直沟道区域，位于所述多层介质膜中，所述垂直沟道区域的底部暴露出半导体材料，其中，所述垂直沟道区域的正下方与所述衬底之间至少一部分不被所述隔离结构所隔离；
位于垂直沟道区域之中的栅介质层、垂直沟道层、沟道隔离层；
共源区，位于所述衬底中，所述共源区的正下方与所述衬底之间至少部分被所述隔离结构所隔离；
隔离侧墙以及各个电极引出和位线。
根据本发明的一个方面，所述垂直沟道区域之中的所述栅介质层为直线形或者L形。
本发明的优点在于：在共源区与其下方的衬底之间嵌入了隔离结构，其能够在进行共源区注入时抑制杂质产生不期望的扩散，避免了由于杂质过度扩散而引起的操作失效。在三维存储器件编程和读状态时候，电子从共源区向位线流动，而在擦除时，空穴从衬底注入，由于隔离结构的存在，三维存储器件实现了编程/擦除时候需要的电子和空穴在空间上的分离，提高了擦写的效率，也有利于提高集成度。
附图说明
图1-12本发明提供的半导体制造方法的流程示意图以及半导体器件结构示意图；
图13现有技术示意图。
具体实施方式
以下，通过附图中示出的具体实施例来描述本发明。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
本发明提供一种半导体器件及其制造方法，具体而言，涉及一种三维存储器件及其制造方法。下面，参照说明书附图，将详细描述本发明提供的半导体器件制造方法。
首先，参见附图1，提供衬底1，在衬底1形成第一掩膜层2。半导体衬底1可以依器件用途需要而合理选择，包括但不限于体硅衬底，SOI衬底，锗衬底，锗硅(SiGe)衬底，化合物半导体材料，例如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)等。出于与传统CMOS工艺兼容的考虑，本实施例中的半导体衬底1优选地采用了体硅衬底，例如是P型硅衬底。第一掩膜层2可以采用SiON、Si3N4等材料。
接着，参见图2，对第一掩膜层2进行图案化处理，在衬底1上形成图案化的第一掩模层2，并利用该图案化的第一掩模层2对衬底1进行刻蚀。之后，参见图3，在刻蚀暴露出的衬底1之上形成隔离结构3。其中，优选地将隔离结构3形成L形，参见图3(a)；可选地，隔离结构3也可以仅形成在衬底1的水平面上呈一字形(参见图3(b))。形成隔离结构3的工艺包括但是不限于沉积二氧化硅，隔离结构3的材料应适于阻挡后续源区杂质的扩散。接着，去除第一掩膜层2。
参见图4，利用外延或者沉积工艺生长半导体材料以完全覆盖隔离结构3并进行平坦化处理。具体而言，可以通过外延的方法生长单晶硅、SiGe等，或者采用沉积的方法沉积半导体材料，比如多晶硅。此步骤形成的半导体材料用于在随后的工艺中形成共源区、水平沟道区域等等。由于其与衬底均属于半导体材料，且功能相同，因此，在图示中并未进行分界，也未对外延的半导体材料赋予新的附图标记。
接下来，参见图5，首先，多次交替沉积二氧化硅层和栅极结构层，形成多层介质膜4；接着，通过光刻和刻蚀工艺，在多层介质膜4中形成垂直沟道区域5，垂直沟道区域的底部暴露出通过外延或者沉积工艺生长半导体材料，并且，垂直沟道区域5的正下方与衬底1之间至少一部分不被隔离结构3所隔离。
多层介质膜4是由二氧化硅层和栅极结构层交替层叠而形成的叠层，且多层介质膜4在靠近衬底1的部分为二氧化硅层。如果采用先栅工艺(Gate first)，多层介质膜4中的栅极结构层即为最终存储器件的栅极层，栅极层的材料为多晶硅，硅化物，金属或者金属的氮化物，例如钨(W)，TaN等，还可以包含金属阻挡层如氮化钨(WN)，栅极层可以由这些材料形成多层或者单层结构。如果采用后栅工艺 (Gate last)，多层介质膜4中的栅极结构层为伪栅极层(Dummy gate)，例如为SiON、Si3N4层，其在随后的工艺中会被去除。在本实施例中，采用了后栅工艺，随后的工艺也是基于后栅工艺进行的，而在可选的实施例中，可以采用先栅工艺。
垂直沟道区域5的形状包括但是不限于圆柱状、条状、菱形柱状、半圆柱等柱状，或者空心环状、空心环状与绝缘层填充的核心-外壳结构，其根据具体器件需要而定。
接着，参见图6，在垂直沟道区域5中形成栅介质层6、垂直沟道层7、沟道隔离层8。
栅介质层6进一步包括隧穿层、存储层和阻挡层(均未给出附图标记)。其中，隧穿层材料为SiO2，SiON，或者HfO2，Al2O3等高K材料形成，可以具有单层或多层结构；存储层材料为具有电荷俘获能力的材料，例如Si3N4，SiON，HfO2，Al2O3,AlN等，也可具有单层或多层结构；阻挡层材料为SiO2，Al2O3，HfO2等介质材料，具有单层或多层结构。垂直沟道层7的材料为非晶Si，多晶Si，SiGe等等，沟道隔离层8为SiO2，Si3N4，空气隙(Airgap),SiGe等等。
在垂直沟道区域5中形成栅介质层6、垂直沟道层7、沟道隔离层8各层之前，可以进行选择性外延生长(SEG)的方式形成下选择晶体管的垂直方向沟道所在的外延半导体区域9。本实施例在SEG外延半导体区域9存在的基础上进行；而在可选的实施例中，可以不进行SEG，也即下选择晶体管不具有垂直方向沟道，例如可以参见图12的情形。
在形成栅介质层6、垂直沟道层7、沟道隔离层8各层之后，可以进行回刻并完成位线接触区10的填充，如非晶Si，多晶Si，SiGe或者金属等导电材料。
接着，参见图7以及图8，利用掩模刻蚀多层介质膜4至通过外延或者沉积工艺生长半导体材料，并进行注入，形成共源区11，共源区11的正下方与衬底1之间至少部分被隔离结构3所隔离。在图7中，通过刻蚀暴露出半导体材料的衬底，也即需要形成共源区11的位置；同时，在本实施例中，由于采用后栅工艺，在刻蚀工艺后，去除多个伪栅极层，形成用于容纳之后的栅极层的空间。
参见图8，在进行共源区11注入时，由于本实施例中衬底采用 了P型材料，共源区11的杂质类型为N+型。本发明在共源区11与其下方的衬底之间嵌入了隔离结构3，尤其是L形的隔离结构3，在进行共源区注入时，能够抑制杂质产生不期望的扩散，更好地将杂质控制在共源区，避免了由于杂质过度扩散而引起的操作失效，例如使得空穴体擦除失效。这样，隔离结构3实现了N型区域和P型区域的空间分离，具体到本实施例来说，是P型衬底与N+型共源区的分离。
在本实施例的后栅工艺中，参见图9，在形成共源区之后，进行栅电极的填充，例如采用TiN、W等，形成包括下选择晶体管栅极12在内的各个栅电极。在进行栅电极填充之前，优先形成下选择晶体管栅极12对应其垂直方向沟道的栅介质层，例如采用氧化工艺。在可选的实施例中，也可以在去除伪栅极层之前，首先去除多层介质膜4中的二氧化硅材料，在去除伪栅极层之后，整个栅介质层6或者部分的栅介质层6可以在去除伪栅极层之后通过沉积的方法填充，然后填充栅电极。后栅工艺中的栅电极和栅介质层的形成可以根据具体需求，设置在刻蚀出共源区之后的工艺流程中的合适位置。
参见图10，沉积绝缘介质形成隔离侧墙，随后沉积金属材料，如W等，形成包括共源区的各个电极引出14以及位线13，从而完成了三维存储器件的制造流程。在三维存储器件编程和读状态时候，电子从共源区11，经过水平方向和垂直方向沟道向位线流动，如图10中的L形虚线箭头，而在擦除时，空穴从衬底注入，如图10中的直线形虚线箭头所示，这样，由于隔离结构的存在，三维存储器件实现了编程/擦除时候需要的电子和空穴在空间上的分离，提高了擦写的效率，也有利于提高集成度。
在可选的实施例中，参见图11，垂直沟道区域5的栅介质层6被形成为L形；或者，参见图12，垂直沟道区域5的底部并不进行SEG外延半导体区域9的工艺，也即下选择晶体管不包括垂直方向的沟道，仅存在水平方向的沟道。
相应地，本发明还提供一种半导体器件，包括三维存储器件，具体包括：衬底1；隔离结构3，位于所述衬底之中；多层介质膜4，包括交替层叠的二氧化硅层和栅极结构层；垂直沟道区域5，位于多层介质膜4中，垂直沟道区域5的底部暴露出半导体材料，其中，垂 直沟道区域5的正下方与衬底1之间至少一部分不被隔离结构3所隔离；位于垂直沟道区域5之中的栅介质层6、垂直沟道层7、沟道隔离层8；共源区11，位于衬底1中，共源区11的正下方与衬底1之间至少部分被隔离结构3所隔离；隔离侧墙以及各个电极引出14和位线13。
其中，衬底1包括位于衬底1之上的外延半导体材料层。
在可选的实施例之中，位于垂直沟道区域5之中的栅介质层6为直线形(参见图10)或者L形(参见图11)；因此，在可选的实施例之中，下选择晶体管在垂直沟道方向，可以有外延的沟道部分9，也可以没有外延的沟道部分(参见图12)。
以上，本发明的半导体器件及其制造方法已得到说明。在本发明的方法中，在共源区与其下方的衬底之间嵌入了隔离结构，其能够在进行共源区注入时抑制杂质产生不期望的扩散，避免了由于杂质过度扩散而引起的操作失效。在三维存储器件编程和读状态时候，电子从共源区向位线流动，而在擦除时，空穴从衬底注入，由于隔离结构的存在，三维存储器件实现了编程/擦除时候需要的电子和空穴在空间上的分离，提高了擦写的效率，也有利于提高集成度。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对器件结构和/或工艺流程做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (9)

  1. 一种半导体器件制造方法，用于制造三维存储器件，其特征在于包括如下步骤：
    提供衬底，在所述衬底上形成图案化的第一掩模层，利用所述第一掩模层对衬底进行刻蚀；
    在刻蚀暴露出的衬底之上形成隔离结构；
    去除图案化的第一掩模层；
    利用外延或者沉积工艺生长半导体材料以完全覆盖所述隔离结构并进行平坦化处理；
    多次交替沉积二氧化硅层和栅极结构层，形成多层介质膜；
    通过光刻和刻蚀工艺，在所述多层介质膜中形成垂直沟道区域，所述垂直沟道区域的底部暴露出所述通过外延或者沉积工艺生长半导体材料，其中，所述垂直沟道区域的正下方与所述衬底之间至少一部分不被所述隔离结构所隔离；
    在垂直沟道区域形成栅介质层、垂直沟道层、沟道隔离层；
    刻蚀所述多层介质膜至所述通过外延或者沉积工艺生长半导体材料，并进行注入，形成共源区，所述共源区的正下方与所述衬底之间至少部分被所述隔离结构所隔离；
    形成隔离侧墙以及各个电极引出和位线。
  2. 根据权利要求1所述的方法，其特征在于，所述隔离结构材料为二氧化硅，其具有L形结构。
  3. 根据权利要求1所述的方法，其特征在于，采用先栅工艺，所述栅极结构层为栅极层；或者，采用后栅工艺，所述栅极结构层为伪栅极层。
  4. 根据权利要求1所述的方法，其特征在于，所述栅极介质层包括隧穿层、存储层和阻挡层，其中，隧穿层材料为SiO2、SiON、Si3N4或者高K材料形成，具有单层或多层结构；存储层材料为具有电荷俘获能力的材料，包括Si3N4，SiON，HfO2，Al2O3,AlN，具有单层或多层结构；阻挡层材料为SiO2，Al2O3，HfO2，具有单层或多层结构。
  5. 根据权利要求1所述的方法，其特征在于，所述垂直沟道层的材料为a-Si，PolySi，SiGe。
  6. 根据权利要求3所述的方法，其特征在于，所述栅极层为多晶硅，硅化物，金属或者金属的氮化物，具有多层或者单层结构。
  7. 根据权利要求1所述的方法，其特征在于，所述垂直沟道区域的形成是柱状、空心环状、空心环状与绝缘层填充的核心-外壳结构。
  8. 一种半导体器件，包括三维存储器件，其特征在于具体包括：
    衬底；
    隔离结构层，位于所述衬底之中；
    多层介质膜，包括交替层叠的二氧化硅层和栅极结构层；
    垂直沟道区域，位于所述多层介质膜中，所述垂直沟道区域的底部暴露出半导体材料，其中，所述垂直沟道区域的正下方与所述衬底之间至少一部分不被所述隔离结构所隔离；
    位于垂直沟道区域之中的栅介质层、垂直沟道层、沟道隔离层；
    共源区，位于所述衬底中，所述共源区的正下方与所述衬底之间至少部分被所述隔离结构所隔离；
    隔离侧墙以及各个电极的引出。
  9. 根据权利要求8所述的器件，其特征在于，所述垂直沟道区域之中的所述栅介质层为直线形或者L形。
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