WO2017035906A1 - Cmos goa 电路 - Google Patents

Cmos goa 电路 Download PDF

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Publication number
WO2017035906A1
WO2017035906A1 PCT/CN2015/091642 CN2015091642W WO2017035906A1 WO 2017035906 A1 WO2017035906 A1 WO 2017035906A1 CN 2015091642 W CN2015091642 W CN 2015091642W WO 2017035906 A1 WO2017035906 A1 WO 2017035906A1
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Prior art keywords
type tft
signal
gate
electrically connected
constant voltage
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PCT/CN2015/091642
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English (en)
French (fr)
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赵莽
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/786,167 priority Critical patent/US9830876B2/en
Publication of WO2017035906A1 publication Critical patent/WO2017035906A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a CMOS GOA circuit.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • the driving method has the advantages of reducing production cost and realizing the narrow frame design of the panel, and is used for various displays.
  • the GOA circuit has two basic functions: the first is to output the scan drive signal, drive the gate line in the panel, open the TFT in the display area to charge the pixel; the second is the shift register function, when the Nth scan After the drive signal output is completed, the output of the (N+1)th scan drive signal is performed by clock control, and is sequentially transmitted.
  • LTPS TFT liquid crystal displays are also receiving more and more attention. Since the silicon crystal arrangement of LTPS is more ordered than amorphous silicon, LTPS semiconductor has ultra-high carrier mobility, and the liquid crystal display using LTPS TFT has the advantages of high resolution, fast response speed, high brightness, and high aperture ratio. The peripheral integrated circuit of the LTPS TFT liquid crystal display has also become the focus of display technology.
  • Figure 1 shows an existing CMOS GOA circuit including a plurality of cascaded GOA units.
  • the existing CMOS GOA circuit has various levels. All of the scan drive signals are simultaneously raised to the high level (All Gate On) function.
  • N be a positive integer
  • the Nth stage GOA unit includes an input control module 100, a latch module 300, a signal processing module 400, and an output buffer module 500.
  • the input control module 100 accesses the level transmission signal Q(N-1) of the upper level GOA unit, the first clock signal CK1, the first inverted clock signal XCK1, the constant voltage high potential signal VGH, and the constant voltage low potential.
  • the signal VGL, the signal P(N) opposite to the potential of the level signal Q(N-1) of the GOA unit of the previous stage is input to the latch module 300;
  • the latch module 300 includes an inverter F, which inverts the signal P(N) to obtain the level-transmitted signal Q(N) of the N-th stage GOA unit, and the latch module 300 locks the level-transmitted signal Q(N). Save
  • the signal processing module 400 accesses the level transmission signal Q(N), the second clock signal CK2, and the constant voltage is high.
  • the signal processing module 400 is configured to perform NAND logic processing on the second clock signal CK2 and the level transmission signal Q(N) to generate the Nth stage
  • the scan driving signal G(N) of the GOA unit performing the logical processing result and the global signal Gas on the second clock signal CK2 and the level transmission signal Q(N), or performing a non-logic processing to realize the global signal Gas control level scan drive
  • the signals all rise to a high potential at the same time;
  • the output buffer module 500 is electrically connected to the signal processing module 400 for increasing the driving capability of the scan driving signal G(N) and reducing the RC loading during signal transmission.
  • each level of the GOA unit of the existing CMOS GOA circuit further includes a reset module 200.
  • the reset module 200 includes a P-type TFT, the gate of the P-type TFT is connected to the reset signal Reset, and the source is connected to the constant-voltage high-potential signal VGH. The drain is connected to the input terminal of the inverter F in the latch module 300.
  • the reset module 200 is separately provided to improve the performance of the circuit, the additional components, traces, and signals increase the area of the GOA circuit, which increases the signal complexity and is not conducive to the design of the narrow bezel.
  • the area of the GOA circuit simplifies the complexity of the signal and facilitates the design of the narrow bezel panel.
  • the present invention provides a CMOS GOA circuit comprising a plurality of cascaded GOA units
  • N be a positive integer
  • the Nth stage GOA unit includes: an input control module, a latch module electrically connected to the input control module, a signal processing module electrically connected to the latch module, and an output buffer module of the electrical connection signal processing module, And electrically connecting the storage capacitor of the latch module and the signal processing module;
  • the input control module accesses a level transmission signal, a first clock signal, a first inverted clock signal, a constant voltage high potential signal, and a constant voltage low potential signal of the upper N-1th GOA unit, and is used for
  • the level-transmitting signal of the N-1th GOA unit is inverted to obtain an inverted-stage signal, and the inverted-stage signal is input to the latch module;
  • the latch module includes a NOR gate, the first input terminal of the NOR gate inputs an inverted phase transmission signal, the second input terminal inputs a global signal, and the output of the NOR gate outputs a level transmission signal.
  • the latch module is configured to latch the level signal;
  • the signal processing module accesses the level transmission signal, the second clock signal, the constant voltage high potential signal, the constant voltage low potential signal, and the global signal, and is used for performing NAND processing on the second clock signal and the level transmission signal, Generating a scan driving signal of the Nth stage GOA unit; performing a logical processing result on the second clock signal and the level transmission signal and performing a non-logic processing on the global signal, so as to realize global signal control, and all the scan driving signals are simultaneously raised to high Potential
  • the output buffer module includes an odd number of first inverters connected in series for sequentially outputting a scan driving signal and increasing a driving capability of the scan driving signal;
  • One end of the storage capacitor is electrically connected to the level transmission signal, and the other end is grounded to store the potential of the level transmission signal;
  • the global signal comprises a single pulse, and when it is at a high potential, all the scanning drive signals of each stage are controlled to rise to a high potential at the same time, and the potential of the signal transmitted by the NAND gates is controlled at a high level, and signals are transmitted to each level. Perform a clear reset.
  • the input control module includes at least a first P-type TFT, a second P-type TFT, a third N-type TFT, and a fourth N-type TFT connected in series; the gate of the first P-type TFT is connected to the first anti- The phase clock signal and the source are connected to the constant voltage high potential signal; the gates of the second P-type TFT and the third N-type TFT are both connected to the level-transmitting signal of the upper-stage N-1th GOA unit; The second P-type TFT and the drain of the third N-type TFT are connected to each other to output an inverted phase-transmitting signal; the gate of the fourth N-type TFT is connected to the first clock signal, and the source is connected to the constant-voltage low-potential signal ;
  • the latch module further includes a fifth P-type TFT, a sixth P-type TFT, a seventh N-type TFT, and an eighth N-type TFT connected in series; the gate of the fifth P-type TFT is connected to the first clock The signal and the source are connected to the constant voltage high potential signal; the gates of the sixth P-type TFT and the seventh N-type TFT are both connected to the level transmission signal; and the leakage of the sixth P-type TFT and the seventh N-type TFT The poles are connected to each other and electrically connected to the drains of the second P-type TFT and the third N-type TFT; the gate of the eighth N-type TFT is connected to the first inverted clock signal, and the source is connected to the constant voltage Low potential signal
  • the signal processing module includes: a ninth P-type TFT, a gate of the ninth P-type TFT is connected to a global signal, a source is connected to a constant voltage high potential signal; a tenth P-type TFT, the tenth P-type The gate of the TFT is connected to the pass signal, the source is electrically connected to the drain of the ninth P-type TFT, the drain is electrically connected to the node, and the eleventh P-type TFT is connected to the gate of the eleventh P-type TFT.
  • the pole is connected to the second clock signal
  • the source is electrically connected to the drain of the ninth P-type TFT
  • the drain is electrically connected to the node
  • the twelfth N-type TFT is connected to the gate of the twelfth N-type TFT Inductive signal
  • the drain is electrically connected to the node
  • the thirteenth N-type TFT, the gate of the thirteenth N-type TFT is connected to the second clock signal
  • the drain Electrode is electrically connected to a source of the twelfth N-type TFT, a source is connected to a constant voltage low potential signal
  • a fourteenth N-type TFT is connected to a global signal by a gate of the fourteenth N-type TFT, The source is connected to a constant voltage low potential signal, and the drain is electrically connected to the node.
  • the input control module further includes a second inverter, wherein the first inverted clock signal is obtained by inverting the first clock signal via the second inverter.
  • the output buffer module includes three first inverters connected in series in series, and an input end of the first inverter closest to the signal processing module is electrically connected to the node, and is farthest from the first inverter of the signal processing module.
  • the output outputs a scan drive signal.
  • the first inverter is composed of a fifteenth P-type TFT connected in series with a sixteenth N-type TFT, and the fifteenth P-type TFT and the gate of the sixteenth N-type TFT are electrically connected to each other to constitute the first An input end of an inverter, a source of the fifteenth P-type TFT is connected to a constant voltage high potential signal, and a source of the sixteenth N-type TFT is connected to a constant voltage low potential signal, the tenth
  • the fifth P-type TFT and the drain of the sixteenth N-type TFT are electrically connected to each other to form an output end of the first inverter; the output end of the previous first inverter is electrically connected to the first inverter Input.
  • the second inverter is composed of a seventeenth P-type TFT connected in series with an eighteenth N-type TFT, and the seventeenth P-type TFT and the eighteenth-type TFT are electrically connected to each other to form the first inverter.
  • the drains of the seven P-type TFTs and the drains of the eighteenth-type TFTs are electrically connected to each other to form an output end of the second inverter; the input end of the second inverter is connected to the first clock signal, and the output end is output An inverted clock signal.
  • the NOR gate includes a nineteenth P-type TFT, a twentieth P-type TFT, a twenty-first N-type TFT, and a twenty-second N-type TFT; the twentieth P-type TFT and the twenty-first The gates of the N-type TFTs are electrically connected to each other to form a first input end of the NOR gate; the gates of the 19th P-type TFT and the 22nd N-type TFT are electrically connected to each other to form the NOR gate a second input end; a source of the nineteenth P-type TFT is connected to a constant voltage high potential signal, and a drain is electrically connected to a source of the twentieth P-type TFT; the twenty-first N-type TFT and the second The sources of the twenty-two N-type TFTs are all connected to a constant voltage low potential signal; the drains of the twentieth P-type TFT, the twenty-first N-type TFT, and the twenty-second N-type TFT are electrically connected to each other Form the output of the NOR gate
  • the gates of the second P-type TFT and the third N-type TFT are all connected to a circuit enable signal.
  • the present invention also provides a CMOS GOA circuit comprising a plurality of cascaded GOA units;
  • N be a positive integer
  • the Nth stage GOA unit includes: an input control module, a latch module electrically connected to the input control module, a signal processing module electrically connected to the latch module, and an output buffer module of the electrical connection signal processing module, And electrically connecting the latch module and the signal processing module storage capacitance;
  • the input control module accesses a level transmission signal, a first clock signal, a first inverted clock signal, a constant voltage high potential signal, and a constant voltage low potential signal of the upper N-1th GOA unit, and is used for
  • the level-transmitting signal of the N-1th GOA unit is inverted to obtain an inverted-stage signal, and the inverted-stage signal is input to the latch module;
  • the latch module includes a NOR gate, the first input terminal of the NOR gate inputs an inverted phase transmission signal, the second input terminal inputs a global signal, and the output of the NOR gate outputs a level transmission signal.
  • the latch module is configured to latch the level signal;
  • the signal processing module accesses the level transmission signal, the second clock signal, the constant voltage high potential signal, the constant voltage low potential signal, and the global signal, and is used for performing NAND processing on the second clock signal and the level transmission signal, Generating a scan driving signal of the Nth stage GOA unit; performing a logical processing result on the second clock signal and the level transmission signal and performing a non-logic processing on the global signal, so as to realize global signal control, and all the scan driving signals are simultaneously raised to high Potential
  • the output buffer module includes an odd number of first inverters connected in series for sequentially outputting a scan driving signal and increasing a driving capability of the scan driving signal;
  • One end of the storage capacitor is electrically connected to the level transmission signal, and the other end is grounded to store the potential of the level transmission signal;
  • the global signal comprises a single pulse, and when it is at a high potential, all the scanning drive signals of each stage are controlled to rise to a high potential at the same time, and the potential of the signal transmitted by the NAND gates is controlled at a high level, and signals are transmitted to each level. Perform a zero reset;
  • the input control module includes at least a first P-type TFT, a second P-type TFT, a third N-type TFT, and a fourth N-type TFT connected in series; a gate of the first P-type TFT is connected to the gate An inverted clock signal, the source is connected to the constant voltage high potential signal; the gates of the second P-type TFT and the third N-type TFT are both connected to the level-transmitting signal of the upper-stage N-1th GOA unit; The second P-type TFT and the drain of the third N-type TFT are connected to each other to output an inverted phase-transmitting signal; the gate of the fourth N-type TFT is connected to the first clock signal, and the source is connected to the low-voltage constant Potential signal
  • the latch module further includes a fifth P-type TFT, a sixth P-type TFT, a seventh N-type TFT, and an eighth N-type TFT connected in series; the gate of the fifth P-type TFT is connected to the first clock The signal and the source are connected to the constant voltage high potential signal; the gates of the sixth P-type TFT and the seventh N-type TFT are both connected to the level transmission signal; and the leakage of the sixth P-type TFT and the seventh N-type TFT The poles are connected to each other and electrically connected to the drains of the second P-type TFT and the third N-type TFT; the gate of the eighth N-type TFT is connected to the first inverted clock signal, and the source is connected to the constant voltage Low potential signal
  • the signal processing module includes: a ninth P-type TFT, a gate of the ninth P-type TFT is connected to a global signal, a source is connected to a constant voltage high potential signal; a tenth P-type TFT, the tenth P-type TFT The gate is connected to the pass signal, the source is electrically connected to the drain of the ninth P-type TFT, the drain is electrically connected to the node, and the eleventh P-type TFT is the gate of the eleventh P-type TFT
  • the second clock signal is connected, the source is electrically connected to the drain of the ninth P-type TFT, the drain is electrically connected to the node, and the twelfth N-type TFT is connected to the gate of the twelfth N-type TFT a stepping signal, the drain is electrically connected to the node; the thirteenth N-type TFT, the gate of the thirteenth N-type TFT is connected to the second clock signal, and the drain is electrically connected to the twelfth N
  • the input control module further includes a second inverter, wherein the first inverted clock signal is obtained by inverting the first clock signal via the second inverter;
  • the output buffer module includes three first inverters connected in series in series, and an input end of the first inverter closest to the signal processing module is electrically connected to the node, and is farthest from the first inversion of the signal processing module.
  • the output of the device outputs a scan driving signal
  • the NOR gate includes a nineteenth P-type TFT, a twentieth P-type TFT, a twenty-first N-type TFT, and a twenty-second N-type TFT; the twentieth P-type TFT and the second The gates of the eleven N-type TFTs are electrically connected to each other to form a first input end of the NOR gate; the gates of the nineteenth P-type TFT and the twenty-second N-type TFT are electrically connected to each other to form the NOR a second input end of the gate; a source of the nineteenth P-type TFT is connected to a constant voltage high potential signal, and a drain is electrically connected to a source of the twentieth P-type TFT; the twenty-first N-type TFT And a source of the twenty-second N-type TFT is connected to the constant voltage low potential signal; the drains of the twentieth P-type TFT, the twenty-first N-type TFT, and the twenty-second N-type TFT are electrically connected to each other
  • the sexual connection constitutes the output of the
  • the gates of the second P-type TFT and the third N-type TFT are all connected to the circuit enable signal.
  • the present invention provides a CMOS GOA circuit in which a NOR gate is provided in a latch module, and two input terminals of the NOR gate are respectively input to an inverted phase transmission signal and a global signal, and a global signal is used.
  • FIG. 1 is a circuit diagram of a conventional CMOS GOA circuit
  • FIG. 2 is a circuit diagram of a CMOS GOA circuit of the present invention
  • FIG. 3 is a circuit diagram of a first stage GOA unit of a CMOS GOA circuit of the present invention
  • FIG. 5 is a schematic diagram showing a specific circuit structure of three first inverters connected in series in an output buffer module of a CMOS GOA circuit according to the present invention
  • FIG. 6 is a schematic diagram showing a specific circuit structure of a second inverter in an input control module of a CMOS GOA circuit according to the present invention
  • FIG. 7 is a schematic structural diagram of a specific circuit of a NOR gate in a CMOS GOA circuit of the present invention.
  • the present invention provides a CMOS GOA circuit including a plurality of cascaded GOA units, each of which uses a plurality of N-type TFTs and a plurality of P-type TFTs, and each TFT is It is a low temperature polysilicon semiconductor thin film transistor.
  • N be a positive integer.
  • the Nth stage GOA unit includes: an input control module 1, a latch module 3 electrically connected to the input control module 1, a signal processing module 4 electrically connected to the latch module 3, and an electrical connection signal processing module.
  • the output buffer module 5 of the 4 and the storage capacitor 7 of the signal processing module 4 are electrically connected to the latch module 3.
  • the input control module 1 accesses the level transmission signal Q(N-1) of the first-stage N-1th GOA unit, the first clock signal CK1, the first inverted clock signal XCK1, the constant voltage high potential signal VGH, And a constant voltage low potential signal VGL for inverting the level transmission signal Q(N-1) of the N-1th GOA unit to obtain an inverted phase transmission signal XQ(N), and transmitting the inverted phase signal
  • the input control module 1 includes a first P-type TFT T1, a second P-type TFT T2, a third N-type TFT T3, and a fourth N-type TFT T4 connected in series in series: the first P-type TFT T1
  • the gate is connected to the first inverted clock signal XCK1, and the source is connected to the constant voltage high potential signal VGH;
  • the gates of the second P-type TFT T2 and the third N-type TFT T3 are connected to the upper level Nth -1 level GOA unit's level pass signal Q(N-1);
  • the second type P type TFT T2 and The drains of the three N-type TFTs T3 are connected to each other, and the inverted phase-level signal XQ(N) is output;
  • the gate of the fourth N-type TFT T4 is connected to the first clock signal CK1, and the source is connected to the constant-voltage low-potential signal.
  • the input control module 1 further includes a second inverter F2, and the first inverted clock signal XCK1 is inverted by the first clock signal CK1 via the second inverter F2.
  • the specific circuit structure of the second inverter F2 is as shown in FIG. 6, and is composed of a seventeenth P-type TFT T17 connected in series with an eighteenth N-type TFT T18, and the seventeenth P-type TFT T17
  • the input terminal K' of the second inverter F2 is electrically connected to the gate of the eighteenth N-type TFT T18, and the source of the seventeenth P-type TFT T17 is connected to the constant voltage high potential signal VGH.
  • the source of the eighteenth N-type TFT T18 is connected to the constant voltage low potential signal VGL, and the seventeenth P-type TFT T17 and the drain of the eighteenth N-type TFT T18 are electrically connected to each other to form the second anti- The output terminal L' of the phase inverter F2; the input terminal K' of the second inverter F2 is connected to the first clock signal CK1, and the output terminal L' outputs the first inverted clock signal XCK1.
  • the first inverted clock signal XCK1 outputted by the output terminal L' is low, and when the second phase is inverted
  • the first clock signal CK1 connected to the input terminal K' of the device F2 is at a low potential
  • the first inverted clock signal XCK1 outputted from the output terminal L' is at a high potential.
  • the first P-type TFT T1, the second P-type TFT T2, the third N-type TFT T3, and the fourth N-type TFT T4 connected in series are normally only when the first clock signal CK1 is high.
  • the third N-type TFT T3 is turned on with the fourth N-type TFT T4, and the third N-type TFT is turned on.
  • the drain of T3 outputs a low-level inverted-stage signal XQ(N); if the level-transmitted signal Q(N-1) of the upper-stage N-1th GOA unit is low, the first P-type TFT T1
  • the second P-type TFT T2 is turned on, and a high-potential inverted-stage signal XQ(N) is outputted from the drain of the second P-type TFT T2.
  • the latch module 3 includes a NOR gate Y.
  • the first input terminal A of the NOR gate Y inputs an inverted phase transmission signal XQ(N), and the second input terminal B inputs a global signal Gas.
  • the output D of the gate Y outputs a level-transmitted signal Q(N).
  • the latch module 3 further includes a fifth P-type TFT T5, a sixth P-type TFT T6, a seventh N-type TFT T7, and an eighth N-type TFT T8: the gate of the fifth P-type TFT T5 connected in series The pole is connected to the first clock signal CK1, the source is connected to the constant voltage high potential signal VGH; the gates of the sixth P-type TFT T6 and the seventh N-type TFT T7 are connected to the level-transmitting signal Q(N); The sixth P-type TFT T6 and the drain of the seventh N-type TFT T7 are connected to each other, and are electrically connected to the drains of the second P-type TFT T2 and the third N-type TFT T3; the eighth N-type TFT The gate of T8 is connected to the first inverted clock signal XCK1, and the source is connected to the constant voltage low potential signal VGL.
  • the specific circuit structure of the NOR gate Y is as shown in FIG. 7, and includes a nineteenth P-type TFT T19, a twentieth P-type TFT T20, a twenty-first N-type TFT T21, and a twenty-second N-type TFT T22; gate of the twentieth P-type TFT T20 and the twenty-first N-type TFT T21
  • the first input terminal A of the NAND gate Y is electrically connected to each other;
  • the gates of the nineteenth P-type TFT T19 and the twenty-second N-type TFT T22 are electrically connected to each other to form the first or the second gate Y a second input terminal B;
  • a source of the nineteenth P-type TFT T19 is connected to a constant voltage high potential signal VGH, and a drain is electrically connected to a source of the twentieth P-type TFT T20;
  • the source of the TFT T21 and the twenty-second N-type TFT T22 are both connected to the constant voltage low potential signal VGL;
  • the output terminal D When at least one of the inverted phase pass signal XQ(N) input to the NOR gate Y and the global signal Gas is at a high potential, the output terminal D outputs a low-level pass signal Q(N).
  • the fifth P-type TFT T5, the sixth P-type TFT T6, the seventh N-type TFT T7, and the eighth N-type TFT T8 connected in series are normally only when the first clock signal CK1 is low.
  • the level transfer signal Q(N) is high, the seventh N-type TFT T7 and the eighth N-type TFT T8 are turned on, and the drain of the seventh N-type TFT T7 outputs a low potential, that is, the inverted stage is maintained.
  • the signal XQ(N) is low, and when the global signal Gas is low, the gradation signal Q(N) of the NAND gate Y output is still high, and the latching of the level signal Q(N) is realized. If the level transfer signal Q(N) is low, the fifth P-type TFT T5 and the sixth P-type TFT T6 are turned on, and the drain of the sixth P-type TFT T6 outputs a high potential, that is, the inverted-stage transmission is maintained. The signal XQ(N) is high, or the gate signal Q(N) of the non-gate Y output is still low, and the latching of the level signal Q(N) is realized.
  • the signal processing module 4 accesses the level transmission signal Q(N), the second clock signal CK2, the constant voltage high potential signal VGH, the constant voltage low potential signal VGL, and the global signal Gas for the second clock signal CK2 and
  • the gradation signal Q(N) is subjected to NAND processing to generate the scan driving signal G(N) of the Nth stage GOA unit; the result of logical processing of the second clock signal CK2 and the level transmission signal Q(N) And global signal Gas or non-logic processing, the global signal Gas control level scan drive signal G (N) all simultaneously rise to a high potential.
  • the signal processing module 4 includes: a ninth P-type TFT T9, a gate of the ninth P-type TFT T9 is connected to the global signal Gas, and a source is connected to the constant-voltage high-potential signal VGH;
  • the gate of the tenth P-type TFT T10 is connected to the pass signal Q(N)
  • the source is electrically connected to the drain of the ninth P-type TFT T9
  • the drain is electrically connected to the node A (N).
  • the eleventh P-type TFT T11, the gate of the eleventh P-type TFT T11 is connected to the second clock signal CK2, and the source is electrically connected to the drain of the ninth P-type TFT T9, and the drain is electrically Connected to node A (N);
  • twelfth N-type TFT T12, the gate of the twelfth N-type TFT T12 is connected to the pass signal Q (N), and the drain is electrically connected to the node A (N);
  • a thirteenth N-type TFT T13, the gate of the thirteenth N-type TFT T13 is connected to the second clock signal CK2, and the drain is electrically connected to the source of the twelfth N-type TFT T12, and the source is connected a constant voltage low potential signal VGL;
  • a fourteenth N-type TFT T14, the fourteenth N-type TFT T14 The gate is connected to the global signal Gas, the source is connected to the constant voltage low potential signal VGL, and the
  • the twelfth N-type TFT T12 and the thirteenth N-type TFT T13 are guided.
  • the potential of the node A(N) is low; and when the second clock signal CK2 and the level signal Q(N) are both low, the ninth P-type TFT T9, the tenth P-type TFT T10, and The eleventh P-type TFT T11 is turned on, and the potential of the node A(N) is high.
  • the fourteenth N-type TFT T14 is turned on regardless of the potential of the second clock signal CK2 and the level-transmitted signal Q(N), and the potential of the node A(N) is low.
  • the output buffer module 5 includes an odd number of first inverters F1 connected in series for outputting the scan driving signal G(N) and increasing the driving capability of the scan driving signal G(N).
  • the output buffer module 5 includes three first inverters F1 connected in series in series.
  • the first inverter F1 is connected in series by a fifteenth P-type TFT T15.
  • the N-type TFT T16 is configured.
  • the fifteenth P-type TFT T15 and the gate of the sixteenth-type TFT T16 are electrically connected to each other to form an input terminal K of the first inverter F1.
  • the source of the TFT T15 is connected to the constant voltage high potential signal VGH
  • the source of the sixteenth N-type TFT T16 is connected to the constant voltage low potential signal VGL
  • the drains of the TFTs T16 are electrically connected to each other to constitute an output terminal L of the first inverter F1.
  • the input end of the first inverter F1 closest to the signal processing module 4 is electrically connected to the node A(N), and the output end L of the first inverter F1 farthest from the signal processing module 4 outputs the scan driving signal G ( N), the output terminal L of the previous first inverter F1 is electrically connected to the input terminal K of the first inverter F1.
  • the scan driving signal G(N) When the potential of the node A(N) is low, the scan driving signal G(N) is high through the reverse action of the three first inverters F1 connected in series in the output buffer module 5; when the node A ( When the potential of N) is high, the scan drive signal G(N) is at a low potential by the reverse action of the three first inverters F1 connected in series in the output buffer module 5.
  • One end of the storage capacitor 7 is electrically connected to the level transmission signal Q(N), and the other end is grounded for storing the potential of the level transmission signal Q(N).
  • the global signal Gas includes a single pulse, and the single pulse is triggered before the GOA circuit operates normally.
  • the global signal Gas is at a high potential, the fourteenth N-type TFT T14 in each level of the GOA unit circuit is turned on, and the potential of the node A(N) in each level of the GOA unit circuit is low, and the GOA is in various stages.
  • the control NAND gate Y pulls down the potential of the signal Q(N) of each level, and resets the signal Q(N) of each level, and at this time, the storage capacitor 7 has a low potential of the level signal Q(N).
  • the global signal Gas is turned to a low potential, and since the storage capacitor 7 stores the low potential, the ninth P-type TFT T9 and the tenth P-type TFT T10 are turned on.
  • the potential of the node A(N) is converted to a high potential, and the driving signals G(N) of the respective stages are scanned by the reverse action of the three first inverters F1 connected in series in the output buffer module 5 in the GOA unit circuits of each stage. All of them are simultaneously turned into a low potential, avoiding the problem that the scan driving signal continues. After that, the CMOS GOA circuit works normally.
  • the above CMOS GOA circuit does not need to separately set the reset module, which eliminates additional components, routing, and reset signals, reduces the area of the GOA circuit, simplifies the complexity of the signal, and is advantageous for narrowing.
  • the design of the bezel panel improves the stability of the GOA circuit.
  • the first clock signal CK1 and the second clock signal CK2 may be in a high-resistance state, that is, the first clock signal CK1 and the second
  • the potential of the clock signal CK2 is not limited to reduce the standby power consumption of the entire circuit.
  • the first clock signal CK1 is one pulse width ahead of the second clock signal CK2.
  • the gates of the second P-type TFT T2 and the third N-type TFT T3 are both connected to the circuit enable signal STV.
  • the circuit enable signal STV is at the same high level as the first clock signal CK1
  • the third N-type TFT T3 and the fourth N-type TFT T4 are turned on, and the third The drain of the N-type TFT T3 outputs a low-potential inverted phase signal XQ(1);
  • the NAND gate Y output of the latch module 3 is high-level, and at the first clock
  • the second N-type TFT T12 is turned on with the thirteenth N-type TFT T13 as the second clock signal CK2 is at a high potential
  • the potential of the node A(1) is low; the scan driving signal G(1) is high through the reverse
  • the CMOS GOA circuit of the present invention sets a NOR gate in the latch module, and inputs the two input terminals of the NOR gate to the inverted phase transmission signal and the global signal respectively, when the global signal is high.
  • the control scan signals of all levels are simultaneously raised to a high potential, and the potentials of the signals transmitted by the NAND gates are controlled at the same time, and the signals transmitted at all levels are reset and reset, compared with the prior art,
  • the reset module needs to be separately set, eliminating the need for additional components, routing, and reset signals, reducing the area of the GOA circuit, simplifying the complexity of the signal, and facilitating the design of the narrow bezel panel.
  • the storage capacitors in each When the level scan drive signals are all raised to a high potential at the same time the low potential of the level transfer signal is stored, which improves the stability of the GOA circuit.

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Abstract

一种CMOS GOA电路，在锁存模块(3)中设置或非门(Y)，将或非门(Y)的两输入端分别输入反相级传信号(XQ(N))与全局信号(Gas)，当全局信号(Gas)为高电位时，控制各级扫描驱动信号(G(N))全部同时上升为高电位，同时控制所述或非门(Y)拉低各级级传信号(Q(N))的电位，对各级级传信号(Q(N))进行清零复位，与现有技术相比，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积，简化了信号的复杂度，利于窄边框面板的设计；此外，通过设置存储电容(7)在各级扫描驱动信号(G(N))全部同时上升为高电位时对级传信号(Q(N))的低电位进行存储，提高了GOA电路的稳定性。

Description

CMOS GOA电路 技术领域
本发明涉及显示技术领域，尤其涉及一种CMOS GOA电路。
背景技术
GOA(Gate Driver on Array)技术即阵列基板行驱动技术，是利用薄膜晶体管(Thin Film Transistor，TFT)液晶显示器阵列制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示器所使用。GOA电路具有两项基本功能：第一是输出扫描驱动信号，驱动面板内的栅极线，打开显示区内的TFT，以对像素进行充电；第二是移位寄存功能，当第N个扫描驱动信号输出完成后，通过时钟控制进行第N+1个扫描驱动信号的输出，并依次传递下去。
随着低温多晶硅(Low Temperature Poly-Silicon，LTPS)半导体薄膜晶体管的发展，LTPS TFT液晶显示器也越来越受关注。由于LTPS的硅结晶排列较非晶硅有次序，LTPS半导体具有超高的载流子迁移率，采用LTPS TFT的液晶显示器具有高分辨率、反应速度快、高亮度、高开口率等优点，相应的，LTPS TFT液晶显示器的面板周边集成电路也成为显示技术关注的焦点。
图1所示为一种现有的CMOS GOA电路，包括级联的多个GOA单元，该现有的CMOS GOA电路除了具备基本的扫描驱动功能与移位寄存功能以外，还带有使各级扫描驱动信号全部同时上升为高电位(All Gate On)的功能。
设N为正整数，第N级GOA单元包括：输入控制模块100、锁存模块300、信号处理模块400、与输出缓冲模块500。
其中，输入控制模块100接入上一级GOA单元的级传信号Q(N-1)、第一时钟信号CK1、第一反相时钟信号XCK1、恒压高电位信号VGH、及恒压低电位信号VGL，将与上一级GOA单元的级传信号Q(N-1)电位相反的信号P(N)输入锁存模块300；
锁存模块300包括一反相器F，将信号P(N)反相后得到该第N级GOA单元的级传信号Q(N)，锁存模块300对级传信号Q(N)进行锁存；
信号处理模块400接入级传信号Q(N)、第二时钟信号CK2、恒压高 电位信号VGH、恒压低电位信号VGL、及全局信号Gas；所述信号处理模块400用于对第二时钟信号CK2与级传信号Q(N)做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号G(N)；对第二时钟信号CK2与级传信号Q(N)做与逻辑处理的结果和全局信号Gas进行或非逻辑处理，实现全局信号Gas控制各级扫描驱动信号全部同时上升为高电位；
所述输出缓冲模块500电性连接信号处理模块400，用于增加扫描驱动信号G(N)的驱动能力，减小信号传输过程中的阻容负载(RC Loading)。
上述现有的CMOS GOA电路，在实现All Gate On功能时，由于扫描驱动信号持续(Holding)的问题，必须在GOA电路正常工作之前，对级传信号和扫描驱动信号进行电位的复位清零处理，因此该现有的CMOS GOA电路的每一级GOA单元还包括一复位模块200。如图1所示，以第N级GOA单元为例，所述复位模块200包括一P型TFT，该P型TFT的栅极接入复位信号Reset，源极接入恒压高电位信号VGH，漏极连接锁存模块300内反相器F的输入端，当复位信号Reset输入一低电位时，所述P型TFT导通，所述反相器F对恒压高电位信号VGH进行反相，从而拉低级传信号Q(N)的电位，对级传信号Q(N)进行清零。单独设置复位模块200虽然会提高电路的性能，但由此附加的元件、走线、与信号却增大了GOA电路的面积，提高了信号复杂度，不利于窄边框面板的设计。
发明内容
本发明的目的在于提供一种CMOS GOA电路，其不仅具有使各级扫描驱动信号全部同时上升为高电位的功能，还能够在不采用复位模块的情况下避免扫描驱动信号持续的问题，减小GOA电路的面积，简化信号的复杂度，利于窄边框面板的设计。
为实现上述目的，本发明提供了一种CMOS GOA电路，包括级联的多个GOA单元；
设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储电容；
所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、第一反相时钟信号、恒压高电位信号、及恒压低电位信号，用于将第N-1级GOA单元的级传信号进行反相，得到反相级传信号，并将反相级传信号输入锁存模块；
所述锁存模块包括一或非门，所述或非门的第一输入端输入反相级传信号、第二输入端输入全局信号，所述或非门的输出端输出级传信号，所述锁存模块用于对级传信号进行锁存；
所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
所述输出缓冲模块包括依次串联的奇数个第一反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述或非门拉低各级级传信号的电位，对各级级传信号进行清零复位。
所述输入控制模块至少包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均接入上一级第N-1级GOA单元的级传信号；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏 极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点。
所述输入控制模块还包括一第二反相器，所述第一反相时钟信号由第一时钟信号经该第二反相器反相得到。
所述输出缓冲模块包括依次串联的三个第一反相器，最靠近信号处理模块的第一反相器的输入端电性连接所述节点，最远离信号处理模块的第一反相器的输出端输出扫描驱动信号。
所述第一反相器由一第十五P型TFT串联一第十六N型TFT构成，所述第十五P型TFT与第十六N型TFT的栅极相互电性连接构成该第一反相器的输入端，所述第十五P型TFT的源极接入恒压高电位信号，所述第十六N型TFT的源极接入恒压低电位信号，所述第十五P型TFT与第十六N型TFT的漏极相互电性连接构成该第一反相器的输出端；前一个第一反相器的输出端电性连接后一个第一反相器的输入端。
所述第二反相器由一第十七P型TFT串联一第十八N型TFT构成，所述第十七P型TFT与第十八N型TFT的栅极相互电性连接构成该第二反相器的输入端，所述第十七P型TFT的源极接入恒压高电位信号，所述第十八N型TFT的源极接入恒压低电位信号，所述第十七P型TFT与第十八N型TFT的漏极相互电性连接构成该第二反相器的输出端；所述第二反相器的输入端接入第一时钟信号，输出端输出第一反相时钟信号。
所述或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该或非门的第一输入端；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该或非门的第二输入端；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该或非门的输出端。
在第一级GOA单元中，所述第二P型TFT与第三N型TFT的栅极均接入电路启动信号。
本发明还提供一种CMOS GOA电路，包括级联的多个GOA单元；
设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储 电容；
所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、第一反相时钟信号、恒压高电位信号、及恒压低电位信号，用于将第N-1级GOA单元的级传信号进行反相，得到反相级传信号，并将反相级传信号输入锁存模块；
所述锁存模块包括一或非门，所述或非门的第一输入端输入反相级传信号、第二输入端输入全局信号，所述或非门的输出端输出级传信号，所述锁存模块用于对级传信号进行锁存；
所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
所述输出缓冲模块包括依次串联的奇数个第一反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述或非门拉低各级级传信号的电位，对各级级传信号进行清零复位；
其中，所述输入控制模块至少包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均接入上一级第N-1级GOA单元的级传信号；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT 的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点；
其中，所述输入控制模块还包括一第二反相器，所述第一反相时钟信号由第一时钟信号经该第二反相器反相得到；
其中，所述输出缓冲模块包括依次串联的三个第一反相器，最靠近信号处理模块的第一反相器的输入端电性连接所述节点，最远离信号处理模块的第一反相器的输出端输出扫描驱动信号；
其中，所述或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该或非门的第一输入端；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该或非门的第二输入端；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该或非门的输出端；
其中，在第一级GOA单元中，所述第二P型TFT与第三N型TFT的栅极均接入电路启动信号。
本发明的有益效果：本发明提供的一种CMOS GOA电路，在锁存模块中设置或非门，将所述或非门的两输入端分别输入反相级传信号与全局信号，当全局信号为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述或非门拉低各级级传信号的电位，对各级级传信号进行清零复位，与现有技术相比，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积，简化了信号的复杂度，利于窄边框面板的设计；此外，通过设置存储电容在各级扫描驱动信号全部同时上升为高电位时对级传信号的低电位进行存储，提高了GOA电路的稳定性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的CMOS GOA电路的电路图；
图2为本发明的CMOS GOA电路的电路图；
图3为本发明的CMOS GOA电路的第一级GOA单元的电路图；
图4为本发明的CMOS GOA电路的工作时序图；
图5为本发明的CMOS GOA电路的输出缓冲模块中依次串联的三个第一反相器的具体电路结构示意图；
图6为本发明的CMOS GOA电路的输入控制模块中第二反相器的具体电路结构示意图；
图7为本发明的CMOS GOA电路中或非门的具体电路结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图2与图4，本发明提供一种CMOS GOA电路，包括级联的多个GOA单元，每一级GOA单元均采用多个N型TFT与多个P型TFT，且各个TFT均为低温多晶硅半导体薄膜晶体管。设N为正整数，第N级GOA单元包括：输入控制模块1、电性连接输入控制模块1的锁存模块3、电性连接锁存模块3的信号处理模块4、电性连接信号处理模块4的输出缓冲模块5、及电性连接锁存模块3与信号处理模块4的存储电容7。
所述输入控制模块1接入上一级第N-1级GOA单元的级传信号Q(N-1)、第一时钟信号CK1、第一反相时钟信号XCK1、恒压高电位信号VGH、及恒压低电位信号VGL，用于将第N-1级GOA单元的级传信号Q(N-1)进行反相，得到反相级传信号XQ(N)，并将反相级传信号XQ(N)输入锁存模块3。具体地，所述输入控制模块1包括依次串联的第一P型TFT T1、第二P型TFT T2、第三N型TFT T3、与第四N型TFT T4：所述第一P型TFT T1的栅极接入第一反相时钟信号XCK1、源极接入恒压高电位信号VGH；所述第二P型TFT T2与第三N型TFT T3的栅极均接入上一级第N-1级GOA单元的级传信号Q(N-1)；所述第二P型TFT T2与第 三N型TFT T3的漏极相互连接，输出反相级传信号XQ(N)；所述第四N型TFT T4的栅极接入第一时钟信号CK1、源极接入恒压低电位信号VGL。所述输入控制模块1还包括一第二反相器F2，所述第一反相时钟信号XCK1由第一时钟信号CK1经该第二反相器F2反相得到。进一步地，所述第二反相器F2的具体电路结构如图6所示，由一第十七P型TFT T17串联一第十八N型TFT T18构成，所述第十七P型TFT T17与第十八N型TFT T18的栅极相互电性连接构成该第二反相器F2的输入端K’，所述第十七P型TFT T17的源极接入恒压高电位信号VGH，所述第十八N型TFT T18的源极接入恒压低电位信号VGL，所述第十七P型TFT T17与第十八N型TFT T18的漏极相互电性连接构成该第二反相器F2的输出端L’；所述第二反相器F2的输入端K’接入第一时钟信号CK1，输出端L’输出第一反相时钟信号XCK1。当该第二反相器F2的输入端K’接入的第一时钟信号CK1为高电位时，输出端L’输出的第一反相时钟信号XCK1为低电位，而当该第二反相器F2的输入端K’接入的第一时钟信号CK1为低电位时，输出端L’输出的第一反相时钟信号XCK1为高电位。需要注意的是，所述依次串联的第一P型TFT T1、第二P型TFT T2、第三N型TFT T3、与第四N型TFT T4仅在第一时钟信号CK1为高电位时正常工作，若上一级第N-1级GOA单元的级传信号Q(N-1)为高电位，则第三N型TFT T3与第四N型TFT T4导通，由第三N型TFT T3的漏极输出低电位的反相级传信号XQ(N)；若上一级第N-1级GOA单元的级传信号Q(N-1)为低电位，则第一P型TFT T1与第二P型TFT T2导通，由第二P型TFT T2的漏极输出高电位的反相级传信号XQ(N)。
所述锁存模块3包括一或非门Y，所述或非门Y的第一输入端A输入反相级传信号XQ(N)、第二输入端B输入全局信号Gas，所述或非门Y的输出端D输出级传信号Q(N)。所述锁存模块3还包括依次串联的第五P型TFT T5、第六P型TFT T6、第七N型TFT T7、与第八N型TFT T8：所述第五P型TFT T5的栅极接入第一时钟信号CK1、源极接入恒压高电位信号VGH；所述第六P型TFT T6与第七N型TFT T7的栅极均接入级传信号Q(N)；所述第六P型TFT T6与第七N型TFT T7的漏极相互连接，并电性连接所述第二P型TFT T2与第三N型TFT T3的漏极；所述第八N型TFT T8的栅极接入第一反相时钟信号XCK1、源极接入恒压低电位信号VGL。进一步地，所述或非门Y的具体电路结构如图7所示，包括第十九P型TFT T19、第二十P型TFT T20、第二十一N型TFT T21、及第二十二N型TFT T22；所述第二十P型TFT T20与第二十一N型TFT T21的栅极 相互电性连接构成该或非门Y的第一输入端A；所述第十九P型TFT T19与第二十二N型TFT T22的栅极相互电性连接构成该或非门Y的第二输入端B；所述第十九P型TFT T19的源极接入恒压高电位信号VGH，漏极电性连接第二十P型TFT T20的源极；所述第二十一N型TFT T21与第二十二N型TFT T22的源极均接入恒压低电位信号VGL；所述第二十P型TFT T20、第二十一N型TFT T21、及第二十二N型TFT T22的漏极相互电性连接构成该或非门Y的输出端D。当输入该或非门Y的反相级传信号XQ(N)与全局信号Gas中的至少一个为高电位时，输出端D即输出低电位的级传信号Q(N)。需要注意的是，所述依次串联的第五P型TFT T5、第六P型TFT T6、第七N型TFT T7、与第八N型TFT T8仅在第一时钟信号CK1为低电位时正常工作，若级传信号Q(N)为高电位，则第七N型TFT T7与第八N型TFT T8导通，由第七N型TFT T7的漏极输出低电位，即保持反相级传信号XQ(N)为低电位，在全局信号Gas为低电位时，或非门Y输出的级传信号Q(N)仍为高电位，实现了对级传信号Q(N)的锁存；若级传信号Q(N)为低电位，则第五P型TFT T5与第六P型TFT T6导通，由第六P型TFT T6的漏极输出高电位，即保持反相级传信号XQ(N)为高电位，或非门Y输出的级传信号Q(N)仍为低电位，实现了对级传信号Q(N)的锁存。
所述信号处理模块4接入级传信号Q(N)、第二时钟信号CK2、恒压高电位信号VGH、恒压低电位信号VGL、及全局信号Gas，用于对第二时钟信号CK2与级传信号Q(N)做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号G(N)；对第二时钟信号CK2与级传信号Q(N)做与逻辑处理的结果和全局信号Gas进行或非逻辑处理，实现全局信号Gas控制各级扫描驱动信号G(N)全部同时上升为高电位。具体地，所述信号处理模块4包括：第九P型TFT T9，所述第九P型TFT T9的栅极接入全局信号Gas，源极接入恒压高电位信号VGH；第十P型TFT T10，所述第十P型TFT T10的栅极接入级传信号Q(N)，源极电性连接于第九P型TFT T9的漏极，漏极电性连接于节点A(N)；第十一P型TFT T11，所述第十一P型TFT T11的栅极接入第二时钟信号CK2，源极电性连接于第九P型TFT T9的漏极，漏极电性连接于节点A(N)；第十二N型TFT T12，所述第十二N型TFT T12的栅极接入级传信号Q(N)，漏极电性连接于节点A(N)；第十三N型TFT T13，所述第十三N型TFT T13的栅极接入第二时钟信号CK2，漏极电性连接于所述第十二N型TFT T12的源极，源极接入恒压低电位信号VGL；第十四N型TFT T14，所述第十四N型TFT T14的 栅极接入全局信号Gas，源极接入恒压低电位信号VGL，漏极电性连接于节点A(N)。进一步地，当全局信号Gas为低电位时：在第二时钟信号CK2与级传信号Q(N)均为高电位的情况下，第十二N型TFT T12与第十三N型TFT T13导通，节点A(N)的电位为低电位；在第二时钟信号CK2与级传信号Q(N)均为低电位的情况下，第九P型TFT T9、第十P型TFT T10、与第十一P型TFT T11导通，节点A(N)的电位为高电位。而当全局信号Gas为高电位时，不管第二时钟信号CK2与级传信号Q(N)处于什么电位，第十四N型TFT T14导通，节点A(N)的电位为低电位。
所述输出缓冲模块5包括依次串联的奇数个第一反相器F1，用于输出扫描驱动信号G(N)并增加扫描驱动信号G(N)的驱动能力。优选的，所述输出缓冲模块5包括依次串联的三个第一反相器F1，如图5所示，所述第一反相器F1由一第十五P型TFT T15串联一第十六N型TFT T16构成，所述第十五P型TFT T15与第十六N型TFT T16的栅极相互电性连接构成该第一反相器F1的输入端K，所述第十五P型TFT T15的源极接入恒压高电位信号VGH，所述第十六N型TFT T16的源极接入恒压低电位信号VGL，所述第十五P型TFT T15与第十六N型TFT T16的漏极相互电性连接构成该第一反相器F1的输出端L。最靠近信号处理模块4的第一反相器F1的输入端电性连接所述节点A(N)，最远离信号处理模块4的第一反相器F1的输出端L输出扫描驱动信号G(N)，前一个第一反相器F1的输出端L电性连接后一个第一反相器F1的输入端K。当节点A(N)的电位为低电位时，经输出缓冲模块5内依次串联的三个第一反相器F1的反向作用，扫描驱动信号G(N)为高电位；当节点A(N)的电位为高电位时，经输出缓冲模块5内依次串联的三个第一反相器F1的反向作用，扫描驱动信号G(N)为低电位。
所述存储电容7的一端电性连接级传信号Q(N)，另一端接地，用于存储级传信号Q(N)的电位。
特别需要说明的是，所述全局信号Gas包含单个脉冲，且该单个脉冲在GOA电路正常工作之前触发。当所述全局信号Gas为高电位时，各级GOA单元电路中的第十四N型TFT T14导通，各级GOA单元电路中的节点A(N)的电位为低电位，经各级GOA单元电路中的输出缓冲模块5内依次串联的三个第一反相器F1的反向作用，各级扫描驱动信号G(N)全部同时上升为高电位；同时所述高电位的全局信号Gas控制或非门Y拉低各级级传信号Q(N)的电位，对各级级传信号Q(N)进行清零复位，此时存储电容7对级传信号Q(N)的低电位进行存储。在使各级扫描驱动信 号G(N)全部同时上升为高电位的功能作用完毕之后，全局信号Gas转变为低电位，由于存储电容7存储了低电位，第九P型TFT T9与第十P型TFT T10导通，节点A(N)的电位转变为高电位，经各级GOA单元电路中的输出缓冲模块5内依次串联的三个第一反相器F1的反向作用，各级扫描驱动信号G(N)全部同时转变为低电位，避免了扫描驱动信号持续的问题。之后，CMOS GOA电路正常工作。
与现有技术相比，上述CMOS GOA电路，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积，简化了信号的复杂度，利于窄边框面板的设计，并提高了GOA电路的稳定性。
值得一提的是，当所述全局信号Gas为高电位时，所述第一时钟信号CK1与第二时钟信号CK2均可处于高阻态(floating)，即对第一时钟信号CK1与第二时钟信号CK2的电位不做限定，以降低整个电路的待机功耗。所述全局信号Gas由高电位转变为低电位后，所述第一时钟信号CK1比第二时钟信号CK2提前一个脉宽。
特别地，如图3所示，在第一级GOA单元中，所述第二P型TFT T2与第三N型TFT T3的栅极均接入电路启动信号STV。结合图3与图4，当CMOS GOA开始电路正常工作时，电路启动信号STV与第一时钟信号CK1同为高电位，第三N型TFT T3与第四N型TFT T4导通，由第三N型TFT T3的漏极输出低电位的反相级传信号XQ(1)；所述锁存模块3的或非门Y输出的级传信号Q(1)为高电位，且在第一时钟信号CK1转变为低电位后，仍锁存级传信号Q(1)的高电位；随着第二时钟信号CK2为高电位，第十二N型TFT T12与第十三N型TFT T13导通，节点A(1)的电位为低电位；经输出缓冲模块5内依次串联的三个第一反相器F1的反向作用，扫描驱动信号G(1)为高电位。之后，第二级GOA单元接收第一级GOA单元的级传信号Q(1)进行扫描驱动，以此类推，直至最后一级GOA单元完成扫描驱动。
综上所述，本发明的CMOS GOA电路，在锁存模块中设置或非门，将所述或非门的两输入端分别输入反相级传信号与全局信号，当全局信号为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述或非门拉低各级级传信号的电位，对各级级传信号进行清零复位，与现有技术相比，不需要单独设置复位模块，省去了附加的元件、走线、与复位信号，减小了GOA电路的面积，简化了信号的复杂度，利于窄边框面板的设计；此外，通过设置存储电容在各级扫描驱动信号全部同时上升为高电位时对级传信号的低电位进行存储，提高了GOA电路的稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种CMOS GOA电路，包括级联的多个GOA单元；
    设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储电容；
    所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、第一反相时钟信号、恒压高电位信号、及恒压低电位信号，用于将第N-1级GOA单元的级传信号进行反相，得到反相级传信号，并将反相级传信号输入锁存模块；
    所述锁存模块包括一或非门，所述或非门的第一输入端输入反相级传信号、第二输入端输入全局信号，所述或非门的输出端输出级传信号，所述锁存模块用于对级传信号进行锁存；
    所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
    所述输出缓冲模块包括依次串联的奇数个第一反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
    所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传信号的电位；
    所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述或非门拉低各级级传信号的电位，对各级级传信号进行清零复位。
  2. 如权利要求1所述的CMOS GOA电路，其中，所述输入控制模块至少包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均接入上一级第N-1级GOA单元的级传信号；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
    所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
    所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点。
  3. 如权利要求2所述的CMOS GOA电路，其中，所述输入控制模块还包括一第二反相器，所述第一反相时钟信号由第一时钟信号经该第二反相器反相得到。
  4. 如权利要求2所述的CMOS GOA电路，其中，所述输出缓冲模块包括依次串联的三个第一反相器，最靠近信号处理模块的第一反相器的输入端电性连接所述节点，最远离信号处理模块的第一反相器的输出端输出扫描驱动信号。
  5. 如权利要求4所述的CMOS GOA电路，其中，所述第一反相器由一第十五P型TFT串联一第十六N型TFT构成，所述第十五P型TFT与第十六N型TFT的栅极相互电性连接构成该第一反相器的输入端，所述第十五P型TFT的源极接入恒压高电位信号，所述第十六N型TFT的源极接入恒压低电位信号，所述第十五P型TFT与第十六N型TFT的漏极相互电性连接构成该第一反相器的输出端；前一个第一反相器的输出端电性连接后一个第一反相器的输入端。
  6. 如权利要求3所述的CMOS GOA电路，其中，所述第二反相器由一第十七P型TFT串联一第十八N型TFT构成，所述第十七P型TFT与第十八N型TFT的栅极相互电性连接构成该第二反相器的输入端，所述第十七P型TFT的源极接入恒压高电位信号，所述第十八N型TFT的源极接 入恒压低电位信号，所述第十七P型TFT与第十八N型TFT的漏极相互电性连接构成该第二反相器的输出端；所述第二反相器的输入端接入第一时钟信号，输出端输出第一反相时钟信号。
  7. 如权利要求2所述的CMOS GOA电路，其中，所述或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该或非门的第一输入端；所述第十九P型TFT与第二十二N型TFT的栅极相互电性连接构成该或非门的第二输入端；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该或非门的输出端。
  8. 如权利要求2所述的CMOS GOA电路，其中，在第一级GOA单元中，所述第二P型TFT与第三N型TFT的栅极均接入电路启动信号。
  9. 一种CMOS GOA电路，包括级联的多个GOA单元；
    设N为正整数，第N级GOA单元包括：输入控制模块、电性连接输入控制模块的锁存模块、电性连接锁存模块的信号处理模块、电性连接信号处理模块的输出缓冲模块、及电性连接锁存模块与信号处理模块的存储电容；
    所述输入控制模块接入上一级第N-1级GOA单元的级传信号、第一时钟信号、第一反相时钟信号、恒压高电位信号、及恒压低电位信号，用于将第N-1级GOA单元的级传信号进行反相，得到反相级传信号，并将反相级传信号输入锁存模块；
    所述锁存模块包括一或非门，所述或非门的第一输入端输入反相级传信号、第二输入端输入全局信号，所述或非门的输出端输出级传信号，所述锁存模块用于对级传信号进行锁存；
    所述信号处理模块接入级传信号、第二时钟信号、恒压高电位信号、恒压低电位信号、及全局信号，用于对第二时钟信号与级传信号做与非逻辑处理，以产生该第N级GOA单元的扫描驱动信号；对第二时钟信号与级传信号做与逻辑处理的结果和全局信号进行或非逻辑处理，实现全局信号控制各级扫描驱动信号全部同时上升为高电位；
    所述输出缓冲模块包括依次串联的奇数个第一反相器，用于输出扫描驱动信号并增加扫描驱动信号的驱动能力；
    所述存储电容的一端电性连接级传信号，另一端接地，用于存储级传 信号的电位；
    所述全局信号包含单个脉冲，其为高电位时，控制各级扫描驱动信号全部同时上升为高电位，同时控制所述或非门拉低各级级传信号的电位，对各级级传信号进行清零复位；
    其中，所述输入控制模块至少包括依次串联的第一P型TFT、第二P型TFT、第三N型TFT、与第四N型TFT；所述第一P型TFT的栅极接入第一反相时钟信号、源极接入恒压高电位信号；所述第二P型TFT与第三N型TFT的栅极均接入上一级第N-1级GOA单元的级传信号；所述第二P型TFT与第三N型TFT的漏极相互连接，输出反相级传信号；所述第四N型TFT的栅极接入第一时钟信号、源极接入恒压低电位信号；
    所述锁存模块还包括依次串联的第五P型TFT、第六P型TFT、第七N型TFT、与第八N型TFT；所述第五P型TFT的栅极接入第一时钟信号、源极接入恒压高电位信号；所述第六P型TFT与第七N型TFT的栅极均接入级传信号；所述第六P型TFT与第七N型TFT的漏极相互连接，并电性连接所述第二P型TFT与第三N型TFT的漏极；所述第八N型TFT的栅极接入第一反相时钟信号、源极接入恒压低电位信号；
    所述信号处理模块包括：第九P型TFT，所述第九P型TFT的栅极接入全局信号，源极接入恒压高电位信号；第十P型TFT，所述第十P型TFT的栅极接入级传信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十一P型TFT，所述第十一P型TFT的栅极接入第二时钟信号，源极电性连接于第九P型TFT的漏极，漏极电性连接于节点；第十二N型TFT，所述第十二N型TFT的栅极接入级传信号，漏极电性连接于节点；第十三N型TFT，所述第十三N型TFT的栅极接入第二时钟信号，漏极电性连接于所述第十二N型TFT的源极，源极接入恒压低电位信号；第十四N型TFT，所述第十四N型TFT的栅极接入全局信号，源极接入恒压低电位信号，漏极电性连接于节点；
    其中，所述输入控制模块还包括一第二反相器，所述第一反相时钟信号由第一时钟信号经该第二反相器反相得到；
    其中，所述输出缓冲模块包括依次串联的三个第一反相器，最靠近信号处理模块的第一反相器的输入端电性连接所述节点，最远离信号处理模块的第一反相器的输出端输出扫描驱动信号；
    其中，所述或非门包括第十九P型TFT、第二十P型TFT、第二十一N型TFT、及第二十二N型TFT；所述第二十P型TFT与第二十一N型TFT的栅极相互电性连接构成该或非门的第一输入端；所述第十九P型TFT 与第二十二N型TFT的栅极相互电性连接构成该或非门的第二输入端；所述第十九P型TFT的源极接入恒压高电位信号，漏极电性连接第二十P型TFT的源极；所述第二十一N型TFT与第二十二N型TFT的源极均接入恒压低电位信号；所述第二十P型TFT、第二十一N型TFT、及第二十二N型TFT的漏极相互电性连接构成该或非门的输出端；
    其中，在第一级GOA单元中，所述第二P型TFT与第三N型TFT的栅极均接入电路启动信号。
  10. 如权利要求9所述的CMOS GOA电路，其中，所述第一反相器由一第十五P型TFT串联一第十六N型TFT构成，所述第十五P型TFT与第十六N型TFT的栅极相互电性连接构成该第一反相器的输入端，所述第十五P型TFT的源极接入恒压高电位信号，所述第十六N型TFT的源极接入恒压低电位信号，所述第十五P型TFT与第十六N型TFT的漏极相互电性连接构成该第一反相器的输出端；前一个第一反相器的输出端电性连接后一个第一反相器的输入端。
  11. 如权利要求9所述的CMOS GOA电路，其中，所述第二反相器由一第十七P型TFT串联一第十八N型TFT构成，所述第十七P型TFT与第十八N型TFT的栅极相互电性连接构成该第二反相器的输入端，所述第十七P型TFT的源极接入恒压高电位信号，所述第十八N型TFT的源极接入恒压低电位信号，所述第十七P型TFT与第十八N型TFT的漏极相互电性连接构成该第二反相器的输出端；所述第二反相器的输入端接入第一时钟信号，输出端输出第一反相时钟信号。
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