WO2017033673A1 - パワー半導体素子の駆動回路、電力変換ユニットおよび電力変換装置 - Google Patents

パワー半導体素子の駆動回路、電力変換ユニットおよび電力変換装置 Download PDF

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Publication number
WO2017033673A1
WO2017033673A1 PCT/JP2016/072465 JP2016072465W WO2017033673A1 WO 2017033673 A1 WO2017033673 A1 WO 2017033673A1 JP 2016072465 W JP2016072465 W JP 2016072465W WO 2017033673 A1 WO2017033673 A1 WO 2017033673A1
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Prior art keywords
power semiconductor
semiconductor element
unit
power
drive circuit
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PCT/JP2016/072465
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English (en)
French (fr)
Japanese (ja)
Inventor
彬 三間
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株式会社日立製作所
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Priority to CN201680050554.XA priority Critical patent/CN108141127B/zh
Publication of WO2017033673A1 publication Critical patent/WO2017033673A1/ja

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

Definitions

  • the present invention relates to a power semiconductor element drive circuit, a power conversion unit, and a power conversion device.
  • inverter device that converts DC power into AC power
  • a converter device that converts AC power into DC power as power conversion devices.
  • power conversion is performed by a switching operation of the power semiconductor elements.
  • a plurality of power semiconductor elements are connected in parallel, and the plurality of power semiconductors are connected. The elements are driven to be switched simultaneously.
  • Patent Document 1 states that “a plurality of variable gate resistance circuits that change the gate resistance of the IGBT and each variable gate resistance circuit according to the time lag of the current pulse that flows through the IGBT, And a control circuit that changes each gate resistance at the start of turn-off control.
  • the present invention relates to a power semiconductor element drive circuit capable of improving not only current imbalance during switching operation but also current imbalance during steady operation, a power conversion unit equipped with the drive circuit, and power provided with the power conversion unit
  • An object is to provide a conversion device.
  • the present application includes a plurality of means for solving the above problems.
  • a drive circuit provided corresponding to each of a plurality of power semiconductor elements connected in parallel and driving the power semiconductor elements,
  • a gate drive control unit that controls the gate drive condition of the power semiconductor element based on the characteristic information stored in the storage unit; It is characterized by providing.
  • FIG. 1 is an example of a block diagram illustrating a configuration of a drive circuit for a power semiconductor element according to Embodiment 1.
  • FIG. It is an example of the characteristic map figure which shows an example of the information of the characteristic map of the power semiconductor element memorize
  • FIG. 3 is an example of a waveform diagram for explaining the effect of the drive circuit for the power semiconductor element according to the first embodiment.
  • FIG. 6 is an example of a block diagram illustrating a configuration of a drive circuit for a power semiconductor element according to a second embodiment. It is an example of the block diagram which shows an example of a current sensor. It is an example of the flowchart which shows an example of the process sequence of the feedback control with respect to a delay circuit part.
  • the power conversion device has an inverter function (inverter device) that converts DC power into AC power, or a converter function (converter device) that converts AC power into DC power.
  • This type of power conversion device is, for example, an uninterruptible power system that aims to supply AC power to a load such as a server without interruption using energy stored in a storage battery. : UPS).
  • the use illustrated here is an example and is not limited to the use for an uninterruptible power supply.
  • the uninterruptible power supply it is used for various applications such as power converters for industrial equipment, power converters for railways, power converters for elevators, power converters for automobiles, and power converters for household electrical products. Can do.
  • FIG. 1 is an example of a block diagram showing a basic configuration of a drive circuit for a power semiconductor element.
  • a power semiconductor element drive circuit 1 includes an upper arm drive circuit 4 that drives an upper arm power semiconductor element 2, a lower arm drive circuit 5 that drives a lower arm power semiconductor element 3, and an upper control circuit unit 6. It has the composition which has.
  • the drive circuit 1 of the power semiconductor element may be simply referred to as the drive circuit 1.
  • the upper arm driving circuit 4 is simply referred to as a driving circuit 4
  • the lower arm driving circuit 5 is simply referred to as a driving circuit 5.
  • Diodes 7 and 8 are connected in parallel with reverse polarity to each of the power semiconductor elements 2 and 3.
  • the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 are switching elements that switch a high power supply voltage in accordance with the gate voltage, and perform power conversion by this switching operation.
  • the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 may be simply referred to as the power semiconductor element 2 and the power semiconductor element 3.
  • an insulated gate bipolar transistor Insulated Bipolar Transistor: IGBT
  • IGBT Insulated Bipolar Transistor
  • the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 are main circuits in the power converter, and are connected in series between the high potential side power source and the low potential side power source. That is, the drain of the upper arm power semiconductor element 2 is connected to the high potential side power source, the source of the lower arm power semiconductor element 3 is connected to the low potential side power source, and the source of the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 is connected to the output terminal 9 in common.
  • the voltage (output voltage) derived to the output terminal 9 is supplied to a load (not shown).
  • the upper arm power semiconductor element 2, the lower arm power semiconductor element 3, and the diodes 7 and 8 are modularized.
  • a module including the upper arm power semiconductor element 2, the lower arm power semiconductor element 3, and the diodes 7 and 8 is referred to as a power module 10.
  • the upper control circuit unit 6 supplies a pulse train signal for controlling these to the upper arm drive circuit 4 and the lower arm drive circuit 5.
  • the pulse train signal is, for example, a pulse width modulation (PWM) signal using a carrier wave that changes at a constant frequency.
  • PWM pulse width modulation
  • the accuracy of control can be increased by increasing the frequency of the carrier wave.
  • FIG. 2 is an example of a circuit diagram showing an example of a circuit configuration for increasing the conversion power capacity by parallel connection of power semiconductor elements.
  • two upper arm power semiconductor elements 2 and two lower arm power semiconductor elements 3 are connected in parallel.
  • two parallel connections are given as an example, but the number of parallel connections of the power semiconductor elements 2 and 3 is not limited to two, and the effect of increasing the conversion power capacity as the number of parallel connections increases. growing.
  • a power module 10 (10-1, 10-2) comprising an upper arm power semiconductor element 2, a lower arm power semiconductor element 3, and diodes 7, 8, an upper arm drive circuit 4 and a lower arm drive circuit 5, are unitized.
  • this unit is referred to as a power conversion unit (power unit) 11.
  • power unit 11 there are two power conversion units 11, and these two power conversion units 11-1 and 11-2 are used in parallel with each other.
  • the drain of the upper arm power semiconductor element 2 on the power conversion unit 11-1 side and the drain of the upper arm power semiconductor element 2 on the power conversion unit 11-2 side are common to the high potential side power supply terminal 12. It is connected to the. Further, the source of the lower arm power semiconductor element 3 on the power conversion unit 11-1 side and the source of the lower arm power semiconductor element 3 on the power conversion unit 11-2 side are commonly connected to the low potential side power supply terminal 13. Yes. The source of the upper arm power semiconductor element 2 on the power conversion unit 11-1 side and the power conversion unit 11-2 side and the drain of the lower arm power semiconductor element 3 are connected to the output terminal 9 in common.
  • the present invention is not limited to this. That is, in addition to the 2-in-1 configuration, a power module with a 1-in-1 configuration in which a power semiconductor element of one arm is mounted may be used.
  • FIG. 3 is an example of a perspective view showing an outline of the configuration of the power conversion unit and the power conversion device.
  • the configuration of the power conversion device illustrated in FIG. 3 is an example, and is not limited to this configuration.
  • the power conversion unit 11 (11-1, 11-2) is configured by integrating components such as a heat receiving block 14, a smoothing capacitor 15, a heat pipe 16, a heat radiating fin 17, a bus bar 18, fuses 19n, 19p. Unit unit.
  • the heat receiving block 14 is provided so as to sandwich the power semiconductor elements 2 and 3 from both sides.
  • the heat pipe 16 is built in the heat receiving block 14.
  • the radiating fins 17 function to release heat from the heat pipe 16.
  • the bus bar 18 is a member for connecting the power semiconductor elements 2 and 3 and the smoothing capacitor 15.
  • the fuses 19n and 19p are connected to the bus bar 18.
  • a control board 20 is further attached to the power conversion unit 11. On the control board 20, drive circuits 4 and 5 for the power semiconductor elements 2 and 3 are mounted.
  • the power conversion device 30 is configured by combining a fan unit 31 for discharging cooling air, a passive component 32 of the power conversion device 30, and the like using a plurality of power conversion units 11 having the above-described configuration.
  • six power conversion units 11 are arranged in the middle part of the power conversion device 30.
  • the six power conversion units 11 include, for example, three power conversion units for three phases of inverters and three power conversion units for three phases of converters.
  • the number of power conversion units 11 arranged in the power conversion device 30 is not limited to six, and the number is arbitrary.
  • the fan unit 31 is disposed on the upper portion of the power conversion device 30, and the passive component 32 is disposed on the lower portion of the power conversion device 30.
  • the power module 10 including the power semiconductor elements 2 and 3 and the diodes 7 and 8, and the upper arm drive circuit 4 and the lower arm drive circuit 5 are unitized. Exchange and expansion are possible in units of 11. Thereby, the maintainability of the power converter device 30 can be improved.
  • a plurality of power semiconductor elements 2 and 3 are connected in parallel for the purpose of increasing the conversion power capacity, and the plurality of power semiconductor elements 2 and 3 are connected. Let us consider the case of switching driving simultaneously. In this case, since individual power semiconductor elements have variations in characteristics inherent to the elements such as threshold voltage and on-voltage, there is a problem that the current values flowing through the power semiconductor elements are unbalanced when they are conducted. .
  • the “steady operation” is an operation during a period from when the power semiconductor elements 2 and 3 are turned on to before the turn-off, that is, when the power semiconductor elements 2 and 3 are in conduction.
  • the drive circuit 1 includes an upper arm drive circuit 4 and a lower arm drive provided in correspondence to the plurality of power semiconductor elements 2 and 3 in the power conversion units 11-1 and 11-2 connected in parallel.
  • Each circuit 5 includes a storage unit 51 (see FIG. 4) that stores characteristic information of the power semiconductor elements 2 and 3. Examples of the characteristic information of the power semiconductor elements 2 and 3 include current change start time, switching speed, threshold voltage, on-voltage, and the like. Then, the upper arm drive circuit 4 and the lower arm drive circuit 5 determine the gate drive conditions of the power semiconductor elements 2 and 3, specifically, based on the characteristic information of the power semiconductor elements 2 and 3 stored in the storage unit 51. Controls the gate current or gate voltage.
  • the storage unit 51 for storing the characteristic information of the power semiconductor elements 2 and 3 is provided for each of the drive circuits 4 and 5, and the gate drive condition (gate current or gate) of the power semiconductor elements 2 and 3 is based on the characteristic information.
  • the gate drive condition gate current or gate
  • the characteristics of the power semiconductor elements 2 and 3 such as the threshold voltage and the ON voltage can be improved. Current imbalance caused by individual differences can be reliably improved.
  • the storage unit 51 is provided for each of the drive circuits 4 and 5, when the power conversion unit 11 is replaced in units, the storage unit 51 of the replaced power conversion unit 11 includes the power conversion unit. Thus, the characteristic information of the power semiconductor element mounted on 11 is stored. Therefore, even if the power conversion unit 11 is replaced, it is not necessary to rewrite the characteristic information in the storage unit 51 each time.
  • storage part 51 in common with respect to the some power conversion unit 11 is taken, whenever the power conversion unit 11 is replaced
  • FIG. 4 is an example of a block diagram illustrating the configuration of the drive circuit 1 for the power semiconductor element according to the first embodiment.
  • the lower arm drive circuit 5 includes a storage unit (storage device) 51, an interface (I / F) circuit unit 52, a delay circuit unit 53, and a gate voltage slope variable circuit unit 54. And a gate voltage variable circuit section 55.
  • the storage unit 51 stores characteristic information of the lower arm power semiconductor element 3.
  • the information stored in the storage unit 51 is preferably, for example, information on a characteristic map of each power semiconductor element acquired at the time of shipping inspection of the power semiconductor element 3.
  • FIG. 5 is an example of a characteristic map diagram illustrating an example of information on a characteristic map of the power semiconductor element stored in the storage unit 51.
  • FIG. 5A shows a characteristic map showing the relationship between the on-voltage and switching speed (SW speed) of the lower arm power semiconductor element 3 on the power conversion unit 11-1 side, and a characteristic map showing the relationship between the on-voltage and delay time. Is shown.
  • FIG. 5B shows a characteristic map showing the relationship between the on-voltage and switching speed (SW speed) of the lower arm power semiconductor element 3 on the power conversion unit 11-2 side, and a characteristic showing the relationship between the on-voltage and delay time. Shows the map.
  • the characteristic maps shown in FIGS. 5A and 5B are examples, and the present invention is not limited to this.
  • the interface circuit unit 52 transmits the information supplied from the upper control circuit unit 6 to the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55.
  • the delay circuit unit 53, the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55 are controlled by the upper control circuit unit 6 based on the characteristic information stored in the storage unit 51.
  • a gate drive control unit for controlling gate drive conditions is configured.
  • the delay circuit unit 53 adjusts the delay variation ⁇ ton of the rising or falling timing of the current during the switching operation of the power semiconductor element 3.
  • the gate voltage gradient variable circuit unit 54 changes the gate voltage gradient dVge / dt in order to adjust the variation in the current gradient di / dt during the switching operation of the power semiconductor element 3.
  • the gate voltage variable circuit unit 55 changes the gate (gate-emitter) voltage ⁇
  • FIG. 6 is an example of a waveform diagram showing the delay variation ⁇ ton of the rise or fall timing of the current during the switching operation of the power semiconductor element 3, the slope dVge / dt of the gate voltage, and the gate voltage ⁇
  • the upper control circuit unit 6 reads characteristic map information (see FIG. 5A) that is characteristic information of the power semiconductor element 3 from the storage unit 51. Then, the upper control circuit unit 6 calculates difference information between the power semiconductor elements 3 connected in parallel based on the read information, and controls the delay circuit unit 53, the gate through the interface circuit unit 52 as a control signal. The voltage gradient variable circuit unit 54 and the gate voltage variable circuit unit 55 are supplied.
  • the delay circuit unit 53, the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55 control the gate drive conditions of the power semiconductor element 3 based on the control signal supplied from the upper control circuit unit 6. In this case, even if the signal input from the input terminal 21 is the same as the drive signal of the power semiconductor element 3, it is different from the power semiconductor element 3 mounted in each of the power conversion units 11-1 and 11-2. A gate voltage waveform is applied.
  • the drive circuits 4 having the same configuration are connected to each other.
  • characteristic map information corresponding to the upper arm power semiconductor element 2 is recorded in a storage unit (corresponding to the storage unit 51 in FIG. 4) mounted on the drive circuit 4 on the high potential side.
  • the upper control circuit unit 6 displays the difference information between the power semiconductor elements 2 connected in parallel as in the case of driving the lower arm power semiconductor element 3.
  • the drive circuit 4 is controlled based on the calculated difference information.
  • FIG. 7 is an example of a waveform diagram for explaining the effect of the drive circuit 1 for the power semiconductor element according to the first embodiment.
  • FIG. 7A is an example of a driving waveform when power semiconductor elements connected in parallel having characteristic variations are controlled by a conventional driving circuit.
  • FIG. 7B is an example of a drive waveform when controlled by the drive circuit 1 according to the first embodiment.
  • the gate drive waveforms match, but the currents I1 and I2 flowing through the power semiconductor elements are the same. It is unbalanced.
  • a difference ⁇ ton may occur in the current change start time due to mutual timing delay variation.
  • a difference ⁇ di / dt may occur in the current switching speed.
  • a difference ⁇ I may occur in the current during steady operation due to variations in characteristics such as threshold voltage and on-voltage.
  • Examples of the information of the characteristic map recorded in the storage unit (recording device) 51 provided in the power semiconductor element drive circuit 1 according to the first embodiment include current change start time, switching speed, threshold voltage, and on-voltage.
  • the upper control circuit unit 6 calculates the difference information ⁇ ton, ⁇ di / dt, ⁇ I from the information of the characteristic map stored in the storage unit 51, and delay circuit unit 53, gate voltage so as to cancel the difference. Control signals are output to the slope variable circuit unit 54 and the gate voltage variable circuit unit 55.
  • the delay circuit unit 53 adjusts the delay variation ⁇ ton of the rising or falling timing of the current during the switching operation. Further, the gate voltage gradient variable circuit unit 54 changes the gate voltage gradient dVge / dt, and the gate voltage variable circuit unit 55 changes the gate voltage ⁇
  • the case where the power semiconductor elements are arranged in parallel is described as an example.
  • n is an integer of 3 or more
  • the present embodiment The drive circuit 1 according to the above is applicable.
  • the upper control circuit unit 6 calculates the difference information.
  • the information of the characteristic map of the nth power semiconductor element is used as the reference information, and the remaining first (n -1) Control for calculating a difference with respect to the information of the characteristic map of the first power semiconductor element can be considered.
  • FIG. 8 is an example of a block diagram illustrating the configuration of the power semiconductor element drive circuit 1 according to the second embodiment.
  • the power semiconductor element drive circuit 1 according to the second embodiment includes current sensors 61-1 and 61-2, in addition to the components of the power semiconductor element drive circuit 1 according to the first embodiment.
  • the current calculation units 62-1 and 62-2 are provided.
  • the current sensors 61-1 and 61-2 detect information corresponding to the current flowing through the power semiconductor elements 2 and 3.
  • the current calculation units 62-1 and 62-2 calculate the current that actually flows through the power semiconductor elements 2 and 3 based on the detection outputs (detection information) of the current sensors 61-1 and 61-2.
  • the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 are illustrated as separate components, but may be integrated.
  • the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 constitute a plurality of current detection units that detect the current flowing through the power semiconductor elements 2 and 3.
  • the detection results of the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 are fed back to the upper control circuit unit 6.
  • the upper control circuit unit 6 is configured by, for example, a CPU (Central Processing Unit), and has characteristics stored in the storage unit 51 with respect to the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55. In addition to control based on information, control based on feedback information is executed.
  • CPU Central Processing Unit
  • the characteristic information stored in the storage unit 51 is information on a characteristic map acquired at the time of shipping inspection. Control of the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55 based on the information of the characteristic map acquired at the time of the shipping inspection can sufficiently obtain the effect of reducing the current imbalance.
  • the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate based on the detection result of the current that actually flows in the power semiconductor elements 2 and 3 are used. Feedback control of the voltage variable circuit unit 55 is performed. Therefore, according to the feedback control by the power semiconductor element drive circuit 1 according to the second embodiment, the current imbalance can be reduced even when the current imbalance is deteriorated after the heat cycle of the power conversion units 11-1 and 11-2. Can be obtained.
  • FIG. 9 is an example of a configuration diagram illustrating an example of the current sensor 61.
  • the current sensor 61 a coreless current sensor that is not used in the core for detecting a magnetic field, specifically, a sensor using a Rogowski coil is illustrated.
  • the current sensor 61 is not limited to a sensor using a Rogowski coil.
  • the current sensor 61 using the Rogowski coil has a configuration in which an air-core coil 612 is arranged around the primary conductor 611.
  • a voltage corresponding to the current flowing through the primary conductor 611 is induced at both ends of the coil 612. This voltage (induced electromotive force) is derived between the terminals 613a and 613b as a differential waveform of the current flowing through the primary conductor 611.
  • the current calculation unit 62 (62-1, 62-2) shown in FIG. 9 takes in the voltage of the differential waveform derived between the terminals 613a, 613b as information corresponding to the current flowing through the power semiconductor elements 2, 3, Based on this voltage, the current that actually flows through the power semiconductor elements 2 and 3 is calculated.
  • the current calculation unit 62 includes an integration circuit 621 and an effective value circuit 622.
  • the current calculation unit 62 reproduces the current flowing through the power semiconductor elements 2 and 3 by integrating the differential waveform voltage. Calculate the current that actually flows.
  • FIG. 10 is an example of a flowchart illustrating an example of a processing procedure of feedback control for the delay circuit unit 53.
  • the CPU takes in the outputs of the current calculation units 62-1 and 62-2, that is, the detected currents of the power semiconductor elements 2 and 3, and obtains the current rise delay time ⁇ ton (step S11), and then the current rise delay time ⁇ ton is obtained. It is determined whether or not it is equal to or less than a predetermined value (step S12). If the current rise delay time ⁇ ton is equal to or less than the predetermined value (YES in S12), the CPU leaves the gate drive condition as it is and ends the feedback control process.
  • the CPU calculates the delay time adjustment amount (step S13), and then controls the delay circuit unit 53 to thereby delay the current rise.
  • the time ⁇ ton is adjusted (step S14).
  • FIG. 11 is an example of a flowchart showing an example of a processing procedure of feedback control for the gate voltage gradient variable circuit unit 54.
  • the CPU takes in the outputs of the current calculation units 62-1 and 62-2, that is, the detected currents of the power semiconductor elements 2 and 3, and obtains the current gradient di / dt (step S21), and then the current gradient di / dt is obtained. It is determined whether it is within a predetermined value (step S22). Then, if the current gradient di / dt is within the predetermined value (YES in S22), the CPU keeps the gate drive condition as it is and ends the process of the feedback control. On the other hand, if the current gradient di / dt is not within the predetermined value (NO in S22), the CPU calculates the gate voltage gradient adjustment amount (step S23), and then controls the gate voltage gradient variable circuit unit 54. The current gradient di / dt is adjusted (step S24).
  • FIG. 12 is an example of a flowchart showing an example of a processing procedure of feedback control for the gate voltage variable circuit unit 55.
  • the CPU takes in the outputs of the current calculation units 62-1 and 62-2, that is, the detected currents of the power semiconductor elements 2 and 3, and obtains a current (steady current) during steady operation (step S31). It is determined whether it is within the range (step S32). If the steady current is within the predetermined range (YES in S32), the CPU leaves the gate drive condition as it is and ends the feedback control process. On the other hand, if the steady current is not within the predetermined range (NO in S32), the CPU calculates the gate voltage adjustment amount (step S33), and then adjusts the gate voltage by controlling the gate voltage variable circuit unit 55 (step S33). Step S34).
  • the upper control circuit unit 6 (specifically, the CPU) is detected by the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 under a predetermined condition.
  • the characteristic information stored in advance in the storage unit 51 may be updated based on the current.
  • the predetermined condition for example, current imbalance at the time of control based on the information of the characteristic map at the time of shipping inspection is detected by the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2. This is a case where the host control circuit unit 6 determines that the current imbalance is worsened.
  • the characteristic data that is the basis of the new control information output by the upper control circuit unit 6 is re-stored in the storage unit 51.
  • the control information from the upper control circuit unit 6 becomes information corresponding to the actual current imbalance.
  • the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55 can be controlled so that the current imbalance is always improved.
  • the third embodiment is a specific example of the gate voltage gradient variable circuit section 54 and the gate voltage variable circuit section 55 in the power semiconductor element drive circuit 1 according to the first embodiment.
  • FIG. 13 is an example of a circuit diagram illustrating an example of a specific circuit configuration of the gate voltage gradient variable circuit unit 54.
  • the gate voltage gradient variable circuit unit 54 includes a pre-driver 71, a variable resistance control unit 72, a buffer unit 73, and a variable resistance unit 74.
  • the delay circuit unit 53 is arranged at the front stage of the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55 is arranged at the rear stage. Then, these illustrations are omitted.
  • a signal for driving the power semiconductor element 3 is input to the input terminal 75 via the delay circuit unit 53. This signal is transmitted to the buffer unit 73 via the pre-driver 71. The signal that has passed through the buffer unit 73 becomes a gate input of the power semiconductor element 3 through the variable resistor unit 74.
  • a switching speed control signal sent from the host control circuit unit 6 is input to the input terminal 76. The switching speed control signal changes the value of the gate input current (gate injection current) of the power semiconductor element 3 by controlling the resistance value of the variable resistor 74.
  • the slope of the gate voltage can be changed by changing the value of the gate injection current when the power semiconductor element 3 is switched.
  • FIG. 14 is an example of a circuit diagram illustrating an example of a specific circuit configuration of the gate voltage variable circuit unit 55.
  • the gate voltage variable circuit unit 55 includes a gate power supply 81, a switch control unit 82, a resistance element 83, and three Zener diodes (constant voltage diodes) 84-1, having different Zener voltages. 84-2, 84-3 and three switches 85-1, 85-2, 85-3.
  • the power supply voltage is input to the gate power supply 81 via the power supply terminals 86 and 87.
  • An on-voltage control signal sent from the upper control circuit unit 6 is input to the switch control unit 82 via the input terminal 88.
  • the switch control unit 82 performs on (close) / off (open) control of the switches 85-1, 85-2, and 85-3 according to the on voltage control signal, and the zener diodes 84-1 and 84 having different zener voltages.
  • -2 Toggles the connection of 84-3.
  • V r V out -V ZD (1)
  • the voltage between the positive bias power source and the negative bias power source is the output voltage V out of the gate power source 81. Further, the voltage between the positive bias power supply and the reference potential is a voltage V r applied across the resistance element 83.
  • the voltage applied to the gate of the power semiconductor element 3 is equal to the inter-terminal voltage V r between the positive bias power supply and the reference potential, so that the Zener voltage V ZD can be changed. For example, the gate applied voltage of the power semiconductor element 3 can be changed.
  • the gate applied voltage of the power semiconductor element 3 by changing the gate applied voltage of the power semiconductor element 3, the on-voltage and current characteristics change, so that the steady current can be changed. Therefore, by controlling the gate voltage of the power semiconductor element 3 based on the characteristic information stored in the storage unit 51, the current imbalance during steady operation can be improved.
  • the delay control in the delay circuit unit 53 includes a delay due to digital control by the upper control circuit unit 6 and the like. A well-known technique can be applied.
  • this invention is not limited to the above-mentioned Example, Various modifications are included.
  • the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations.
  • a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment.
  • SYMBOLS 1 Power semiconductor element drive circuit, 2 ... Upper arm power semiconductor element, 3 ... Lower arm power semiconductor element, 4 ... Upper arm drive circuit 4, 5 ... Lower arm drive circuit, 6 ... Upper control circuit part, 10 (10 -1, 10-2) ... power module, 11 (11-1, 11-2) ... power conversion unit, 20 ... control board, 30 ... power conversion device, 51 ... storage unit (storage device), 53 ... delay circuit 54, gate voltage slope variable circuit, 55 ... gate voltage variable circuit, 61 (61-1, 61-2) ... current sensor, 62 (62-1, 62-2) ... current calculator

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  • Power Conversion In General (AREA)
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PCT/JP2016/072465 2015-08-26 2016-08-01 パワー半導体素子の駆動回路、電力変換ユニットおよび電力変換装置 WO2017033673A1 (ja)

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