WO2017024607A1 - 一种液晶显示面板 - Google Patents

一种液晶显示面板 Download PDF

Info

Publication number
WO2017024607A1
WO2017024607A1 PCT/CN2015/087588 CN2015087588W WO2017024607A1 WO 2017024607 A1 WO2017024607 A1 WO 2017024607A1 CN 2015087588 W CN2015087588 W CN 2015087588W WO 2017024607 A1 WO2017024607 A1 WO 2017024607A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
pixel
pixels
row
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/087588
Other languages
English (en)
French (fr)
Inventor
杜鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to JP2018506859A priority Critical patent/JP6531219B2/ja
Priority to GB1802170.9A priority patent/GB2557760B/en
Priority to US14/891,744 priority patent/US9958743B2/en
Priority to EA201890474A priority patent/EA035140B1/ru
Priority to KR1020187006812A priority patent/KR102054412B1/ko
Publication of WO2017024607A1 publication Critical patent/WO2017024607A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel.
  • the prior art generally divides a pixel into two regions, as shown in FIG. 1, including a main pixel region 101 and a sub-pixel region 102, to improve the problem of large-view character bias.
  • a main pixel region 101 Mainn
  • the brightness of the sub-pixel area (Sub) 102 is low, thereby improving the problem of the large-view character bias of the panel.
  • the main pixel area accounts for about 40% of the pixel opening area
  • the Sub area accounts for about 60% of the pixel opening area.
  • the transmittance of the entire pixel is greatly reduced, and the work of the backlight is increased. Consumption.
  • the scan line includes a first branch and a second branch; the first branch is located at an upper edge of the pixel, and the second branch is located at a lower edge of the pixel;
  • the first branch and the second branch respectively correspond to positions at the junction of two adjacent pixels;
  • the pixel comprising a main pixel and a sub-pixel, the main pixel and the sub-pixel being disposed adjacent to each other;
  • the main pixel is correspondingly provided with a first main thin film transistor and a second main thin film transistor, and a first capacitor;
  • a control end of the first main thin film transistor located in the nth row of pixels is connected to one of the scan lines corresponding to the nth row of pixels;
  • a control end of the second main thin film transistor located in the nth row of pixels is connected to a first branch of the scan line corresponding to the n+1th row of pixels;
  • a control end of the auxiliary thin film transistor located in the n+1th row of pixels is connected to one of the scan lines corresponding to the n+1th row of pixels;
  • An input end of the first main thin film transistor is connected to the data line, an output end of the first main thin film transistor is connected to the first capacitor; an output end of the first main thin film transistor is further connected to the second main An input terminal of the thin film transistor;
  • n is greater than or equal to 2 and is a positive integer
  • the sub-pixels are correspondingly provided with a first auxiliary thin film transistor and a second auxiliary thin film transistor;
  • An input end of the first auxiliary thin film transistor is connected to the data line, an output end of the first auxiliary thin film transistor is connected to the second capacitor; an output end of the first auxiliary thin film transistor is further connected to the second auxiliary An input end of the thin film transistor; a control end of the second auxiliary thin film transistor located in the n+1th row of pixels is connected to a second branch of the scan line corresponding to the nth row of pixels.
  • the control end of the first main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line corresponding to the nth row of pixels; a control end of the first auxiliary thin film transistor of n pixels adjacent to the pixel is connected to the second branch of the scan line corresponding to the nth row of pixels;
  • the control end of the second main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line corresponding to the n+1th row of pixels; the nth row and the pixel are located a control end of the second auxiliary thin film transistor of an adjacent pixel is connected to the second branch of the scan line corresponding to the n-1th row of pixels;
  • a control end of the first auxiliary thin film transistor located in the n+1th row of pixels is connected to the second branch of the scan line corresponding to the n+1th row of pixels; at the n+1th row and the pixel A control end of the first main thin film transistor of an adjacent pixel is connected to the first branch of the scan line corresponding to the n+1th row of pixels.
  • the control end of the first main thin film transistor located in the nth row of pixels is connected to the second branch of the scan line corresponding to the nth row of pixels; a control end of the first auxiliary thin film transistor located in the nth row adjacent to the pixel is connected to the first branch of the scan line corresponding to the nth row of pixels;
  • the control end of the second main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line corresponding to the n+1th row of pixels; the nth row is adjacent to the pixel a control end of the second auxiliary thin film transistor of the pixel is connected to the second branch of the scan line corresponding to the n-1th row of pixels;
  • a control end of the first auxiliary thin film transistor located in the n+1th row of pixels is connected to the first branch of the scan line corresponding to the n+1th row of pixels; located in an n+1th row A control end of the first main thin film transistor of the pixel adjacent to the pixel is connected to the second branch of the scan line corresponding to the n+1th row of pixels.
  • the output end of the second main thin film transistor is connected to the third capacitor
  • An output end of the second auxiliary thin film transistor is connected to the fourth capacitor.
  • the liquid crystal display panel includes a common electrode, an output end of the second main thin film transistor is connected to the common electrode, and an output end of the second auxiliary thin film transistor is also connected to the common electrode .
  • the display brightness of the main pixel is smaller than the display brightness of the sub-pixel
  • the display brightness of the main pixel is greater than or equal to the display brightness of the sub-pixel.
  • the present invention constructs a liquid crystal display panel, which includes:
  • the scan line includes a first branch and a second branch; the first branch is located at an upper edge of the pixel, and the second branch is located at a lower edge of the pixel;
  • the pixel comprising a main pixel and a sub-pixel, the main pixel and the sub-pixel being disposed adjacent to each other;
  • the main pixel is correspondingly provided with a first main thin film transistor and a second main thin film transistor, and a first capacitor;
  • the sub-pixel is correspondingly provided with at least one auxiliary thin film transistor and a second capacitor;
  • a control end of the first main thin film transistor located in the nth row of pixels is connected to one of the scan lines corresponding to the nth row of pixels;
  • a control end of the second main thin film transistor located in the nth row of pixels is connected to a first branch of the scan line corresponding to the n+1th row of pixels;
  • a control end of the auxiliary thin film transistor located in the n+1th row of pixels is connected to one of the scan lines corresponding to the n+1th row of pixels;
  • An input end of the first main thin film transistor is connected to the data line, an output end of the first main thin film transistor is connected to the first capacitor; an output end of the first main thin film transistor is further connected to the second main An input terminal of the thin film transistor;
  • n is greater than or equal to 2 and is a positive integer.
  • the sub-pixels are correspondingly provided with a first auxiliary thin film transistor and a second auxiliary thin film transistor;
  • An input end of the first auxiliary thin film transistor is connected to the data line, an output end of the first auxiliary thin film transistor is connected to the second capacitor; an output end of the first auxiliary thin film transistor is further connected to the second auxiliary An input end of the thin film transistor; a control end of the second auxiliary thin film transistor located in the n+1th row of pixels is connected to a second branch of the scan line corresponding to the nth row of pixels.
  • the control end of the first main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line corresponding to the nth row of pixels; a control end of the first auxiliary thin film transistor of n pixels adjacent to the pixel is connected to the second branch of the scan line corresponding to the nth row of pixels;
  • the control end of the second main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line corresponding to the n+1th row of pixels; the nth row and the pixel are located a control end of the second auxiliary thin film transistor of an adjacent pixel is connected to the second branch of the scan line corresponding to the n-1th row of pixels;
  • a control end of the first auxiliary thin film transistor located in the n+1th row of pixels is connected to the second branch of the scan line corresponding to the n+1th row of pixels; at the n+1th row and the pixel A control end of the first main thin film transistor of an adjacent pixel is connected to the first branch of the scan line corresponding to the n+1th row of pixels.
  • the control end of the first main thin film transistor located in the nth row of pixels is connected to the second branch of the scan line corresponding to the nth row of pixels; a control end of the first auxiliary thin film transistor located in the nth row adjacent to the pixel is connected to the first branch of the scan line corresponding to the nth row of pixels;
  • the control end of the second main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line corresponding to the n+1th row of pixels; the nth row is adjacent to the pixel a control end of the second auxiliary thin film transistor of the pixel is connected to the second branch of the scan line corresponding to the n-1th row of pixels;
  • a control end of the first auxiliary thin film transistor located in the n+1th row of pixels is connected to the first branch of the scan line corresponding to the n+1th row of pixels; located in an n+1th row A control end of the first main thin film transistor of the pixel adjacent to the pixel is connected to the second branch of the scan line corresponding to the n+1th row of pixels.
  • the liquid crystal display panel includes a common electrode, the main pixel is further provided with a third capacitor; the sub-pixel is further provided with a fourth capacitor;
  • the output end of the second main thin film transistor is connected to the third capacitor
  • An output end of the second auxiliary thin film transistor is connected to the fourth capacitor.
  • the liquid crystal display panel includes a common electrode, an output end of the second main thin film transistor is connected to the common electrode, and an output end of the second auxiliary thin film transistor is also connected to the common electrode .
  • the sub-pixels are provided with only one of the auxiliary thin film transistors;
  • the control end of the first main thin film transistor located in the nth row of pixels is connected to the second branch of the scan line corresponding to the nth row of pixels; the pixel located adjacent to the pixel in the nth row The control end of the auxiliary thin film transistor is connected to the first branch of the scan line corresponding to the nth row of pixels;
  • a control end of the second main thin film transistor located in the nth row of pixels is connected to a first branch of the scan line corresponding to the n+1th row of pixels; and a pixel located in the n+1th row of pixels
  • the control end of the auxiliary thin film transistor is connected to the first branch of the scan line corresponding to the n+1th row of pixels; the first main film of the pixel adjacent to the pixel in the n+1th row
  • a control terminal of the transistor is connected to the second branch of the scan line corresponding to the n+1th row of pixels.
  • the liquid crystal display panel includes a common electrode, and the main pixel is further provided with a third capacitor;
  • An output end of the second main thin film transistor is connected to the third capacitor or the common electrode.
  • the first branch and the second branch respectively correspond to positions at the boundary of two adjacent pixels.
  • the display brightness of the main pixel is smaller than the display brightness of the sub-pixel
  • the display brightness of the main pixel is greater than or equal to the display brightness of the sub-pixel.
  • the liquid crystal display panel of the present invention improves the aperture ratio and display effect of the panel by rearranging the drive lines on the existing panel.
  • 1 is a schematic view showing the arrangement of pixels on a conventional liquid crystal display panel
  • FIG. 2 is a schematic structural view of a first type of a conventional liquid crystal display panel
  • Figure 3 is a schematic view showing the first display effect of Figure 2;
  • Figure 4 is a schematic view showing the second display effect of Figure 2;
  • FIG. 5 is a schematic structural view of a second liquid crystal display panel
  • FIG. 6 is a schematic structural view of a first liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a second liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a first liquid crystal display panel according to a second embodiment of the present invention.
  • FIG. 9 is a schematic structural view of a second liquid crystal display panel according to a second embodiment of the present invention.
  • FIG. 10 is a schematic structural view of a first liquid crystal display panel according to a third embodiment of the present invention.
  • FIG. 11 is a schematic structural view of a second liquid crystal display panel according to a third embodiment of the present invention.
  • Figure 12 is a schematic view showing one of the display effects of the third embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a first type of a conventional liquid crystal display panel.
  • the conventional liquid crystal display panel includes: a plurality of data lines D(n) to D(n+5), and a plurality of scanning lines G(n) to G(n+3), each pixel setting
  • One end of the output end of the first thin film transistor is connected to the pixel electrode, and the other end is connected to the first capacitor C1; the other end of the first capacitor C1 is connected to the common electrode;
  • An input end of the second thin film transistor of one of the pixels is connected to an output end of the first thin film transistor of the pixel adjacent to the pixel in the same column, and an output end of the second thin film transistor is connected to the second capacitor C2; the second capacitor C2 The other end is connected to the common electrode;
  • the first thin film transistor 23 and the second thin film transistor 24 are included;
  • the first thin film transistor 25 and the second thin film transistor 26 are included; the broken line frame indicates the line crossing, that is, the output end of the first thin film transistor 23 of the pixel 21 and the second thin film transistor
  • the input terminal of 24 is not connected, but is connected to the input end of the second thin film transistor 26 of the pixel 22.
  • the output end of the first thin film transistor 25 of the opposite pixel 22 is not connected to the input end of the second thin film transistor 26, but with the pixel.
  • the input terminals of the second thin film transistors 24 of 21 are connected.
  • the scanning line G(n) of the nth row is turned on first, so that the first thin film transistor 23 of the pixel 21 is closed, and the pixel 21 is charged, at which time the second thin film transistor 24 is also closed.
  • the n+1th row scan line G(n+1) is turned on, the first thin film transistor 25 of the pixel 22 is closed, and the pixel 22 is charged; at this time, the second thin film transistor 26 is also closed, due to the second film of the pixel 22.
  • the input end of the transistor 26 is connected to the output end of the first thin film transistor 23 of the pixel 21 such that the voltage of the pixel electrode of the pixel 21 is shared to the second capacitance C2 of the pixel 22, so that the brightness of the pixel 21 is lowered;
  • the second thin film transistor 24 of the pixel 21 is turned off, and after the pixel electrode of the pixel 22 is charged, it is not pulled down by the second capacitor C2 of the pixel 21, so the pixel 22 maintains a high brightness.
  • the display effect diagram of the display panel is as shown in FIG. 3, and the arrow direction in FIG. 3 indicates the scanning direction.
  • 201 denotes a red pixel
  • 202 denotes a green pixel
  • 203 denotes a green pixel
  • H and L denote luminance levels.
  • the scan line G(n+1) of the n+1th row is turned on first, so that the first thin film transistor 25 of the pixel 22 is closed, and the pixel 22 is charged, and at this time, the second thin film transistor 26 is charged. Also closed.
  • the nth row of scan lines G(n) is turned on, the first thin film transistor 23 of the pixel 21 is closed, and the pixel 21 is charged; at this time, the second thin film transistor 24 is also closed, due to the input of the second thin film transistor 24 of the pixel 21.
  • FIG. 5 is a schematic structural diagram of a second liquid crystal display panel.
  • the display panel in FIG. 5 is different from that in FIG. 2 in that the output end of the second thin film transistor of each pixel is no longer connected to the second capacitor, but is directly connected to the common electrode, and the potential of the pixel electrode is made by resistance division. Was pulled low.
  • the above two display panels are as shown by the dashed box in FIG. 2 or 5, and the input end of the second thin film transistor of each pixel is connected to the first thin film transistor of the pixel adjacent to the pixel in the same column by the cross-line manner.
  • the output is connected; since the via is required to make a via, it takes up more space and affects the aperture ratio of the pixel; it also causes dark lines inside the pixel.
  • FIG. 6-7 is a schematic structural diagram of a liquid crystal display panel according to a first embodiment of the present invention.
  • the first liquid crystal display panel of the present invention includes: a plurality of data lines D(n) to D(n+5) and a plurality of scanning lines G(n) to G(n+3),
  • the data line is used to input a data signal; wherein n is greater than or equal to 2 and is a positive integer;
  • the scan line is for inputting a scan signal;
  • the scan line includes a first branch and a second branch; the first branch is located at an upper edge of the pixel, and the second branch is located at a lower edge of the pixel;
  • the pixel comprising a main pixel 31 and a sub-pixel 32, the main pixel 31 and the sub-pixel 32 being disposed adjacent to each other;
  • the main pixel 31 is provided with a first main thin film transistor T1 and a second main thin film transistor T2, and a first capacitor C1.
  • the sub-pixel 32 is provided with a first auxiliary thin film transistor T3 and a second auxiliary thin film transistor T4. Two capacitors C2;
  • a control end of the first main thin film transistor located in the nth row of pixels is connected to a first branch of the scan line G(n) corresponding to the nth row of pixels; a pixel adjacent to the pixel in the nth row The control end of the first auxiliary thin film transistor is connected to the second branch of the scan line G(n) corresponding to the nth row of pixels;
  • a control end of the second main thin film transistor located in the nth row of pixels is connected to a first branch of the scan line G(n+1) corresponding to the n+1th row of pixels; a control end of the second auxiliary thin film transistor of the pixel adjacent to the pixel is connected to the second branch of the scan line corresponding to the n-1th row of pixels;
  • a control end of the first auxiliary thin film transistor located in the n+1th row of pixels is connected to a second branch of the scan line G(n+1) corresponding to the n+1th row of pixels; at the n+1th A control end of the first main thin film transistor that is adjacent to the pixel is connected to the first branch of the scan line G(n+1) corresponding to the n+1th row of pixels.
  • An input end of the first main thin film transistor T1 is connected to the data line, an output end of the first main thin film transistor T1 is connected to the first capacitor C1; and an output end of the first main thin film transistor T1 is further connected to the An input end of the second main thin film transistor T2;
  • An input end of the first auxiliary thin film transistor T3 is connected to the data line, an output end of the first auxiliary thin film transistor T3 is connected to the second capacitor C2; and an output end of the first auxiliary thin film transistor T3 is further connected
  • the input end of the second auxiliary thin film transistor T4; the control end of the second auxiliary thin film transistor T4 located in the n+1th row of pixels is connected to the second of the scan line G(n) corresponding to the nth row of pixels Branch.
  • the liquid crystal display panel includes a common electrode, an output end of the second main thin film transistor T2 is connected to the common electrode, and an output end of the second auxiliary thin film transistor T4 is also connected to the common electrode.
  • the scanning line G(n) of the nth row is first turned on, so that the first main thin film transistor T1 of the main pixel 31 is closed, and the main pixel 31 is charged, and the second auxiliary film is at this time.
  • Transistor T4 is also closed.
  • the n+1th row scan line G(n+1) is turned on, the first auxiliary thin film transistor T3 of the subpixel 32 is closed, and the subpixel 32 is charged; at this time, the second main thin film transistor T2 is also closed.
  • the input end of the second main thin film transistor T2 of the main pixel 31 is connected to the output end of the first main thin film transistor T1 of the main pixel 31, so that the voltage of the pixel electrode of the main pixel 31 passes through the second main film.
  • the transistor T2 is shared on the common electrode such that the brightness of the main pixel 31 is lowered; meanwhile, since the scan line of the nth row is turned off at this time, the second auxiliary thin film transistor T4 of the sub-pixel 32 is turned off. After the pixel electrode of the sub-pixel 32 is charged, it is not pulled low by the second auxiliary thin film transistor T4, so the sub-pixel 32 maintains a high brightness, that is, the brightness of the main pixel 31 is smaller than that of the sub-pixel 32. brightness.
  • the display effect diagram of the display panel is as shown in FIG. 3, and the arrow direction in FIG. 3 indicates the scanning direction.
  • the scan line G(n+1) of the n+1th row is turned on first, so that the first auxiliary thin film transistor T3 of the sub-pixel 32 is closed, and the sub-pixel 32 is charged.
  • the second main thin film transistor T2 is also closed.
  • the first main thin film transistor T1 of the main pixel 31 is closed, and the main pixel 31 is charged; at this time, the second auxiliary thin film transistor T4 is also closed, due to the An input end of the second auxiliary thin film transistor T4 of the sub-pixel 32 is connected to an output end of the first auxiliary thin film transistor T3 of the sub-pixel 32 such that a voltage of a pixel electrode of the sub-pixel 32 is shared by the second auxiliary thin film transistor T4 On the common electrode, the brightness of the sub-pixel 32 is lowered; meanwhile, since the scan line of the n+1th row is turned off at this time, the second main thin film transistor T2 of the main pixel 31 is turned off, for the main After the pixel electrode of the pixel 31 is charged, it is not pulled down by the second main thin film transistor T2, and thus the main pixel 31 maintains a high luminance. That is, the brightness of the main pixel is greater than the brightness of the sub-pixel.
  • FIG. 7 is a schematic view showing a second structure of a liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 7 and FIG. 6 are different in that: the main pixel is further provided with a third capacitor C3; Fourth capacitor C4;
  • the voltage of the pixel electrode of the main pixel 31 is shared onto the third capacitor C3, so that the brightness of the main pixel 31 is lowered;
  • the voltage of the pixel electrode of the sub-pixel 32 is shared onto the fourth capacitor C4, so that the luminance of the sub-pixel 32 is lowered.
  • the control terminal connection of the thin film transistor for performing charge sharing is connected to one of the scan line branches of the previous row or the next row closest to the control terminal, thereby avoiding the trace Crossing occurs inside the pixel opening area, which improves the aperture ratio of the panel, avoids dark lines, and improves the display effect.
  • FIG. 8-9 is a schematic structural diagram of a liquid crystal display panel according to a second embodiment of the present invention.
  • the liquid crystal display panel of the present invention includes: a plurality of data lines D(n) to D(n+5) and a plurality of scanning lines G(n) to G(n+3), the data lines For inputting data signals;
  • the scan line is for inputting a scan signal;
  • the scan line includes a first branch and a second branch; the first branch is located at an upper edge of the pixel, and the second branch is located at a lower edge of the pixel;
  • the pixel comprising a main pixel 41 and a sub-pixel 42 , the main pixel 41 and the sub-pixel 42 being disposed adjacent to each other;
  • the main pixel 41 is correspondingly provided with a first main thin film transistor T1 and a second main thin film transistor T2, and a first capacitor C1;
  • the sub-pixel 42 is correspondingly provided with a first auxiliary thin film transistor T3 and a second auxiliary thin film transistor T4, Two capacitors C2;
  • a control end of the first main thin film transistor T1 located in the nth row of pixels is connected to the second branch of the scan line G(n) corresponding to the nth row of pixels; and located in the nth row and the pixel a control end of the first auxiliary thin film transistor T1 of an adjacent pixel is connected to the first branch of the scan line G(n) corresponding to the nth row of pixels;
  • the control end of the second main thin film transistor located in the nth row of pixels is connected to the first branch of the scan line G(n+1) corresponding to the n+1th row of pixels; the nth row and the pixel are located a control end of the second auxiliary thin film transistor of an adjacent pixel is connected to the second branch of the scan line corresponding to the n-1th row of pixels;
  • a control end of the first auxiliary thin film transistor located in the n+1th row of pixels is connected to the first branch of the scan line G(n+1) corresponding to the n+1th row of pixels;
  • a control end of the first main thin film transistor of a pixel adjacent to the pixel in the +1 row is connected to the second branch of the scan line corresponding to the n+1th row of pixels.
  • An input end of the first main thin film transistor T1 is connected to the data line, an output end of the first main thin film transistor T1 is connected to the first capacitor C1; and an output end of the first main thin film transistor T1 is further connected to the An input end of the second main thin film transistor T2;
  • An input end of the first auxiliary thin film transistor T3 is connected to the data line, an output end of the first auxiliary thin film transistor T3 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to a common electrode.
  • the output end of the first auxiliary thin film transistor T1 is further connected to the input end of the second auxiliary thin film transistor T2; the control end of the second auxiliary thin film transistor T2 located in the n+1th line pixel is connected to the nth row of pixels Corresponding to the second branch of the scan line G(n).
  • the liquid crystal display panel includes a common electrode, an output end of the second main thin film transistor T2 is connected to the common electrode, and an output end of the second auxiliary thin film transistor T4 is also connected to the common electrode.
  • the scanning line G(n) of the nth row is first turned on, so that the first main thin film transistor T1 of the main pixel 41 is closed, and the main pixel 41 is charged, and the second auxiliary film is at this time.
  • Transistor T4 is also closed.
  • the n+1th row scan line G(n+1) is turned on, the first auxiliary thin film transistor T3 of the subpixel 42 is closed, and the subpixel 42 is charged; at this time, the second main thin film transistor T2 is also closed.
  • the input end of the second main thin film transistor T2 of the main pixel 41 is connected to the output end of the first main thin film transistor T1 of the main pixel 41, so that the voltage of the pixel electrode of the main pixel 41 passes through the second main film.
  • the transistor T2 is shared on the common electrode such that the brightness of the main pixel 41 is lowered; meanwhile, since the scan line of the nth row is turned off at this time, the second auxiliary thin film transistor T4 of the sub-pixel 42 is turned off. After the pixel electrode of the sub-pixel 42 is charged, it is not pulled low by the second auxiliary thin film transistor T4, so the sub-pixel 42 maintains a high brightness, that is, the brightness of the main pixel 41 is smaller than that of the sub-pixel 42. brightness.
  • the display effect diagram of the display panel is as shown in FIG. 3, and the arrow direction in FIG. 3 indicates the scanning direction.
  • the scanning line G(n+1) of the n+1th row is turned on first.
  • the first auxiliary thin film transistor T3 of the sub-pixel 42 is closed, and the sub-pixel 42 is charged, at which time the second main thin film transistor T2 is also closed.
  • the second auxiliary thin film transistor T4 is also closed, due to the An input end of the second auxiliary thin film transistor T4 of the sub-pixel 42 is connected to an output end of the first auxiliary thin film transistor T3 of the sub-pixel 42 such that a voltage of a pixel electrode of the sub-pixel 42 is shared by the second auxiliary thin film transistor T4
  • the brightness of the sub-pixel 42 is lowered; meanwhile, since the scan line of the n+1th row is turned off at this time, the second main thin film transistor T2 of the main pixel 41 is turned off, for the main After the pixel electrode of the pixel 41 is charged, it is not pulled down by the second
  • FIG. 9 is a schematic view showing a second structure of a liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 9 and FIG. 8 are different in that: the main pixel 41 is further provided with a third capacitor C3; Set a fourth capacitor C4;
  • the voltage of the pixel electrode of the main pixel 41 is shared onto the third capacitor C3, so that the brightness of the main pixel 41 is lowered;
  • the voltage of the pixel electrode of the sub-pixel 42 is shared onto the fourth capacitor C4, so that the luminance of the sub-pixel 42 is lowered.
  • both TFTs of the main pixel and the two TFTs of the sub-pixel in the second embodiment are located on the same side of the pixel, the aperture ratio can be better improved as compared with the first embodiment.
  • such a wiring structure is such that the positions of the first branch and the second branch correspond to the position of the boundary of two adjacent pixels, since a black matrix is disposed at the boundary of two adjacent pixels, The interface is blocked by the black matrix, so although the number of scanning lines is increased, the aperture ratio of the pixel is not affected at all, and the display effect is better improved.
  • FIG. 10-11 is a schematic structural diagram of a liquid crystal display panel according to a third embodiment of the present invention.
  • the liquid crystal display panel of the present invention includes: a plurality of data lines D(n) to D(n+5) and a plurality of scanning lines G(n) to G(n+3), the data lines For inputting data signals;
  • the scan line is for inputting a scan signal;
  • the scan line includes a first branch and a second branch; the first branch is located at an upper edge of the pixel, and the second branch is located at a lower edge of the pixel;
  • the pixel comprising a main pixel 51 and a sub-pixel 52, the main pixel 51 and the sub-pixel 52 being disposed adjacent to each other;
  • the main pixel 51 is correspondingly provided with a first main thin film transistor T1 and a second main thin film transistor T2, a first capacitor C1;
  • the sub-pixel 52 is correspondingly provided with an auxiliary thin film transistor T3 and a second capacitor C2;
  • a control end of the first main thin film transistor T1 located in the nth row of pixels is connected to the second branch of the scan line G(n) corresponding to the nth row of pixels; and located in the nth row and the pixel a control end of the auxiliary thin film transistor T3 of an adjacent pixel is connected to the first branch of the scan line G(n) corresponding to the nth row of pixels;
  • a control end of the second main thin film transistor located in the nth row of pixels is connected to a first branch of the scan line G(n+1) corresponding to the n+1th row of pixels;
  • the control end of the auxiliary thin film transistor located in the n+1th row of pixels is connected to the first branch of the scan line G(n+1) corresponding to the n+1th row of pixels; the n+1th row is The control end of the first main thin film transistor of the pixel adjacent to the pixel is connected to the second branch of the scan line G(n+1) corresponding to the n+1th row of pixels.
  • An input end of the first main thin film transistor is connected to the data line, an output end of the first main thin film transistor is connected to the first capacitor C1; an output end of the first main thin film transistor is further connected to the second An input terminal of the main thin film transistor;
  • the input end of the auxiliary thin film transistor is connected to the data line, the output end of the auxiliary thin film transistor is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the common electrode.
  • the liquid crystal display panel includes a common electrode, and an output end of the second main thin film transistor T2 is connected to the common electrode.
  • the scanning line G(n) of the nth row is first turned on, so that the first main thin film transistor T1 of the main pixel 51 is closed, and the main pixel 51 is charged.
  • the n+1th row scan line G(n+1) is turned on, the auxiliary thin film transistor T3 of the subpixel 52 is closed, and the subpixel 52 is charged; at this time, the second main thin film transistor T2 is also closed due to An input end of the second main thin film transistor T2 of the main pixel 51 is connected to an output end of the first main thin film transistor T1 of the main pixel 51 such that a voltage of a pixel electrode of the main pixel 51 passes through the second main thin film transistor T2 Sharing on the common electrode causes the brightness of the main pixel 51 to decrease; meanwhile, since the output terminal of the auxiliary thin film transistor is not connected to the sub-thin film transistor for voltage sharing, the pixel electrode of the sub-pixel 52 is charged It is not pulled low, so the sub-pixel 52 maintains a high
  • the scanning line G(n+1) of the n+1th row is turned on first.
  • the auxiliary thin film transistor T3 of the sub-pixel 52 is closed, and the sub-pixel 52 is charged, at which time the second main thin film transistor T2 is also closed.
  • the nth row of scan lines G(n) is turned on, the first main thin film transistor T1 of the main pixel 51 is closed, and the main pixel 51 is charged; meanwhile, since the scan line of the n+1th row has been Turning off, the second main thin film transistor T2 of the main pixel 51 is turned off, and after charging the pixel electrode of the main pixel 51, it is not pulled down by the second main thin film transistor T2, so the main pixel 51 maintains a high brightness. That is, the brightness of the main pixel is equal to the brightness of the sub-pixel.
  • the display effect diagram of the display panel is as shown in FIG. 12, and the arrow direction in FIG. 12 indicates the scanning direction.
  • FIG. 11 is a schematic view showing a second structure of a liquid crystal display panel according to a first embodiment of the present invention.
  • FIG. 11 and FIG. 10 are different in that the main pixel 41 is further provided with a third capacitor C3.
  • the voltage of the pixel electrode of the main pixel 51 is shared onto the third capacitor C3, so that the luminance of the main pixel 51 is lowered.
  • both TFTs of the main pixel and the two TFTs of the sub-pixel in the second embodiment are located on the same side of the pixel, the aperture ratio can be better improved as compared with the first embodiment.
  • the positions of the first branch and the second branch correspond to the position of the boundary of two adjacent pixels, and the black matrix is disposed at the boundary of the adjacent two pixels, and the boundary is blocked by the black matrix Therefore, although the number of scanning lines is increased, the aperture ratio of the pixels is not affected.
  • This technical solution is equally applicable to other embodiments.
  • the control terminal connection of the thin film transistor for performing charge sharing is connected to one of the scan line branches of the previous row or the next row closest to the control terminal, thereby avoiding the trace Crossing occurs inside the pixel opening area, which improves the aperture ratio of the panel, avoids dark lines, and improves the display effect.
  • the liquid crystal display panel of the present invention improves the aperture ratio and display effect of the panel by rearranging the drive lines on the existing panel.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示面板，其包括：位于第n行像素(21,31,41,51)的第一主薄膜晶体管(T1)的控制端与第n行像素(21,31,41,51)对应的扫描线(G(n))的其中一个分支连接；位于第n行像素(21,31,41,51)的第二主薄膜晶体管(T2)的控制端与第n+1行的扫描线(G(n+1))的第一分支连接；位于第n+1行像素(22,32,42,52)的辅助薄膜晶体管(T3)的控制端与第n+1行扫描线(G(n+1))的其中一个分支连接。

Description

一种液晶显示面板 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种液晶显示面板。
 背景技术
传统的VA（ Vertical Alignment，垂直配向技术）液晶显示面板，在大视角观看时，往往会出现色偏的问题。现有技术一般是将像素分为两个区，如图1所示，包括主像素区101和子像素区102，来改善大视角色偏的问题。在面板输入相同灰阶信号时，，主像素区101（Main）的亮度较高，子像素区（Sub）102的亮度较低，以此来改善面板的大视角色偏问题。主像素区占像素开口区的40%左右，Sub区占像素开口区的60%左右，但由于Sub区的面积较大，导致整个像素的穿透率会大幅度下降，同时增加了背光的功耗。
因此，有必要提供一种液晶显示面板，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶显示面板，以解决现有液晶显示面板开口率较低的技术问题。
 技术解决方案
多条数据线，用于输入数据信号；
多条扫描线，用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；且所述第一分支和所述第二分支分别与相邻两个所述像素的交界处的位置相对应；以及
多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素和子像素，所述主像素和所述子像素相邻设置；
所述主像素对应设置有第一主薄膜晶体管和第二主薄膜晶体管、第一电容；
位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的其中一个分支连接；
位于所述第n行像素的所述第二主薄膜晶体管的控制端与第n+1行像素对应的所述扫描线的第一分支连接；
位于第n+1行像素的所述辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的其中一个分支连接；
所述第一主薄膜晶体管的输入端连接所述数据线，所述第一主薄膜晶体管的输出端连接所述第一电容；所述第一主薄膜晶体管的输出端还连接所述第二主薄膜晶体管的输入端；
所述辅助薄膜晶体管的输入端连接所述数据线，所述辅助薄膜晶体管的输出端连接所述第二电容，其中n大于等于2，且为正整数；
所述子像素对应设置有第一辅助薄膜晶体管和第二辅助薄膜晶体管；
所述第一辅助薄膜晶体管的输入端连接所述数据线，所述第一辅助薄膜晶体管的输出端连接所述第二电容；所述第一辅助薄膜晶体管的输出端还连接所述第二辅助薄膜晶体管的输入端；位于第n+1行像素的所述第二辅助薄膜晶体管的控制端连接所述第n行像素对应的所述扫描线的第二分支。
在本发明的液晶显示面板中，所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；
所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于所述第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
位于第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接。
在本发明的液晶显示面板中，所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；所述位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；
所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
位于所述第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
在本发明的液晶显示面板中，所述主像素还设置有第三电容；所述子像素还设置有第四电容；
所述第二主薄膜晶体管的输出端连接所述第三电容；
所述第二辅助薄膜晶体管的输出端连接所述第四电容。
在本发明的液晶显示面板中，所述液晶显示面板包括公共电极，所述第二主薄膜晶体管的输出端连接所述公共电极，所述第二辅助薄膜晶体管的输出端也连接所述公共电极。
在本发明的液晶显示面板中，当所述液晶显示面板从上到下进行扫描时，所述主像素的显示亮度小于所述子像素的显示亮度；
当所述液晶显示面板从下到上进行扫描时，所述主像素的显示亮度大于或等于所述子像素的显示亮度。
为解决上述技术问题，本发明构造了一种液晶显示面板，其包括：
多条数据线，用于输入数据信号；
多条扫描线，用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；
多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素和子像素，所述主像素和所述子像素相邻设置；
所述主像素对应设置有第一主薄膜晶体管和第二主薄膜晶体管、第一电容；所述子像素对应设置有至少一个辅助薄膜晶体管、第二电容；
位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的其中一个分支连接；
位于所述第n行像素的所述第二主薄膜晶体管的控制端与第n+1行像素对应的所述扫描线的第一分支连接；
位于第n+1行像素的所述辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的其中一个分支连接；
所述第一主薄膜晶体管的输入端连接所述数据线，所述第一主薄膜晶体管的输出端连接所述第一电容；所述第一主薄膜晶体管的输出端还连接所述第二主薄膜晶体管的输入端；
所述辅助薄膜晶体管的输入端连接所述数据线，所述辅助薄膜晶体管的输出端连接所述第二电容，其中n大于等于2，且为正整数。
在本发明的液晶显示面板中，所述子像素对应设置有第一辅助薄膜晶体管和第二辅助薄膜晶体管；
所述第一辅助薄膜晶体管的输入端连接所述数据线，所述第一辅助薄膜晶体管的输出端连接所述第二电容；所述第一辅助薄膜晶体管的输出端还连接所述第二辅助薄膜晶体管的输入端；位于第n+1行像素的所述第二辅助薄膜晶体管的控制端连接所述第n行像素对应的所述扫描线的第二分支。
在本发明的液晶显示面板中，所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；
所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于所述第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
位于第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接。
在本发明的液晶显示面板中，所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；所述位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；
所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
位于所述第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
在本发明的液晶显示面板中，所述液晶显示面板包括公共电极，所述主像素还设置有第三电容；所述子像素还设置有第四电容；
所述第二主薄膜晶体管的输出端连接所述第三电容；
所述第二辅助薄膜晶体管的输出端连接所述第四电容。
在本发明的液晶显示面板中，所述液晶显示面板包括公共电极，所述第二主薄膜晶体管的输出端连接所述公共电极，所述第二辅助薄膜晶体管的输出端也连接所述公共电极。
在本发明的液晶显示面板中，所述子像素对应仅设置有一个所述辅助薄膜晶体管；
所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；位于第n行与该像素相邻的像素的所述辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；
位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于所述第n+1行像素的所述辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
在本发明的液晶显示面板中，所述液晶显示面板包括公共电极，所述主像素还设置有第三电容；
所述第二主薄膜晶体管的输出端连接所述第三电容或者公共电极。
在本发明的液晶显示面板中，所述第一分支和所述第二分支分别与相邻两个所述像素的交界处的位置相对应。
在本发明的液晶显示面板中，当所述液晶显示面板从上到下进行扫描时，所述主像素的显示亮度小于所述子像素的显示亮度；
当所述液晶显示面板从下到上进行扫描时，所述主像素的显示亮度大于或等于所述子像素的显示亮度。
 有益效果
本发明的液晶显示面板，通过对现有的面板上的驱动线路进行重新布局，提高面板的开口率以及显示效果。
 附图说明
图1为现有液晶显示面板上像素的排布示意图；
图2为现有液晶显示面板第一种的结构示意图；
图3为图2第一种显示效果示意图；
图4为图2第二种显示效果示意图；
图5为现有液晶显示面板第二种的结构示意图；
图6为本发明第一实施例的第一种液晶显示面板的结构示意图；
图7为本发明第一实施例的第二种液晶显示面板的结构示意图；
图8为本发明第二实施例的第一种液晶显示面板的结构示意图；
图9为本发明第二实施例的第二种液晶显示面板的结构示意图；
图10为本发明第三实施例的第一种液晶显示面板的结构示意图；
图11为本发明第三实施例的第二种液晶显示面板的结构示意图；
图12为本发明第三实施例的其中一种显示效果示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为现有液晶显示面板第一种的结构示意图。
如图2所示，现有的液晶显示面板包括：多条数据线D(n)至D(n+5)，多条扫描线G(n)至G(n+3)，每个像素设置有两个薄膜晶体管，包括第一薄膜晶体管和第二薄膜晶体管，第一薄膜晶体管的输出端的一端接像素电极，另一端接第一电容C1；第一电容C1的另一端接公共电极；
其中一个像素的第二薄膜晶体管的输入端与位于同一列中与该像素相邻的像素的第一薄膜晶体管的输出端连接，第二薄膜晶体管的输出端连接第二电容C2；第二电容C2的另一端接公共电极；
以第一行第一列的像素21为例，其包括第一薄膜晶体管23和第二薄膜晶体管24；
以第二行第一列的像素22为例，其包括第一薄膜晶体管25和第二薄膜晶体管26；虚线框表示跨线，即像素21的第一薄膜晶体管23的输出端与第二薄膜晶体管24的输入端不连接，但与像素22的第二薄膜晶体管26的输入端连接，同理像素22的第一薄膜晶体管25的输出端与第二薄膜晶体管26的输入端不连接，但与像素21的第二薄膜晶体管24的输入端连接。
当从上到下进行扫描时，第n行的扫描线G(n)先打开，使得像素21的第一薄膜晶体管23闭合，对像素21进行充电，此时第二薄膜晶体管24也闭合。当第n+1行扫描线G(n+1)打开时，使得像素22的第一薄膜晶体管25闭合，对像素22充电；此时第二薄膜晶体管26也闭合，由于像素22的第二薄膜晶体管26的输入端连接像素21的第一薄膜晶体管23的输出端，使得像素21的像素电极的电压分享到所述像素22的第二电容C2上，使得像素21的亮度降低；同时，由于此时第n行的扫描线已关闭，使得像素21的第二薄膜晶体管24断开，所述像素22的像素电极进行充电后，不会被所述像素21的第二电容C2拉低，因此像素22维持较高的亮度。所述显示面板的显示效果图如图3所示，图3中的箭头方向表示扫描方向。图3中201表示红色像素、202表示绿色像素、203表示绿色像素，H、L表示亮度高低。
当从下到上进行扫描时，第n+1行的扫描线G(n+1)先打开，使得像素22的第一薄膜晶体管25闭合，对像素22进行充电，此时第二薄膜晶体管26也闭合。当第n行扫描线G(n)打开时，使得像素21的第一薄膜晶体管23闭合，对像素21充电；此时第二薄膜晶体管24也闭合，由于像素21的第二薄膜晶体管24的输入端连接像素22的第一薄膜晶体管25的输出端，使得像素22的像素电极的电压被分享到所述像素21的第二电容C2上，使得像素22的亮度降低；同时，由于此时第n+1行的扫描线已关闭，使得像素22的第二薄膜晶体管26断开，所述像素21的像素电极进行充电后，不会被所述像素22的第二电容C2拉低，因此像素21维持较高的亮度；所述显示面板的显示效果图如图4所示，图4中的箭头方向表示扫描方向。图4中201表示红色像素、202表示绿色像素、203表示绿色像素，H、L表示亮度高低。
请参照图5，图5为现有液晶显示面板第二种的结构示意图。
图5中的显示面板与图2的区别在于，每个像素的第二薄膜晶体管的输出端不再连接第二电容，而是与公共电极直接连接，通过电阻分压的方式使像素电极的电位被拉低。
但上述两种显示面板如图2或者5的虚线框所示，每一个像素的第二薄膜晶体管的输入端通过跨线方式与位于同一列中与该像素相邻的像素的第一薄膜晶体管的输出端连接；由于跨线连接需要制作过孔，因此会占用较多的空间，以及影响到像素的开口率；另外还会导致像素内部出现暗纹。
请参照图6-7，图6-7为本发明第一实施例的液晶显示面板的结构示意图；
如图6所示，本发明的第一种液晶显示面板包括：多条数据线D(n)至D(n+5)和多条扫描线G(n)至G(n+3)，所述数据线用于输入数据信号；其中n大于等于2，且为正整数；
所述扫描线用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；
多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素31和子像素32，所述主像素31和所述子像素32相邻设置；
所述主像素31对应设置有第一主薄膜晶体管T1和第二主薄膜晶体管T2、第一电容C1；所述子像素32对应设置有第一辅助薄膜晶体管T3、第二辅助薄膜晶体管T4、第二电容C2；
位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线G(n)的第一分支连接；位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线G(n)的所述第二分支连接；
位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线G(n+1)的第一分支连接；位于第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
位于第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线G(n+1)的第二分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线G(n+1)的所述第一分支连接。
所述第一主薄膜晶体管T1的输入端连接所述数据线，所述第一主薄膜晶体管T1的输出端连接所述第一电容C1；所述第一主薄膜晶体管T1的输出端还连接所述第二主薄膜晶体管T2的输入端；
所述第一辅助薄膜晶体管T3的输入端连接所述数据线，所述第一辅助薄膜晶体管T3的输出端连接所述第二电容C2；所述第一辅助薄膜晶体管T3的输出端还连接所述第二辅助薄膜晶体管T4的输入端；位于第n+1行像素的所述第二辅助薄膜晶体管T4的控制端连接所述第n行像素对应的所述扫描线G(n)的第二分支。
所述液晶显示面板包括公共电极，所述第二主薄膜晶体管T2的输出端连接所述公共电极，所述第二辅助薄膜晶体管T4的输出端也连接所述公共电极。
当从上到下进行扫描时，第n行的扫描线G(n)先打开，使得主像素31的第一主薄膜晶体管T1闭合，对所述主像素31进行充电，此时第二辅助薄膜晶体管T4也闭合。当第n+1行扫描线G(n+1)打开时，使得所述子像素32的第一辅助薄膜晶体管T3闭合，对所述子像素32充电；此时第二主薄膜晶体管T2也闭合，由于所述主像素31的第二主薄膜晶体管T2的输入端连接所述主像素31的第一主薄膜晶体管T1的输出端，使得主像素31的像素电极的电压通过所述第二主薄膜晶体管T2分享到公共电极上，使得所述主像素31的亮度降低；同时，由于此时第n行的扫描线已关闭，使得所述子像素32的第二辅助薄膜晶体管T4断开，对所述子像素32的像素电极进行充电后，不会被所述第二辅助薄膜晶体管T4拉低，因此子像素32维持较高的亮度，即所述主像素31的亮度小于所述子像素32的亮度。所述显示面板的显示效果图如图3所示，图3中的箭头方向表示扫描方向。
当从下到上进行扫描时，第n+1行的扫描线G(n+1)先打开，使得子像素32的第一辅助薄膜晶体管T3闭合，对所述子像素32进行充电，此时第二主薄膜晶体管T2也闭合。当第n行扫描线G(n)打开时，使得所述主像素31的第一主薄膜晶体管T1闭合，对所述主像素31充电；此时第二辅助薄膜晶体管T4也闭合，由于所述子像素32的第二辅助薄膜晶体管T4的输入端连接所述子像素32的第一辅助薄膜晶体管T3的输出端，使得子像素32的像素电极的电压通过所述第二辅助薄膜晶体管T4分享到公共电极上，使得所述子像素32的亮度降低；同时，由于此时第n+1行的扫描线已关闭，使得所述主像素31的第二主薄膜晶体管T2断开，对所述主像素31的像素电极进行充电后，不会被所述第二主薄膜晶体管T2拉低，因此主像素31维持较高的亮度。即所述主像素的亮度大于所述子像素的亮度。所述显示面板的显示效果图如图4所示，图4中的箭头方向表示扫描方向。
如图7所示，本发明第一实施例的液晶显示面板第二种结构示意图；图7和图6的区别在于：所述主像素还设置有第三电容C3；所述子像素还设置有第四电容C4；
当从上到下进行扫描时，所述主像素31的像素电极的电压被分享到所述第三电容C3上，使得主像素31的亮度降低；
当从下到上进行扫描时，所述子像素32的像素电极的电压被分享到所述第四电容C4上，使得子像素32的亮度降低。
由于本发明将每条扫描线分为两支，将用于进行电荷分享的薄膜晶体管的控制端连接与上一行或者下一行的扫描线分支中最靠近该控制端的一支连接，从而避免走线在像素开口区内部出现交叉，提高了面板的开口率，避免出现暗纹，提高了显示效果。
请参照图8-9，图8-9为本发明第二实施例的液晶显示面板的结构示意图；
如图8所示，本发明的液晶显示面板包括：多条数据线D(n)至D(n+5)和多条扫描线G(n)至G(n+3)，所述数据线用于输入数据信号；
所述扫描线用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；
多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素41和子像素42，所述主像素41和所述子像素42相邻设置；
所述主像素41对应设置有第一主薄膜晶体管T1和第二主薄膜晶体管T2、第一电容C1；所述子像素42对应设置有第一辅助薄膜晶体管T3、第二辅助薄膜晶体管T4、第二电容C2；
位于第n行像素的所述第一主薄膜晶体管T1的控制端与所述第n行像素对应的所述扫描线G(n)的所述第二分支连接；位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管T1的控制端与所述第n行像素对应的所述扫描线G(n)的所述第一分支连接；
位于所述第n行像素的所述第二主薄膜晶体管的控制端与第n+1行像素对应的所述扫描线G(n+1)的第一分支连接；位于第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
位于第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线G(n+1)的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
所述第一主薄膜晶体管T1的输入端连接所述数据线，所述第一主薄膜晶体管T1的输出端连接所述第一电容C1；所述第一主薄膜晶体管T1的输出端还连接所述第二主薄膜晶体管T2的输入端；
所述第一辅助薄膜晶体管T3的输入端连接所述数据线，所述第一辅助薄膜晶体管T3的输出端连接所述第二电容C2的一端，所述第二电容C2的另一端连接公共电极；所述第一辅助薄膜晶体管T1的输出端还连接所述第二辅助薄膜晶体管T2的输入端；位于第n+1行像素的所述第二辅助薄膜晶体管T2的控制端连接第n行像素对应的所述扫描线G(n)的第二分支。
所述液晶显示面板包括公共电极，所述第二主薄膜晶体管T2的输出端连接所述公共电极，所述第二辅助薄膜晶体管T4的输出端也连接所述公共电极。
当从上到下进行扫描时，第n行的扫描线G(n)先打开，使得主像素41的第一主薄膜晶体管T1闭合，对所述主像素41进行充电，此时第二辅助薄膜晶体管T4也闭合。当第n+1行扫描线G(n+1)打开时，使得所述子像素42的第一辅助薄膜晶体管T3闭合，对所述子像素42充电；此时第二主薄膜晶体管T2也闭合，由于所述主像素41的第二主薄膜晶体管T2的输入端连接所述主像素41的第一主薄膜晶体管T1的输出端，使得主像素41的像素电极的电压通过所述第二主薄膜晶体管T2分享到公共电极上，使得所述主像素41的亮度降低；同时，由于此时第n行的扫描线已关闭，使得所述子像素42的第二辅助薄膜晶体管T4断开，对所述子像素42的像素电极进行充电后，不会被所述第二辅助薄膜晶体管T4拉低，因此子像素42维持较高的亮度，即所述主像素41的亮度小于所述子像素42的亮度。所述显示面板的显示效果图如图3所示，图3中的箭头方向表示扫描方向。
当从下到上进行扫描时，第n+1行的扫描线G(n+1)先打开，
使得子像素42的第一辅助薄膜晶体管T3闭合，对所述子像素42进行充电，此时第二主薄膜晶体管T2也闭合。当第n行扫描线G(n)打开时，使得所述主像素41的第一主薄膜晶体管T1闭合，对所述主像素41充电；此时第二辅助薄膜晶体管T4也闭合，由于所述子像素42的第二辅助薄膜晶体管T4的输入端连接所述子像素42的第一辅助薄膜晶体管T3的输出端，使得子像素42的像素电极的电压通过所述第二辅助薄膜晶体管T4分享到公共电极上，使得所述子像素42的亮度降低；同时，由于此时第n+1行的扫描线已关闭，使得所述主像素41的第二主薄膜晶体管T2断开，对所述主像素41的像素电极进行充电后，不会被所述第二主薄膜晶体管T2拉低，因此所述主像素41维持较高的亮度。即所述主像素的亮度大于所述子像素的亮度。所述显示面板的显示效果图如图4所示，图4中的箭头方向表示扫描方向。
如图9所示，本发明第一实施例的液晶显示面板第二种结构示意图；图9和图8的区别在于：所述主像素41还设置有第三电容C3；所述子像素42还设置有第四电容C4；
当从上到下进行扫描时，所述主像素41的像素电极的电压被分享到所述第三电容C3上，使得主像素41的亮度降低；
当从下到上进行扫描时，所述子像素42的像素电极的电压被分享到所述第四电容C4上，使得子像素42的亮度降低。
由于第二实施例中的主像素的两TFT和子像素的两个TFT都位于像素的同一侧，与第一实施例相比能更好地提高开口率。
优选地，这种布线结构，使得所述第一分支和所述第二分支的位置与相邻两个像素的交界处位置相对应，由于在相邻两个像素的交界处设置有黑色矩阵，交界处被黑色矩阵遮挡，因此虽然增加了扫描线的条数，但是完全不会影响像素的开口率，更好地提高显示效果。
请参照图10-11，图10-11为本发明第三实施例的液晶显示面板的结构示意图；
如图10所示，本发明的液晶显示面板包括：多条数据线D(n)至D(n+5)和多条扫描线G(n)至G(n+3)，所述数据线用于输入数据信号；
所述扫描线用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；
多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素51和子像素52，所述主像素51和所述子像素52相邻设置；
所述主像素51对应设置有第一主薄膜晶体管T1和第二主薄膜晶体管T2、第一电容C1；所述子像素52对应设置有辅助薄膜晶体管T3、第二电容C2；
位于第n行像素的所述第一主薄膜晶体管T1的控制端与所述第n行像素对应的所述扫描线G(n)的所述第二分支连接；位于第n行与该像素相邻的像素的所述辅助薄膜晶体管T3的控制端与所述第n行像素对应的所述扫描线G(n)的所述第一分支连接；
位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线G(n+1)的第一分支连接；
位于第n+1行像素的所述辅助薄膜晶体管的控制端与第n+1行像素对应的所述扫描线G(n+1)的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与第n+1行像素对应的所述扫描线G(n+1)的所述第二分支连接。
所述第一主薄膜晶体管的输入端连接所述数据线，所述第一主薄膜晶体管的输出端连接所述第一电容C1；所述第一主薄膜晶体管的输出端还连接所述第二主薄膜晶体管的输入端；
所述辅助薄膜晶体管的输入端连接所述数据线，所述辅助薄膜晶体管的输出端连接所述第二电容C2的一端，所述第二电容C2的另一端连接公共电极。所述液晶显示面板包括公共电极，所述第二主薄膜晶体管T2的输出端连接所述公共电极。
当从上到下进行扫描时，第n行的扫描线G(n)先打开，使得主像素51的第一主薄膜晶体管T1闭合，对所述主像素51进行充电。当第n+1行扫描线G(n+1)打开时，使得所述子像素52的辅助薄膜晶体管T3闭合，对所述子像素52充电；此时第二主薄膜晶体管T2也闭合，由于所述主像素51的第二主薄膜晶体管T2的输入端连接所述主像素51的第一主薄膜晶体管T1的输出端，使得主像素51的像素电极的电压通过所述第二主薄膜晶体管T2分享到公共电极上，使得所述主像素51的亮度降低；同时，由于所述辅助薄膜晶体管的输出端未连接用于电压分享的子薄膜晶体管，对所述子像素52的像素电极进行充电后，不会被拉低，因此子像素52维持较高的亮度，即所述主像素51的亮度小于所述子像素52的亮度。所述显示面板的显示效果图如图3所示，图3中的箭头方向表示扫描方向。
当从下到上进行扫描时，第n+1行的扫描线G(n+1)先打开，
使得子像素52的辅助薄膜晶体管T3闭合，对所述子像素52进行充电，此时第二主薄膜晶体管T2也闭合。当第n行扫描线G(n)打开时，使得所述主像素51的第一主薄膜晶体管T1闭合，对所述主像素51充电；同时，由于此时第n+1行的扫描线已关闭，使得所述主像素51的第二主薄膜晶体管T2断开，对所述主像素51的像素电极进行充电后，不会被所述第二主薄膜晶体管T2拉低，因此所述主像素51维持较高的亮度。即所述主像素的亮度等于所述子像素的亮度。所述显示面板的显示效果图如图12所示，图12中的箭头方向表示扫描方向。
如图11所示，本发明第一实施例的液晶显示面板第二种结构示意图；图11和图10的区别在于：所述主像素41还设置有第三电容C3。
当从上到下进行扫描时，所述主像素51的像素电极的电压被分享到所述第三电容C3上，使得主像素51的亮度降低。
由于第二实施例中的主像素的两TFT和子像素的两个TFT都位于像素的同一侧，与第一实施例相比能更好地提高开口率。
优选地，所述第一分支和所述第二分支的位置与相邻两个像素的交界处位置相对应，由于在相邻两个像素的交界处设置有黑色矩阵，交界处被黑色矩阵遮挡，因此虽然增加了扫描线的条数，但是不会影响像素的开口率。该技术方案同样适用于其他实施例。
由于本发明将每条扫描线分为两支，将用于进行电荷分享的薄膜晶体管的控制端连接与上一行或者下一行的扫描线分支中最靠近该控制端的一支连接，从而避免走线在像素开口区内部出现交叉，提高了面板的开口率，避免出现暗纹，提高了显示效果。
本发明的液晶显示面板，通过对现有的面板上的驱动线路进行重新布局，提高面板的开口率以及显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种液晶显示面板，其包括：
    多条数据线，用于输入数据信号；
    多条扫描线，用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；且所述第一分支和所述第二分支分别与相邻两个所述像素的交界处的位置相对应；以及
    多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素和子像素，所述主像素和所述子像素相邻设置；
    所述主像素对应设置有第一主薄膜晶体管和第二主薄膜晶体管、第一电容；
    位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的其中一个分支连接；
    位于所述第n行像素的所述第二主薄膜晶体管的控制端与第n+1行像素对应的所述扫描线的第一分支连接；
    位于第n+1行像素的所述辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的其中一个分支连接；
    所述第一主薄膜晶体管的输入端连接所述数据线，所述第一主薄膜晶体管的输出端连接所述第一电容；所述第一主薄膜晶体管的输出端还连接所述第二主薄膜晶体管的输入端；其中n大于等于2，且为正整数；
    所述子像素对应设置有第一辅助薄膜晶体管和第二辅助薄膜晶体管；
    所述第一辅助薄膜晶体管的输入端连接所述数据线，所述第一辅助薄膜晶体管的输出端连接所述第二电容；所述第一辅助薄膜晶体管的输出端还连接所述第二辅助薄膜晶体管的输入端；位于第n+1行像素的所述第二辅助薄膜晶体管的控制端连接所述第n行像素对应的所述扫描线的第二分支。
  2. 根据权利要求1所述的液晶显示面板，其中
    所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；
    所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于所述第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
    位于第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接。
  3. 根据权利要求1所述的液晶显示面板，其中
    所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；所述位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；
    所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
    位于所述第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
  4. 根据权利要求1所述的液晶显示面板，其中所述主像素还设置有第三电容；所述子像素还设置有第四电容；
    所述第二主薄膜晶体管的输出端连接所述第三电容；
    所述第二辅助薄膜晶体管的输出端连接所述第四电容。
  5. 根据权利要求1所述的液晶显示面板，其中所述液晶显示面板包括公共电极，所述第二主薄膜晶体管的输出端连接所述公共电极，所述第二辅助薄膜晶体管的输出端也连接所述公共电极。
  6. 根据权利要求1所述的液晶显示面板，其中
    当所述液晶显示面板从上到下进行扫描时，所述主像素的显示亮度小于所述子像素的显示亮度；
    当所述液晶显示面板从下到上进行扫描时，所述主像素的显示亮度大于或等于所述子像素的显示亮度。
  7. 一种液晶显示面板，其包括：
    多条数据线，用于输入数据信号；
    多条扫描线，用于输入扫描信号；所述扫描线包括第一分支和第二分支；所述第一分支位于像素的上边缘，所述第二分支位于所述像素的下边缘；
    多个像素，由所述数据线和所述扫描线限定形成，所述像素包括主像素和子像素，所述主像素和所述子像素相邻设置；
    所述主像素对应设置有第一主薄膜晶体管和第二主薄膜晶体管、第一电容；所述子像素对应设置有至少一个辅助薄膜晶体管、第二电容；
    位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的其中一个分支连接；
    位于所述第n行像素的所述第二主薄膜晶体管的控制端与第n+1行像素对应的所述扫描线的第一分支连接；
    位于第n+1行像素的所述辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的其中一个分支连接；
    所述第一主薄膜晶体管的输入端连接所述数据线，所述第一主薄膜晶体管的输出端连接所述第一电容；所述第一主薄膜晶体管的输出端还连接所述第二主薄膜晶体管的输入端；
    所述辅助薄膜晶体管的输入端连接所述数据线，所述辅助薄膜晶体管的输出端连接所述第二电容，其中n大于等于2，且为正整数。
  8. 根据权利要求7所述的液晶显示面板，其中
    所述子像素对应设置有第一辅助薄膜晶体管和第二辅助薄膜晶体管；
    所述第一辅助薄膜晶体管的输入端连接所述数据线，所述第一辅助薄膜晶体管的输出端连接所述第二电容；所述第一辅助薄膜晶体管的输出端还连接所述第二辅助薄膜晶体管的输入端；位于第n+1行像素的所述第二辅助薄膜晶体管的控制端连接所述第n行像素对应的所述扫描线的第二分支。
  9. 根据权利要求8所述的液晶显示面板，其中
    所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；
    所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于所述第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
    位于第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接。
  10. 根据权利要求8所述的液晶显示面板，其中
    所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；所述位于第n行与该像素相邻的像素的所述第一辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；
    所述位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；位于第n行与该像素相邻的像素的所述第二辅助薄膜晶体管的控制端与第n-1行像素对应的所述扫描线的所述第二分支连接；
    位于所述第n+1行像素的所述第一辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
  11. 根据权利要求8所述的液晶显示面板，其中所述主像素还设置有第三电容；所述子像素还设置有第四电容；
    所述第二主薄膜晶体管的输出端连接所述第三电容；
    所述第二辅助薄膜晶体管的输出端连接所述第四电容。
  12. 根据权利要求8所述的液晶显示面板，其中所述液晶显示面板包括公共电极，所述第二主薄膜晶体管的输出端连接所述公共电极，所述第二辅助薄膜晶体管的输出端也连接所述公共电极。
  13. 根据权利要求7所述的液晶显示面板，其中
    所述子像素对应仅设置有一个所述辅助薄膜晶体管；
    所述位于第n行像素的所述第一主薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第二分支连接；位于第n行与该像素相邻的像素的所述辅助薄膜晶体管的控制端与所述第n行像素对应的所述扫描线的所述第一分支连接；
    位于所述第n行像素的所述第二主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的第一分支连接；
    位于所述第n+1行像素的所述辅助薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第一分支连接；位于第n+1行与该像素相邻的像素的所述第一主薄膜晶体管的控制端与所述第n+1行像素对应的所述扫描线的所述第二分支连接。
  14. 根据权利要求13所述的液晶显示面板，其中所述液晶显示面板包括公共电极，所述主像素还设置有第三电容；
    所述第二主薄膜晶体管的输出端连接所述第三电容或者公共电极。
  15. 根据权利要求7所述的液晶显示面板，其中
    所述第一分支和所述第二分支分别与相邻两个所述像素的交界处的位置相对应。
  16. 根据权利要求7所述的液晶显示面板，其中
    当所述液晶显示面板从上到下进行扫描时，所述主像素的显示亮度小于所述子像素的显示亮度；
    当所述液晶显示面板从下到上进行扫描时，所述主像素的显示亮度大于或等于所述子像素的显示亮度。
PCT/CN2015/087588 2015-08-11 2015-08-20 一种液晶显示面板 Ceased WO2017024607A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2018506859A JP6531219B2 (ja) 2015-08-11 2015-08-20 液晶表示パネル
GB1802170.9A GB2557760B (en) 2015-08-11 2015-08-20 Liquid crystal display panel
US14/891,744 US9958743B2 (en) 2015-08-11 2015-08-20 Liquid crystal display panel
EA201890474A EA035140B1 (ru) 2015-08-11 2015-08-20 Жидкокристаллическая дисплейная панель
KR1020187006812A KR102054412B1 (ko) 2015-08-11 2015-08-20 액정표시패널

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510490646.7A CN105068345B (zh) 2015-08-11 2015-08-11 一种液晶显示面板
CN201510490646.7 2015-08-11

Publications (1)

Publication Number Publication Date
WO2017024607A1 true WO2017024607A1 (zh) 2017-02-16

Family

ID=54497745

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/087588 Ceased WO2017024607A1 (zh) 2015-08-11 2015-08-20 一种液晶显示面板

Country Status (7)

Country Link
US (1) US9958743B2 (zh)
JP (1) JP6531219B2 (zh)
KR (1) KR102054412B1 (zh)
CN (1) CN105068345B (zh)
EA (1) EA035140B1 (zh)
GB (1) GB2557760B (zh)
WO (1) WO2017024607A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107045240B (zh) * 2017-06-07 2018-12-11 深圳市华星光电半导体显示技术有限公司 一种液晶显示面板及装置
CN109521593B (zh) * 2018-12-25 2021-07-09 厦门天马微电子有限公司 显示面板和显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281309A (zh) * 2007-04-06 2008-10-08 群康科技(深圳)有限公司 垂直配向型液晶显示装置的驱动电路及驱动方法
CN101452169A (zh) * 2007-12-06 2009-06-10 胜华科技股份有限公司 液晶显示面板与应用其的液晶显示装置
CN101526710A (zh) * 2009-04-21 2009-09-09 友达光电股份有限公司 像素阵列及显示面板
WO2014059690A1 (zh) * 2012-10-18 2014-04-24 深圳市华星光电技术有限公司 一种阵列基板及液晶显示装置
CN104216187A (zh) * 2014-09-04 2014-12-17 深圳市华星光电技术有限公司 像素结构、液晶显示面板及其驱动方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0535222A (ja) * 1991-08-02 1993-02-12 Seiko Epson Corp 表示パネルおよび表示装置
JPH05257165A (ja) * 1992-03-10 1993-10-08 Fujitsu Ltd 液晶表示パネル
KR101187207B1 (ko) * 2005-08-04 2012-10-02 삼성디스플레이 주식회사 디스플레이장치
KR101207543B1 (ko) * 2006-02-03 2012-12-03 삼성디스플레이 주식회사 표시 장치
KR101435527B1 (ko) * 2007-07-25 2014-08-29 삼성디스플레이 주식회사 표시 장치
CN101369075B (zh) * 2007-08-15 2010-05-26 群康科技(深圳)有限公司 液晶显示装置及其驱动方法
US8264439B2 (en) * 2007-11-01 2012-09-11 Wintek Corporation Liquid crystal display panel and liquid crystal display device using the same
JP2011059380A (ja) * 2009-09-10 2011-03-24 Renesas Electronics Corp 表示装置及びそれに使用される駆動回路
US8902373B2 (en) * 2010-03-04 2014-12-02 Sharp Kabushiki Kaisha Liquid crystal display device
KR101793176B1 (ko) * 2010-08-05 2017-11-03 삼성디스플레이 주식회사 표시 장치
US8665264B2 (en) * 2011-11-23 2014-03-04 Shenzhen China Star Optoelectronics Technology Co., Ltd. LCD panel and LCD device
TWI447696B (zh) * 2012-05-02 2014-08-01 Au Optronics Corp 有機發光二極體顯示面板的驅動方法
WO2014087781A1 (ja) * 2012-12-07 2014-06-12 堺ディスプレイプロダクト株式会社 液晶表示装置及び該液晶表示装置の駆動方法
CN103353698B (zh) * 2013-07-19 2016-03-30 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板
US20150022510A1 (en) * 2013-07-19 2015-01-22 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array substrate and liquid crystal panel with the same
KR102102155B1 (ko) * 2013-12-23 2020-05-29 엘지디스플레이 주식회사 액정표시장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101281309A (zh) * 2007-04-06 2008-10-08 群康科技(深圳)有限公司 垂直配向型液晶显示装置的驱动电路及驱动方法
CN101452169A (zh) * 2007-12-06 2009-06-10 胜华科技股份有限公司 液晶显示面板与应用其的液晶显示装置
CN101526710A (zh) * 2009-04-21 2009-09-09 友达光电股份有限公司 像素阵列及显示面板
WO2014059690A1 (zh) * 2012-10-18 2014-04-24 深圳市华星光电技术有限公司 一种阵列基板及液晶显示装置
CN104216187A (zh) * 2014-09-04 2014-12-17 深圳市华星光电技术有限公司 像素结构、液晶显示面板及其驱动方法

Also Published As

Publication number Publication date
US20170212380A1 (en) 2017-07-27
EA201890474A1 (ru) 2018-07-31
KR20180039140A (ko) 2018-04-17
KR102054412B1 (ko) 2019-12-10
GB2557760A (en) 2018-06-27
CN105068345A (zh) 2015-11-18
JP6531219B2 (ja) 2019-06-12
GB2557760B (en) 2021-07-07
JP2018525674A (ja) 2018-09-06
EA035140B1 (ru) 2020-05-06
US9958743B2 (en) 2018-05-01
CN105068345B (zh) 2018-06-22
GB201802170D0 (en) 2018-03-28

Similar Documents

Publication Publication Date Title
WO2016095239A1 (zh) 一种图像显示方法、图像显示装置及显示器件
WO2015176326A1 (zh) 一种显示面板及显示装置
WO2013139046A1 (zh) 电荷分享型像素结构
WO2017197687A1 (zh) 一种cmos goa电路结构及液晶显示面板
WO2016074283A1 (zh) 用于液晶显示的goa电路及液晶显示装置
WO2019132216A1 (en) Electroluminescent display device and method for driving the same
WO2016074263A1 (zh) 曲面液晶显示面板及曲面液晶显示装置
WO2019205208A1 (zh) 一种多路复用型驱动电路以及驱动方法、显示设备
WO2017049659A1 (zh) 一种goa电路、显示装置和goa电路的驱动方法
WO2017000358A1 (zh) 液晶显示面板的Gamma调整方法及装置
WO2015192393A1 (zh) 像素结构及液晶显示装置
WO2016026167A1 (zh) 一种液晶显示面板及阵列基板
WO2018016745A1 (ko) 대칭적 배열을 가진 rgbgr 디스플레이 장치
WO2016074262A1 (zh) 一种coa阵列基板及液晶显示面板
WO2020135075A1 (zh) 显示器及其显示面板的驱动装置、方法
WO2014012280A1 (zh) 子像素显示结构及其应用的液晶显示面板
WO2019000577A1 (zh) 内嵌式触摸屏
WO2020062556A1 (zh) 伽马电压调节电路及显示装置
WO2020113692A1 (zh) 阵列基板行驱动电路及显示装置
WO2017049742A1 (zh) 一种goa电路及其驱动方法、液晶显示器
WO2018113167A1 (zh) 液晶显示器的驱动方法、装置及液晶显示器
WO2020155257A1 (zh) 显示面板的驱动方法、装置及设备
WO2020056840A1 (zh) 显示面板及其过驱动查找表的建立方法和可读存储介质
WO2023038234A1 (ko) 디스플레이 패널 및 그 동작 방법
WO2017024607A1 (zh) 一种液晶显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14891744

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15900804

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2018506859

Country of ref document: JP

Kind code of ref document: A

Ref document number: 201802170

Country of ref document: GB

Kind code of ref document: A

Free format text: PCT FILING DATE = 20150820

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 201890474

Country of ref document: EA

ENP Entry into the national phase

Ref document number: 20187006812

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 15900804

Country of ref document: EP

Kind code of ref document: A1