WO2015176326A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2015176326A1
WO2015176326A1 PCT/CN2014/078374 CN2014078374W WO2015176326A1 WO 2015176326 A1 WO2015176326 A1 WO 2015176326A1 CN 2014078374 W CN2014078374 W CN 2014078374W WO 2015176326 A1 WO2015176326 A1 WO 2015176326A1
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WIPO (PCT)
Prior art keywords
pixel
sub
driving chip
pixels
display panel
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PCT/CN2014/078374
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English (en)
French (fr)
Inventor
徐向阳
Original Assignee
深圳市华星光电技术有限公司
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Priority to US14/382,272 priority Critical patent/US20160240117A1/en
Publication of WO2015176326A1 publication Critical patent/WO2015176326A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0613—The adjustment depending on the type of the information to be displayed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/08—Arrangements within a display terminal for setting, manually or automatically, display parameters of the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
  • the mainstream display panels include: TFT-LCD (Thin Film Transistor Liquid Crystal Display) and AMOLED (Active Matrix Organic Light Emitting Diode Display Panel).
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode Display Panel
  • color gamut Wide, correspondingly faster, better brightness, larger viewing angle, lower power consumption, smaller size, etc.
  • the resolution of the display panel is also increasing.
  • the highest display resolution on the market has reached 3840*2160 (4K*2K) (ie, high definition). Due to the limitation of the signal source, it has not been popularized yet. However, with the development of information technology, 4K high-definition signal sources will also be popularized, so high-definition display panels will gradually move toward thousands of households. In addition, 3D displays are also rapidly evolving.
  • An object of the present invention is to provide a display panel and a display device capable of automatically switching between a 2D image and a 3D image, and making the screen smoother and reducing the production cost.
  • the invention provides a display panel
  • the display panel is a liquid crystal display panel or an active matrix organic light emitting diode display panel
  • the display panel includes an array substrate
  • the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line;
  • the pixel unit includes four of the pixel sub-units, four of the blue sub-pixels are arranged in a matrix structure of 2*2, and four of the red sub-pixels are arranged in a matrix structure of 2*2, four
  • the green sub-pixels are arranged in a matrix structure of 2*2, and all sub-pixels in the pixel unit are in a matrix structure of 2*6.
  • the first 2D image when the display panel displays the first 2D image, the first 2D image includes a plurality of display pixels;
  • Each of the pixel subunits of the pixel unit receives a data signal of a different display pixel and a scan signal.
  • the 3D image when the display panel displays a 3D image, the 3D image includes a plurality of display pixels;
  • the pixel sub-unit formed by the sub-pixels located in the odd-numbered columns of the pixel unit receives a data signal of a left-eye display pixel and a scan signal;
  • the pixel sub-unit formed by the sub-pixels located in the even-numbered columns of the pixel unit receives a data signal of a right-eye display pixel and a scan signal.
  • the 3D image when the display panel displays a 3D image, the 3D image includes a plurality of display pixels;
  • the pixel subunits of the sub-pixels of the odd-numbered columns in the pixel unit receive a data signal of a right-eye display pixel and a scan signal;
  • the pixel sub-unit formed by the sub-pixels located in the even-numbered columns of the pixel unit receives a data signal of a left-eye display pixel and a scan signal.
  • the second 2D image when the display panel displays the second 2D image, the second 2D image includes a plurality of display pixels;
  • Each of the pixel subunits of the pixel unit receives a data signal of the same display pixel and a scan signal.
  • the sub-pixel includes a thin film transistor
  • the array substrate further includes a source driving chip and a gate driving chip:
  • the gate driving chip includes a first gate driving chip and a second gate driving chip
  • the source driving chip includes a first source driving chip and a second source driving chip
  • the first gate driving chip is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel of the odd-numbered row in the pixel unit through the scan line;
  • the second gate driving chip is configured to input a scan signal to a control end of the thin film transistor of the sub-pixels of the even-numbered rows in the pixel unit through the scan line;
  • the first source driving chip is configured to input a data signal to an input end of the thin film transistor of the sub-pixel of the odd-numbered column in the pixel unit through the data line;
  • the second source driving chip is configured to input a data signal to an input end of the thin film transistor of the sub-pixel of the even-numbered column in the pixel unit through the data line.
  • the display panel further includes a signal control module, and the signal control module includes:
  • a signal analysis chip configured to analyze a sharpness and a display mode of the input signal source of the display panel, and generate an analysis result
  • a timing controller configured to process the signal source according to the analysis result obtained by the signal analysis chip to obtain a data signal and a scan signal, and transmit the obtained data signal and scan signal to the source driving chip And the gate drive chip.
  • the present invention constructs a display panel, the display panel comprising an array substrate
  • the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line;
  • the pixel unit includes at least two pixel sub-units, where the pixel sub-unit includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the blue sub-pixels in the same pixel unit are adjacently disposed, the same The red sub-pixels in the pixel unit are adjacently disposed, and the green sub-pixels in the same pixel unit are adjacently disposed.
  • the pixel unit includes four of the pixel sub-units, four of the blue sub-pixels are arranged in a matrix structure of 2*2, and the four red sub-pixels are pressed by 2*2
  • the matrix structure is set, and the four green sub-pixels are arranged in a matrix structure of 2*2, and all sub-pixels in the pixel unit are in a matrix structure of 2*6.
  • the first 2D image when the display panel displays the first 2D image, the first 2D image includes a plurality of display pixels;
  • Each of the pixel subunits of the pixel unit receives a data signal of a different display pixel and a scan signal.
  • the 3D image when the display panel displays a 3D image, the 3D image includes a plurality of display pixels;
  • the pixel sub-unit formed by the sub-pixels located in the odd-numbered columns of the pixel unit receives a data signal of a left-eye display pixel and a scan signal;
  • the pixel sub-unit formed by the sub-pixels located in the even-numbered columns of the pixel unit receives a data signal of a right-eye display pixel and a scan signal.
  • the 3D image when the display panel displays a 3D image, the 3D image includes a plurality of display pixels;
  • the pixel subunits of the sub-pixels of the odd-numbered columns in the pixel unit receive a data signal of a right-eye display pixel and a scan signal;
  • the pixel sub-unit formed by the sub-pixels located in the even-numbered columns of the pixel unit receives a data signal of a left-eye display pixel and a scan signal.
  • the second 2D image when the display panel displays the second 2D image, the second 2D image includes a plurality of display pixels;
  • Each of the pixel subunits of the pixel unit receives a data signal of the same display pixel and a scan signal.
  • the sub-pixel includes a thin film transistor
  • the array substrate further includes a source driving chip and a gate driving chip:
  • the gate driving chip includes a first gate driving chip and a second gate driving chip
  • the source driving chip includes a first source driving chip and a second source driving chip
  • the first gate driving chip is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel of the odd-numbered row in the pixel unit through the scan line;
  • the second gate driving chip is configured to input a scan signal to a control end of the thin film transistor of the sub-pixels of the even-numbered rows in the pixel unit through the scan line;
  • the first source driving chip is configured to input a data signal to an input end of the thin film transistor of the sub-pixel of the odd-numbered column in the pixel unit through the data line;
  • the second source driving chip is configured to input a data signal to an input end of the thin film transistor of the sub-pixel of the even-numbered column in the pixel unit through the data line.
  • the display panel further includes a signal control module, and the signal control module includes:
  • a signal analysis chip configured to analyze a sharpness and a display mode of the input signal source of the display panel, and generate an analysis result
  • a timing controller configured to process the signal source according to the analysis result obtained by the signal analysis chip to obtain a data signal and a scan signal, and transmit the obtained data signal and scan signal to the source driving chip And the gate drive chip.
  • the display panel is a liquid crystal display panel or an active matrix organic light emitting diode display panel.
  • Another object of the present invention is to provide a display device, the display device comprising: a display panel;
  • the display panel includes an array substrate
  • the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line.
  • the pixel unit includes at least two pixel sub-units, where the pixel sub-unit includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the blue sub-pixels in the same pixel unit are adjacently disposed, the same The red sub-pixels in the pixel unit are adjacently disposed, and the green sub-pixels in the same pixel unit are adjacently disposed.
  • the present invention can automatically switch between a 2D image and a 3D image by providing an array substrate with different sub-pixels arranged in a pixel unit, and make the picture smoother; and adopt two conventional gate driving chips and two conventional ones.
  • the source driver chip implements a complex driving process, thereby reducing production costs.
  • FIG. 1 is a schematic structural diagram of a pixel unit according to a first embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a pixel unit according to a second embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a pixel unit according to a third embodiment of the present invention.
  • FIG. 4 is a schematic structural view of a driving circuit in the first to third embodiments of the embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the working flow and structure of a signal control module according to a fourth embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a pixel unit according to a first embodiment of the present invention.
  • the display panel of the present invention includes an array substrate, the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line, the pixel unit including: a red pixel and a green pixel , blue pixels (such as R, G, B), of course, may also include a yellow pixel or a white pixel.
  • the present invention is exemplified by the manner in which the pixel arrangement order in the pixel unit is red, green, or blue (RGB), and does not constitute the present invention.
  • the pixel unit may also include other order of arrangement: blue, red, green (BRG).
  • the red pixel is divided into four red sub-pixels R1, R2, R3, and R4, and the four red sub-pixels are arranged in a matrix structure of 2*2 (the red sub-pixel R1 is located The 0th row and the 0th column of the 2*2 matrix of the red pixel, the red sub-pixel R2 is located in the 0th row and the 1st column of the 2*2 matrix of the red pixel, the red sub-pixel R3 is located in the first row and the 0th column of the 2*2 matrix of the red pixel, and the red sub-pixel R4 is located in the 1st row and the 1st column of the 2*2 matrix of the red pixel);
  • the green pixel is divided into four green sub-pixels G1, G2, G3, and G4, and the four green sub-pixels are arranged in a matrix structure of 2*2 (the matrix structure of the four green sub-pixels and the above four The matrix structure of the red sub-pixels is the same, and will not be enumerated here);
  • the blue pixel is divided into four blue sub-pixels B1, B2, B3, and B4, and the four blue sub-pixels are arranged in a matrix structure of 2*2 (four matrices of the blue sub-pixels)
  • the structure is the same as the matrix structure of the above four red sub-pixels, and will not be enumerated here).
  • the above matrix structure may also be other matrix structures (for example, the red sub-pixel R1 is located in the 0th row and the 0th column of the 2*2 matrix of the red pixel, and the red sub-pixel R2 is located at the red pixel.
  • the red sub-pixel R3 is located in the 0th row and the 1st column of the 2*2 matrix of the red pixel, and the red sub-pixel R4 is located in the 1st row and the 1st column of the 2*2 matrix of the red pixel) All of them are within the protection scope of the present invention, and are not enumerated here.
  • R1G1B1 constitutes a first pixel subunit
  • R2G2B2 constitutes a second pixel subunit
  • R3G3B3 constitutes a third pixel subunit
  • R4G4B4 constitutes a fourth pixel subunit
  • all subpixels in the pixel unit are in a 2*6 matrix structure.
  • All of the sub-pixels in the pixel unit may also be other matrix structures (such as 6*2), which are all within the protection scope of the present invention, and are not enumerated here.
  • the first 2D image when the display panel displays the first 2D image, the first 2D image includes a plurality of display pixels; the first 2D image is a high definition 2D image (for example, a 4K image);
  • Each of the pixel subunits of the pixel unit receives a data signal of a different display pixel and a scan signal.
  • the sub-pixel arrangement in the odd-numbered rows in the pixel unit is R1G1B1R2G2B2, that is, sub-pixels of different colors are adjacently arranged, so that when the HD picture is actually displayed, in the human eye In the case where the distinction is not made, the picture is not smooth enough;
  • the sub-pixel arrangement in the odd-numbered rows in the pixel unit in the present invention is, for example, R1R2G1G2B1B2, such that sub-pixels of the same color in the final displayed picture are adjacent to each other (ie, the red in the same pixel unit)
  • the sub-pixels are disposed adjacent to each other, and the green sub-pixels in the same pixel unit are adjacently disposed, and the blue sub-pixels in the same pixel unit are adjacently disposed, and the above structure can be different from the prior art.
  • the pixels of the color are adjacent to each other, and the picture is smoother when displaying a high-definition 2D image.
  • the array substrate includes a source driving chip and a gate driving chip, and each of the source driving chip and the gate driving chip is used to scan each pixel in the pixel unit through a scan line.
  • the control terminal of the thin film transistor inputs a scan signal for inputting a data signal to an input terminal of a thin film transistor of each pixel in the pixel unit through a data line.
  • the gate driving chip inputs a scanning signal to the first row of pixels
  • the source driving chip inputs a data signal to the first row of pixels
  • the gate driving chip inputs a scanning signal to the second row of pixels
  • the source driving The chip inputs a data signal to the second row of pixels.
  • each of the sub-pixels includes a thin film transistor
  • the array substrate further includes a source driving chip and a gate driving chip (not shown): the gate driving chip includes a first gate driving chip 11 and a second gate driving chip 12; the source driving chip includes a first source Driving chip 21 and second source driving chip 22;
  • the first gate driving chip 11 is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel (for example, R1R2G1G2B1B2) of the odd-numbered row in the pixel unit through the scan line;
  • the second gate driving chip 12 is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel (such as R3R4G3G4B3B4) of the even-numbered row in the pixel unit through the scan line;
  • the first source driving chip 21 is configured to input a data signal to an input end of the thin film transistor of the sub-pixel (for example, R1G1B1R3G3B3) of the odd-numbered column in the pixel unit through the data line;
  • the second source driving chip 22 is configured to input a data signal to an input end of the thin film transistor of the sub-pixel (such as R2G2B2R4G4B4) of the even-numbered column in the pixel unit through the data line.
  • the display panel is a liquid crystal display panel or an active matrix organic light emitting diode display panel.
  • FIG. 2 is a schematic structural diagram of a pixel unit according to a second embodiment of the present invention.
  • the display panel of the present invention includes an array substrate, the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line, the pixel unit including: a red pixel and a green pixel , blue pixels (such as R, G, B), of course, may also include yellow pixels or white pixels.
  • the present invention is exemplified by the manner in which the pixel arrangement order in the pixel unit is red, green, or blue (RGB), and does not constitute a limitation of the present invention.
  • the pixel unit may also include other arrangement order: blue, red, green (BRG).
  • the red pixel is divided into four red sub-pixels R1, R2, R3, and R4, and the four red sub-pixels are arranged in a matrix structure of 2*2 (the red sub-pixel R1 is located The 0th row and the 0th column of the 2*2 matrix of the red pixel, the red sub-pixel R2 is located in the 0th row and the 1st column of the 2*2 matrix of the red pixel, the red sub-pixel R3 is located in the first row and the 0th column of the 2*2 matrix of the red pixel, and the red sub-pixel R4 is located in the 1st row and the 1st column of the 2*2 matrix of the red pixel);
  • the green pixel is divided into four green sub-pixels G1, G2, G3, and G4, and the four green sub-pixels are arranged in a matrix structure of 2*2 (the matrix structure of the four green sub-pixels and the above four The matrix structure of the red sub-pixels is the same, and will not be enumerated here);
  • the blue pixel is divided into four blue sub-pixels B1, B2, B3, and B4, and the four blue sub-pixels are arranged in a matrix structure of 2*2 (four matrices of the blue sub-pixels)
  • the structure is the same as the matrix structure of the above four red sub-pixels, and will not be enumerated here).
  • the above matrix structure may also be other matrix structures (for example, the red sub-pixel R1 is located in the 0th row and the 0th column of the 2*2 matrix of the red pixel, and the red sub-pixel R2 is located at the red pixel.
  • the red sub-pixel R3 is located in the 0th row and the 1st column of the 2*2 matrix of the red pixel
  • the red sub-pixel R4 is located in the red pixel
  • the first row and the first column in the 2*2 matrix are all within the scope of the present invention, and are not enumerated here.
  • R1G1B1 constitutes a first pixel subunit
  • R2G2B2 constitutes a second pixel subunit
  • R3G3B3 constitutes a third pixel subunit
  • R4G4B4 constitutes a fourth pixel subunit
  • all subpixels in the pixel unit are in a 2*6 matrix structure.
  • All of the sub-pixels in the pixel unit may also be other matrix structures (such as 6*2), which are all within the protection scope of the present invention, and are not enumerated here.
  • the display panel when the display panel displays a 3D image, the 3D image includes a plurality of display pixels;
  • Each of the sub-pixels in the pixel sub-unit is located at the same position in a corresponding pixel matrix of the sub-pixel (for example, in the first pixel sub-unit R1G1B1, the red sub-pixel R1 is located in the 2*2 matrix of the red pixel)
  • the green sub-pixel G1 is located in the 0th row and the 0th column of the 2*2 matrix of the green pixel
  • the blue sub-pixel B1 is located in the 2*2 matrix of the blue pixel. Line 0, column 0).
  • the pixel sub-units (such as R1G1B1, R3G3B3) of the sub-pixels located in the odd-numbered columns of the pixel unit receive a data signal of a left-eye or right-eye display pixel and a scan signal, and the pixel unit is located in an even number
  • the pixel sub-units (such as R2G2B2, R4G4B4) composed of the sub-pixels of the column receive the data signals of the right-eye or left-eye display pixels and the scan signals.
  • R1G1B1, R3G3B3 receive the data signal of the left eye display pixel and the scan signal
  • the R2G2B2, R4G4B4 receive the data signal of the right eye display pixel and the scan signal; at this time, the equivalent structure diagram in the pixel unit is as shown in FIG. Shown: wherein the red sub-pixels R1 and R3 are equivalent to R1 (red left-eye pixels), The green sub-pixels G1 and G3 are equivalent to G1 (green left-eye pixels), and the blue sub-pixels B1 and B3 are equivalent to Bl (blue left-eye pixels).
  • the red sub-pixels R2 and R4 are equivalent to Rr (red right-eye pixel), and the green sub-pixels G2 and G4 are equivalent to Gr (green right eye pixel), the blue sub-pixels B2 and B4 are equivalent to Br (blue right-eye pixel).
  • R1G1B1, R3G3B3 receive the data signal of the right eye display pixel and the scan signal
  • the R2G2B2, R4G4B4 receive the data signal of the left eye display pixel and the scan signal.
  • the equivalent structure diagram of the pixel unit is to interchange the left and right eye pixel positions of all colors in FIG. 2, and will not be enumerated here.
  • the sub-pixel arrangement in the odd-numbered rows in the pixel unit is, for example, R1G1B1R2G2B2, that is, sub-pixels of different colors are adjacently arranged, so that when the 3D image is actually displayed, in the human eye When the distinction is not made, the left and right eye images are not smooth enough;
  • the sub-pixel arrangement in the odd-numbered rows in the pixel unit in the present invention is R1R2G1G2B1B2, such that the sub-pixels of the same color in the final displayed picture are adjacent to each other (ie, the red sub-pixel in the same pixel unit)
  • the pixels are adjacently disposed, and the green sub-pixels in the same pixel unit are adjacently disposed, and the blue sub-pixels in the same pixel unit are adjacently disposed).
  • the array substrate includes a source driving chip and a gate driving chip, and each of the source driving chip and the gate driving chip is used to scan each pixel in the pixel unit through a scan line.
  • the control terminal of the thin film transistor inputs a scan signal
  • the source driving chip is configured to input a data signal to an input end of the thin film transistor of each pixel in the pixel unit through a data line, when the gate driving chip is to the first row
  • the source drive chip inputs a data signal to the first row of pixels
  • the gate drive chip inputs the scan signal to the second row of pixels
  • the source drive chip inputs a data signal to the second row of pixels.
  • each of the sub-pixels includes a thin film transistor
  • the array substrate further includes a source driving chip and a gate driving chip: the gate driving chip includes a first gate driving chip 11 and a second gate driving chip 12; the source driving chip includes a first source driving chip 21 and a second source Driving chip 22;
  • the first gate driving chip 11 is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel (for example, R1R2G1G2B1B2) of the odd-numbered row in the pixel unit through the scan line;
  • the second gate driving chip 12 is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel (such as R3R4G3G4B3B4) of the even-numbered row in the pixel unit through the scan line;
  • the first gate driving chip 11 and the second gate driving chip 12 simultaneously input the same scanning signal to the sub-pixels located in the odd rows and the sub-pixels located in the even rows, respectively.
  • the first source driving chip 21 is configured to input a data signal to the input end of the thin film transistor of the sub-pixel (such as R1G1B1R3G3B3) of the odd-numbered column in the pixel unit through the data line (the data signal is left)
  • the eye or right eye displays the data signal of the pixel
  • the second source driving chip 22 is configured to input a data signal to the input end of the thin film transistor of the sub-pixel (such as R2G2B2R4G4B4) in the even-numbered column through the data line (the data signal is right The eye or left eye displays the data signal of the pixel).
  • the first source driving chip 21 inputs the data signal of the left eye display pixel
  • the second source driving chip 22 inputs the data signal of the right eye display pixel
  • the first source driving chip 21 inputs the data of the right eye display pixel.
  • the second source driving chip 22 inputs the data signal of the left eye display pixel.
  • the display panel is a liquid crystal display panel or an active matrix organic light emitting diode display panel.
  • FIG. 3 a schematic structural diagram of a pixel unit according to a third embodiment of the present invention is shown.
  • the display panel of the present invention includes an array substrate, the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line, the pixel unit including: a red pixel and a green pixel , blue pixels (such as R, G, B), of course, may also include yellow pixels or white pixels.
  • the present invention is exemplified by the manner in which the pixel arrangement order in the pixel unit is red, green, or blue (RGB), and does not constitute a limitation of the present invention.
  • the pixel unit may also include other sorting order: blue, red, green (BRG)
  • the red pixel is divided into four red sub-pixels R1, R2, R3, and R4, and the four red sub-pixels are arranged in a matrix structure of 2*2 (the red sub-pixel R1 is located The 0th row and the 0th column of the 2*2 matrix of the red pixel, the red sub-pixel R2 is located in the 0th row and the 1st column of the 2*2 matrix of the red pixel, the red sub-pixel R3 is located in the first row and the 0th column of the 2*2 matrix of the red pixel, and the red sub-pixel R4 is located in the 1st row and the 1st column of the 2*2 matrix of the red pixel);
  • the green pixel is divided into four green sub-pixels G1, G2, G3, and G4, and the four green sub-pixels are arranged in a matrix structure of 2*2 (the matrix structure of the four green sub-pixels and the above four The matrix structure of the red sub-pixels is the same, and will not be enumerated here);
  • the blue pixel is divided into four blue sub-pixels B1, B2, B3, and B4, and the four blue sub-pixels are arranged in a matrix structure of 2*2 (four matrices of the blue sub-pixels)
  • the structure is the same as the matrix structure of the above four red sub-pixels, and will not be enumerated here).
  • the above matrix structure may also be other matrix structures (for example, the red sub-pixel R1 is located in the 0th row and the 0th column of the 2*2 matrix of the red pixel, and the red sub-pixel R2 is located at the red pixel.
  • the red sub-pixel R3 is located in the 0th row and the 1st column of the 2*2 matrix of the red pixel, and the red sub-pixel R4 is located in the 1st row and the 1st column of the 2*2 matrix of the red pixel) All of them are within the protection scope of the present invention, and are not enumerated here.
  • R1G1B1 constitutes a first pixel subunit
  • R2G2B2 constitutes a second pixel subunit
  • R3G3B3 constitutes a third pixel subunit
  • R4G4B4 constitutes a fourth pixel subunit
  • all subpixels in the pixel unit are in a 2*6 matrix structure.
  • All of the sub-pixels in the pixel unit may also be other matrix structures (such as 6*2), which are all within the scope of the present invention, and are not enumerated here.
  • the second 2D image when the display panel displays the second 2D image, the second 2D image includes a plurality of display pixels; the second 2D image is a plain 2D image;
  • Each of the pixel subunits of the pixel unit receives a data signal of the same display pixel and a scan signal.
  • the equivalent structure diagram of the pixel unit is as shown in FIG. 3:
  • red sub-pixels R1, R2, R3, R4 are equivalent to R (red pixels)
  • all of the green sub-pixels G1, G2, G3, G4 are equivalent to G (green pixels)
  • all of the blue Sub-pixels B1, B2, B3, B4 are equivalent to B (blue pixels).
  • the sub-pixel arrangement in the odd-numbered rows in the pixel unit is R1G1B1R2G2B2, that is, sub-pixels of different colors are adjacently disposed, and in the pixel unit in the present invention
  • the sub-pixel arrangement in the odd-numbered row is R1R2G1G2B1B2, such that the sub-pixels of the same color are adjacent between the finally displayed pictures (ie, the red sub-pixels in the same pixel unit are adjacently disposed, the same pixel unit)
  • the green sub-pixels are disposed adjacent to each other, and the blue sub-pixels in the same pixel unit are adjacently disposed).
  • the pixels of different colors in the prior art can be adjacent to each other, and when the 2D image is displayed, the display effect equivalent to the prior art can be achieved.
  • the array substrate includes a source driving chip and a gate driving chip, and each of the source driving chip and the gate driving chip is used to scan each pixel in the pixel unit through a scan line.
  • the control terminal of the thin film transistor inputs a scan signal
  • the source driving chip is configured to input a data signal to an input end of the thin film transistor of each pixel in the pixel unit through a data line, when the gate driving chip is to the first row
  • the source drive chip inputs a data signal to the first row of pixels
  • the gate drive chip inputs the scan signal to the second row of pixels
  • the source drive chip inputs a data signal to the second row of pixels.
  • each of the sub-pixels includes a thin film transistor
  • Each of the sub-pixels includes a thin film transistor
  • the array substrate further includes a source driving chip and a gate driving chip: the gate driving chip includes a first gate driving chip 11 and a second gate driving chip 12; the source driving chip includes a first source driving chip 21 and a second source Driving chip 22;
  • the first gate driving chip 11 is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel (for example, R1R2G1G2B1B2) of the odd-numbered row in the pixel unit through the scan line;
  • the second gate driving chip 12 is configured to input a scan signal to a control end of the thin film transistor of the sub-pixel (such as R3R4G3G4B3B4) of the even-numbered row in the pixel unit through the scan line;
  • the first gate driving chip 11 and the second gate driving chip 12 simultaneously input the same scanning signal to the sub-pixels located in the odd rows and the sub-pixels located in the even rows, respectively.
  • the first source driving chip 21 is configured to input a data signal to an input end of the thin film transistor of the sub-pixel (for example, R1G1B1R3G3B3) of the odd-numbered column in the pixel unit through the data line;
  • the second source driving chip 22 is configured to input a data signal to an input end of the thin film transistor of the sub-pixel (such as R2G2B2R4G4B4) of the even-numbered column in the pixel unit through the data line.
  • the first source driving chip 21 and the second source driving chip 22 simultaneously input the same data signal to the sub-pixels located in the odd columns and the sub-pixels located in the even columns, respectively.
  • the present invention adopts two conventional gate driving chips and two conventional source driving chips, and can display the same display as the prior art in displaying the general clear 2D image. effect.
  • the display panel is a liquid crystal display panel or an active matrix organic light emitting diode display panel.
  • FIG. 5 is a schematic diagram showing the working flow and structure of a signal control module according to a fourth embodiment of the present invention.
  • the display panel further includes a signal control module 30, the signal control module 30 includes: a signal analysis chip 31 and a timing controller 32;
  • the signal analysis chip 31 is configured to analyze the sharpness and display mode of the input signal source of the display panel, and generate an analysis result; wherein the display mode is a 3D or 2D mode.
  • the timing controller 32 is configured to process the signal source according to the analysis result obtained by the signal analysis chip 31 to obtain a data signal and a scan signal, and transmit the obtained data signal and scan signal to the source. Driving the chip and the gate driving chip.
  • the image input by the display panel is analyzed, and the input image includes a high definition 2D image, a 3D image, and a Puqing 2 A D image, wherein the input image includes a plurality of display pixels.
  • the timing controller 32 processes the input image to obtain a high definition 2
  • the scanning signal and the data signal of the display pixel of the D image are input to the first gate driving chip 11 and the second gate driving chip 12 in the first embodiment, and the obtained data signal is input to the first source driving chip. 21 and second source drive chip 22 to display HD 2 D image.
  • the timing controller 32 processes the input image to obtain a scan signal and a data signal of the display pixel of the 3D image, and inputs the obtained scan signal into the first gate driving chip 11 and the second in the second embodiment.
  • the gate driving chip 12 and the obtained data signal are input to the first source driving chip 21 and the second source driving chip 22 to display 3 D image.
  • the timing controller 32 processes the input image to obtain a scan signal and a data signal of the display pixel of the plain 2D image, and inputs the obtained scan signal into the first gate driving chip 11 in the third embodiment.
  • the second gate driving chip 12 and the obtained data signal are input to the first source driving chip 21 and the second source driving chip 22 to display the Puqing 2 D image.
  • Embodiments 1 to 3 of the present invention please refer to Embodiments 1 to 3 of the present invention, which will not be described in detail herein.
  • the present invention provides a signal control module capable of analyzing the sharpness of an input image and a display mode (such as a high definition 2D image, a plain 2D image, and a 3D image), and processing the image determined according to the analysis result.
  • a signal control module capable of analyzing the sharpness of an input image and a display mode (such as a high definition 2D image, a plain 2D image, and a 3D image), and processing the image determined according to the analysis result.
  • the scanning signal and the data signal in the driving circuit of the above image can be automatically switched between the 2D image and the 3D image, and the production cost can be reduced, and the life can be facilitated.
  • the present invention also includes a display device, the display device comprising: a display panel; the display panel comprising an array substrate;
  • the array substrate includes a data line, a scan line, and a plurality of pixel units alternately formed by the data line and the scan line.
  • the pixel unit includes at least two pixel sub-units, where the pixel sub-unit includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the blue sub-pixels in the same pixel unit are adjacently disposed, the same The red sub-pixels in the pixel unit are adjacently disposed, and the green sub-pixels in the same pixel unit are adjacently disposed.

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Abstract

一种显示面板，所述显示面板包括至少两个像素子单元，所述像素子单元包括蓝色子像素（B1，B2，B3，B4）、红色子像素（R1，R2，R3，R4）、绿色子像素（G1，G2，G3，G4），同一所述像素子单元中的所述蓝色子像素（B1，B2，B3，B4）相邻设置，同一所述像素单元中的所述红色子像素（R1，R2，R3，R4）相邻设置，同一所述像素单元中的所述绿色子像素（G1，G2，G3,G4）相邻设置。该显示面板可自动切换2D图像和3D图像，使画面更流畅。

Description

一种显示面板及显示装置 技术领域
本发明涉及显示技术领域，特别是涉及一种显示面板及显示装置。
 背景技术
目前主流的显示面板包括：TFT-LCD（薄膜晶体管液晶显示器）和AMOLED（有源矩阵有机发光二极体显示面板）两种，作为新一代显示技术AMOLED具有它独特的显示优势，如色域更广，相应更快，亮度更好，视角更大，功耗更低，体积更小等。
但随着新材料与新技术的不断发展，TFT-LCD与AMOLED的画质差距也在不断缩小，并且由于受限于技术不成熟及生产成本较高的原因，AMOLED目前还只能应用在小尺寸上。
除此之外，显示面板的分辨率也在不断增加，目前市面上最高显示分辨率已达到3840*2160(4K*2K)（即高清），由于受限于信号源，目前尚未得到推广。但随着信息技术的发展，4K高画质信号源也会得到普及，因此高清显示面板会逐渐走向千家万户。此外，3D显示器也在迅速发展当中。
 技术问题
本发明的一个目的在于提供一种显示面板及显示装置，能够在2D图像和3D图像之间自动切换，并使得画面更流畅以及降低生产成本。
 技术解决方案
本发明提供一种显示面板，
所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板；
所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括四个所述像素子单元，四个所述蓝色子像素按2*2的矩阵结构进行设置，四个所述红色子像素按2*2的矩阵结构进行设置，四个所述绿色子像素按2*2的矩阵结构进行设置，所述像素单元中的所有子像素按2*6的矩阵结构。
在本发明的显示面板中，所述显示面板显示第一2D图像时，所述第一2D图像包括多个显示像素；
所述像素单元中的每个所述像素子单元接收不同显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号；
所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号；
所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述显示面板显示第二2D图像时，所述第二2D图像包括多个显示像素；
所述像素单元中的每个所述像素子单元接收相同显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述子像素包括一薄膜晶体管；
所述阵列基板还包括源驱动芯片和栅驱动芯片：
所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
在本发明的显示面板中，所述显示面板还包括信号控制模块，所述信号控制模块包括：
信号分析芯片，用于分析所述显示面板输入信号源的清晰度及显示模式，生成分析结果；
时序控制器，用于根据所述信号分析芯片得到的分析结果对所述信号源进行相应地处理得到数据信号和扫描信号，并将得到的所述数据信号和扫描信号传输给所述源驱动芯片和所述栅驱动芯片。
本发明构造了一种显示面板，所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括至少两个像素子单元，所述像素子单元包括蓝色子像素、红色子像素以及绿色子像素，同一所述像素单元中的所述蓝色子像素相邻设置，同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置。
在本发明的显示面板中，所述像素单元包括四个所述像素子单元，四个所述蓝色子像素按2*2的矩阵结构进行设置，四个所述红色子像素按2*2的矩阵结构进行设置，四个所述绿色子像素按2*2的矩阵结构进行设置，所述像素单元中的所有子像素按2*6的矩阵结构。
在本发明的显示面板中，所述显示面板显示第一2D图像时，所述第一2D图像包括多个显示像素；
所述像素单元中的每个所述像素子单元接收不同显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号；
所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号；
所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述显示面板显示第二2D图像时，所述第二2D图像包括多个显示像素；
所述像素单元中的每个所述像素子单元接收相同显示像素的数据信号以及扫描信号。
在本发明的显示面板中，所述子像素包括一薄膜晶体管；
所述阵列基板还包括源驱动芯片和栅驱动芯片：
所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
在本发明的显示面板中，所述显示面板还包括信号控制模块，所述信号控制模块包括：
信号分析芯片，用于分析所述显示面板输入信号源的清晰度及显示模式，生成分析结果；
时序控制器，用于根据所述信号分析芯片得到的分析结果对所述信号源进行相应地处理得到数据信号和扫描信号，并将得到的所述数据信号和扫描信号传输给所述源驱动芯片和所述栅驱动芯片。
在本发明的显示面板中，所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板。
本发明的另一个目的在于提供一种显示装置，所述显示装置包括：显示面板；
所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元，
所述像素单元包括至少两个像素子单元，所述像素子单元包括蓝色子像素、红色子像素以及绿色子像素，同一所述像素单元中的所述蓝色子像素相邻设置，同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置。
 有益效果
本发明通过提供一种像素单元中子像素的排列不同的阵列基板，能够在2D图像和3D图像之间自动切换，并使得画面更流畅；以及采用2个常规的栅驱动芯片和2个常规的源驱动芯片，实现复杂的驱动过程，从而降低生产成本。
 附图说明
图1是本发明实施例中第一实施例的像素单元结构示意图。
图2是本发明实施例中第二实施例的像素单元结构示意图。
图3是本发明实施例中第三实施例的像素单元结构示意图。
图4是本发明实施例中第一至第三实施例中的驱动电路结构示意图。
图5是本发明实施例中第四实施例的信号控制模块的工作流程及结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图1，本发明实施例中第一实施例的像素单元结构示意图。
本发明的显示面板，包括阵列基板，所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元，所述像素单元包括：红色像素、绿色像素、蓝色像素（譬如 R、G、B），当然也可以包括黄色像素或白色像素，本发明仅以所述像素单元中的像素排列顺序为红色、绿色、蓝色（RGB）的方式举例说明，不构成对本发明的限定，譬如所述像素单元还可以包括其他排列顺序：蓝色、红色、绿色（BRG）。
如图1所示，将所述红色像素划分为四个红色子像素R1、R2、R3、R4，所述四个红色子像素按2*2的矩阵结构进行设置（所述红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，所述红色子像素R2位于所述红色像素的2*2矩阵中的第0行第1列，所述红色子像素 R3位于所述红色像素的2*2矩阵中的第1行第0列，所述红色子像素R4位于所述红色像素的2*2矩阵中的第1行第1列）；
将所述绿色像素划分为四个绿色子像素G1、G2、G3、G4，所述四个绿色子像素按2*2的矩阵结构进行设置（四个所述绿色子像素的矩阵结构与上述四个所述红色子像素的矩阵结构相同，此处不再一一列举）；
将所述蓝色像素划分为四个蓝色子像素B1、B2、B3、B4，所述四个蓝色子像素按2*2的矩阵结构进行设置（四个所述蓝色子像素的矩阵结构与上述四个所述红色子像素的矩阵结构相同，此处不再一一列举）。
当然上述矩阵结构也可以是其他的矩阵结构（譬如所述红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，所述红色子像素R2位于所述红色像素的2*2矩阵中的第1行第0列, 所述红色子像素R3位于所述红色像素的2*2矩阵中的第0行第1列，所述红色子像素R4位于所述红色像素的2*2矩阵中的第1行第1列），均在本发明的保护范围之内，此处不一一列举。
其中R1G1B1构成第一像素子单元，R2G2B2构成第二像素子单元，R3G3B3构成第三像素子单元、R4G4B4构成第四像素子单元，所述像素单元中的所有子像素按2*6的矩阵结构，所述像素单元中的所有子像素也可以是其他矩阵结构（譬如6*2），均在本发明的保护范围之内，此处不一一列举。
在本发明中，所述显示面板显示第一2D图像时，所述第一2D图像包括多个显示像素；所述第一2D图像为高清2D图像（譬如，4K图像）；
所述像素单元中的每个所述像素子单元接收不同显示像素的数据信号以及扫描信号。
由于现有技术中显示高清2D图像时，所述像素单元中的位于奇数行的所述子像素排列是R1G1B1R2G2B2，即不同颜色的子像素相邻设置，使得在实际显示高清画面时，在人眼区分不出的情况下，画面不够流畅；
而本发明中所述像素单元中的位于奇数行的所述子像素排列譬如是R1R2G1G2B1B2，使得最终显示的画面中同一颜色的子像素之间相邻（即同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置、同一所述像素单元中的所述蓝色子像素相邻设置），采用上述结构能够比现有技术中不同颜色的像素相邻，在显示高清2D图像时，画面更流畅。
现有技术中，所述阵列基板包括源驱动芯片和栅驱动芯片，所述源驱动芯片和栅驱动芯片各一个，所述栅驱动芯片用于通过扫描线向所述像素单元中的每个像素的薄膜晶体管的控制端输入扫描信号，所述源驱动芯片用于通过数据线向所述像素单元中的每个像素的薄膜晶体管的输入端输入数据信号。当所述栅驱动芯片向第一行像素输入扫描信号时，所述源驱动芯片向第一行像素输入数据信号，当所述栅驱动芯片向第二行像素输入扫描信号时，所述源驱动芯片向第二行像素输入数据信号。
本实施例还包括一种驱动电路，其结构如图4所示，每个所述子像素包括一薄膜晶体管；
所述阵列基板还包括源驱动芯片和栅驱动芯片（图中未示出）：所述栅驱动芯片包括第一栅驱动芯片11和第二栅驱动芯片12；所述源驱动芯片包括第一源驱动芯片21和第二源驱动芯片22；
其中，所述第一栅驱动芯片11，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素（譬如R1R2G1G2B1B2）的薄膜晶体管的控制端输入扫描信号；
所述第二栅驱动芯片12，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素（譬如R3R4G3G4B3B4）的薄膜晶体管的控制端输入扫描信号；
所述第一源驱动芯片21，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素（譬如R1G1B1R3G3B3）的薄膜晶体管的输入端输入数据信号；
所述第二源驱动芯片22，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素（譬如R2G2B2R4G4B4）的薄膜晶体管的输入端输入数据信号。
现有技术中仅设置一个栅驱动芯片和一个源驱动芯片，为了显示高清2D图像需要比较复杂的驱动过程，对上述单个栅驱动芯片和单个源驱动芯片功能要求更高，需要将单个栅驱动芯片和单个源驱动芯片结构设计的更加复杂；而本发明仅采用2个常规的栅驱动芯片和2个常规的源驱动芯片就可以实现比较复杂的驱动过程，因而降低了生产成本。
所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板。
请参照图2，本发明实施例中第二实施例的像素单元结构示意图。
本发明的显示面板，包括阵列基板，所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元，所述像素单元包括：红色像素、绿色像素、蓝色像素（譬如 R、G、B），当然也可以包括黄色像素或白色像素，本发明仅以像素单元中像素排列顺序为红色、绿色、蓝色（RGB）的方式举例说明，不构成对本发明的限定。譬如所述像素单元还可以包括其他排列顺序：蓝色、红色、绿色（BRG）。
如图1所示，将所述红色像素划分为四个红色子像素R1、R2、R3、R4，所述四个红色子像素按2*2的矩阵结构进行设置（所述红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，所述红色子像素R2位于所述红色像素的2*2矩阵中的第0行第1列，所述红色子像素 R3位于所述红色像素的2*2矩阵中的第1行第0列，所述红色子像素R4位于所述红色像素的2*2矩阵中的第1行第1列）；
将所述绿色像素划分为四个绿色子像素G1、G2、G3、G4，所述四个绿色子像素按2*2的矩阵结构进行设置（四个所述绿色子像素的矩阵结构与上述四个所述红色子像素的矩阵结构相同，此处不再一一列举）；
将所述蓝色像素划分为四个蓝色子像素B1、B2、B3、B4，所述四个蓝色子像素按2*2的矩阵结构进行设置（四个所述蓝色子像素的矩阵结构与上述四个所述红色子像素的矩阵结构相同，此处不再一一列举）。
当然上述矩阵结构也可以是其他的矩阵结构（譬如所述红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，所述红色子像素R2位于所述红色像素的2*2矩阵中的第1行第0列，所述红色子像素R3位于所述红色像素的2*2矩阵中的第0行第1列，所述红色子像素R4位于所述红色像素的2*2矩阵中的第1行第1列），均在本发明的保护范围之内，此处不一一列举。
其中R1G1B1构成第一像素子单元，R2G2B2构成第二像素子单元，R3G3B3构成第三像素子单元、R4G4B4构成第四像素子单元，所述像素单元中的所有子像素按2*6的矩阵结构，所述像素单元中的所有子像素也可以是其他矩阵结构（譬如6*2），均在本发明的保护范围之内，此处不一一列举。
在本发明中，所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
所述像素子单元中的每个所述子像素位于所述子像素相应的像素矩阵中的同一位置（譬如第一像素子单元R1G1B1中，红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，绿色子像素G1位于所述绿色像素的2*2矩阵中的第0行第0列，蓝色子像素B1位于所述蓝色像素的2*2矩阵中的第0行第0列）。
所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元（譬如R1G1B1、R3G3B3）接收左眼或者右眼显示像素的数据信号以及扫描信号，所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元（譬如R2G2B2、R4G4B4）接收右眼或左眼显示像素的数据信号以及扫描信号。
当R1G1B1、R3G3B3接收左眼显示像素的数据信号以及扫描信号时，所述R2G2B2、R4G4B4接收右眼显示像素的数据信号以及扫描信号；此时，所述像素单元中的等效结构图如图2所示：其中所述红色子像素R1和R3等效于Rl（红色左眼像素）， 所述绿色子像素G1和G3等效于Gl（绿色左眼像素），所述蓝色子像素B1和B3等效于Bl（蓝色左眼像素）。
所述红色子像素R2和R4等效于 Rr（红色右眼像素），所述绿色子像素G2和G4等效于 Gr（绿色右眼像素），所述蓝色子像素B2和B4等效于 Br（蓝色右眼像素）。
当R1G1B1、R3G3B3接收右眼显示像素的数据信号以及扫描信号时，所述R2G2B2、R4G4B4接收左眼显示像素的数据信号以及扫描信号。此时，所述像素单元的等效结构图是将图2中全部颜色的左右眼像素位置互换，在此不再一一列举。
由于现有技术中显示3D图像时，所述像素单元中的位于奇数行的所述子像素排列譬如是R1G1B1R2G2B2，即不同颜色的子像素相邻设置，使得在实际显示3D图像时，在人眼区分不出的情况下，左右眼画面不够流畅；
而本发明中所述像素单元中的位于奇数行的所述子像素排列是R1R2G1G2B1B2，使得最终显示的画面中同一颜色的子像素之间相邻（即同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置、同一所述像素单元中的所述蓝色子像素相邻设置）。
采用上述的结构能够比现有技术中不同颜色的像素相邻，在显示3D图像时，使得左右眼画面更流畅。
现有技术中，所述阵列基板包括源驱动芯片和栅驱动芯片，所述源驱动芯片和栅驱动芯片各一个，所述栅驱动芯片用于通过扫描线向所述像素单元中的每个像素的薄膜晶体管的控制端输入扫描信号，所述源驱动芯片用于通过数据线向所述像素单元中的每个像素的薄膜晶体管的输入端输入数据信号，当所述栅驱动芯片向第一行像素输入扫描信号时，所述源驱动芯片向第一行像素输入数据信号，当所述栅驱动芯片向第二行像素输入扫描信号时，所述源驱动芯片向第二行像素输入数据信号。
本实施例还包括一种驱动电路，结构如图4所示，每个所述子像素包括一薄膜晶体管；
所述阵列基板还包括源驱动芯片和栅驱动芯片：所述栅驱动芯片包括第一栅驱动芯片11和第二栅驱动芯片12；所述源驱动芯片包括第一源驱动芯片21和第二源驱动芯片22；
其中，所述第一栅驱动芯片11，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素（譬如R1R2G1G2B1B2）的薄膜晶体管的控制端输入扫描信号；
所述第二栅驱动芯片12，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素（譬如R3R4G3G4B3B4）的薄膜晶体管的控制端输入扫描信号；
在本实施例中所述第一栅驱动芯片11和所述第二栅驱动芯片12分别向位于奇数行的所述子像素和位于偶数行的所述子像素同时输入相同的扫描信号。
所述第一源驱动芯片21，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素（譬如R1G1B1R3G3B3）的薄膜晶体管的输入端输入数据信号（该数据信号为左眼或右眼显示像素的数据信号）；
所述第二源驱动芯片22，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素（譬如R2G2B2R4G4B4）的薄膜晶体管的输入端输入数据信号（该数据信号为右眼或左眼显示像素的数据信号）。所述第一源驱动芯片21输入左眼显示像素的数据信号时，所述第二源驱动芯片22输入右眼显示像素的数据信号；所述第一源驱动芯片21输入右眼显示像素的数据信号时，所述第二源驱动芯片22输入左眼显示像素的数据信号。
现有技术中仅设置一个栅驱动芯片和一个源驱动芯片，为了显示3D图像需要比较复杂的驱动过程，对上述单个栅驱动芯片和单个源驱动芯片功能要求更高，需要将单个栅驱动芯片和单个源驱动芯片结构设计的更加复杂，而本发明仅采用2个常规的栅驱动芯片和2个常规的源驱动芯片就可以实现比较复杂的驱动过程，因而降低了生产成本。
所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板。
请参照图3，本发明实施例中第三实施例的像素单元结构示意图。
本发明的显示面板，包括阵列基板，所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元，所述像素单元包括：红色像素、绿色像素、蓝色像素（譬如 R、G、B），当然也可以包括黄色像素或白色像素，本发明仅以像素单元中像素排列顺序为红色、绿色、蓝色（RGB）的方式举例说明，不构成对本发明的限定。譬如所述像素单元还可以包括其他排列顺序：蓝色、红色、绿色（BRG）
如图1所示，将所述红色像素划分为四个红色子像素R1、R2、R3、R4，所述四个红色子像素按2*2的矩阵结构进行设置（所述红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，所述红色子像素R2位于所述红色像素的2*2矩阵中的第0行第1列，所述红色子像素 R3位于所述红色像素的2*2矩阵中的第1行第0列，所述红色子像素R4位于所述红色像素的2*2矩阵中的第1行第1列）；
将所述绿色像素划分为四个绿色子像素G1、G2、G3、G4，所述四个绿色子像素按2*2的矩阵结构进行设置（四个所述绿色子像素的矩阵结构与上述四个所述红色子像素的矩阵结构相同，此处不再一一列举）；
将所述蓝色像素划分为四个蓝色子像素B1、B2、B3、B4，所述四个蓝色子像素按2*2的矩阵结构进行设置（四个所述蓝色子像素的矩阵结构与上述四个所述红色子像素的矩阵结构相同，此处不再一一列举）。
当然上述矩阵结构也可以是其他的矩阵结构（譬如所述红色子像素R1位于所述红色像素的2*2矩阵中的第0行第0列，所述红色子像素R2位于所述红色像素的2*2矩阵中的第1行第0列， 所述红色子像素R3位于所述红色像素的2*2矩阵中的第0行第1列，所述红色子像素R4位于所述红色像素的2*2矩阵中的第1行第1列），均在本发明的保护范围之内，此处不一一列举。
其中R1G1B1构成第一像素子单元，R2G2B2构成第二像素子单元，R3G3B3构成第三像素子单元、R4G4B4构成第四像素子单元，所述像素单元中的所有子像素按2*6的矩阵结构，所述像素单元中的所有子像素也可以是其他矩阵结构（譬如6*2），均在本发明的保护范围内，此处不一一列举。
在本实施例中，当所述显示面板显示第二2D图像时，所述第二2D图像包括多个显示像素；所述第二2D图像为普清2D图像；
所述像素单元中的每个所述像素子单元接收相同显示像素的数据信号以及扫描信号。此时，所述像素单元的等效结构图如图3所示：
其中所有所述红色子像素R1、R2、R3、R4等效于R（红色像素），所有所述绿色子像素G1、G2、G3、G4等效于G（绿色像素），所有所述蓝色子像素B1、B2、B3、B4等效于B（蓝色像素）。
由于现有技术中显示普清2D图像时，所述像素单元中的位于奇数行的所述子像素排列是R1G1B1R2G2B2，即不同颜色的子像素相邻设置，而本发明中所述像素单元中的位于奇数行的所述子像素排列是R1R2G1G2B1B2，使得最终显示的画面中同一颜色的子像素之间相邻（即同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置、同一所述像素单元中的所述蓝色子像素相邻设置）。
采用上述结构能够比现有技术中不同颜色的像素相邻，在显示普清2D图像时，能够达到现有技术同等的显示效果。
现有技术中，所述阵列基板包括源驱动芯片和栅驱动芯片，所述源驱动芯片和栅驱动芯片各一个，所述栅驱动芯片用于通过扫描线向所述像素单元中的每个像素的薄膜晶体管的控制端输入扫描信号，所述源驱动芯片用于通过数据线向所述像素单元中的每个像素的薄膜晶体管的输入端输入数据信号，当所述栅驱动芯片向第一行像素输入扫描信号时，所述源驱动芯片向第一行像素输入数据信号，当所述栅驱动芯片向第二行像素输入扫描信号时，所述源驱动芯片向第二行像素输入数据信号。
本实施例还包括一种驱动电路，结构如图4所示，每个所述子像素包括一薄膜晶体管；
每个所述子像素包括一薄膜晶体管；
所述阵列基板还包括源驱动芯片和栅驱动芯片：所述栅驱动芯片包括第一栅驱动芯片11和第二栅驱动芯片12；所述源驱动芯片包括第一源驱动芯片21和第二源驱动芯片22；
其中，所述第一栅驱动芯片11，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素（譬如R1R2G1G2B1B2）的薄膜晶体管的控制端输入扫描信号；
所述第二栅驱动芯片12，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素（譬如R3R4G3G4B3B4）的薄膜晶体管的控制端输入扫描信号；
在本实施例中所述第一栅驱动芯片11和所述第二栅驱动芯片12分别向位于奇数行的所述子像素和位于偶数行的所述子像素同时输入相同的扫描信号。
所述第一源驱动芯片21，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素（譬如R1G1B1R3G3B3）的薄膜晶体管的输入端输入数据信号；
所述第二源驱动芯片22，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素（譬如R2G2B2R4G4B4）的薄膜晶体管的输入端输入数据信号。
在本实施例中所述第一源驱动芯片21和所述第二源驱动芯片22分别向位于奇数列的所述子像素和位于偶数列的所述子像素同时输入相同的数据信号。
现有技术中仅设置一个栅驱动芯片和一个源驱动芯片，本发明采用2个常规的栅驱动芯片和2个常规的源驱动芯片，在显示普清2D图像能达到与现有技术同等的显示效果。
所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板。
请参照图5，图5是本发明实施例中第四实施例的信号控制模块的工作流程及结构示意图。
如图5所示，所述显示面板还包括信号控制模块30，所述信号控制模块30包括：信号分析芯片31和时序控制器32；
信号分析芯片31，用于分析所述显示面板输入信号源的清晰度及显示模式，生成分析结果；其中，所述显示模式为3D或2D模式。
时序控制器32，用于根据所述信号分析芯片31得到的分析结果对所述信号源进行相应地处理得到数据信号和扫描信号，并将得到的所述数据信号和扫描信号传输给所述源驱动芯片和所述栅驱动芯片。
即对显示面板输入的图像进行分析，所述输入的图像包括高清2 D图像、3D图像、普清2 D图像，其中所述输入的图像包括多个显示像素。
譬如当所述信号分析芯片31分析出输入图像是高清2 D图像时，所述时序控制器32对输入的图像进行处理得到高清2 D图像的显示像素的扫描信号和数据信号，并将得到的扫描信号输入实施例1中的第一栅驱动芯片11和第二栅驱动芯片12、以及将得到的数据信号输入第一源驱动芯片21和第二源驱动芯片22，以显示高清2 D图像。
譬如当所述信号分析芯片31分析出输入图像是3 D图像时，所述时序控制器32对输入的图像进行处理得到3D图像的显示像素的扫描信号和数据信号，并将得到的扫描信号输入实施例2中的第一栅驱动芯片11和第二栅驱动芯片12、以及将得到的数据信号输入第一源驱动芯片21和第二源驱动芯片22，以显示3 D图像。
譬如当所述信号分析芯片31分析出输入图像是普清2 D图像时，所述时序控制器32对输入的图像进行处理得到普清2D图像的显示像素的扫描信号和数据信号，并将得到的扫描信号输入实施例3中的第一栅驱动芯片11和第二栅驱动芯片12、以及将得到的数据信号输入第一源驱动芯片21和第二源驱动芯片22，以显示普清2 D图像。
上述驱动芯片的具体的驱动方式请参照本发明实施例1至3，在此不详细描述。
本发明通过提供一种信号控制模块，能够对输入图像的清晰度和显示模式（譬如高清2D图像、普清2D图像、以及3D图像）进行分析，并根据对分析结果所确定的图像进行处理，得到上述图像的驱动电路中的扫描信号和数据信号，能够在2D图像和3D图像之间自动切换，并能够降低生产成本，给生活提供便利。
本发明还包括一种显示装置，所述显示装置包括：显示面板；所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元，
所述像素单元包括至少两个像素子单元，所述像素子单元包括蓝色子像素、红色子像素以及绿色子像素，同一所述像素单元中的所述蓝色子像素相邻设置，同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置。
鉴于所述显示面板在上文已有详细的描述，此处不再赘述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
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Claims (20)

  1. 一种显示面板，其中所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板；
    所述显示面板包括阵列基板；
    所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
    所述像素单元包括四个所述像素子单元，四个所述蓝色子像素按2*2的矩阵结构进行设置，四个所述红色子像素按2*2的矩阵结构进行设置，四个所述绿色子像素按2*2的矩阵结构进行设置，所述像素单元中的所有子像素按2*6的矩阵结构。
  2. 2、根据权利要求1所述的显示面板，其中所述显示面板显示第一2D图像时，所述第一2D图像包括多个显示像素；
    所述像素单元中的每个所述像素子单元接收不同显示像素的数据信号以及扫描信号。
  3. 3、根据权利要求1所述的显示面板，其中所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
    所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号；
    所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号。
  4. 4、根据权利要求1所述的显示面板，其中所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
    所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号；
    所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号。
  5. 5、根据权利要求1所述的显示面板，其中所述显示面板显示第二2D图像时，所述第二2D图像包括多个显示像素；
    所述像素单元中的每个所述像素子单元接收相同显示像素的数据信号以及扫描信号。
  6. 6、根据权利要求2所述的显示面板，其中所述子像素包括一薄膜晶体管；
    所述阵列基板还包括源驱动芯片和栅驱动芯片：
    所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
    所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
    其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
    所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
  7. 7、根据权利要求6所述的显示面板，其中所述显示面板还包括信号控制模块；所述信号控制模块包括：
    信号分析芯片，用于分析所述显示面板输入信号源的清晰度及显示模式，生成分析结果；
    时序控制器，用于根据所述信号分析芯片得到的分析结果对所述信号源进行相应地处理得到数据信号和扫描信号，并将得到的所述数据信号和扫描信号传输给所述源驱动芯片和所述栅驱动芯片。
  8. 8、一种显示面板，其中所述显示面板包括阵列基板；
    所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
    所述像素单元包括至少两个像素子单元，所述像素子单元包括蓝色子像素、红色子像素以及绿色子像素，同一所述像素单元中的所述蓝色子像素相邻设置，同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置。
  9. 9、根据权利要求8所述的显示面板，其中所述像素单元包括四个所述像素子单元，四个所述蓝色子像素按2*2的矩阵结构进行设置，四个所述红色子像素按2*2的矩阵结构进行设置，四个所述绿色子像素按2*2的矩阵结构进行设置，所述像素单元中的所有子像素按2*6的矩阵结构。
  10. 10、根据权利要求9所述的显示面板，其中所述显示面板显示第一2D图像时，所述第一2D图像包括多个显示像素；
    所述像素单元中的每个所述像素子单元接收不同显示像素的数据信号以及扫描信号。
  11. 11、根据权利要求9所述的显示面板，其中所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
    所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号；
    所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号。
  12. 12、根据权利要求9所述的显示面板，其中所述显示面板显示3D图像时，所述3D图像包括多个显示像素；
    所述像素单元中的位于奇数列的所述子像素构成的所述像素子单元接收右眼显示像素的数据信号以及扫描信号；
    所述像素单元中的位于偶数列的所述子像素构成的所述像素子单元接收左眼显示像素的数据信号以及扫描信号。
  13. 13、根据权利要求9所述的显示面板，其中所述显示面板显示第二2D图像时，所述第二2D图像包括多个显示像素；
    所述像素单元中的每个所述像素子单元接收相同显示像素的数据信号以及扫描信号。
  14. 14、根据权利要求10所述的显示面板，其中所述子像素包括一薄膜晶体管；
    所述阵列基板还包括源驱动芯片和栅驱动芯片：
    所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
    所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
    其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
    所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
  15. 15、根据权利要求11所述的显示面板，其中所述子像素包括一薄膜晶体管；
    所述阵列基板还包括源驱动芯片和栅驱动芯片：
    所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
    所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
    其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
    所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
  16. 16、根据权利要求12所述的显示面板，其中所述子像素包括一薄膜晶体管；
    所述阵列基板还包括源驱动芯片和栅驱动芯片：
    所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
    所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
    其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
    所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
  17. 17、根据权利要求13所述的显示面板，其中所述子像素包括一薄膜晶体管；
    所述阵列基板还包括源驱动芯片和栅驱动芯片：
    所述栅驱动芯片包括第一栅驱动芯片和第二栅驱动芯片；
    所述源驱动芯片包括第一源驱动芯片和第二源驱动芯片；
    其中，所述第一栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于奇数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第二栅驱动芯片，用于通过所述扫描线向所述像素单元中的位于偶数行的所述子像素的薄膜晶体管的控制端输入扫描信号；
    所述第一源驱动芯片，用于通过所述数据线向所述像素单元中的位于奇数列的所述子像素的薄膜晶体管的输入端输入数据信号；
    所述第二源驱动芯片，用于通过所述数据线向所述像素单元中的位于偶数列的所述子像素的薄膜晶体管的输入端输入数据信号。
  18. 18、根据权利要求14所述的显示面板，其中所述显示面板还包括信号控制模块，所述信号控制模块包括：
    信号分析芯片，用于分析所述显示面板输入信号源的清晰度及显示模式，生成分析结果；
    时序控制器，用于根据所述信号分析芯片得到的分析结果对所述信号源进行相应地处理得到数据信号和扫描信号，并将得到的所述数据信号和扫描信号传输给所述源驱动芯片和所述栅驱动芯片。
  19. 19、根据权利要求8所述的显示面板，其中所述显示面板为液晶显示面板或者是有源矩阵有机发光二极体显示面板。
  20. 20、一种显示装置，其中所述显示装置包括显示面板；
    所述显示面板包括阵列基板；
    所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元，
    所述像素单元包括至少两个像素子单元，所述像素子单元包括蓝色子像素、红色子像素以及绿色子像素，同一所述像素单元中的所述蓝色子像素相邻设置，同一所述像素单元中的所述红色子像素相邻设置，同一所述像素单元中的所述绿色子像素相邻设置。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104297832B (zh) * 2014-09-28 2017-02-15 合肥鑫晟光电科技有限公司 彩色滤光片及制作方法、显示面板、显示装置及驱动方法
US10062317B2 (en) * 2014-10-16 2018-08-28 Lg Display Co., Ltd. Panel array for display device with narrow bezel
CN104635395A (zh) * 2015-03-06 2015-05-20 合肥京东方光电科技有限公司 一种平板显示装置
JP2017003894A (ja) * 2015-06-15 2017-01-05 ソニー株式会社 表示装置及び電子機器
US11262865B2 (en) 2015-12-09 2022-03-01 Novatek Microelectronics Corp. Sensor device and system and related controller, multiplexer and panel apparatus
US10055049B2 (en) * 2015-12-09 2018-08-21 Novatek Microelectronics Corp. Touch sensor system and multiplexer thereof
US10678369B2 (en) 2015-12-09 2020-06-09 Novatek Microelectronics Corp. Touch sensor system and multiplexer thereof
US10339882B2 (en) * 2015-12-09 2019-07-02 L-3 Communications Corporation Fault-tolerant AMLCD display
CN106791796B (zh) * 2017-01-11 2019-02-01 京东方科技集团股份有限公司 显示面板及其驱动方法和制作方法、显示装置
CN106935167A (zh) * 2017-05-19 2017-07-07 京东方科技集团股份有限公司 用于显示面板画面测试的装置及显示面板画面的测试方法
CN107068101B (zh) * 2017-05-22 2018-05-18 惠科股份有限公司 一种显示装置的驱动电路、驱动方法及显示装置
CN108492771B (zh) * 2018-04-03 2020-07-07 京东方科技集团股份有限公司 双面显示装置及其控制方法
CN112929644A (zh) * 2019-12-05 2021-06-08 北京芯海视界三维科技有限公司 多视点裸眼3d显示屏、多视点裸眼3d显示设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1607871A (zh) * 2003-10-14 2005-04-20 Lg电子株式会社 电致发光显示设备
US20060290859A1 (en) * 2005-06-27 2006-12-28 Ko Jeong H Liquid crystal display device
CN102006491A (zh) * 2009-08-31 2011-04-06 卡西欧计算机株式会社 三维显示设备以及控制视差屏障的方法
CN103680396A (zh) * 2012-09-18 2014-03-26 乐金显示有限公司 有机电致发光显示设备及其驱动方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3713193B2 (ja) * 2000-01-18 2005-11-02 シャープ株式会社 液晶表示装置及びその製造方法
JP4076367B2 (ja) * 2002-04-15 2008-04-16 富士通日立プラズマディスプレイ株式会社 プラズマディスプレイパネル、プラズマ表示装置及びプラズマディスプレイパネルの駆動方法
KR101071137B1 (ko) * 2005-06-29 2011-10-10 엘지디스플레이 주식회사 렌티큘러방식 입체영상표시장치
TWI268737B (en) * 2005-07-29 2006-12-11 Au Optronics Corp Full-color organic electroluminescence panel with high resolution
TWI275052B (en) * 2006-04-07 2007-03-01 Ind Tech Res Inst OLED pixel structure and method of manufacturing the same
TWI360804B (en) * 2006-06-30 2012-03-21 Au Optronics Corp Pixel structure of electroluminescent panel and me
KR101448004B1 (ko) * 2008-04-22 2014-10-07 삼성디스플레이 주식회사 유기 발광 표시 장치
US20110234605A1 (en) * 2010-03-26 2011-09-29 Nathan James Smith Display having split sub-pixels for multiple image display functions
CN103325952A (zh) * 2013-07-04 2013-09-25 京东方科技集团股份有限公司 一种oled器件及其制造方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1607871A (zh) * 2003-10-14 2005-04-20 Lg电子株式会社 电致发光显示设备
US20060290859A1 (en) * 2005-06-27 2006-12-28 Ko Jeong H Liquid crystal display device
CN102006491A (zh) * 2009-08-31 2011-04-06 卡西欧计算机株式会社 三维显示设备以及控制视差屏障的方法
CN103680396A (zh) * 2012-09-18 2014-03-26 乐金显示有限公司 有机电致发光显示设备及其驱动方法

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