WO2017015940A1 - 一种阵列基板及其制作方法 - Google Patents

一种阵列基板及其制作方法 Download PDF

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Publication number
WO2017015940A1
WO2017015940A1 PCT/CN2015/085513 CN2015085513W WO2017015940A1 WO 2017015940 A1 WO2017015940 A1 WO 2017015940A1 CN 2015085513 W CN2015085513 W CN 2015085513W WO 2017015940 A1 WO2017015940 A1 WO 2017015940A1
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WIPO (PCT)
Prior art keywords
layer
array substrate
transparent conductive
color resist
light shielding
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PCT/CN2015/085513
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English (en)
French (fr)
Inventor
刘国和
祝秀芬
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/891,695 priority Critical patent/US20170184930A1/en
Publication of WO2017015940A1 publication Critical patent/WO2017015940A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a method of fabricating the same.
  • the existing array substrate for example, BOA (BM on Array) substrate
  • BOA substrate is a color filter film and a black matrix on the array substrate
  • the array substrate comprises: a substrate substrate 11, the first metal layer 12 is located on the substrate substrate 11, including a gate; the gate insulating layer 13 portion Located on the first metal layer 12 for isolating the first metal layer 12 and the active layer 14; the active layer 14 is partially disposed on the gate insulating layer 13 for forming a channel; the second metal layer 15 is active
  • the layer 14 includes a source and a drain; a second insulating layer 16 is disposed on the second metal layer 15; a color resist layer 17 is disposed on the second insulating layer 16, and the color resist layer and the light shielding layer are formed thereon. Hole 18; and black matrix layer 19 Located on the color resist layer 17, the transparent conductive layer 20 is partially located on the black matrix layer 19.
  • the transparent conductive layer In order to make the transparent conductive layer in contact with the second metal layer, it is necessary to provide via holes on the color resist layer and the light shielding layer respectively, and after the via holes are provided in the color resist layer, the light shielding layer in the holes is relatively thick, which is disadvantageous for the light shielding layer.
  • the fabrication of the via holes may cause the holes on the color resist layer and the positions of the holes on the light shielding layer to be deviated, so that the subsequent transparent conductive layer is prone to cracks and affects the display effect.
  • the switch array layer includes a first metal layer, an active layer, and a second metal layer; wherein the first metal layer is patterned to form a plurality of gates The second metal layer is patterned to form a plurality of sources and a plurality of drains, and the active layer is used to form a channel;
  • the color resist layer comprises a red color film, a green color film, a blue color film, and a via hole is formed on the color resist layer;
  • a first insulating layer is formed on the light shielding layer.
  • the light shielding layer is a black matrix.
  • the thickness of the first insulating layer is 0.2 ⁇ m or less.
  • the transparent conductive layer is connected to the second metal layer through the via.
  • the material of the first insulating layer is an inorganic transparent material.
  • a second insulating layer is further formed between the switch array layer and the color resist layer.
  • the present invention constructs a method for fabricating an array substrate, which includes:
  • the switch array layer includes a first metal layer, an active layer, and a second metal layer; wherein the first metal layer is patterned to form a plurality of gates The second metal layer is patterned to form a plurality of sources and a plurality of drains, and the active layer is used to form a channel;
  • the color resist layer comprises a red color film, a green color film, a blue color film, and a via hole is formed on the color resist layer;
  • a light shielding layer is formed on the transparent conductive layer.
  • the light shielding layer is also filled in the via holes above the transparent conductive layer.
  • the light shielding layer is a black matrix.
  • the method further includes forming a first insulating layer on the light shielding layer.
  • the thickness of the first insulating layer is 0.2 ⁇ m or less.
  • the transparent conductive layer is connected to the second metal layer through the via.
  • the invention also provides an array substrate comprising:
  • the switch array layer includes a first metal layer, an active layer, and a second metal layer; wherein the first metal layer includes a plurality of gates, and the second metal The layer includes a plurality of sources and a plurality of drains, the active layer being used to form a channel;
  • the color resist layer comprises a red color film, a green color film, a blue color film, and a via hole is formed on the color resist layer;
  • a light shielding layer is disposed on the transparent conductive layer.
  • the light shielding layer is also provided in a via hole above the transparent conductive layer.
  • the light shielding layer is a black matrix.
  • a first insulating layer is further provided on the light shielding layer.
  • the thickness of the first insulating layer is 0.2 ⁇ m or less.
  • the transparent conductive layer is connected to the second metal layer through the via.
  • FIG. 1 is a schematic structural view of a prior art array substrate
  • FIG. 2 is a schematic structural view of an array substrate of the present invention
  • Figure 3 is a schematic view showing the electric field strength as a function of the thickness of the insulating layer
  • FIG. 5 is a flow chart of a method for fabricating an array substrate of the present invention.
  • FIG. 6 is a schematic structural view of a liquid crystal display panel of the present invention.
  • FIG. 2 is a schematic structural view of the array substrate of the present invention.
  • the array substrate of the present invention comprises: a substrate substrate 21, a switch array layer, a color resist layer 27, a transparent conductive layer 28, and a light shielding layer 29;
  • the switch array layer is disposed on the base substrate 21, and the switch array layer includes a plurality of thin film transistors; specifically including: a first metal layer 22, a gate insulating layer 23, an active layer 24, and a second metal layer 25. ;
  • the first metal layer 22 is located on the base substrate 21 and may include a plurality of gates.
  • the gate insulating layer 23 is located on the first metal layer 22, and the active layer 24 is partially located at the gate.
  • the second metal layer 25 is located on the active layer 24;
  • the color resist layer 27 is located on the second metal layer 25, and the color resist layer comprises a plurality of color film color resists;
  • the color resist layer 27 may further be provided with a via hole; the transparent conductive layer 28 is connected to the second metal layer 25 through the via hole.
  • the transparent conductive layer 28 is located on the color resist layer 27; the light shielding layer 29 is located on the transparent conductive layer 28.
  • the light shielding layer 29 may be a black matrix.
  • the light shielding layer is also filled in the via hole above the transparent conductive layer 28.
  • the transparent conductive layer can transmit light, light leakage occurs at the edge of the via hole, and by filling the light shielding layer in the via hole, light leakage at the edge of the via hole can be avoided, thereby improving the display effect. It can be understood that filling the via hole with the black matrix until the via is filled can make the surface of the via hole more flat and better improve the display effect.
  • a first insulating layer 30 is further disposed on the light shielding layer 29, and the first insulating layer 30 prevents the material in the light shielding layer or the color resist layer from volatilizing during high temperature processing, thereby generating bubbles, thereby affecting the display effect.
  • the material of the first insulating layer is mainly an inorganic transparent material such as silicon nitride SiNx or the like.
  • the thickness of the first insulating layer 30 is less than or equal to 0.2 micrometers; since the vertical direction liquid crystal electric field strength decreases as the thickness of the first insulating layer increases, although in practice, the liquid crystal driving voltage can be compensated for
  • the increase in the thickness of the first insulating layer reduces the electric field, but increases the energy consumption, thereby increasing the production cost. It has been experimentally verified that by setting the thickness of the first insulating layer to the above range, it is possible to avoid affecting the electric field strength while reducing energy consumption.
  • the thickness of the first insulating layer 30 is more preferably 0.1 ⁇ m or less.
  • the electric field strength varies with the thickness of the insulating layer, as shown in Fig. 3.
  • the abscissa indicates the thickness of the insulating layer (unit: um)
  • the ordinate indicates the electric field strength (unit: V/um); the electric field strength varies with the thickness of the insulating layer.
  • the specific values of the changes are as follows:
  • Fig. 4 is a waveform diagram showing the influence of different thicknesses of the insulating layer on the electric field strength, as shown in Fig. 4.
  • the abscissa indicates the position of the insulating layer in the longitudinal direction of the liquid crystal display panel (unit: um), and the ordinate indicates Electric field strength (unit: V/um);
  • 101 is a schematic diagram showing the electric field intensity waveform when no insulating layer is provided
  • 102 is a schematic diagram showing the electric field intensity waveform when the thickness of the insulating layer is 1000 angstroms
  • 103 is the thickness of the insulating layer at 2000 angstroms.
  • 104 is a schematic diagram showing the electric field intensity waveform of the insulating layer at a thickness of 5000 angstroms.
  • the intensity of the electric field is weakened to a small extent.
  • a second insulating layer 26 is further formed between the switch array layer and the color resist layer 27. That is, a second insulating layer 26 is disposed between the color resist layer 27 and the second metal layer 25; the second insulating layer 26 is used to isolate the second metal layer and the color resist layer for The second metal layer is prevented from being oxidized.
  • FIG. 5 is a flow chart of a method for fabricating an array substrate according to the present invention.
  • the switch array layer comprises a plurality of thin film transistors, wherein the specific processing manner of the switch array layer is:
  • the step S111 is specifically: forming a gate by exposing, developing, and etching the first metal layer through a patterned mask, and the first metal layer other than the gate portion is etched away during the process.
  • the material of the metal layer may be chromium, molybdenum, aluminum or copper.
  • the active layer is used to form a channel between the drain and the source, and the material of the active layer is, for example, an amorphous silicon material.
  • Forming a plurality of drains and a plurality of sources by exposing and etching the second metal layer through a mask having a pattern, and the second metal layer other than the drain and source portions is processed during the process Etched off, where the number of gates matches the number of sources and drains.
  • the method further includes:
  • a gate insulating layer is formed on the gate and the base substrate not covered by the gate.
  • a via hole may also be formed on the color resist layer, and the transparent conductive layer is connected to the second metal layer through the via hole.
  • the color resist layer may include a red color film, a green color film, and a blue color film.
  • a transparent conductive layer may be formed on the black matrix layer by a sputter coating method; the transparent conductive layer includes a pixel electrode.
  • the light shielding layer may be a black matrix; a light shielding material is coated on the transparent conductive layer, and the light shielding material is exposed and developed through a patterned mask to form a black matrix.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel of the present invention includes a first substrate 40 and a second substrate 50.
  • the liquid crystal layer 33 is located between the first substrate 40 and the second substrate 50, and the second substrate 50 is
  • the substrate substrate 31 includes a common electrode
  • the transparent substrate includes a common electrode
  • the first substrate 40 is a BOA array substrate
  • the first substrate 40 includes a substrate substrate 21, a switch array layer, Color resist layer 27, transparent conductive layer 28, light shielding layer 29;
  • the switch array layer is disposed on the base substrate 21, and the switch array layer includes a plurality of thin film transistors; specifically including: a first metal layer 22, a gate insulating layer 23, an active layer 24, and a second metal layer 25. ;
  • the first metal layer 22 is located on the base substrate 21 and may include a plurality of gates.
  • the gate insulating layer 23 is located on the first metal layer 22, and the active layer 24 is partially located at the gate.
  • the second metal layer 25 is located on the active layer 24;
  • the color resist layer 27 is located on the second metal layer 25, and the color resist layer comprises a plurality of color film color resists;
  • the color resist layer 27 may further be provided with a via hole; the transparent conductive layer 28 is connected to the second metal layer 25 through the via hole.
  • the transparent conductive layer 28 is located on the color resist layer 27; the light shielding layer 29 is located on the transparent conductive layer 28.
  • the light shielding layer is also filled in the via hole above the transparent conductive layer 28.
  • the transparent conductive layer can transmit light, light leakage occurs at the edge of the via hole, and by filling the light shielding layer in the via hole, light leakage at the edge of the via hole can be avoided, thereby improving the display effect. It can be understood that filling the via hole with the black matrix until the via is filled can make the surface of the via hole more flat and better improve the display effect.
  • a first insulating layer 30 is further disposed on the light shielding layer 29, and the first insulating layer 30 prevents a change in material properties in the light shielding layer during the high temperature process, thereby generating a gas and affecting the display effect.
  • the thickness of the first insulating layer is 0.2 ⁇ m or less; more preferably 0.1 ⁇ m or less.
  • a second insulating layer 26 is further formed between the switch array layer and the color resist layer 27. That is, a second insulating layer 26 is disposed between the color resist layer 27 and the second metal layer 25; the second insulating layer 26 is used to isolate the second metal layer and the color resist layer for The second metal layer is prevented from being oxidized.
  • the array substrate of the present invention and the method for fabricating the same have a black matrix before the color resist layer is formed, thereby saving the manufacturing process, reducing the production cost, and improving the display effect.

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Abstract

一种阵列基板及其制作方法，所述方法包括：在衬底基板（21）上制作开关阵列层；在所述开关阵列层上形成色阻层（27），所述色阻层（27）包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层（27）上形成有过孔；在色阻层（27）上形成透明导电层（28）；以及在所述透明导电层（28）上形成遮光层（29）。

Description

一种阵列基板及其制作方法 技术领域
本发明涉及液晶显示器技术领域，特别是涉及一种阵列基板及其制作方法。
 背景技术
如图1所示，现有的阵列基板：譬如为BOA（BM on Array）基板，BOA基板是在阵列基板上制作彩色滤光膜和黑色矩阵，阵列基板包括：衬底基板11、第一金属层12位于衬底基板11上，包括栅极；栅绝缘层13部分位于第一金属层12上，用于隔离所述第一金属层12和有源层14；有源层14部分位于栅绝缘层13上，用于形成沟道；第二金属层15位于有源层14上，包括源极、漏极；第二绝缘层16，位于第二金属层15上；色阻层17，位于所述第二绝缘层16上，色阻层和遮光层上形成有过孔18；以及黑色矩阵层19 位于色阻层17上，透明导电层20部分位于黑色矩阵层19上。
为了使透明导电层与第二金属层接触，需要分别在色阻层和遮光层上设置过孔，且在色阻层设置过孔后，使得孔内的遮光层比较厚，不利于遮光层的过孔的制作，其次会使得色阻层上的孔和遮光层上孔的位置出现偏差，使得后续的透明导电层容易产生裂缝，影响显示效果。
因此，有必要提供一种阵列基板及其制作方法，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种阵列基板及其制作方法，以解决现有技术中遮光层和色阻层的过孔位置容易发生偏差，容易使得透明导电层产生裂缝，显示效果差的技术问题。
 技术解决方案
在衬底基板上制作开关阵列层，所述开关阵列层包括第一金属层、有源层、第二金属层；其中对所述第一金属层进行图形化处理形成多个栅极，对所述第二金属层进行图形化处理形成多个源极和多个漏极，所述有源层用于形成沟道；
在所述开关阵列层上形成色阻层，所述色阻层包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层上形成有过孔；
在所述色阻层上形成透明导电层；
在所述透明导电层上以及所述透明导电层上方的过孔内形成遮光层；以及
在所述遮光层上形成第一绝缘层。
在本发明的阵列基板的制作方法中，所述遮光层为黑色矩阵。
在本发明的阵列基板的制作方法中，所述第一绝缘层的厚度小于等于0.2微米。
在本发明的阵列基板的制作方法中，所述透明导电层通过所述过孔与所述第二金属层连接。
在本发明的阵列基板的制作方法中，所述第一绝缘层的材料为无机透明材料。
在本发明的阵列基板的制作方法中，在所述开关阵列层和所述色阻层之间还形成有第二绝缘层。
为解决上述技术问题，本发明构造了一种阵列基板的制作方法，其包括：
在衬底基板上制作开关阵列层，所述开关阵列层包括第一金属层、有源层、第二金属层；其中对所述第一金属层进行图形化处理形成多个栅极，对所述第二金属层进行图形化处理形成多个源极和多个漏极，所述有源层用于形成沟道；
在所述开关阵列层上形成色阻层，所述色阻层包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层上形成有过孔；
在所述色阻层上形成透明导电层；以及
在所述透明导电层上形成遮光层。
在本发明的阵列基板的制作方法中，在所述透明导电层上方的过孔内也填充有所述遮光层。
在本发明的阵列基板的制作方法中，所述遮光层为黑色矩阵。
在本发明的阵列基板的制作方法中，所述方法还包括：在所述遮光层上形成第一绝缘层。
在本发明的阵列基板的制作方法中，所述第一绝缘层的厚度小于等于0.2微米。
在本发明的阵列基板的制作方法中，所述透明导电层通过所述过孔与所述第二金属层连接。
本发明还提供一种阵列基板，其包括：
衬底基板；
开关阵列层，位于所述衬底基板上，所述开关阵列层包括第一金属层、有源层、第二金属层；其中所述第一金属层包括多个栅极，所述第二金属层包括多个源极和多个漏极，所述有源层用于形成沟道；
色阻层，位于所述开关阵列层上，所述色阻层包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层上形成有过孔；
透明导电层，位于所述色阻层上；以及
遮光层，位于所述透明导电层上。
在本发明的阵列基板中，在所述透明导电层上方的过孔内也设置有所述遮光层。
在本发明的阵列基板中，所述遮光层为黑色矩阵。
在本发明的阵列基板中，在所述遮光层上还设置有第一绝缘层。
在本发明的阵列基板中，所述第一绝缘层的厚度小于等于0.2微米。
在本发明的阵列基板中，所述透明导电层通过所述过孔与所述第二金属层连接。
 有益效果
本发明的阵列基板及其制作方法，通过在制作透明导电层之后制作黑色矩阵，避免透明导电层产生裂缝，提高了显示效果。
 附图说明
图1为现有技术的阵列基板的结构示意图；
图2为本发明的阵列基板的结构示意图；
图3为电场强度随绝缘层厚度变化的示意图；
图4为本发明的不同厚度的绝缘层对电场强度影响的波形图；
图5为本发明的阵列基板的制作方法流程图；
图6为本发明的液晶显示面板的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的阵列基板的结构示意图。
如图2所示，本发明的阵列基板包括：衬底基板21、开关阵列层、色阻层27、透明导电层28、遮光层29；
所述开关阵列层位于所述衬底基板21上，所述开关阵列层包括多个薄膜晶体管；其具体包括：第一金属层22、栅绝缘层23、有源层24、第二金属层25；
所述第一金属层22位于所述衬底基板21上，可包括多个栅极，所述栅绝缘层23位于所述第一金属层22上，所述有源层24部分位于所述栅绝缘层23上，所述第二金属层25位于所述有源层24上；所述色阻层27位于所述第二金属层25上，所述色阻层包括多个彩膜色阻；所述色阻层27上还可设置有过孔；所述透明导电层28通过所述过孔与所述第二金属层25连接。
所述透明导电层28位于所述色阻层27上；所述遮光层29位于所述透明导电层28上。所述遮光层29可为黑色矩阵。
通过将遮光层在透明导电层之后制作，仅需要在色阻层上制作过孔，从而节省制程程序，避免同时在色阻层和遮光层上制作过孔，容易出现偏差的问题，从而防止透明导电层出现裂缝，
优选地，在所述透明导电层28上方的过孔内也填充有所述遮光层。
由于透明导电层可透光，因此导致过孔边缘出现漏光，通过在过孔内也填充上遮光层，能够避免过孔边缘出现漏光的现象，从而更好地提高显示效果。可以理解的是，向所述过孔内填充黑色矩阵，直至过孔填满，能够使过孔表面更加平整，更好地提高显示效果。
优选地，在所述遮光层29上还可设置第一绝缘层30，所述第一绝缘层30，防止高温制程中容易导致遮光层或者色阻层内材料挥发，产生气泡，从而影响显示效果。所述第一绝缘层的材料主要为无机透明材料，如氮化硅SiNx等。
进一步地，所述第一绝缘层30的厚度小于等于0.2微米；由于垂直方向液晶电场强度会随着第一绝缘层的厚度增加而减弱，虽然在实际操作中，可通过调整液晶驱动电压来弥补第一绝缘层的厚度增加对电场的减弱作用，但会增加能耗，从而增加生产成本。通过实验验证发现，通过将第一绝缘层的厚度设置在上述范围时，在降低能耗的同时，避免影响电场强度。所述第一绝缘层30的厚度更优选为小于等于0.1微米。
电场强度随绝缘层厚度的变化示意图，如图3所示，图3中横坐标表示绝缘层厚度（单位为um），纵坐标表示电场强度（单位为V/um）；电场强度随绝缘层厚度的变化具体数值如下表：
表1
绝缘层厚度(um) 电场强度（V/um） 电场削弱（%）
0 1.806 0.00%
0.1 1.73 4.20%
0.2 1.66 8.08%
0.5 1.514 16.17%
从图3和表1，不难看出绝缘层厚度等于0.2um时，电场强度下降8.08%；绝缘层厚度等于0.5um时；电场强度下降16.2%；当绝缘层厚度大于0.2微米时，电场强度下降幅度变大，而在液晶驱动电压附近绝缘层厚度在0.2um以下时，电场强度下降缓慢，能够满足正常制程需求。特别是绝缘层厚度在0.1微米以下时，基本上不会对电场强度造成影响。
图4给出不同厚度的绝缘层对电场强度影响的波形图，如图4所示，图4中横坐标表示绝缘层的在液晶显示面板长边方向的位置（单位为um），纵坐标表示电场强度（单位为V/um）；101表示没有设置绝缘层时的电场强度波形示意图，102表示绝缘层的厚度在1000埃时的电场强度波形示意图；103表示绝缘层的厚度在2000埃时的电场强度波形示意图；104表示绝缘层的厚度在5000埃时的电场强度波形示意图。
可见绝缘层厚度在0.1微米以下时，对电场强度减弱程度很小。
优选地，在所述开关阵列层和所述色阻层27之间还形成有第二绝缘层26。即在所述色阻层27和所述第二金属层25之间设置第二绝缘层26；所述第二绝缘层26用于隔离所述第二金属层和所述色阻层，用于防止所述第二金属层被氧化。
请参照图5，图5为本发明的阵列基板的制作方法流程图。
现有技术的阵列基板的制作方法包括以下步骤：
S101、在衬底基板上形成开关阵列层；
开关阵列层包括多个薄膜晶体管，其中开关阵列层的具体制程方式为：
S111、在所述衬底基板上形成第一金属层，对所述第一金属层进行图形化处理，以形成多个栅极；
所述步骤S111具体是通过带有图形的掩模板，对所述第一金属层经过曝光显影、刻蚀后形成栅极，栅极部分以外的第一金属层在制程过程中被刻蚀掉。该金属层的材料可为铬、钼、铝或铜等。
S112、在所述第一金属层上形成有源层；
所述有源层用于形成漏极和源极之间的沟道，所述有源层的材料譬如为非晶硅材料。
S113、在所述有源层上形成第二金属层；
通过带有图形的掩模板，对所述第二金属层经过曝光显影、刻蚀后形成多个漏极和多个源极，漏极和源极部分以外的第二金属层在制程过程中被刻蚀掉，其中栅极的个数与源极和漏极的个数匹配。
优选地，在制作有源层之前，所述方法还包括：
在所述栅极及未被所述栅极覆盖的衬底基板上形成栅绝缘层。
S102、在所述开关阵列层上形成色阻层；
色阻层上还可形成有过孔，所述透明导电层通过过孔与第二金属层连接。所述色阻层可包括红色彩膜、绿色彩膜、蓝色彩膜。
S103、在所述色阻层上形成透明导电层；
可以利用溅射镀膜法，在黑色矩阵层上形成透明导电层；所述透明导电层包括像素电极。
S104、在所述透明导电层上形成遮光层；
所述遮光层可为黑色矩阵；在所述透明导电层上涂布遮光材料，通过带有图形的掩模板，对所述遮光材料进行曝光显影形成黑色矩阵。
请参照图6，图6为本发明的液晶显示面板的结构示意图。
本发明的液晶显示面板如图6所示，包括：第一基板40、第二基板50，液晶层33位于所述第一基板40和所述第二基板50之间，所述第二基板50包括衬底基板31和另一透明导电层32，该透明导电层包括公共电极，所述第一基板40譬如为BOA阵列基板，所述第一基板40包括：衬底基板21、开关阵列层、色阻层27、透明导电层28、遮光层29；
所述开关阵列层位于所述衬底基板21上，所述开关阵列层包括多个薄膜晶体管；其具体包括：第一金属层22、栅绝缘层23、有源层24、第二金属层25；
所述第一金属层22位于所述衬底基板21上，可包括多个栅极，所述栅绝缘层23位于所述第一金属层22上，所述有源层24部分位于所述栅绝缘层23上，所述第二金属层25位于所述有源层24上；所述色阻层27位于所述第二金属层25上，所述色阻层包括多个彩膜色阻；所述色阻层27上还可设置有过孔；所述透明导电层28通过所述过孔与所述第二金属层25连接。
所述透明导电层28位于所述色阻层27上；所述遮光层29位于所述透明导电层28上。
通过将遮光层在透明导电层之后制作，仅需要在色阻层上制作过孔，从而节省制程程序，避免同时在色阻层和遮光层上制作过孔，容易出现偏差的问题，从而防止透明导电层出现裂缝。
优选地，在所述透明导电层28上方的过孔内也填充有所述遮光层。
由于透明导电层可透光，因此导致过孔边缘出现漏光，通过在过孔内也填充上遮光层，能够避免过孔边缘出现漏光的现象，从而更好地提高显示效果。可以理解的是，向所述过孔内填充黑色矩阵，直至过孔填满，能够使过孔表面更加平整，更好地提高显示效果。
优选地，在所述遮光层29上还可设置第一绝缘层30，所述第一绝缘层30，防止高温制程中容易导致遮光层内材料特性发生变化，从而产生气体，影响显示效果。
进一步地，所述第一绝缘层的厚度小于等于0.2微米；更优选为小于等于0.1微米。
优选地，在所述开关阵列层和所述色阻层27之间还形成有第二绝缘层26。即在所述色阻层27和所述第二金属层25之间设置第二绝缘层26；所述第二绝缘层26用于隔离所述第二金属层和所述色阻层，用于防止所述第二金属层被氧化。
本发明的阵列基板及其制作方法，通过在制作色阻层之前制作黑色矩阵，从而节省了制程工序，降低生产成本，提高显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板的制作方法，其包括：
    在衬底基板上制作开关阵列层，所述开关阵列层包括第一金属层、有源层、第二金属层；其中对所述第一金属层进行图形化处理形成多个栅极，对所述第二金属层进行图形化处理形成多个源极和多个漏极，所述有源层用于形成沟道；
    在所述开关阵列层上形成色阻层，所述色阻层包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层上形成有过孔；
    在所述色阻层上形成透明导电层；
    在所述透明导电层上以及所述透明导电层上方的过孔内形成遮光层；以及
    在所述遮光层上形成第一绝缘层。
  2. 根据权利要求1所述的阵列基板的制作方法，其中所述遮光层为黑色矩阵。
  3. 根据权利要求1所述的阵列基板的制作方法，其中所述第一绝缘层的厚度小于等于0.2微米。
  4. 根据权利要求1所述的阵列基板的制作方法，其中所述透明导电层通过所述过孔与所述第二金属层连接。
  5. 根据权利要求1所述的阵列基板的制作方法，其中所述第一绝缘层的材料为无机透明材料。
  6. 根据权利要求1所述的阵列基板的制作方法，其中在所述开关阵列层和所述色阻层之间还形成有第二绝缘层。
  7. 一种阵列基板的制作方法，其包括：
    在衬底基板上制作开关阵列层，所述开关阵列层包括第一金属层、有源层、第二金属层；其中对所述第一金属层进行图形化处理形成多个栅极，对所述第二金属层进行图形化处理形成多个源极和多个漏极，所述有源层用于形成沟道；
    在所述开关阵列层上形成色阻层，所述色阻层包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层上形成有过孔；
    在所述色阻层上形成透明导电层；以及
    在所述透明导电层上形成遮光层。
  8. 根据权利要求7所述的阵列基板的制作方法，其中在所述透明导电层上方的过孔内也填充有所述遮光层。
  9. 根据权利要求7所述的阵列基板的制作方法，其中所述遮光层为黑色矩阵。
  10. 根据权利要求7所述的阵列基板的制作方法，其中所述方法还包括：在所述遮光层上形成第一绝缘层。
  11. 根据权利要求10所述的阵列基板的制作方法，其中所述第一绝缘层的厚度小于等于0.2微米。
  12. 根据权利要求7所述的阵列基板的制作方法，其中
    所述透明导电层通过所述过孔与所述第二金属层连接。
  13. 一种阵列基板，其包括：
    衬底基板；
    开关阵列层，位于所述衬底基板上，所述开关阵列层包括第一金属层、有源层、第二金属层；其中所述第一金属层包括多个栅极，所述第二金属层包括多个源极和多个漏极，所述有源层用于形成沟道；
    色阻层，位于所述开关阵列层上，所述色阻层包括红色彩膜、绿色彩膜、蓝色彩膜，所述色阻层上形成有过孔；
    透明导电层，位于所述色阻层上；以及
    遮光层，位于所述透明导电层上。
  14. 根据权利要求13所述的阵列基板，其中在所述透明导电层上方的过孔内也设置有所述遮光层。
  15. 根据权利要求13所述的阵列基板，其中所述遮光层为黑色矩阵。
  16. 根据权利要求13所述的阵列基板，其中在所述遮光层上还设置有第一绝缘层。
  17. 根据权利要求16所述的阵列基板，其中所述第一绝缘层的厚度小于等于0.2微米。
  18. 根据权利要求13所述的阵列基板，其中所述透明导电层通过所述过孔与所述第二金属层连接。
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