WO2017013769A1 - Dispositif à semi-conducteurs - Google Patents

Dispositif à semi-conducteurs Download PDF

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Publication number
WO2017013769A1
WO2017013769A1 PCT/JP2015/070836 JP2015070836W WO2017013769A1 WO 2017013769 A1 WO2017013769 A1 WO 2017013769A1 JP 2015070836 W JP2015070836 W JP 2015070836W WO 2017013769 A1 WO2017013769 A1 WO 2017013769A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
inductor
signal
signal path
chip
Prior art date
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PCT/JP2015/070836
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English (en)
Japanese (ja)
Inventor
孝靜 朴
一修 田島
Original Assignee
サンケン電気株式会社
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Application filed by サンケン電気株式会社 filed Critical サンケン電気株式会社
Priority to PCT/JP2015/070836 priority Critical patent/WO2017013769A1/fr
Publication of WO2017013769A1 publication Critical patent/WO2017013769A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H04B5/48—
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Definitions

  • the present invention relates to a semiconductor device having a plurality of semiconductor chips that are insulated from each other.
  • the number of components can be reduced and space can be saved. realizable. It is also effective for space saving to mount a high-voltage semiconductor chip and a semiconductor chip that controls the operation of the high-voltage semiconductor chip in one semiconductor device.
  • An object of the present invention is to provide a semiconductor device having an improved signal propagation speed between insulated semiconductor chips.
  • the first semiconductor chip and the second semiconductor chip that are electrically insulated from each other, and the first magnetic field coupling by the chip transformer in which the conductor layer and the insulating layer are stacked.
  • a first signal path and a second signal path for transmitting a signal from the semiconductor chip to the second semiconductor chip, and the first control signal and the second signal transmitted via the first signal path A semiconductor device is provided in which the operation of the second semiconductor chip is controlled by the second control signal transmitted through the path.
  • FIG. 4 It is a schematic diagram which shows the structural example of the semiconductor device which concerns on embodiment of this invention. 4 is a timing chart for explaining an operation example of the semiconductor device according to the embodiment of the present invention. It is typical sectional drawing which shows the structural example of the chip transformer used for the semiconductor device which concerns on embodiment of this invention. It is a typical perspective view showing the 1st inductor of the chip transformer used for the semiconductor device concerning the embodiment of the present invention. It is a typical perspective view showing the 2nd inductor of the chip transformer used for the semiconductor device concerning the embodiment of the present invention. It is a typical perspective view which shows the shield of the chip transformer used for the semiconductor device which concerns on embodiment of this invention.
  • the semiconductor device 1 includes a first semiconductor chip 11, a second semiconductor chip 12, a third semiconductor chip 13, a first transmission transformer 21, and a second semiconductor chip 11.
  • the transmission transformer 22 is provided.
  • the first semiconductor chip 11, the second semiconductor chip 12, and the third semiconductor chip 13 are disposed so as to be electrically insulated from each other.
  • the first transmission transformer 21 and the second transmission transformer 22 are chip transformers having a structure in which a conductor layer and an insulating layer are stacked.
  • the first transmission transformer 21 has a first signal path 201 and a second signal path 202 through which signals propagate due to magnetic field coupling in the chip transformer.
  • the second transmission transformer 22 includes a third signal path 203 and a fourth signal path 204 through which signals propagate due to magnetic field coupling in the chip transformer. Details of the structure of the chip transformer will be described later.
  • the first semiconductor chip 11, the second semiconductor chip 12, the third semiconductor chip 13, the first transmission transformer 21 and the second transmission transformer 22 are molded and sealed with a molding material 15 such as an insulating resin. It is mounted on one package.
  • the first semiconductor chip 11 outputs a first control signal Sc1 and a second control signal Sc2 that control the operation of the second semiconductor chip 12. Further, the first semiconductor chip 11 outputs a third control signal Sc3 and a fourth control signal Sc4 that control the operation of the third semiconductor chip 13. The operation of the first semiconductor chip 11 is controlled by, for example, the microprocessor 2.
  • the first control signal Sc1 and the second control signal Sc2 are transmitted from the first semiconductor chip 11 to the second semiconductor chip 12 via the first transmission transformer 21. That is, the transmission side terminal Tx1 of the first signal path 201 of the first transmission transformer 21 and the transmission side terminal Tx2 of the second signal path 202 are connected to the first semiconductor chip 11. In addition, the reception-side terminal Rx 1 of the first signal path 201 of the first transmission transformer 21 and the reception-side terminal Rx 2 of the second signal path 202 are connected to the second semiconductor chip 12.
  • a terminal to which a signal propagating through the chip transformer is input from the outside is referred to as a “transmission side terminal”, and a terminal from which the signal is output to the outside is referred to as a “reception side terminal”.
  • the first control signal Sc ⁇ b> 1 is transmitted from the first semiconductor chip 11 to the second semiconductor chip 12 through the first signal path 201.
  • the second control signal Sc ⁇ b> 2 is transmitted from the first semiconductor chip 11 to the second semiconductor chip 12 through the second signal path 202.
  • the third control signal Sc3 and the fourth control signal Sc4 are transmitted from the first semiconductor chip 11 to the third semiconductor chip 13 via the second transmission transformer 22. That is, the transmission side terminal Tx3 of the third signal path 203 of the second transmission transformer 22 and the transmission side terminal Tx4 of the fourth signal path 204 are connected to the first semiconductor chip 11. Further, the reception-side terminal Rx3 of the third signal path 203 of the second transmission transformer 22 and the reception-side terminal Rx4 of the fourth signal path 204 are connected to the third semiconductor chip 13. As a result, the third control signal Sc3 is transmitted from the first semiconductor chip 11 to the third semiconductor chip 13 via the third signal path 203. Then, the fourth control signal Sc4 is transmitted from the first semiconductor chip 11 to the third semiconductor chip 13 through the fourth signal path 204.
  • transmission side terminal Tx1, the transmission side terminal Tx2, the transmission side terminal Tx3, and the transmission side terminal Tx4 are collectively referred to as “transmission side terminal Tx”.
  • reception side terminal Rx1, the reception side terminal Rx2, the reception side terminal Rx3, and the reception side terminal Rx4 are collectively referred to as “reception side terminal Rx”.
  • the channel through which the first control signal Sc1 and the second control signal Sc2 propagate from the first semiconductor chip 11 to the second semiconductor chip 12 has an insulating structure using the first transmission transformer 21. is there.
  • the channel through which the third control signal Sc3 and the fourth control signal Sc4 propagate from the first semiconductor chip 11 to the third semiconductor chip 13 has an insulating structure using the second transmission transformer 22. Therefore, the first semiconductor chip 11, the second semiconductor chip 12, and the third semiconductor chip 13 can be electrically insulated from each other. For this reason, the safety and operational stability of the semiconductor device 1 are improved.
  • the second semiconductor chip 12 and the third semiconductor chip 13 are formed with drive circuits for driving external elements.
  • a drive signal Sd 1 for driving the external element 31 is output from the second semiconductor chip 12 to the external element 31.
  • a drive signal Sd 2 for driving the external element 32 is output from the third semiconductor chip 13 to the external element 32.
  • the external elements 31 and 32 are, for example, power MOSFETs. At this time, the driving capabilities of the second semiconductor chip 12 and the third semiconductor chip 13 may be the same or different.
  • the first semiconductor chip 11 is a control chip for controlling the drive chip.
  • the first control signal Sc ⁇ b> 1 is transmitted to the second semiconductor chip 12 as a set signal for turning on the external element 31 by the second semiconductor chip 12.
  • a second control signal Sc2 is transmitted to the second semiconductor chip 12 as a reset signal that causes the external element 31 to be turned off by the second semiconductor chip 12. That is, the semiconductor device 1 employs a set reset (SR) method in which the set signal and the reset signal are transmitted through different signal paths.
  • SR set reset
  • FIG. 2 shows an operation example of the first transmission transformer 21.
  • an input signal IN is input to the first semiconductor chip 11.
  • the first semiconductor chip 11 transmits the first control signal Sc1 to the second semiconductor chip 12. That is, the first semiconductor chip 11 outputs a pulse signal to the transmission side terminal Tx1 of the first signal path 201 of the first transmission transformer 21. As a result, a pulse signal is output to the reception-side terminal Rx1 of the first signal path 201.
  • This pulse signal propagating through the first signal path 201 is input to the second semiconductor chip 12 as a set signal, and the second semiconductor chip 12 turns on the external element 31. For example, the drive signal Sd1 becomes high level and the external element 31 is turned on.
  • the first semiconductor chip 11 transmits the second control signal Sc2 to the second semiconductor chip 12. That is, the first semiconductor chip 11 outputs a pulse signal to the transmission-side terminal Tx2 of the second signal path 202 of the first transmission transformer 21. As a result, a pulse signal is output to the reception-side terminal Rx2 of the second signal path 202.
  • This pulse signal propagating through the second signal path 202 is input to the second semiconductor chip 12 as a reset signal, and the second semiconductor chip 12 turns off the external element 31. For example, the drive signal Sd1 becomes a low level and the external element 31 is turned off.
  • the first signal path 201 is used as a signal path for transmitting a set signal
  • the second signal path 202 is used as a signal path for transmitting a reset signal.
  • the external element 31 can be operated at high speed by the SR method in which the set signal and the reset signal are transmitted through different signal paths.
  • the input / output delay time is shortened.
  • the input / output delay time is about 400 nanoseconds
  • the input / output delay time is about 80 nanoseconds.
  • the third signal path 203 and the fourth signal path 204 can also be used as signal paths for transmitting the set signal and the reset signal.
  • the third control signal Sc3 is transmitted to the third semiconductor chip 13 as a set signal for turning on the external element 32 by the third semiconductor chip 13.
  • the fourth control signal Sc4 is transmitted to the third semiconductor chip 13 as a reset signal that causes the external element 32 to be turned off by the third semiconductor chip 13.
  • FIG. 3 a structure as shown in FIG. 3 can be adopted for the chip transformer used in the semiconductor device 1.
  • the chip transformer 100 shown in FIG. 3 has a laminated structure in which a plurality of conductor layers are laminated with an insulating layer interposed therebetween.
  • a stacked body 130 including a plurality of conductor layers is disposed over a semiconductor substrate 110 such as a silicon substrate with an insulating film 120 such as a silicon oxide film interposed therebetween.
  • the stacked body 130 has a structure in which a first conductor layer 1M, a second conductor layer 2M, a third conductor layer 3M, and a fourth conductor layer 4M are stacked with an insulating layer 135 interposed therebetween. is there.
  • the thickness of the semiconductor substrate 110 is about 400 ⁇ m
  • the thickness of the stacked body 130 is about 10 to 30 ⁇ m.
  • the second conductor layer 2M is a first inductor layer in which a first inductor L1 having a spiral conductive pattern as shown in FIG. 4 is formed.
  • One end of the first inductor L1 located at the center of the conductive pattern is electrically connected to the first conductor layer 1M by the plug 101 disposed in the insulating layer 135.
  • the “plug” has a structure in which a conductive material is embedded in a through hole formed in the insulating layer 135.
  • the first conductor layer 1M is electrically connected to the pad P1a disposed on the upper surface of the chip transformer 100 via the plug 102. That is, the first conductor layer 1M is used as part of the wiring that electrically connects the first inductor L1 and the pad P1a. On the other hand, the other end located at the outer edge of the first inductor L1 is electrically connected to the pad P1b disposed on the upper surface of the chip transformer 100 via the plug 103.
  • the fourth conductor layer 4M is exposed on the surface of the stacked body 130 and disposed on the upper surface of the chip transformer 100.
  • the fourth conductor layer 4M is a second inductor layer in which a second inductor L2 having a spiral conductive pattern as shown in FIG. 5 is formed.
  • One end of the second inductor L2 located at the center of the conductive pattern is electrically connected to the pad P2a disposed on the inner side of the conductive pattern on the upper surface of the chip transformer 100.
  • the other end located at the outer edge of the second inductor L2 is electrically connected to a pad P2b disposed outside the conductive pattern on the upper surface of the chip transformer 100.
  • the chip transformer 100 signal propagation due to magnetic field coupling between the pads P1a and P1b and the pads P2a and P2b is achieved by the above structure in which the first inductor layer and the second inductor layer are stacked via the insulating layer. Done. It is preferable to form the first inductor L1 and the second inductor L2 so that the respective center positions coincide in plan view. According to the chip transformer 100, high-speed pulse signal communication having a pulse width of about several nanoseconds is possible.
  • a conductive shield 136 as shown in FIG. 6 between the first inductor L1 and the second inductor L2.
  • the shield 136 is formed on the third conductor layer 3M. This is due to the following reason.
  • a parasitic capacitance is formed between the first inductor L1 and the second inductor L2.
  • the charges accumulated in the parasitic capacitance move to an external circuit and an abnormal voltage or current is generated.
  • the shield 136 By arranging the shield 136 between the first inductor L1 and the second inductor L2, the charge of the parasitic capacitance is discharged through the shield 136. Thereby, it can suppress that noise generate
  • the shield 136 is formed so as not to disturb the magnetic field communication in the chip transformer 100.
  • a U-shaped plate-shaped conductor shield 136 as shown in FIG. 6 is used so that the shield 136 does not shield between the centers of the first inductor L1 and the second inductor L2.
  • the shield 136 is electrically connected to the pad Ps disposed on the upper surface of the chip transformer 100 via the plug 106.
  • the pad Ps is grounded via a semiconductor chip to which the receiving side terminal Rx of the chip transformer 100 is connected, for example.
  • the thickness of the second conductor layer 2M is set to about 1 ⁇ m
  • the thickness of the fourth conductor layer 4M is set to about 4 ⁇ m.
  • the on-resistance on the transmission side is smaller than that on the reception side in order to stably perform high-frequency signal propagation.
  • the pad P2a and the pad P2b connected to the second inductor L2 formed in the fourth conductor layer 4M having a large thickness are used as the transmission side terminal Tx.
  • the pads P1a and P1b connected to the first inductor L1 formed on the second conductor layer 2M having a small film thickness are used as the reception-side terminal Rx. This facilitates the manufacture of the chip transformer 100 with good flatness.
  • the film thickness of the second conductor layer 2M may be set to the same thickness as the film thickness of the fourth conductor layer 4M. Or you may make the film thickness of the 2nd conductor layer 2M thicker than the film thickness of the 4th conductor layer 4M.
  • the first inductor L1 formed in the second conductor layer 2M may be used as a transmitting inductor
  • the second inductor L2 formed in the fourth conductor layer 4M may be used as a receiving inductor. it can.
  • Examples of the material of the first conductor layer 1M, the second conductor layer 2M, the third conductor layer 3M, and the fourth conductor layer 4M include aluminum (Al), copper (Cu), and AlCu. Conductive materials can be used. Further, the above conductive material can be used for the plug embedded in the insulating layer 135.
  • the first transmission transformer 21 has a structure in which a chip transformer constituting the first signal path 201 and a chip transformer constituting the second signal path 202 are formed on the same semiconductor substrate 110.
  • the first inductor L1 hereinafter referred to as “inductor L11”
  • the first inductor L1 that constitutes the second signal path 202 (
  • the second inductor L2 (hereinafter referred to as “inductor L21”) constituting the first signal path 201 and the second inductor L2 (hereinafter referred to as “inductor L22”) constituting the second signal path 202.
  • inductor L21 constituting the first signal path 201
  • inductor L22 constituting the second signal path 202.
  • the end located at the center of the inductor L21 is electrically connected to the pad P21a disposed inside the inductor L21 on the upper surface of the first transmission transformer 21. Further, the end portion located at the center portion of the inductor L22 is electrically connected to the pad P22a disposed inside the inductor L22 on the upper surface of the first transmission transformer 21.
  • the plugs connected to the inductor L11 and the inductor L12, the first conductor layer 1M, and the third conductor layer 3M are not shown.
  • the end portion located at the center of the inductor L11 has a pad P11a disposed on the upper surface of the first transmission transformer 21 via the plug 1011, the first conductor layer 1M, and the plug 1021. And electrically connected.
  • An end portion located at the outer edge portion of the inductor L11 is electrically connected to a pad P11b disposed on the upper surface of the first transmission transformer 21 via a plug 1031.
  • the end portion located at the center of the inductor L12 is electrically connected to the pad P12a disposed on the upper surface of the first transmission transformer 21 through the plug 1012, the first conductor layer 1M, and the plug 1022. Is done.
  • the end located at the outer edge of the inductor L12 is electrically connected to the pad P12b disposed on the upper surface of the first transmission transformer 21 via the plug 1032.
  • the number of pads can be reduced by connecting one end of each of the inductor L21 and the inductor L22 to the common pad P20b. Further, as shown in FIG. 8, by connecting the shield of the chip transformer constituting the first signal path 201 and the chip transformer constituting the second signal path 202, the shield pad Ps can be made common.
  • a signal is propagated by magnetic field coupling between the pads P11a and P11b and the pads P21a and P20b by a structure in which the inductor L11 and the inductor L21 are stacked via an insulating layer.
  • a signal is propagated by magnetic field coupling between the pads P12a and P12b and the pads P22a and P20b by a structure in which the inductor L12 and the inductor L22 are stacked via an insulating layer.
  • FIG. 8 by using a common pad, the number of pads of the first transmission transformer 21 can be reduced as compared with the case where two chip transformers 100 are arranged.
  • FIG. 9 shows a pad arrangement example of the first transmission transformer 21. Further, by using the first transmission transformer 21 including two chip transformers, the area required for the chip transformer arrangement can be reduced as compared with the case where the two chip transformers 100 are arranged side by side.
  • the second transmission transformer 22 it is possible to adopt a structure in which the chip transformer constituting the third signal path 203 and the chip transformer constituting the fourth signal path 204 are formed on the same semiconductor substrate 110.
  • the structure of the second transmission transformer 22 can be made the same as the structure of the first transmission transformer 21 shown in FIGS. That is, the inductor L11 constituting the third signal path 203 and the inductor L12 constituting the fourth signal path 204 are formed in the same first inductor layer. Then, the inductor L21 constituting the third signal path 203 and the inductor L22 constituting the fourth signal path 204 are formed in the same second inductor layer.
  • the input / output of signals to / from the semiconductor device 1 is performed through external leads 16 that penetrate the molding material 15 as shown in FIG. That is, the connection between the first semiconductor chip 11 and the microprocessor 2, the connection between the second semiconductor chip 12 and the external element 31, and the connection between the third semiconductor chip 13 and the external element 32 are the external leads 16. Is done through.
  • bonding wires are used to connect the first semiconductor chip 11, the second semiconductor chip, the third semiconductor chip, and the external leads 16.
  • the connection between the first semiconductor chip 11 and the first transmission transformer 21 and the second transmission transformer 22 the connection between the first transmission transformer 21 and the second semiconductor chip 12, and the second transmission transformer.
  • a bonding wire is used for the connection between 22 and the third semiconductor chip 13.
  • the region where the second semiconductor chip 12 is disposed and the region where the third semiconductor chip 13 is disposed are the first semiconductor chip 11, the first transmission transformer 21, and the second semiconductor chip 13.
  • the transmission transformer 22 is arranged so as to face each other. For this reason, in the semiconductor device 1, the electromagnetic noise generated in the second semiconductor chip 12 or the third semiconductor chip 13 is suppressed from interfering with the other semiconductor chip.
  • the die pad that is the semiconductor chip mounting portion of the metal frame is divided into three parts, and the first semiconductor chip 11, the second semiconductor chip 12, The third semiconductor chip 13 is mounted on a separate die pad.
  • the semiconductor chips are electrically and electromagnetically isolated from each other.
  • the first transmission transformer 21 can be mounted on a die pad on which the second semiconductor chip 12 is mounted.
  • the second transmission transformer 22 can be mounted on a die pad on which the third semiconductor chip 13 is mounted.
  • the semiconductor device 1 can be used for a part of an in-vehicle electronic circuit system of a hybrid vehicle.
  • the second semiconductor chip 12 and the third semiconductor chip 13 are used as a driving device for driving a high-voltage system circuit of a hybrid car, and the first semiconductor chip 11 is driven to drive a low-voltage system circuit of a hybrid car.
  • the low voltage system circuit is a circuit that is powered by a 12V system or 24V system battery, such as an in-vehicle electronic circuit, lights such as a headlight and a winker, and an ignition device for an internal combustion engine such as a gasoline engine or a diesel engine. It is.
  • the high voltage system circuit is a circuit that drives an electric motor. In order to drive the electric motor, for example, the output of the 200V battery is boosted to a high voltage of 500V to 900V.
  • the signal propagation speed between the insulated semiconductor chips is improved by using the chip transformer in the signal propagation path. Can do.
  • the light receiving characteristic of the light receiving element is deteriorated due to the deterioration of the luminance of the light emitting element such as a light emitting diode, and the signal transmission response is lowered.
  • the optical device is placed in a high temperature environment, the luminance of the light emitting element is deteriorated and the light receiving characteristics of the light receiving element are rapidly deteriorated, and the service life is shortened.
  • the semiconductor device 1 according to the embodiment of the present invention since a chip transformer is used instead of an optical device in the signal propagation path, the signal transmission responsiveness is not deteriorated and the useful life is shortened. Absent.
  • the semiconductor device 1 according to the embodiment is suitable for in-vehicle use in which the environmental temperature is high.
  • the chip transformer is smaller than the substrate transformer and has a smaller coupling capacity. For this reason, the propagation speed of a signal can be improved by using a chip transformer.
  • the size of the entire semiconductor device 1 can be reduced by using a chip transformer.
  • the size of the chip transformer is small, the influence of the external magnetic field received by the semiconductor device 1 can be suppressed. For example, when an external element having a large element current is arranged around the semiconductor device 1, the first transmission transformer 21 and the second transmission transformer 22 are affected by the magnetic field generated due to the operation of the external element. Can be suppressed.
  • a pair of signal paths including the first signal path 201 and the second signal path 202 and a pair of signal paths including the third signal path 203 and the fourth signal path 204 are used.
  • a two-channel semiconductor device 1 is shown.
  • the present invention can also be applied to a one-channel semiconductor device 1 having a pair of signal paths.
  • the semiconductor device of the present invention can be used for a semiconductor device in which a plurality of semiconductor chips are arranged so as to be insulated from each other.

Abstract

L'invention concerne un dispositif à semi-conducteurs qui comprend : une première puce à semi-conducteurs et une seconde puce à semi-conducteurs, qui sont disposées en étant isolées électriquement l'une de l'autre ; et un premier trajet de signal et un second trajet de signal, qui émettent des signaux entre la première puce à semi-conducteurs et la seconde puce à semi-conducteurs au moyen d'un couplage de champ magnétique dans un transformateur de puce dans lequel une couche conductrice et une couche isolante sont stratifiées. Les opérations de la seconde puce à semi-conducteurs sont commandées au moyen de premiers signaux de commande émis par l'intermédiaire du premier trajet de signal, et de second signaux de commande émis par l'intermédiaire du second trajet de signal.
PCT/JP2015/070836 2015-07-22 2015-07-22 Dispositif à semi-conducteurs WO2017013769A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/070836 WO2017013769A1 (fr) 2015-07-22 2015-07-22 Dispositif à semi-conducteurs

Applications Claiming Priority (1)

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PCT/JP2015/070836 WO2017013769A1 (fr) 2015-07-22 2015-07-22 Dispositif à semi-conducteurs

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WO2017013769A1 true WO2017013769A1 (fr) 2017-01-26

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04133408A (ja) * 1990-09-26 1992-05-07 Toshiba Lighting & Technol Corp 平面トランス
WO2013027454A1 (fr) * 2011-08-25 2013-02-28 サンケン電気株式会社 Dispositif à semi-conducteurs
JP2013229812A (ja) * 2012-04-26 2013-11-07 Renesas Electronics Corp 送信回路及びそれを備えた半導体集積回路
JP2015015697A (ja) * 2013-06-07 2015-01-22 ローム株式会社 信号伝達装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04133408A (ja) * 1990-09-26 1992-05-07 Toshiba Lighting & Technol Corp 平面トランス
WO2013027454A1 (fr) * 2011-08-25 2013-02-28 サンケン電気株式会社 Dispositif à semi-conducteurs
JP2013229812A (ja) * 2012-04-26 2013-11-07 Renesas Electronics Corp 送信回路及びそれを備えた半導体集積回路
JP2015015697A (ja) * 2013-06-07 2015-01-22 ローム株式会社 信号伝達装置

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