WO2016207956A1 - 駆動回路、半導体装置 - Google Patents
駆動回路、半導体装置 Download PDFInfo
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- WO2016207956A1 WO2016207956A1 PCT/JP2015/067916 JP2015067916W WO2016207956A1 WO 2016207956 A1 WO2016207956 A1 WO 2016207956A1 JP 2015067916 W JP2015067916 W JP 2015067916W WO 2016207956 A1 WO2016207956 A1 WO 2016207956A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/12—Modifications for increasing the maximum permissible switched current
- H03K17/127—Modifications for increasing the maximum permissible switched current in composite switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature
Definitions
- the present invention relates to a drive circuit that controls a plurality of semiconductor switching elements, and a semiconductor device including the drive circuit.
- Patent Document 1 discloses that a mirror voltage of a semiconductor switching element is detected and a gate voltage is controlled.
- the gate voltage is increased to speed up the turn-on operation, and when the semiconductor switching element is turned off, the mirror time is adjusted to facilitate parallel connection of the semiconductor switching elements.
- Patent Document 2 discloses a method for suppressing an overcurrent flowing through a semiconductor switching element as a method for preventing the semiconductor switching element from deteriorating. Specifically, by limiting the gate voltage of the semiconductor switching element, a short-circuit current that can flow through the semiconductor switching element is suppressed.
- a plurality of semiconductor switching elements such as IGBT (Insulated Gate Bipolar Transistor) may be connected in parallel.
- the plurality of semiconductor switching elements connected in parallel are preferably turned on all at once and turned off all at once.
- the Vth of the plurality of semiconductor switching elements may vary, or the gate drive signal may be supplied to the plurality of semiconductor switching elements at different timings.
- Patent Document 1 since a circuit for detecting a gate voltage and a circuit for controlling the semiconductor switching element are required for each semiconductor switching element, there is a problem that the control becomes complicated when the number of semiconductor switching elements connected in parallel increases. Moreover, since the gate wiring of the semiconductor switching elements connected in parallel is shared, there is a problem of gate oscillation.
- the present invention has been made to solve the above-described problems, and provides a drive circuit and a semiconductor device that can suppress a large current from flowing through a specific semiconductor switching element when switching a plurality of semiconductor switching elements connected in parallel.
- the purpose is to provide.
- a driving circuit includes a constant voltage circuit that generates a first voltage and a second voltage, and is connected to the constant voltage circuit, and receives the first voltage and the second voltage, and a gate driving signal. Is input to the constant voltage circuit, the second output circuit to which the first voltage and the second voltage are input, and the gate drive signal is input, and the first output circuit. A first terminal connected to the output of the second output circuit and a second terminal connected to the output of the second output circuit, and the first output circuit is provided only during a first period predetermined at the rising edge of the gate drive signal. The first voltage is applied to the first terminal, and after the elapse of the first period, the voltage of the gate drive signal is increased and applied to the first terminal, and predetermined when the gate drive signal falls.
- Applying the second voltage to the first terminal only for a second period of time, and outputting the second output circuit The first voltage is applied to the second terminal only during the first period when the gate driving signal rises, and after the first period, the voltage of the gate driving signal is increased to the second terminal. And the second voltage is applied to the second terminal only during the second period when the gate drive signal falls.
- a semiconductor device includes a constant voltage circuit that generates a first voltage and a second voltage, and is connected to the constant voltage circuit, to which the first voltage and the second voltage are input, and a gate drive signal And a plurality of terminals connected to the outputs of the plurality of output circuits, and a plurality of semiconductor switching elements connected to the plurality of terminals and connected in parallel.
- the output circuit applies the first voltage to the plurality of terminals for a predetermined first period when the gate drive signal rises, and increases the voltage of the gate drive signal after the first period has elapsed.
- the second voltage is applied to the plurality of terminals, and the second voltage is applied to the plurality of terminals for a predetermined second period when the gate drive signal falls.
- Another driving circuit includes a first constant voltage circuit that generates a first voltage and a second voltage, a second constant voltage circuit that generates a third voltage and a fourth voltage, and the first constant voltage.
- a first output circuit to which the first voltage and the second voltage are input and a gate drive signal is input, and the third voltage and the fourth voltage connected to the second constant voltage circuit.
- a second output circuit to which the gate drive signal is input, a first terminal connected to the output of the first output circuit, and a second terminal connected to the output of the second output circuit,
- the first output circuit applies the first voltage to the first terminal for a predetermined first period when the gate drive signal rises, and after the first period, the voltage of the gate drive signal Is applied to the first terminal, and the second period is determined in advance when the gate drive signal falls.
- the second voltage is applied to the first terminal only, and the second output circuit applies the third voltage to the second terminal only during the first period when the gate drive signal rises, After the lapse of one period, the voltage of the gate drive signal is increased and applied to the second terminal, and the fourth voltage is applied to the second terminal only during the second period when the gate drive signal falls.
- the first constant voltage circuit, the second constant voltage circuit, the first output circuit, and the second output circuit are integrated into one IC.
- Another drive circuit according to the present invention includes a first constant voltage circuit that generates a first voltage and a second voltage, a second constant voltage circuit that generates the same voltage as the first voltage and the second voltage, A plurality of first output circuits connected to the first constant voltage circuit, to which the first voltage and the second voltage are input, and to which a gate drive signal is input; and to the second constant voltage circuit; A plurality of second output circuits to which one voltage and the second voltage are input and a gate drive signal is input; a plurality of terminals connected to outputs of the plurality of first output circuits and outputs of the plurality of second output circuits; The plurality of first output circuits and the plurality of second output circuits apply the first voltage to the plurality of terminals only for a predetermined first period when the gate drive signal rises.
- the voltage of the gate drive signal is increased and applied to the plurality of terminals. And applying the second voltage to the plurality of terminals for a predetermined second period at the fall of the first drive signal, the first constant voltage circuit, the second constant voltage circuit, and the plurality of first outputs.
- the circuit and the plurality of second output circuits are integrated into one IC.
- the present invention since a voltage generated by one constant voltage circuit is applied when switching a plurality of semiconductor switching elements connected in parallel, it is possible to suppress a large current from flowing through a specific semiconductor switching element.
- FIG. 3 is a block diagram of a drive circuit according to Embodiment 1.
- FIG. It is a circuit diagram showing an example of the 1st output circuit. It is a waveform diagram.
- 3 is a circuit diagram of a constant voltage circuit according to a second embodiment.
- FIG. FIG. 6 is a block diagram of a drive circuit according to a third embodiment.
- FIG. 10 is a block diagram of a drive circuit according to a fourth embodiment.
- FIG. 10 is a circuit diagram of a semiconductor device according to a fifth embodiment.
- FIG. 10 is a block diagram of a drive circuit according to a sixth embodiment.
- FIG. 10 is a block diagram of a drive circuit according to a seventh embodiment.
- a driving circuit and a semiconductor device will be described with reference to the drawings.
- the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
- FIG. 1 is a block diagram of a drive circuit 10 according to Embodiment 1 of the present invention.
- the drive circuit 10 is formed by one IC (integrated circuit).
- the drive circuit 10 includes an input terminal 12 that receives a gate drive signal from the outside, and first and second terminals 24 and 26 that output the gate drive signal to the outside.
- the first terminal 24 is connected to the gate of the first semiconductor switching element
- the second terminal 26 is connected to the gate of the second semiconductor switching element connected in parallel to the first semiconductor switching element.
- the first and second semiconductor switching elements are not particularly limited, but are, for example, IGBTs.
- the drive circuit 10 controls a plurality of semiconductor switching elements connected in parallel.
- a signal transmission circuit 14 is connected to the input terminal 12.
- the signal transmission circuit 14 generates a gate drive signal (Preout) in synchronization with the signal input from the input terminal 12.
- the signal transmission circuit 14 includes at least one of a filter circuit, a delay circuit, and a level shift circuit.
- the filter circuit is a circuit that removes noise contained in the input signal.
- the delay circuit sets the dead time (off period) provided to prevent the upper and lower arm semiconductor switching elements from turning on at the same time and short-circuiting the power supply when the upper and lower arm semiconductor switching elements repeat on and off alternately. Circuit.
- the level shift circuit is a circuit that increases the signal level of the gate drive signal when the semiconductor switching element to be controlled is an element driven at a high voltage.
- the signal transmission circuit 14 is composed of an arbitrary circuit.
- the driving circuit 10 includes one constant voltage circuit 16 that generates the first voltage VEp and the second voltage VEn.
- the constant voltage circuit 16 may be provided outside the drive circuit. Whether the constant voltage circuit 16 is provided in the drive circuit 10 or outside the drive circuit 10, there is one constant voltage circuit.
- the constant voltage circuit 16 only needs to output the first voltage VEp and the second voltage VEn to the outside, and the configuration thereof is arbitrary.
- the drive circuit 10 includes a first output circuit 20 and a second output circuit 22.
- the first output circuit 20 is connected to the signal transmission circuit 14 and the constant voltage circuit 16 and receives a gate drive signal, a first voltage, and a second voltage.
- the second output circuit 22 is connected to the signal transmission circuit 14 and the constant voltage circuit 16 and receives the gate drive signal, the first voltage, and the second voltage.
- the first terminal 24 is connected to the output of the first output circuit 20.
- the output of the first output circuit 20 is applied to the first terminal 24.
- a second terminal 26 is connected to the output of the second output circuit 22.
- the output of the second output circuit 22 is applied to the second terminal 26.
- the first output circuit 20 and the second output circuit 22 output an output signal in synchronization with the gate drive signal Preout. Specifically, the signals OUTa and OUTb of the first and second terminals 24 and 26 rise in synchronization with the rise of the gate drive signal Preout, and the first and second terminals 24 in synchronization with the fall of the gate drive signal Preout. 26, signals OUTa and OUTb fall.
- the first output circuit 20 includes a first limiting circuit 20a, a first delay circuit 20b, and a first drive circuit 20c.
- the second output circuit 22 includes a second limiting circuit 22a, a second delay circuit 22b, and a second drive circuit 22c.
- the first limit circuit 20a and the second limit circuit 22a are circuits that receive the gate drive signal Preout and limit the voltage value of the output signal in synchronization with the gate drive signal Preout. Specifically, the rise of the output signals OUTa and OUTb is limited to the first voltage VEp when the gate drive signal Preout rises, and the fall of the output signals OUTa and OUTb is reduced to the second voltage when the gate drive signal Preout falls. Limited to VEn.
- the first delay circuit 20b and the second delay circuit 22b are circuits that delay the gate drive signal Preout.
- the delay time of the gate drive signal by the first delay circuit 20b and the second delay circuit 22b is sufficiently longer than the switching timing variation when the gate drive signal is supplied to the plurality of semiconductor switching elements at the same timing. And That is, a time longer than the switching time difference caused by the characteristic variation of the plurality of semiconductor switching elements is set as the delay time.
- the first drive circuit 20c and the second drive circuit 22c are circuits that control the voltage values of the output signals OUTa and OUTb during normal operation (non-switching).
- the first drive circuit 20c is driven by the gate drive signal Preout delayed by the first delay circuit 20b.
- the second drive circuit 22c is driven by the gate drive signal Preout delayed by the second delay circuit 22b.
- the first output circuit 20 and the second output circuit 22 output the gate drive signal input from the signal transmission circuit 14.
- the signal transmission circuit 14, the constant voltage circuit 16, the first output circuit 20, and the second output circuit 22 are formed as one IC.
- FIG. 2 is a circuit diagram showing an example of the first output circuit 20.
- the first output circuit 20 receives the first voltage VEp, the gate drive signal Preout, and the second voltage VEn.
- the first limiting circuit 20a is a source follower circuit. That is, the first limiting circuit 20a includes an NMOS 36 and a PMOS 38 that are connected as a source follower. The NMOS 36 and the PMOS 38 are controlled by the outputs of the inverters 32 and 34, respectively.
- the inverters 32 and 34 apply a voltage to the gates of the NMOS 36 and the PMOS 38 in synchronization with the gate drive signal Preout via the inverter 30.
- the power supply voltage of the inverter 32 is the first voltage VEp.
- the reference potential of the inverter 34 is the second voltage VEn.
- the first voltage VEp and the second voltage VEn are set so that the current value concentrated on any of the plurality of semiconductor switching elements connected in parallel is equal to or less than the breakdown tolerance of the semiconductor switching element.
- the first drive circuit 20c includes a PMOS 50 and an NMOS 52 connected in series.
- the PMOS 50 and the NMOS 52 are controlled by the gate drive signal Preout delayed by the first delay circuit 20b.
- the first delay circuit 20b includes delay circuits 40 and.
- the delay circuits 40 and 42 delay the signal only when the input signal rises.
- the gate drive signal is delayed by the delay circuit 40 when the gate drive signal Preout rises.
- the delayed gate drive signal is inverted by a NOT circuit (inverter) subsequent to the delay circuit 40 and input to the PMOS 50.
- the gate drive signal Preout falls, the signal inverted by the NOT circuit is delayed by the delay circuit 42.
- the delayed gate drive signal is input to the NMOS 52.
- the first voltage VEp is first applied to the first terminal 24 by the first limiting circuit 20a, and the PMOS 50 is turned on after a certain delay time has elapsed.
- the second voltage VEn is first applied to the first terminal 24 by the first limiting circuit 20a, and the NMOS 52 is turned on after a certain delay time has elapsed. That is, the voltage value of the first terminal 24 can be limited to the first voltage VEp or the second voltage VEn during the period in which the gate drive signal Preout is delayed by the delay circuits 40 and 42.
- the second output circuit 22 can have the same circuit configuration as that of the first output circuit 20, and thus the description thereof is omitted.
- the operation of the drive circuit 10 will be described with reference to the waveform diagram of FIG.
- the first period Ta starts with the rise of the gate drive signal Preout.
- the period from time t1 to t2 is the first period Ta.
- the first voltage VEp is applied to the first terminal 24 by the first limiting circuit 20a. Further, the first voltage VEp is applied to the second terminal 26 by the second limiting circuit 22a.
- the first period Ta is equal to the period in which the gate drive signal is delayed by the first delay circuit 20b and the second delay circuit 22b.
- a steady period starting from time t2 to t3 starts.
- the gate drive signal delayed by the first delay circuit 20 b is amplified by the first drive circuit 20 c and applied to the first terminal 24.
- the first drive circuit 20 c amplifies the output of the first delay circuit 20 b and applies it to the first terminal 24 from the first period Ta to the start of the second period (time t 3) (steady period).
- the gate drive signal delayed by the second delay circuit 22 b is amplified by the second drive circuit 22 c and applied to the second terminal 26.
- the output of the second delay circuit 22 b is amplified, and the amplified signal is applied to the second terminal 26.
- the gate drive signal Preout falls.
- the period from time t3 to time t4 is the second period Tb.
- the first limiting circuit 20a applies the second voltage VEn to the first terminal 24 during the second period Tb.
- the second limiting circuit 22a applies the second voltage VEn to the second terminal 26 in the second period Tb.
- the second period Tb is equal to the period in which the gate drive signal is delayed by the first delay circuit 20b and the second delay circuit 22b.
- the voltage applied to the first second terminals 24 and 26 when the gate drive signal Preout rises is limited to the first voltage VEp, and when the gate drive signal Preout falls, the first second terminal 24 and The voltage applied to 26 is prevented from dropping below the second voltage VEn.
- the gate voltage at the time of switching of the several semiconductor switching element connected in parallel can be restrict
- the current concentrates on the semiconductor switching element that is turned on relatively quickly. Therefore, by limiting the rise in the gate voltage of the semiconductor switching element, the semiconductor switching element A large current can be prevented from flowing.
- the effect of the present invention will be specifically described assuming that two semiconductor switching elements connected in parallel are turned off.
- any semiconductor switching element connected in parallel for example, the first semiconductor switching element
- the current flowing through the first semiconductor switching element is still in the on state. It flows into some other semiconductor switching element (second semiconductor switching element). That is, the current flowing in the on state (steady period) is concentrated on the second semiconductor switching element.
- the second semiconductor switching element may deteriorate or break down.
- the decrease in the gate voltage of the first semiconductor switching element that is turned off in advance is limited to the second voltage VEn, thereby flowing into the second semiconductor switching element.
- the current value can be limited.
- the second voltage VEn is set so that the current value flowing into the second semiconductor switching element is equal to or less than the breakdown tolerance.
- the delay time set by the first delay circuit 20b and the second delay circuit 22b needs to be sufficiently long with respect to the switching variation (switching time difference) of the plurality of semiconductor switching elements. However, if this delay time is lengthened, desired control cannot be realized.
- a plurality of output circuits (first output circuit 20 and second output circuit 22) are integrated in one drive circuit 10 in order to shorten the delay time. Since the gate drive signal Preout is supplied from one signal transmission circuit 14 to a plurality of output circuits, there is almost no transmission delay difference between the gate drive signals input to the first delay circuit 20b and the second delay circuit 22b. .
- the delay circuits (the first delay circuit 20b and the second delay circuit 22b are suppressed while suppressing variations in operation of the plurality of semiconductor switching elements. ) Can be shortened.
- the first voltage and the second voltage are supplied from one constant voltage circuit 16 to a plurality of output circuits. Therefore, the plurality of output circuits use the common first voltage and second voltage, and the operation variation of the plurality of semiconductor switching elements can be suppressed.
- the drive circuit 10 can be variously modified without losing its characteristics.
- the signal transmission circuit 14 may be omitted.
- the first output circuit 20 applies the first voltage VEp to the first terminal 24 only for a predetermined first period when the gate drive signal rises, and after the first period, the voltage of the gate drive signal is applied. Is applied to the first terminal 24, and the second voltage VEn is applied to the first terminal 24 for a predetermined second period when the gate drive signal falls.
- a first output circuit having a configuration different from that of the first output circuit 20 may be used.
- the second output circuit 22 applies the first voltage VEp to the second terminal 26 only during the first period when the gate drive signal rises, and increases the voltage of the gate drive signal after the first period has elapsed to increase the second terminal.
- the second voltage VEn is applied to the second terminal 26 only during the second period when the gate drive signal falls.
- a second output circuit having a configuration different from that of the second output circuit 22 may be used.
- the drive circuit 10 has two output circuits, and two semiconductor switching elements are connected to the drive circuit 10.
- the number of output circuits included in the drive circuit 10 and those connected in parallel are connected.
- the number of semiconductor switching elements to be used is arbitrary. For example, when three semiconductor switching elements are controlled by one drive circuit, the first voltage VEp is lowered and the second voltage VEn is raised compared to the case where two semiconductor switching elements are controlled.
- the first voltage VEp is lowered and the second voltage VEn is raised compared to the case where two semiconductor switching elements are controlled.
- the current concentrated on one semiconductor switching element may become large. By doing so, it is possible to suppress a large current from flowing to a specific semiconductor switching element.
- FIG. 4 is a circuit diagram of the constant voltage circuit 16 according to the second embodiment.
- the constant voltage circuit 16 includes resistors 101, 102, 103, 104, 105, 106, variable resistor units 110, 112, and MOSs 114, 116.
- the variable resistance unit 110 includes a plurality of fuses between the resistor 101 and the resistor 102.
- the variable resistance unit 112 includes a plurality of fuses between the resistor 103 and the resistor 104. By selecting whether or not the laser is irradiated to the fuse, the resistance values of the variable resistance units 110 and 112 can be freely changed.
- the first voltage VEp and the second voltage VEn can be controlled (adjusted) by setting the resistance values of the variable resistance units 110 and 112 to desired values and controlling the gate input voltages of the MOSs 114 and 116.
- MOSs 114 and 116 have a source follower configuration in which drain terminals are connected to GND and VCC, respectively, and source terminals are connected to terminals (denoted by VEp and VEn).
- the resistors 105 and 106 connected to the source terminals of the MOSs 114 and 116 are inserted in order to prevent the source terminals of the MOSs 114 and 116 from becoming high impedance. It can be omitted.
- One of the resistors 101 and 102 can be a constant current source.
- One of the resistors 103 and 104 can be a constant current source.
- the first voltage VEp and the second voltage VEn can be adjusted by configuring the constant voltage circuit 16 using a fuse. Accordingly, the first voltage VEp and the second voltage VEn that are optimal for a plurality of semiconductor switching elements can be set in consideration of variations in Vth of the semiconductor switching elements.
- the configuration can be changed as appropriate.
- FIG. 5 is a block diagram of a drive circuit according to Embodiment 3 of the present invention.
- This drive circuit is provided with one protection circuit 200 connected to the signal transmission circuit 14.
- the protection circuit 200 cuts off the gate drive signal Preout when the power supply voltage (VCC) of the first drive circuit 20c or the second drive circuit 22c falls below a predetermined value, whereby the first drive circuit 20c.
- the output of the second drive circuit 22c is stopped.
- the protection operation of the plurality of drive circuits is performed by one protection circuit 200, uniform protection can be applied to the plurality of drive circuits. Specifically, since the outputs of the plurality of drive circuits can be stopped simultaneously by the protection circuit 200, the turn-off timings of the plurality of semiconductor switching elements can be made uniform. Furthermore, the signal transmission circuit 14, the constant voltage circuit 16, the first output circuit 20, the second output circuit 22, and the protection circuit 200 are integrated into one IC, so that the protection circuit is provided outside the drive circuit. The device configuration can be simplified. Note that one protection circuit may be connected to the first drive circuit 20c and the second drive circuit 22c to stop their output, or their output may be stopped by another method.
- FIG. FIG. 6 is a block diagram of a drive circuit according to the fourth embodiment.
- This drive circuit includes a temperature detection circuit 202 that measures the temperature of the drive circuit.
- the temperature detection circuit 202 measures the temperature of the drive circuit 10 by a known method.
- the temperature detection circuit 202 is connected to the constant voltage circuit 16.
- the constant voltage circuit 16 obtains information on the temperature measured by the temperature detection circuit 202.
- the constant voltage circuit 16 lowers the first voltage VEp and sets the second voltage VEn. Make it high.
- the temperature information and the output voltage (first voltage and second voltage) can be linked in this way by a known method using an amplifier, for example.
- the main heat source in the semiconductor device is a semiconductor switching element
- the temperature of the semiconductor switching element is predicted to be higher if the temperature of the drive circuit 10 is higher. For this reason, when the temperature of the drive circuit 10 is higher than a predetermined temperature, the temperature of the semiconductor switching element is also considered to be considerably high.
- the semiconductor switching element Deterioration of the device proceeds. Therefore, as described above, the current value concentrated on one of the plurality of semiconductor switching elements can be reduced by lowering the first voltage VEp and increasing the second voltage VEn.
- the temperature detection circuit When the temperature detection circuit is provided in the drive circuit, the temperature of the drive circuit is measured by the temperature detection circuit to indirectly detect the temperature of the semiconductor switching element.
- a temperature detection circuit may be provided on or near the semiconductor switching element.
- FIG. FIG. 7 is a circuit diagram of the semiconductor device 300 according to the fifth embodiment.
- the semiconductor device 300 includes a drive module 302 in which drive circuits 304 and 306 are formed.
- the drive circuits 304 and 306 basically have the same configuration as that of the drive circuit 10 of FIG. 1 described in the first embodiment, but are illustrated in that they have an output circuit and three output terminals. 1 different from the driving circuit 10 of FIG.
- the drive circuit 304 receives a gate drive signal from the input terminal HIN, and outputs a gate drive signal to the first terminal HO1, the second terminal HO2, and the third terminal HO3.
- the drive circuit 306 receives a gate drive signal from the input terminal LIN and outputs a gate drive signal to the first terminal LO1, the second terminal LO2, and the third terminal LO3.
- one constant voltage circuit supplies the first voltage and the second voltage to the three output circuits.
- One signal transmission circuit supplies a gate drive signal to three output circuits.
- the gate of the semiconductor switching element 310 is connected to the first terminal HO1, the gate of the semiconductor switching element 312 is connected to the second terminal HO2, and the gate of the semiconductor switching element 314 is connected to the third terminal HO3.
- the semiconductor switching elements 310, 312, and 314 are connected in parallel.
- the semiconductor switching elements 310, 312, and 314 are high potential side semiconductor switching elements.
- the gate of the semiconductor switching element 320 is connected to the first terminal LO1, the gate of the semiconductor switching element 322 is connected to the second terminal LO2, and the gate of the semiconductor switching element 324 is connected to the third terminal LO3.
- the semiconductor switching elements 320, 322, and 324 are connected in parallel.
- the semiconductor switching elements 320, 322, and 324 are low potential side semiconductor switching elements.
- the plurality of output circuits (provided by three each in the drive circuits 304 and 306) are provided with a plurality of terminals (first terminals HO1, LO1, and second) for a predetermined first period when the gate drive signal rises.
- the first voltage VEp is applied to the terminals HO2, LO2 and the third terminals HO3, LO3).
- the plurality of output circuits increase the voltage of the gate drive signal and apply it to the plurality of terminals after the first period has elapsed.
- the plurality of output circuits apply the second voltage VEn to the plurality of terminals only during a predetermined second period when the gate drive signal falls.
- the gate voltage of the semiconductor switching elements 310, 312, and 314 driven in parallel is suppressed to be equal to or lower than the first voltage VEp, so that no excessive current flows through any one of the elements. .
- the gate voltage of the semiconductor switching elements 310, 312, and 314 driven in parallel is limited to the second voltage VEn or more, so that an excessive current flows through any one of the elements. There is no. Similar effects can be obtained for the semiconductor switching elements 320, 322, and 324.
- each semiconductor switching element is controlled by an individual gate drive signal, there is no concern about gate oscillation, and control of the semiconductor switching element is also easy because it is unnecessary to detect the gate voltage.
- an element in which SOA (safe operation area) is set may be used.
- SOA safety operation area
- a more stable and large-capacity semiconductor device can be realized by setting the first voltage VEp and the second voltage VEn so that the maximum current value that can flow through the semiconductor switching element falls within the SOA.
- the first voltage VEp is set to a value at which a current equal to or lower than the rated current flows through an element that is first turned on among a plurality of semiconductor switching elements when the gate drive signal rises.
- the second voltage VEn is set to a value at which a current equal to or lower than the rated current flows through an element that is turned off last among the plurality of semiconductor switching elements when the gate drive signal falls.
- the number of semiconductor switching elements controlled by one drive circuit is not particularly limited as long as it is plural.
- the same number of output circuits and terminals as the number of semiconductor switching elements to be controlled are provided.
- these two drive circuits may be integrated into one IC (integrated circuit).
- a gate drive signal may be input to the drive circuits 304 and 306 from one terminal.
- a gate resistor may be provided between the output terminal of the drive circuit and the gate of the semiconductor switching element.
- IGBTs are illustrated as semiconductor switching elements, other types of switching elements may be used.
- the power source VB may be generated inside the semiconductor device instead of being supplied from outside the semiconductor device 300 as shown in FIG.
- a known technique such as one using a bootstrap circuit including a bootstrap diode can be used.
- a bridge circuit can be formed by providing two configurations shown in FIG. 7, and a three-phase AC inverter can be formed by providing three configurations.
- the drive circuits 304 and 306 any of the drive circuits described in the above embodiments can be used.
- FIG. 8 is a block diagram of a drive circuit according to the sixth embodiment.
- the drive circuit 10 includes a first constant voltage circuit 16A that generates a first voltage VEp1 and a second voltage VEn1, and a second constant voltage circuit 16B that generates a third voltage VEp2 and a fourth voltage VEn2.
- the first voltage VEp1 and the third voltage VEp2 are different, and the second voltage VEn1 and the fourth voltage VEn2 are different.
- the first output circuit 20 is connected to the first constant voltage circuit 16A, to which the first voltage VEp1 and the second voltage VEn1 are input, and the gate drive signal is input.
- the second output circuit 22 is connected to the second constant voltage circuit 16B, receives the third voltage VEp2 and the fourth voltage VEn2, and receives the gate drive signal.
- the first output circuit 20 applies the first voltage VEp1 to the first terminal 24 only for a predetermined first period when the gate drive signal rises, and increases the voltage of the gate drive signal after the first period has elapsed. Then, the second voltage VEn1 is applied to the first terminal 24 for a predetermined second period when the gate drive signal falls.
- the second output circuit 22 applies the third voltage VEp2 to the second terminal 26 only during the first period when the gate drive signal rises, and increases the voltage of the gate drive signal after the first period has elapsed to increase the second terminal.
- the fourth voltage VEn2 is applied to the second terminal 26 only during the second period when the gate drive signal falls.
- the first constant voltage circuit 16A, the second constant voltage circuit 16B, the first output circuit 20, and the second output circuit 22 are provided in one IC.
- an IGBT gate may be connected to the first terminal 24 and a MOSFET gate connected in parallel to the IGBT may be connected to the second terminal 26. Since the IGBT and MOSFET have different electrical characteristics, the upper limit voltage in the first period (period from t1 to t2 in FIG. 3) and the lower limit in the second period (period from t3 to t4 in FIG. 3) are separately applied to the IGBT and MOSFET. It is preferable to set the voltage.
- the first constant voltage circuit 16A and the second constant voltage circuit 16B are provided, different voltages can be applied to the IGBT and the MOSFET in the first period and the second period.
- the first constant voltage circuit 16A, the second constant voltage circuit 16B, the first output circuit 20, and the second output circuit 22 are provided in one IC, the switching timing shift (non-deterministic) of a plurality of semiconductor switching elements is not possible. (Equilibrium) can be suppressed.
- the plurality of semiconductor switching elements are not limited to IGBTs and MOSFETs, and known semiconductor switching elements can be used as appropriate.
- FIG. 9 is a block diagram of a drive circuit according to the seventh embodiment.
- the drive circuit 10 controls 10 semiconductor switching elements connected in parallel.
- 10 output circuits are provided.
- five first output circuits 210 and five second output circuits 212 are provided.
- the first constant voltage circuit 16A supplies the first voltage VEp and the second voltage VEn to the five first output circuits 210.
- the second constant voltage circuit 16B also supplies the first voltage VEp and the second voltage VEn to the five second output circuits 212.
- the first voltage generated by the first constant voltage circuit 16A and the first voltage generated by the second constant voltage circuit 16B are equal, and the second voltage generated by the first constant voltage circuit 16A and the second constant voltage circuit 16B are generated.
- the second voltage is equal.
- the first constant voltage circuit 16A is connected to each of the five first output circuits 210, the first voltage and the second voltage are input, and the gate drive signal is input.
- Each of the five second output circuits 212 is connected to the second constant voltage circuit 16B, to which the first voltage and the second voltage are input, and the gate drive signal is input.
- the outputs of a total of ten output circuits are connected to the terminal 214, respectively.
- Each of the ten output circuits has a configuration equivalent to that of the first output circuit 20 of FIG.
- the first output circuit 210 and the second output circuit 212 apply the first voltage VEp to a plurality of terminals only during a predetermined first period when the gate drive signal rises, and drive the gate after the first period has elapsed.
- the voltage of the signal is increased and applied to the plurality of terminals, and the second voltage VEn is applied to the plurality of terminals for a predetermined second period when the gate drive signal falls.
- the first constant voltage circuit 16A, the second constant voltage circuit 16B, the plurality of first output circuits 210, and the plurality of second output circuits 212 are configured as one IC.
- the voltage values supplied to the plurality of output circuits can be made substantially equal.
- first constant voltage circuit 16A, the second constant voltage circuit 16B, the plurality of first output circuits 210, and the plurality of second output circuits 212 are made into one IC, control variations of the plurality of output circuits can be suppressed.
- the number of output circuits is not limited to ten. Even if the number of output circuits is about four, a plurality of constant voltage circuits should be provided when it is necessary to equalize constant voltage values supplied to a plurality of output circuits. Note that the effects of the present invention may be enhanced by appropriately combining the characteristics of the driver circuits described in the above embodiments.
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Abstract
Description
本願の発明に係る他の駆動回路は、第1電圧と第2電圧を生成する第1定電圧回路と、第3電圧と第4電圧を生成する第2定電圧回路と、該第1定電圧回路に接続され、該第1電圧及び該第2電圧が入力され、ゲート駆動信号が入力される第1出力回路と、該第2定電圧回路に接続され、該第3電圧及び該第4電圧が入力され、該ゲート駆動信号が入力される第2出力回路と、該第1出力回路の出力につながる第1端子と、該第2出力回路の出力につながる第2端子と、を備え、該第1出力回路は、該ゲート駆動信号の立ち上がりの際に予め定められた第1期間だけ該第1端子に該第1電圧を印加し、該第1期間の経過後には該ゲート駆動信号の電圧を高めて該第1端子に印加し、該ゲート駆動信号の立ち下がりの際に予め定められた第2期間だけ該第1端子に該第2電圧を印加し、該第2出力回路は、該ゲート駆動信号の立ち上がりの際に該第1期間だけ該第2端子に該第3電圧を印加し、該第1期間の経過後には該ゲート駆動信号の電圧を高めて該第2端子に印加し、該ゲート駆動信号の立ち下がりの際に該第2期間だけ該第2端子に該第4電圧を印加し、該第1定電圧回路、該第2定電圧回路、該第1出力回路及び該第2出力回路を1つのICとしたことを特徴とする。
本願の発明に係る他の駆動回路は、第1電圧と第2電圧を生成する第1定電圧回路と、該第1電圧と該第2電圧と同じ電圧を生成する第2定電圧回路と、該第1定電圧回路に接続され、該第1電圧及び該第2電圧が入力され、ゲート駆動信号が入力される複数の第1出力回路と、該第2定電圧回路に接続され、該第1電圧及び該第2電圧が入力され、ゲート駆動信号が入力される複数の第2出力回路と、該複数の第1出力回路の出力と該複数の第2出力回路の出力につながる複数の端子と、を備え、該複数の第1出力回路と該複数の第2出力回路は、該ゲート駆動信号の立ち上がりの際に予め定められた第1期間だけ該複数の端子に該第1電圧を印加し、該第1期間の経過後には該ゲート駆動信号の電圧を高めて該複数の端子に印加し、該ゲート駆動信号の立ち下がりの際に予め定められた第2期間だけ該複数の端子に該第2電圧を印加し、該第1定電圧回路、該第2定電圧回路、該複数の第1出力回路及び該複数の第2出力回路を1つのICとしたことを特徴とする。
図1は、本発明の実施の形態1に係る駆動回路10のブロック図である。駆動回路10は1つのIC(集積回路)で形成されている。駆動回路10は、外部からゲート駆動信号を受ける入力端子12と、外部へゲート駆動信号を出力する第1第2端子24、26とを備えている。第1端子24には第1半導体スイッチング素子のゲートが接続され、第2端子26には第1半導体スイッチング素子に並列接続された第2半導体スイッチング素子のゲートが接続される。第1第2半導体スイッチング素子は特に限定されないが例えばIGBTである。駆動回路10は並列接続された複数の半導体スイッチング素子を制御するものである。
実施の形態2に係る駆動回路は定電圧回路の構成に特徴がある。図4は、実施の形態2に係る定電圧回路16の回路図である。定電圧回路16は、抵抗101、102、103、104、105、106と、可変抵抗部110、112と、MOS114、116を備えている。可変抵抗部110は抵抗101と抵抗102の間に複数のヒューズを備えている。可変抵抗部112は抵抗103と抵抗104の間に複数のヒューズを備えている。ヒューズにレーザを照射するか否かを選択することで、可変抵抗部110、112の抵抗値を自在に変更することができる。可変抵抗部110、112の抵抗値を所望の値とし、MOS114、116のゲート入力電圧を制御することで、第1電圧VEpと第2電圧VEnを制御(調節)することができる。
実施の形態3に係る駆動回路は保護回路を設けたことに特徴がある。図5は、本発明の実施の形態3に係る駆動回路のブロック図である。この駆動回路には、信号伝達回路14に接続された1つの保護回路200が設けられている。保護回路200は、第1駆動回路20c又は第2駆動回路22cの電源電圧(VCC)が予め定められた値よりも低下したときに、ゲート駆動信号Preoutを遮断することで、第1駆動回路20cと第2駆動回路22cの出力をストップさせるものである。
図6は、実施の形態4に係る駆動回路のブロック図である。この駆動回路は、駆動回路の温度を測定する温度検出回路202を備えている。温度検出回路202は周知の方法で駆動回路10の温度を測定する。温度検出回路202は定電圧回路16に接続されている。定電圧回路16は、温度検出回路202で測定した温度の情報を得て、駆動回路10の温度が予め定められた温度より高くなった場合、第1電圧VEpを低くし、第2電圧VEnを高くする。このように温度情報と出力電圧(第1電圧と第2電圧)を連動させるのは、例えば増幅器を利用する周知の方法により実現可能である。
図7は、実施の形態5に係る半導体装置300の回路図である。半導体装置300は、駆動回路304、306が形成された駆動モジュール302を備えている。駆動回路304、306は基本的には実施の形態1で説明した図1の駆動回路10と同じ構成を有しているが、出力回路と出力用の端子を3つ有している点で図1の駆動回路10と異なっている。
実施の形態1~5では、1つの駆動回路に1つの定電圧回路を設けた。しかし、1つの駆動回路の中に複数の定電圧回路を設けることが適切な場合があるので、そのような場合について実施の形態6、7で説明する。図8は、実施の形態6に係る駆動回路のブロック図である。この駆動回路10は、第1電圧VEp1と第2電圧VEn1を生成する第1定電圧回路16Aと、第3電圧VEp2と第4電圧VEn2を生成する第2定電圧回路16Bを備えている。第1電圧VEp1と第3電圧VEp2は異なり、第2電圧VEn1と第4電圧VEn2は異なる。
図9は、実施の形態7に係る駆動回路のブロック図である。この駆動回路10は、並列接続された10個の半導体スイッチング素子を制御するものである。そのために、10個の出力回路を備える。具体的には5個の第1出力回路210と5個の第2出力回路212を備える。第1定電圧回路16Aは第1電圧VEpと第2電圧VEnを5個の第1出力回路210に供給する。第2定電圧回路16Bも第1電圧VEpと第2電圧VEnを5個の第2出力回路212に供給する。第1定電圧回路16Aが生成する第1電圧と第2定電圧回路16Bが生成する第1電圧は等しく、第1定電圧回路16Aが生成する第2電圧と第2定電圧回路16Bが生成する第2電圧は等しい。
Claims (13)
- 第1電圧と第2電圧を生成する1つの定電圧回路と、
前記定電圧回路に接続され、前記第1電圧及び前記第2電圧が入力され、ゲート駆動信号が入力される第1出力回路と、
前記定電圧回路に接続され、前記第1電圧及び前記第2電圧が入力され、前記ゲート駆動信号が入力される第2出力回路と、
前記第1出力回路の出力につながる第1端子と、
前記第2出力回路の出力につながる第2端子と、を備え、
前記第1出力回路は、前記ゲート駆動信号の立ち上がりの際に予め定められた第1期間だけ前記第1端子に前記第1電圧を印加し、前記第1期間の経過後には前記ゲート駆動信号の電圧を高めて前記第1端子に印加し、前記ゲート駆動信号の立ち下がりの際に予め定められた第2期間だけ前記第1端子に前記第2電圧を印加し、
前記第2出力回路は、前記ゲート駆動信号の立ち上がりの際に前記第1期間だけ前記第2端子に前記第1電圧を印加し、前記第1期間の経過後には前記ゲート駆動信号の電圧を高めて前記第2端子に印加し、前記ゲート駆動信号の立ち下がりの際に前記第2期間だけ前記第2端子に前記第2電圧を印加することを特徴とする駆動回路。 - 前記第1出力回路は、
前記第1期間に前記第1端子に前記第1電圧を印加し、前記第2期間に前記第1端子に前記第2電圧を印加する第1制限回路と、
前記ゲート駆動信号を遅延させて出力する第1遅延回路と、
前記第1期間の後から前記第2期間の開始までの間、前記第1遅延回路の出力を増幅して前記第1端子に印加する第1駆動回路と、を備え、
前記第2出力回路は、
前記第1期間に前記第2端子に前記第1電圧を印加し、前記第2期間に前記第2端子に前記第2電圧を印加する第2制限回路と、
前記ゲート駆動信号を遅延させて出力する第2遅延回路と、
前記第1期間の後から前記第2期間の開始までの間、前記第2遅延回路の出力を増幅して前記第2端子に印加する第2駆動回路と、を備えたことを特徴とする請求項1に記載の駆動回路。 - 少なくとも、フィルタ回路、ディレイ回路、又はレベルシフト回路のいずれか1つを備え、前記第1出力回路と前記第2出力回路に前記ゲート駆動信号を出力する1つの信号伝達回路を備えたことを特徴とする請求項2に記載の駆動回路。
- 前記定電圧回路、前記第1出力回路、前記第2出力回路及び前記信号伝達回路を1つのICとしたことを特徴とする請求項3に記載の駆動回路。
- 前記第1制限回路と前記第2制限回路はソースフォロワ回路であることを特徴とする請求項2に記載の駆動回路。
- 前記定電圧回路は、溶断の前後で前記第1電圧又は前記第2電圧を変化させるヒューズを備えることを特徴とする請求項1~5のいずれか1項に記載の駆動回路。
- 前記第1駆動回路又は前記第2駆動回路の電源電圧が予め定められた値よりも低下したときに前記第1駆動回路と前記第2駆動回路の出力をストップさせる1つの保護回路を備え、
前記定電圧回路、前記第1出力回路、前記第2出力回路、前記信号伝達回路及び前記保護回路を1つのICとしたことを特徴とする請求項3に記載の駆動回路。 - 前記駆動回路の温度を測定する温度検出回路を備え、
前記定電圧回路は、前記温度検出回路で測定した温度の情報を得て、前記駆動回路の温度が予め定められた温度より高くなった場合、前記第1電圧を低くし、前記第2電圧を高くすることを特徴とする請求項1~7のいずれか1項に記載の駆動回路。 - 第1電圧と第2電圧を生成する1つの定電圧回路と、
前記定電圧回路に接続され、前記第1電圧及び前記第2電圧が入力され、ゲート駆動信号が入力される複数の出力回路と、
前記複数の出力回路の出力につながる複数の端子と、
前記複数の端子に接続され、並列に接続された複数の半導体スイッチング素子と、を備え、
前記複数の出力回路は、前記ゲート駆動信号の立ち上がりの際に予め定められた第1期間だけ前記複数の端子に前記第1電圧を印加し、前記第1期間の経過後には前記ゲート駆動信号の電圧を高めて前記複数の端子に印加し、前記ゲート駆動信号の立ち下がりの際に予め定められた第2期間だけ前記複数の端子に前記第2電圧を印加することを特徴とする半導体装置。 - 前記第1電圧は、前記ゲート駆動信号の立ち上がり時に前記複数の半導体スイッチング素子のうち最初にターンオンした素子に定格電流以下の電流が流れる値に設定され、
前記第2電圧は、前記ゲート駆動信号の立ち下がり時に前記複数の半導体スイッチング素子のうち最後にターンオフした素子に定格電流以下の電流が流れる値に設定されたことを特徴とする請求項9に記載の半導体装置。 - 前記複数の半導体スイッチング素子の温度を測定する温度検出回路を備え、
前記定電圧回路は、前記温度検出回路で測定した温度の情報を得て、前記複数の半導体スイッチング素子の温度が予め定められた温度より高くなった場合、前記第1電圧を低くし、前記第2電圧を高くすることを特徴とする請求項9に記載の半導体装置。 - 第1電圧と第2電圧を生成する第1定電圧回路と、
第3電圧と第4電圧を生成する第2定電圧回路と、
前記第1定電圧回路に接続され、前記第1電圧及び前記第2電圧が入力され、ゲート駆動信号が入力される第1出力回路と、
前記第2定電圧回路に接続され、前記第3電圧及び前記第4電圧が入力され、前記ゲート駆動信号が入力される第2出力回路と、
前記第1出力回路の出力につながる第1端子と、
前記第2出力回路の出力につながる第2端子と、を備え、
前記第1出力回路は、前記ゲート駆動信号の立ち上がりの際に予め定められた第1期間だけ前記第1端子に前記第1電圧を印加し、前記第1期間の経過後には前記ゲート駆動信号の電圧を高めて前記第1端子に印加し、前記ゲート駆動信号の立ち下がりの際に予め定められた第2期間だけ前記第1端子に前記第2電圧を印加し、
前記第2出力回路は、前記ゲート駆動信号の立ち上がりの際に前記第1期間だけ前記第2端子に前記第3電圧を印加し、前記第1期間の経過後には前記ゲート駆動信号の電圧を高めて前記第2端子に印加し、前記ゲート駆動信号の立ち下がりの際に前記第2期間だけ前記第2端子に前記第4電圧を印加し、
前記第1定電圧回路、前記第2定電圧回路、前記第1出力回路及び前記第2出力回路を1つのICとしたことを特徴とする駆動回路。 - 第1電圧と第2電圧を生成する第1定電圧回路と、
前記第1電圧と前記第2電圧と同じ電圧を生成する第2定電圧回路と、
前記第1定電圧回路に接続され、前記第1電圧及び前記第2電圧が入力され、ゲート駆動信号が入力される複数の第1出力回路と、
前記第2定電圧回路に接続され、前記第1電圧及び前記第2電圧が入力され、ゲート駆動信号が入力される複数の第2出力回路と、
前記複数の第1出力回路の出力と前記複数の第2出力回路の出力につながる複数の端子と、を備え、
前記複数の第1出力回路と前記複数の第2出力回路は、前記ゲート駆動信号の立ち上がりの際に予め定められた第1期間だけ前記複数の端子に前記第1電圧を印加し、前記第1期間の経過後には前記ゲート駆動信号の電圧を高めて前記複数の端子に印加し、前記ゲート駆動信号の立ち下がりの際に予め定められた第2期間だけ前記複数の端子に前記第2電圧を印加し、
前記第1定電圧回路、前記第2定電圧回路、前記複数の第1出力回路及び前記複数の第2出力回路を1つのICとしたことを特徴とする駆動回路。
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PCT/JP2015/067916 WO2016207956A1 (ja) | 2015-06-22 | 2015-06-22 | 駆動回路、半導体装置 |
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WO2016207956A1 true WO2016207956A1 (ja) | 2016-12-29 |
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PCT/JP2015/067916 WO2016207956A1 (ja) | 2015-06-22 | 2015-06-22 | 駆動回路、半導体装置 |
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Country | Link |
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US (1) | US20180048302A1 (ja) |
JP (1) | JPWO2016207956A1 (ja) |
CN (1) | CN107710616A (ja) |
DE (1) | DE112015006645T5 (ja) |
WO (1) | WO2016207956A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11463081B2 (en) | 2019-07-08 | 2022-10-04 | Mitsubishi Electric Corporation | Driving circuit and semiconductor module |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11262243A (ja) * | 1998-03-10 | 1999-09-24 | Toshiba Corp | 電圧駆動型電力素子の駆動装置 |
JP2000040951A (ja) * | 1998-05-18 | 2000-02-08 | Toshiba Corp | 半導体素子、その駆動方法及び駆動装置 |
JP2009071956A (ja) * | 2007-09-12 | 2009-04-02 | Mitsubishi Electric Corp | ゲート駆動回路 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3260036B2 (ja) * | 1994-06-06 | 2002-02-25 | 株式会社東芝 | 電圧駆動形電力用スイッチ素子のゲート駆動回路 |
JPH0969764A (ja) * | 1995-09-01 | 1997-03-11 | Nec Eng Ltd | Mosバッファ回路 |
JPH0974344A (ja) * | 1995-09-04 | 1997-03-18 | Fuji Electric Co Ltd | 絶縁ゲート半導体素子の駆動回路 |
JP4909684B2 (ja) * | 2006-09-06 | 2012-04-04 | 三菱電機株式会社 | 半導体装置 |
JP5767018B2 (ja) * | 2011-05-17 | 2015-08-19 | トヨタ自動車株式会社 | 絶縁ゲート型スイッチング素子のゲートの電位を制御する回路 |
CN104937839B (zh) * | 2013-01-23 | 2017-09-08 | 三菱电机株式会社 | 半导体元件的驱动装置、半导体装置 |
-
2015
- 2015-06-22 JP JP2017524297A patent/JPWO2016207956A1/ja active Pending
- 2015-06-22 US US15/557,136 patent/US20180048302A1/en not_active Abandoned
- 2015-06-22 WO PCT/JP2015/067916 patent/WO2016207956A1/ja active Application Filing
- 2015-06-22 DE DE112015006645.4T patent/DE112015006645T5/de not_active Withdrawn
- 2015-06-22 CN CN201580081184.1A patent/CN107710616A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11262243A (ja) * | 1998-03-10 | 1999-09-24 | Toshiba Corp | 電圧駆動型電力素子の駆動装置 |
JP2000040951A (ja) * | 1998-05-18 | 2000-02-08 | Toshiba Corp | 半導体素子、その駆動方法及び駆動装置 |
JP2009071956A (ja) * | 2007-09-12 | 2009-04-02 | Mitsubishi Electric Corp | ゲート駆動回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11463081B2 (en) | 2019-07-08 | 2022-10-04 | Mitsubishi Electric Corporation | Driving circuit and semiconductor module |
Also Published As
Publication number | Publication date |
---|---|
DE112015006645T5 (de) | 2018-03-08 |
JPWO2016207956A1 (ja) | 2017-11-16 |
US20180048302A1 (en) | 2018-02-15 |
CN107710616A (zh) | 2018-02-16 |
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