WO2016199797A1 - マルチバンド増幅器およびデュアルバンド増幅器 - Google Patents
マルチバンド増幅器およびデュアルバンド増幅器 Download PDFInfo
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- WO2016199797A1 WO2016199797A1 PCT/JP2016/067003 JP2016067003W WO2016199797A1 WO 2016199797 A1 WO2016199797 A1 WO 2016199797A1 JP 2016067003 W JP2016067003 W JP 2016067003W WO 2016199797 A1 WO2016199797 A1 WO 2016199797A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B1/0483—Transmitters with multiple parallel paths
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/602—Combinations of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/429—Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
- H04B2001/0408—Circuits with power amplifiers
- H04B2001/045—Circuits with power amplifiers with means for improving efficiency
Definitions
- the present invention relates to a transmission power amplifier for a next-generation mobile communication system, and more particularly to transmission for a radio communication apparatus capable of supporting a plurality of band bands required for a next-generation mobile communication system in which advanced use of frequencies such as cognitive radio advances.
- the present invention relates to a power amplifier.
- the wireless devices are multiband, aiming for miniaturization and single reception.
- Research and development of a type that processes a plurality of frequency band signals by a transmitter or a transmitter is underway.
- the latter is configured such that filters, mixers, amplifiers, and the like constituting the receiver and the transmitter can correspond to a plurality of frequency bands.
- the multi-band transmission power amplifier which is the key of radio equipment, is the biggest issue.
- the type that switches and amplifies multiple frequency band signals cannot amplify multiple frequency bands at the same time.
- concurrent multiband power amplifiers that amplify multiple frequency band signals simultaneously will become key technologies.
- Non-Patent Document 1 the concurrent type amplifier originally started with an approach of a low noise amplifier. Since then, research and development of concurrent power amplifiers has started, and research and development of multiple matching types that achieve multiple impedance matching conditions in multiple frequency bands for a single transistor has become active. There are many reports. For example, there are Non-Patent Document 2, Non-Patent Document 3, and the like as documents other than patent documents. Moreover, patent documents 1, 2, 3, 4 etc. are mentioned as a related patent document.
- the amplifier of the above type has a problem that the design of the input and output impedance matching circuit needs to satisfy a plurality of matching conditions at the same time, and the circuit configuration is complicated and the number of elements increases. For this reason, it is not easy to increase the design accuracy, and the circuit loss is large.
- the invention according to the present application has been made to solve the above-described problems, and the object of the invention is to solve the problems caused by the simultaneous use of a single transistor, It is an object of the present invention to provide a concurrent multiband power amplifier that realizes easy circuit design and good power amplification characteristics.
- a plurality of (N: N is a natural number of 2 or more) frequency band signals are independently amplified.
- a concurrent multiband amplifier that is configured by (N) transistor amplifier circuits 10, 20,..., 50, 70 and amplifies signals in a plurality of frequency bands simultaneously.
- the n-th transistor amplifier circuit 50 includes, for each corresponding frequency band, an input to a transistor that is an amplifying element including circuits 52 and 53 that block frequency bands other than the n-th included in the input coupling unit and the output coupling unit. And design an output impedance matching circuit. Thereby, the optimum characteristic can be realized for each corresponding frequency band. According to the present invention, since signals in a plurality of frequency bands are not simultaneously amplified by a single amplifier circuit, the above-described problem when amplified by a single transistor does not occur. A highly efficient and low distortion multiband power amplifier can be realized.
- each amplifier circuit includes an input impedance matching circuit and an output impedance matching circuit
- a multiband amplifier characterized in that an input impedance matching circuit and an output impedance matching circuit of an nth amplifier circuit have a transistor signal source impedance and a load impedance that realize optimal signal input / output characteristics in the nth frequency band. is there.
- a third invention according to the present application is a dual-band amplifier that simultaneously amplifies signals in the first and second frequency bands, as shown in FIG. 2 as an example.
- the first amplifier circuit 30 includes second frequency band blocking circuits 32 and 33 for blocking a signal of the second frequency band at the signal input coupling unit and the output coupling unit thereof,
- the second amplifying circuit 40 is a dual band amplifier characterized in that the signal input coupling section and the output coupling section include first frequency band blocking circuits 42 and 43 for blocking signals of the first frequency band. .
- the first amplifying circuit 30 includes the circuits 36 and 37 having a parallel resonance frequency in the second frequency band in the signal input coupling unit and the output coupling unit in series to constitute the second frequency band blocking circuit.
- the second amplifying circuit 40 includes the circuits 46 and 47 having a parallel resonance frequency in the first frequency band in the signal input coupling unit and the output coupling unit in series, thereby configuring the first frequency band blocking circuit. This is a dual-band amplifier.
- the first amplifier circuit 30A includes, in its signal input coupling portion and output coupling portion, circuits 36 and 37 having a parallel resonance frequency in the second frequency band in series, and the first frequency of the circuits 36 and 37 is the first frequency.
- a second frequency band blocking circuit 36A, 37A is configured by including circuit elements 361, 371 inserted in series to cancel the series reactance component in the band in the first frequency band;
- the second amplifier circuit 40A includes, in its signal input coupling portion and output coupling portion, circuits 46 and 47 whose parallel resonance frequency is in the first frequency band in series, and the second frequency of the circuits 46 and 47
- the dual band amplifier is characterized in that the first frequency band blocking circuits 46A and 47A are configured by including circuit elements 461 and 471 inserted in series that cancel the series reactance component in the band in the second frequency band.
- a sixth invention is the above third or fourth invention,
- a dual circuit characterized in that the circuits 36 and 37 whose parallel resonance frequency is in the second frequency band and the circuits 46 and 47 whose parallel resonance frequency is in the first frequency band are constituted by an inductor and a capacitor connected in parallel. It is a band amplifier.
- the first amplifying circuit 30 includes, in its signal input coupling section and output coupling section, serial transmission lines 72, 74 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to signals in the second frequency band.
- the second frequency band blocking circuit 32, 33 comprising circuits 73, 75 for short-circuiting the signal of the second frequency band.
- the second amplifier circuit 40 includes, in its signal input coupling section and output coupling section, serial transmission lines 82, 84 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to signals in the first frequency band.
- the dual-band amplifier includes the first frequency band blocking circuits and 43 including circuits 83 and 85 for short-circuiting a signal in the first frequency band.
- the first amplifying circuit 30B includes, in its signal input coupling section and output coupling section, serial transmission lines 72, 74 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to signals in the second frequency band, and Second frequency band blocking comprising circuits 73 and 75 for short-circuiting signals in the second frequency band, and circuits 38 and 39 for canceling susceptance components in the first frequency band of the short-circuiting circuits 73 and 75 in the first frequency band.
- the second amplifier circuit 40B includes, in its signal input coupling section and output coupling section, serial transmission lines 82, 84 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to signals in the first frequency band.
- First frequency band blocking comprising circuits 83 and 85 for short-circuiting signals in the first frequency band, and circuits 48 and 49 for canceling susceptance components in the second frequency band of the short-circuiting circuits 83 and 85 in the second frequency band.
- a dual-band amplifier including circuits 421 and 431.
- a circuit for short-circuiting the signal in the second frequency band provided in the signal input coupling unit and the output coupling unit of the first amplifier circuit 30C is configured by parallel stubs 731 and 751 having open ends
- a circuit for short-circuiting the signal in the first frequency band provided in the signal input coupling unit and the output coupling unit of the second amplifier circuit 40C is configured by parallel stubs 831 and 851 having open ends. It is a dual band amplifier.
- a circuit for short-circuiting the signal of the second frequency band provided in the signal input coupling unit and the output coupling unit of the first amplifier circuit 30D is configured by series resonance circuits 732 and 752 of inductors and capacitors
- a circuit for short-circuiting the signal of the first frequency band provided in the signal input coupling unit and the output coupling unit of the second amplifier circuit 40D is configured by series resonance circuits 832 and 852 of inductors and capacitors. Is a dual band amplifier.
- Circuits 731 and 751 for short-circuiting the signal of the second frequency band provided in the signal input coupling unit and the output coupling unit of the first amplifier circuit 30B, and the susceptance in the first frequency band of the circuits 731 and 751 are constituted by parallel stubs with open ends or shorted ends, Circuits 831 and 851 for short-circuiting signals in the first frequency band and susceptances in the second frequency band of the circuits 831 and 851 provided in the signal input coupling unit and output coupling unit of the second amplifier circuit 40B
- the dual band amplifier is characterized in that the circuits 481 and 491 for canceling the components in the second frequency band are constituted by parallel stubs with open ends or short ends.
- the circuits 731 and 751 provided in the signal input coupling unit and the output coupling unit of the first amplifier circuit 30B for short-circuiting the signal in the second frequency band are configured by parallel stubs with open ends, and the circuit 731 Circuits 382 and 392 that cancel the susceptance component in the first frequency band of 751 in the first frequency band are configured by inductors,
- the circuits 831 and 851 provided in the signal input coupling unit and the output coupling unit of the second amplifier circuit 40B for short-circuiting the signals in the first frequency band are configured by parallel stubs with open ends, and the circuit 831
- the dual band amplifier is characterized in that the circuits 482 and 492 for canceling the susceptance component in the second frequency band of 851 in the second frequency band are constituted by capacitors.
- a circuit for short-circuiting the signal of the second frequency band provided in the signal input coupling unit and the output coupling unit of the first amplifier circuit 30B is constituted by series resonance circuits 732 and 752 of inductors and capacitors, Circuits 383 and 393 that cancel the susceptance components in the first frequency band of the circuits 732 and 752 in the first frequency band are configured by inductors, A circuit for short-circuiting the signal of the first frequency band provided in the signal input coupling unit and the output coupling unit of the second amplifier circuit 40B is configured by inductor and capacitor series resonance circuits 832 and 852, and
- the dual band amplifier is characterized in that the circuits 483 and 493 for canceling the susceptance components in the second frequency band of the circuits 832 and 852 in the second frequency band are constituted by capacitors.
- a circuit for short-circuiting the signal of the second frequency band provided in the signal input coupling unit and the output coupling unit of the first amplifier circuit 30B is configured by inductor and capacitor series resonance circuits 732 and 752, and the circuit A circuit that cancels the susceptance component in the first frequency band of 732 and 752 in the first frequency band is configured by parallel stubs 384 and 394 having open ends or shorted ends
- a circuit for short-circuiting the signal of the first frequency band provided in the signal input coupling unit and the output coupling unit of the second amplifier circuit 40B is configured by inductor and capacitor series resonance circuits 832 and 852, and the circuit
- the dual band amplifier is characterized in that a circuit for canceling the susceptance component in the second frequency band of 832 and 852 in the second frequency band is configured by parallel stubs 484 and 494 having open ends or shorted ends.
- the first and second amplifier circuits include input impedance matching circuits 34 and 44 and output impedance matching circuits 35 and 45, respectively.
- Have The input impedance matching circuits 34 and 44 and the output impedance matching circuits 35 and 45 of the first and second amplifying circuits have a signal source impedance of a transistor that realizes optimum signal input / output characteristics in the first and second frequency bands, and A dual-band amplifier having a load impedance.
- the output power saturation characteristic and the distortion characteristic deterioration due to the increase in the influence of the above can be solved, and independent design of each amplifier circuit becomes possible. As a result, improvement in design accuracy, suppression of output power saturation characteristic degradation, and suppression of distortion characteristic increase can be realized.
- FIG. 1A is a schematic configuration diagram
- FIG. 1B is a schematic diagram of an example of a circuit.
- FIG. FIG. 3A shows output power P out with respect to input power, power added efficiency PAE with respect to input power, and drain efficiency ⁇ D
- FIG. 3B shows an output power spectrum of each frequency.
- FIG. 1 is a schematic diagram showing the configuration of a multiband amplifier according to a first embodiment of the present invention.
- the multiband amplifier in the present embodiment is a multiband amplifier that simultaneously amplifies signals in a plurality of frequency bands from 1st to Nth (N is a natural number of 2 or more).
- the multiband amplifier according to the first embodiment of the present invention includes a signal input terminal 1 and a signal output terminal 2 as shown in FIG. 1A.
- the multiband amplifier has first to Nth amplifier circuits 10, 20,... 50,.
- N is a natural number of 2 or more.
- Each amplifier circuit is a “transistor amplifier circuit” composed of an FET (Field Effect Transistor), but is simply abbreviated as “amplifier circuit” hereinafter.
- the first amplifier circuit 10 includes an input side blocking circuit 12 that blocks a frequency band signal other than the first frequency band at an input coupling unit corresponding to the input side of the amplifier circuit 10.
- the amplifier circuit 10 includes an output side blocking circuit 13 that blocks a frequency band signal other than the first frequency band at an output coupling unit corresponding to the output side of the amplifier circuit 10.
- the second amplifier circuit 20 includes an input side blocking circuit 22 and an output side blocking circuit 23 for blocking frequency band signals other than the second frequency band in the input coupling unit and the output coupling unit, respectively.
- a side blocking circuit 53 is provided.
- the N-th amplifier circuit 70 includes an input-side blocking circuit 72 and an output-side blocking circuit 73 that block frequency band signals other than the N-th frequency band, respectively, in the input coupling unit and the output coupling unit.
- the first to Nth multi-frequency band signals applied from the signal input terminal 1 to the multi-band amplifier are blocked by the input side blocking circuit 12 from frequency bands other than the first frequency band. Only the frequency band signal is input to the amplifier circuit 10. The first frequency band signal amplified by the amplifier circuit 10 is output from the signal output terminal 2 through the output side blocking circuit 13.
- the multi-frequency band signal applied from the signal input terminal 1 to the multi-band amplifier is blocked by the input side blocking circuit 22 from frequency bands other than the second frequency band, and only the second frequency band signal is amplified by the amplifier circuit 20. Is input.
- the second frequency band signal amplified by the amplifier circuit 20 is output from the signal output terminal 2 through the output side blocking circuit 23.
- only the Nth frequency band signal is input to the amplifier circuit 70, amplified by the amplifier circuit 70, and output from the signal output terminal 2.
- the multi-frequency band signals in the first to Nth frequency bands amplified by the amplifier circuits 10, 20,..., 50, and 70 are combined and output from the signal output terminal 2.
- each amplifier circuit of this embodiment when configured by a transistor, the amplification operation of the transistor is performed in a specific mode (Class A, Class B, Class C, Class F, inverse class F, class E, harmonic reactance). It is not limited to termination amplifiers, Doherty amplifiers, and the like.
- Each amplifier circuit is not limited to a single-stage amplifier circuit, and may be a multi-stage amplifier circuit. When each amplifier circuit is composed of transistors, the number of amplifier circuits in each frequency band is not necessarily the same. Further, it goes without saying that each frequency band signal amplifier circuit may be configured independently of other frequency band amplifier circuits, and each characteristic may be designed independently.
- Each amplifier circuit includes an FET as an amplification element, an input impedance matching circuit disposed on the input side of the FET, and an output impedance matching circuit disposed on the output side of the FET.
- the input impedance matching circuit and the output impedance matching circuit provided in the nth amplifier circuit 50 include an input side blocking circuit 52 and an output side blocking circuit 53 that block frequency band signals other than the nth frequency band. Input impedance matching and output impedance matching are performed for a transistor as an element.
- the input impedance matching circuit is designed so that the impedance when the signal source side is viewed from the FET becomes the signal source impedance ZST1 of the FET realizing the maximum added power efficiency of the FET.
- the output impedance matching circuit is designed so that the impedance when the load side is viewed from the FET becomes the load impedance ZLT1 of the FET realizing the maximum added power efficiency of the FET. That is, the input impedance matching circuit and the output impedance matching circuit have the signal source impedance Z S1 and the load impedance Z L1 as viewed from the amplifier circuit 50 of the input side blocking circuit 52 and the output side blocking circuit 53, respectively. Each of them realizes a function of converting into a signal source impedance ZST1 and a load impedance ZLT1 of the FET realizing the above. Thereby, the optimum characteristic can be realized for each corresponding frequency band.
- FIG. 1B shows an example in which an input impedance matching circuit is arranged on the input side of the FET and an output impedance matching circuit is arranged on the output side of the FET.
- the first amplifier circuit 10 includes an FET 11 that is an amplifier element, and an input impedance matching circuit 14 that realizes input impedance matching for the first frequency band signal of the FET 11 and reactance termination for the second harmonic is disposed.
- the first amplifier circuit 10 is also provided with an output impedance matching circuit 15 that realizes output impedance matching for the first frequency band signal of the FET 11 and reactance termination for the second and third harmonics.
- the input impedance matching circuit 14 performs reactance termination with respect to the second harmonic
- the output impedance matching circuit 15 performs reactance termination with respect to the second and third harmonics. May be performed.
- the other amplifier circuits 20, 50, and 70 include FETs 21, 51, and 71 that are amplifier elements, and input impedance matching having the same configuration as the input impedance matching circuit 14 is provided in front of each FET 21, 51, and 71. Circuits 24, 54 and 74 are arranged. Further, output impedance matching circuits 25, 55, and 75 having the same configuration as that of the output impedance matching circuit 15 are arranged at the subsequent stage of the respective FETs 21, 51, and 71.
- Each of the input impedance matching circuits 14, 24, 54, 74 has an impedance when the signal source side is viewed from the FETs 11, 21, 51, 71 and the FET 11 that realizes the maximum added power efficiency of the FETs 11, 21, 51, 71.
- 21, 51, 71 are designed to have a signal source impedance Z ST1 .
- the output impedance matching circuits 15, 25, 55, and 75 realize the maximum added power efficiency of the FETs 11, 21, 51, and 71 when the load side is viewed from the FETs 11, 21, 51, and 71.
- the FET 11, 21, 51, 71 is designed to have a load impedance Z LT1 .
- the input impedance matching circuits 14, 24, 54 and 74 and the output impedance matching circuits 15, 25, 55 and 75 are formed by distributed constant circuits such as microstrip lines.
- FIG. 2 is a schematic diagram showing a configuration of an amplifier according to the second embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier composed of two transistor amplifier circuits (hereinafter simply referred to as “amplifier circuit”). is there.
- the dual-band amplifier includes a signal input terminal 3 and a signal output terminal 4.
- the dual-band amplifier has two amplifier circuits 30 and 40.
- the first amplifier circuit 30 includes an input side blocking circuit 32 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30.
- the first amplifier circuit 30 includes an output side blocking circuit 33 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30.
- the second amplifying circuit 40 includes an input side blocking circuit 42 and an output side blocking circuit 43 that block the first frequency band signal in the input coupling unit and the output coupling unit, respectively.
- the first frequency band signal is passed through the input side blocking circuit 32 that blocks the second frequency band signal, and the first amplifier circuit 30. Is input.
- the first frequency band signal amplified by the first amplifier circuit 30 is output from the signal output terminal 4 through the output side blocking circuit 33 that blocks the second frequency band signal.
- the impedance when the input side blocking circuit 32 that blocks the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance of the output side blocking circuit 33 that blocks the second frequency band signal from the output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal is input to the second amplifier circuit 40 via the input side blocking circuit 42 that blocks the first frequency band signal. And amplified. Then, the second frequency band signal is output from the signal output terminal 4 of the dual band amplifier via the output side blocking circuit 43 that blocks the first frequency band signal.
- the impedances when the input side blocking circuit 42 and the output side blocking circuit 43 that block the first frequency band signal with respect to the first frequency band are viewed from the signal input terminal 3 and the output terminal 4 are open.
- the first amplifier circuit 30 includes an FET 31 that is an amplifier element, an input impedance matching circuit 34 disposed on the input side of the FET 31, and an output impedance matching circuit 35 disposed on the output side of the FET 31.
- the input impedance matching circuit 34 and the output impedance matching circuit 35 include an input side blocking circuit 32 and an output side blocking circuit 33 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34 is designed so that the impedance when the signal source side is viewed from the FET 31 becomes the signal source impedance Z ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35 is designed so that the impedance when the load side is viewed from the FET 31 becomes the load impedance Z LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the input impedance matching circuit 34 and the output impedance matching circuit 35 are configured to obtain the signal source impedance Z S1 and the load impedance Z L1 when the input side blocking circuit 32 and the output side blocking circuit 33 are viewed from the first amplifier circuit 30, respectively, by the FET 31. It serves to convert the maximum power added efficiency to realize FET31 signal source impedance Z ST1 and the load impedance Z LT1 of each.
- the second amplifier circuit 40 includes an FET 41 that is an amplifier element, an input impedance matching circuit 44 disposed on the input side of the FET 41, and an output impedance matching circuit 45 disposed on the output side of the FET 41.
- the input impedance matching circuit 44 and the output impedance matching circuit 45 are respectively a signal source impedance Z S2 and a load impedance Z when the input side blocking circuit 42 and the output side blocking circuit 43 blocking the first frequency band signal are viewed from the amplifier circuit 40, respectively.
- the L2 converted respectively to the maximum power added efficiency to realize the FET 41 source impedance Z ST2 and a load impedance Z LT2 of the FET 41.
- the impedance matching circuit of the frequency blocking circuit and the amplifier circuit By designing the impedance matching circuit of the frequency blocking circuit and the amplifier circuit in this way, a simultaneous dual band power amplifier that realizes the maximum added power efficiency characteristic for each frequency band signal can be obtained.
- the amplifier circuit that amplifies each frequency band signal can design a matching circuit independently, so that the type and gate width of the FET can be freely selected, and the accuracy of the optimum design with respect to power efficiency and output power is improved. It becomes high and it becomes easy to achieve high-efficiency power characteristics.
- each frequency band signal is amplified by an independent amplifier circuit, so that distortion such as intermodulation and cross modulation between different frequency band signals does not occur.
- the amplifier circuit has a multi-stage configuration.
- the amplification operation of the transistor is not limited to a specific mode (class A, class B, class C, class F, inverse class F, class E, high frequency reactance termination amplifier, Doherty amplifier, etc.).
- the first amplifier circuit 30 amplifies the first frequency band signal (f 1 ), and the second amplifier circuit 40 amplifies the second frequency band signal (f 2 ).
- the first frequency band signal (f 1 ) is 4.5 GHz
- the second frequency band signal (f 2 ) is 8.5 GHz.
- Figure 3A the output power P out of the output power P out (f 1) and second frequency band signals of the first frequency band signal (f 1) (f 2) (f 2), the first frequency band signal drain efficiency eta D power added efficiency PAE (f 1) and second frequency band signal power added efficiency PAE of (f 2) (f 2) , and a first frequency band signal (f 1) of (f 1) (f 1) and shows drain efficiency eta D a (f 2) of the second frequency band signal (f 2).
- the solid line is the characteristic of the first frequency band signal (f 1 )
- the broken line is the characteristic of the second frequency band signal (f 2 ).
- the power added efficiency PAE (f 1 ) and PAE (f 2 ) are obtained from [(output power P out ⁇ input power P in ) / amplifier power P DC ].
- the amplifier power P DC is DC power supplied to the amplification element.
- the drain efficiencies ⁇ D (f 1 ) and ⁇ D (f 2 ) are obtained from [output power P out / amplifier power P DC ].
- the output power P out of input power P in is the sufficient level in first and second frequency band signals (f 1, f 2), and power added efficiency PAE and drain efficiency ⁇ D also has good characteristics.
- FIG. 3B shows each frequency component included in the output power (dBm).
- 29 dBm input power P in the first frequency band signal (f 1) the input power P in the second frequency band signal (f 2) as 32 dBm
- the harmonic 2f 1 of the first frequency f 1, 3f 1, ... are sufficiently suppressed
- the frequency component of the difference between the first frequency f 1 and the second frequency f 2 such as [f 2 ⁇ f 1 ] is sufficiently smaller than the frequencies f 1 and f 2, and the intermodulation distortion is also present. It turns out that it is fully suppressed.
- FIG. 4 is a schematic diagram showing a configuration of an amplifier according to the third embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply abbreviated as “amplifier circuit”). is there. 4, parts having the same configuration as in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.
- the first amplifier circuit 30 includes an input side blocking circuit 36 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30.
- the input side blocking circuit 36 is a circuit having a parallel resonance frequency in the second frequency band, and is arranged in series with the amplifier circuit 30. Since the parallel resonant circuit has an impedance close to open at the parallel resonant frequency, the input side blocking circuit 36 is arranged in series with the first amplifier circuit 30, so that the second frequency band to the first amplifier circuit 30 is provided. Signal input is blocked.
- the first amplifier circuit 30 includes an output side blocking circuit 37 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30.
- the output side blocking circuit 37 is a circuit having a parallel resonance frequency in the second frequency band, and is arranged in series with the first amplifier circuit 30.
- the second amplifying circuit 40 includes an input side blocking circuit 46 and an output side blocking circuit 47 for blocking the first frequency band signal in the input coupling unit and the output coupling unit, respectively.
- the first frequency band signal is input to the first amplifier circuit 30 via the input side blocking circuit 36.
- the first frequency band signal amplified by the first amplifier circuit 30 is output from the signal output terminal 4 through the output side blocking circuit 37.
- the impedance of the input side blocking circuit 36 that blocks the second frequency band signal from the signal input terminal 3 with respect to the second frequency band is open.
- the impedance of the output side blocking circuit 37 that blocks the second frequency band signal from the output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal is supplied to the second amplifier circuit via an input side blocking circuit 46 that blocks the first frequency band signal. 40 is amplified.
- the second frequency band signal is output from the signal output terminal 4 of the dual-band amplifier via an output side blocking circuit 47 that blocks the first frequency band signal.
- the impedance when the input side blocking circuit 46 and the output side blocking circuit 47 that block the first frequency band signal from the signal input terminal 3 and the output terminal 4 are blocked with respect to the first frequency band is open.
- the first amplifier circuit 30 includes an FET 31 that is an amplifier element, an input impedance matching circuit 34 disposed on the input side of the FET 31, and an output impedance matching circuit 35 disposed on the output side of the FET 31.
- the input impedance matching circuit 34 and the output impedance matching circuit 35 include an input side blocking circuit 36 and an output side blocking circuit 37 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET 31 that is an amplifying element. To do.
- the input impedance matching circuit 34 is designed so that the impedance when the signal source side is viewed from the FET 31 becomes the signal source impedance Z ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35 is designed so that the impedance when the load side is viewed from the FET 31 becomes the load impedance Z LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the input impedance matching circuit 34 and the output impedance matching circuit 35 are configured to obtain the signal source impedance Z S1 and the load impedance Z L1 when the input side blocking circuit 36 and the output side blocking circuit 37 are viewed from the first amplifier circuit 30, respectively, by the FET 31. It serves to convert the maximum power added efficiency to realize FET31 signal source impedance Z ST1 and the load impedance Z LT1 of each.
- the second amplifier circuit 40 includes an FET 41 that is an amplifier element, an input impedance matching circuit 44 disposed on the input side of the FET 41, and an output impedance matching circuit 45 disposed on the output side of the FET 41.
- the input impedance matching circuit 44 and the output impedance matching circuit 45 are respectively a signal source impedance Z S2 and a load impedance Z when the input side blocking circuit 46 and the output side blocking circuit 47 that block the first frequency band signal are viewed from the amplifier circuit 40.
- the L2 converted respectively to the maximum power added efficiency to realize the FET 41 source impedance Z ST2 and a load impedance Z LT2 of the FET 41.
- FIG. 5 is a schematic diagram showing a configuration of an amplifier according to the fourth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply abbreviated as “amplifier circuit”). is there. 5, parts having the same configuration as in FIG. 2 are given the same reference numerals and description thereof is omitted.
- the circuits having the suffix A, B, C, or D, such as the amplifier circuits 30A and 40A are the same as the original circuits (amplifier circuits 30, 40, etc.). Since it may not be the structure of, it distinguishes and shows.
- the dual band amplifier has two amplifier circuits 30A and 40A.
- the first amplifier circuit 30A includes an input-side blocking circuit 57 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30A.
- the input-side blocking circuit 57 includes an input-side blocking circuit 36 whose parallel resonance frequency is in the second frequency band, and a circuit element that cancels the series reactance component in the first frequency band of the input-side blocking circuit 36 in the first frequency band. 56.
- the input side blocking circuit 36 and the circuit element 56 are arranged in series to form an input side blocking circuit 57.
- the first amplifier circuit 30A includes an output side blocking circuit 59 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30A.
- the output side blocking circuit 59 includes an output side blocking circuit 37 having a parallel resonance frequency in the second frequency band, and a circuit element that cancels the series reactance component in the first frequency band of the output side blocking circuit 37 in the first frequency band. 58.
- the output side blocking circuit 37 and the circuit element 58 are arranged in series to constitute an output side blocking circuit 59.
- the second amplifier circuit 40A includes an input-side blocking circuit 67 that blocks the first frequency band signal at the input coupling unit corresponding to the input side of the second amplifier circuit 40A.
- the input-side blocking circuit 67 is a circuit element that cancels the series-reactance component in the second frequency band of the input-side blocking circuit 46 in the second frequency band, and the input-side blocking circuit 46 whose parallel resonance frequency is in the first frequency band. 66.
- the input side blocking circuit 46 and the circuit element 66 are arranged in series to constitute an input side blocking circuit 67.
- the second amplifier circuit 40A includes an output side blocking circuit 69 that blocks the first frequency band signal at the output coupling unit corresponding to the output side of the second amplifier circuit 60.
- the output-side blocking circuit 69 includes an output-side blocking circuit 47 whose parallel resonance frequency is in the first frequency band, and a circuit element that cancels the series reactance component in the second frequency band of the output-side blocking circuit 47 in the second frequency band. 68.
- the output side blocking circuit 47 and the circuit element 68 are arranged in series to constitute an output side blocking circuit 69.
- the first frequency band signal is input to the first amplifier circuit 30A via the input side blocking circuit 57.
- the first frequency band signal amplified by the first amplifier circuit 30 ⁇ / b> A is output from the signal output terminal 4 through the output side blocking circuit 59.
- the impedance when the input side blocking circuit 57 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance of the output side blocking circuit 59 that blocks the second frequency band signal from the output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal is supplied to the second amplifier circuit 40A via the input side blocking circuit 67 for blocking the first frequency band signal. And amplified.
- the second frequency band signal is output from the signal output terminal 4 of the dual band amplifier via an output side blocking circuit 69 that blocks the first frequency band signal.
- the impedances of the input side blocking circuit 67 and the output side blocking circuit 69 that block the first frequency band signal with respect to the first frequency band from the signal input terminal 3 and the signal output terminal 4 are open.
- the first amplifier circuit 30A includes an FET 51 as an amplifying element, an input impedance matching circuit 54 disposed on the input side of the FET 51, and an output impedance matching circuit 55 disposed on the output side of the FET 51.
- the input impedance matching circuit 54 and the output impedance matching circuit 55 include an input side blocking circuit 57 and an output side blocking circuit 59 that block the second frequency band signal, and perform input and output impedance matching to the transistor FET 51 that is an amplifying element. To do.
- the input impedance matching circuit 54 is designed so that the impedance when the signal source side is viewed from the FET 51 becomes the signal source impedance Z ST1 of the FET 51 that realizes the maximum added power efficiency of the FET 51.
- the output impedance matching circuit 55 is designed so that the impedance when the load side is viewed from the FET 51 becomes the load impedance Z LT1 of the FET 51 that realizes the maximum added power efficiency of the FET 51. That is, the input impedance matching circuit 54 and the output impedance matching circuit 55 represent the signal source impedance Z S1 and the load impedance Z L1 when the input side blocking circuit 57 and the output side blocking circuit 59 are viewed from the first amplifier circuit 30A, respectively.
- the second amplifier circuit 40A includes an FET 61 that is an amplifier element, an input impedance matching circuit 64 disposed on the input side of the FET 61, and an output impedance matching circuit 65 disposed on the output side of the FET 41.
- the input impedance matching circuit 64 and the output impedance matching circuit 65 are the signal source impedance Z S2 and the input side blocking circuit 67 and the output side blocking circuit 69 that block the first frequency band signal as viewed from the second amplifier circuit 40A, respectively.
- the load impedance Z L2 converted respectively to the maximum power added efficiency to realize the signal source impedance Z ST2 and a load impedance Z LT2 of FET 41 of the FET 41.
- Z L2 is 50 ⁇ .
- the design and evaluation of the impedance matching circuit can be facilitated, and the performance can be improved. It has advantageous features. By designing the frequency blocking circuit and the impedance matching circuit of the amplifier circuit in this way, a simultaneous dual band power amplifier that realizes the maximum added power efficiency characteristic for each frequency band signal can be obtained.
- the input side blocking circuit 36 and the output side blocking circuit 37 whose parallel resonance frequency is in the second frequency band are respectively connected in parallel to the inductor and A capacitor was used. Further, the input side blocking circuit 46 and the output side blocking circuit 47 whose parallel resonance frequency is in the first frequency band are each configured by an inductor and a capacitor connected in parallel.
- FIG. 6 is a schematic diagram showing a configuration of an amplifier according to a sixth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply abbreviated as “amplifier circuit”). is there. 6, parts having the same configuration as in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.
- the first amplifier circuit 30 includes an input side blocking circuit 32 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30.
- the input-side blocking circuit 32 includes a serial transmission line 72 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to the signal in the second frequency band, and a parallel circuit 73 that short-circuits the signal in the second frequency band.
- the serial transmission line 72 is connected in series to the main line, and the parallel circuit 73 is connected in parallel to the main line, whereby the input side blocking circuit 32 is configured.
- the first amplifier circuit 30 includes an output side blocking circuit 33 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30.
- the output-side blocking circuit 33 includes a serial transmission line 74 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to the signal in the second frequency band, and a parallel circuit 75 that short-circuits the signal in the second frequency band.
- the serial transmission line 74 is connected in series to the main line, and the parallel circuit 75 is connected in parallel to the main line, whereby the output side blocking circuit 33 is configured.
- the second amplifier circuit 40 includes an input side blocking circuit 42 that blocks the first frequency band signal at the input coupling unit corresponding to the input side of the second amplifier circuit 40.
- the input-side blocking circuit 42 includes a serial transmission line 82 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to a signal in the first frequency band, and a parallel circuit 83 that short-circuits the signal in the first frequency band.
- the serial transmission line 82 is connected in series to the main line, and the parallel circuit 83 is connected in parallel to the main line, so that the input side blocking circuit 42 is configured.
- the second amplifier circuit 40 includes an output side blocking circuit 43 that blocks the first frequency band signal at the output coupling unit corresponding to the output side of the second amplifier circuit 40.
- the output side blocking circuit 43 includes a serial transmission line 84 having a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to a signal in the first frequency band, and a parallel circuit 85 that short-circuits the signal in the first frequency band.
- the serial transmission line 84 is connected in series to the main line, and the parallel circuit 85 is connected in parallel to the main line, so that the output side blocking circuit 43 is configured.
- the first frequency band signal is input to the first amplifier circuit 30 via the input side blocking circuit 32.
- the first frequency band signal amplified by the first amplifier circuit 30 is output from the signal output terminal 4 through the output side blocking circuit 33.
- the impedance when the input side blocking circuit 32 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 4 is open.
- the impedance of the output side blocking circuit 33 that blocks the second frequency band signal from the signal output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal is sent to the second amplifier circuit 40 via the input side blocking circuit 42 that blocks the first frequency band signal. Input and amplified. Then, the second frequency band signal is output from the signal output terminal 4 of the dual band amplifier via the output side blocking circuit 43 that blocks the first frequency band signal.
- the impedances when the input side blocking circuit 42 and the output side blocking circuit 43 that block the first frequency band signal with respect to the first frequency band are viewed from the signal input terminal 3 and the output terminal 4 are open.
- the first amplifier circuit 30 includes an FET 31 that is an amplifier element, an input impedance matching circuit 34 disposed on the input side of the FET 31, and an output impedance matching circuit 35 disposed on the output side of the FET 31.
- the input impedance matching circuit 34 and the output impedance matching circuit 35 include an input side blocking circuit 32 and an output side blocking circuit 33 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34 is designed so that the admittance when the signal source side is viewed from the FET 31 becomes the signal source admittance Y ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35 is designed so that the admittance when the load side is viewed from the FET 31 becomes the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the input impedance matching circuit 34 and the output impedance matching circuit 35 convert the signal source admittance Y S1 and the load admittance Y L1 when the input side blocking circuit 32 and the output side blocking circuit 33 are viewed from the first amplifier circuit 30, respectively, to the FET 31.
- Each of the FETs 31 functions to convert the signal admittance Y ST1 and the load admittance Y LT1 of the FET 31 to achieve the maximum added power efficiency.
- the second amplifier circuit 40 includes an FET 41 that is an amplifier element, an input impedance matching circuit 44 disposed on the input side of the FET 41, and an output impedance matching circuit 45 disposed on the output side of the FET 41.
- the input impedance matching circuit 44 and the output impedance matching circuit 45 are the signal source admittance Y S2 and the input side blocking circuit 42 and the output side blocking circuit 43 that block the first frequency band signal as viewed from the second amplifier circuit 40, respectively.
- the load admittance Y L2 is converted into a signal source admittance Y ST2 and a load admittance Y LT2 of the FET 41 that realizes the maximum added power efficiency of the FET 41, respectively.
- the parallel circuits 73, 75, 83, 85 for short-circuiting the signal are not limited to specific circuits / elements such as a transmission line having an open end, a radial line, and a series resonance circuit of an inductor and a capacitive element.
- FIG. 7 is a schematic diagram showing a configuration of an amplifier according to a seventh embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply referred to as “amplifier circuit”). is there.
- amplifier circuit two transistor amplifier circuits
- the first amplifier circuit 30B includes an input-side blocking circuit 321 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30B.
- the input-side blocking circuit 321 includes a serial transmission line 72 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to a signal in the second frequency band, and a parallel circuit 73 that short-circuits the signal in the second frequency band. And a circuit 38 that cancels the susceptance component in the first frequency band of the parallel circuit 73 in the first frequency band (hereinafter referred to as “cancellation circuit 38”).
- the serial transmission line 72 is connected in series to the main line, and the parallel circuit 73 and the cancellation circuit 38 are connected in parallel to the main line to constitute the input side blocking circuit 321.
- the first amplifier circuit 30B includes an output side blocking circuit 331 that blocks the second frequency band signal in the output coupling unit corresponding to the output side of the first amplifier circuit 30B.
- the output blocking circuit 331 includes a serial transmission line 74 having a characteristic impedance of 50 ⁇ and a quarter-wavelength of the second frequency band signal, and a parallel circuit 75 that short-circuits the second frequency band signal.
- a circuit 39 that cancels the susceptance component in the first frequency band of the parallel circuit 75 in the first frequency band hereinafter referred to as “cancellation circuit 39”).
- the serial transmission line 74 is connected in series to the main line, and the parallel circuit 75 and the cancellation circuit 39 are connected in parallel to the main line to constitute an output side blocking circuit 331.
- the second amplifier circuit 40B includes an input side blocking circuit 421 that blocks the first frequency band signal at the input coupling portion thereof.
- the input-side blocking circuit 421 includes a serial transmission line 82 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to a signal in the first frequency band, and a parallel circuit 83 that short-circuits the signal in the first frequency band.
- a circuit 48 that cancels the susceptance component in the second frequency band of the parallel circuit 83 in the second frequency band hereinafter referred to as “cancellation circuit 48”.
- the second amplifier circuit 40B includes an output side blocking circuit 431 that blocks the first frequency band signal at the output coupling unit thereof.
- the output-side blocking circuit 431 includes a serial transmission line 84 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to a signal in the first frequency band, and a parallel circuit that short-circuits the signal in the first frequency band. 85 and a circuit 49 (hereinafter referred to as “cancellation circuit 49”) for canceling the susceptance component in the second frequency band of the parallel circuit 85 in the second frequency band.
- the first frequency band signal is input to the first amplifier circuit 30B via the input side blocking circuit 321.
- the first frequency band signal amplified by the first amplifier circuit 30B is output from the signal output terminal 4 through the output side blocking circuit 331.
- the impedance when the input side blocking circuit 321 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance when the output side blocking circuit 331 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal output terminal 4 is also opened.
- the second frequency band signal is input to the second amplifier circuit 40B via the input side blocking circuit 421 that blocks the first frequency band signal. And amplified.
- the second frequency band signal is output from the signal output terminal 4 of the dual band amplifier via an output side blocking circuit 431 that blocks the first frequency band signal.
- the impedances of the input side blocking circuit 421 and the output side blocking circuit 431 that block the first frequency band signal with respect to the first frequency band from the signal input terminal 3 and the signal output terminal 4 are open.
- the first amplifier circuit 30B includes an FET 31 that is an amplifier element, an input impedance matching circuit 34B disposed on the input side of the FET 31, and an output impedance matching circuit 35B disposed on the output side of the FET 31.
- the input impedance matching circuit 34B and the output impedance matching circuit 35B include an input side blocking circuit 321 and an output side blocking circuit 331 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34B is designed such that the admittance when the signal source side is viewed from the FET 31 is the signal source admittance Y ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35B is designed such that the admittance when the load side is viewed from the FET 31 is the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the input impedance matching circuit 34B and the output impedance matching circuit 35B are configured such that the input side blocking circuit 321 and the output side blocking circuit 331 that block the second frequency band signal are the signal source admittance Y viewed from the first amplifier circuit 30, respectively.
- the second amplifier circuit 40B includes an FET 41 that is an amplifier element, an input impedance matching circuit 44B disposed on the input side of the FET 41, and an output impedance matching circuit 45B disposed on the output side of the FET 41.
- the input impedance matching circuit 44B and the output impedance matching circuit 45B are the signal source admittance Y S2 when the input side blocking circuit 421 and the output side blocking circuit 431 blocking the first frequency band signal are viewed from the second amplifier circuit 40, respectively.
- the present embodiment is characterized in that the design and evaluation of each amplifier circuit is facilitated because the signal source and load impedance seen by each amplifier circuit are 50 ⁇ .
- the parallel circuits 73, 75, 83, 85 for short-circuiting the signal are not limited to specific circuits / elements such as an open-ended transmission line, a radial line, and a series resonance circuit of an inductor and a capacitive element.
- the cancellation circuits 38, 39, 48, and 49 for canceling the susceptance component are not limited to specific circuits and elements such as transmission lines, radial lines, inductors, and capacitive elements.
- FIG. 8 is a schematic diagram showing a configuration of an amplifier according to an eighth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply referred to as “amplifier circuit”). is there. 8, parts having the same configuration as in FIG. 6 are denoted by the same reference numerals and description thereof is omitted.
- the input side blocking circuits 32C and 42C for blocking frequency band signals and the circuits 73, 75, 83, and 85 for short-circuiting the frequency signals in the output side blocking circuits 33C and 43C are connected to parallel stubs with open ends. It is characterized by comprising 731, 751, 831, 851.
- the input-side blocking circuit 32C and the output-side blocking circuit 33C that block the second frequency band signal have a characteristic impedance of 50 ⁇ and a series transmission line 72 that has a quarter wavelength with respect to the signal of the second frequency band.
- the input side blocking circuit 42C and the output side blocking circuit 43C that block the first frequency band signal are also connected in series with a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to the signal of the first frequency band. It comprises transmission lines 82 and 84, and circuits 831 and 851 in a parallel stub configuration with an open end for short-circuiting the first frequency band signal having a quarter-wave strip line configuration in the first frequency band signal.
- the first amplifier circuit 30C connected to the input side blocking circuit 32C includes an FET 31 that is an amplifying element, an input impedance matching circuit 34C that is disposed on the input side of the FET 31, and an output impedance matching that is disposed on the output side of the FET 31.
- a circuit 35C is provided.
- the output impedance matching circuit 35C is connected to the output side blocking circuit 33C.
- the second amplifier circuit 40C connected to the input side blocking circuit 42C includes an FET 41 as an amplification element, an input impedance matching circuit 44C disposed on the input side of the FET 41, and an output impedance matching disposed on the output side of the FET 41.
- a circuit 45C is provided.
- the output impedance matching circuit 45C is connected to the output side blocking circuit 43C.
- the parallel stub is not limited to a specific transmission line such as a microstrip line, a coplanar line, or a radial line.
- FIG. 9 is a schematic diagram showing a configuration of an amplifier according to the ninth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier composed of two transistor amplifier circuits (hereinafter simply referred to as “amplifier circuit”). is there. 9, parts having the same configuration as in FIG. 6 are denoted by the same reference numerals and description thereof is omitted.
- circuits 73, 75, 83, and 85 for short-circuiting respective frequency signals in the input-side blocking circuits 32D and 42D and the output-side blocking circuits 33D and 43D for blocking frequency band signals are connected in series with inductors and capacitors. It is characterized by comprising circuits 732, 752, 832, and 852.
- the input-side blocking circuit 32D and the output-side blocking circuit 33D that block the second frequency band signal have a characteristic impedance of 50 ⁇ and a series transmission line 72 that has a quarter wavelength with respect to the signal of the second frequency band. And 74, and inductor-capacitor series circuits 732 and 752 that result in a series resonant short circuit in the second frequency band signal.
- the input side blocking circuit 42D and the output side blocking circuit 43D that block the first frequency band signal are also connected in series with a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to the signal of the first frequency band. It consists of transmission lines 82 and 84, and inductor-capacitor series circuits 832 and 852 that result in a series resonant short circuit in the first frequency band signal.
- the first amplifier circuit 30D connected to the input side blocking circuit 32D includes an FET 31 that is an amplification element, an input impedance matching circuit 34D that is disposed on the input side of the FET 31, and an output impedance matching that is disposed on the output side of the FET 31.
- a circuit 35D is provided.
- the output impedance matching circuit 35D is connected to the output side blocking circuit 33D.
- the second amplifier circuit 40D connected to the input side blocking circuit 42D includes an FET 41 as an amplifier element, an input impedance matching circuit 44D disposed on the input side of the FET 41, and an output impedance matching disposed on the output side of the FET 41.
- a circuit 45D is provided.
- the output impedance matching circuit 45D is connected to the output side blocking circuit 43D.
- FIG. 10 is a schematic diagram showing a configuration of an amplifier according to a tenth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply abbreviated as “amplifier circuit”). is there. 10, parts having the same configuration as in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.
- the first amplifier circuit 30B includes an input-side blocking circuit 321 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30B.
- the input-side blocking circuit 321 includes a serial transmission line 72 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to a signal in the second frequency band, and a parallel stub 731 that short-circuits the signal in the second frequency band. And a parallel stub 381 having a tip open or a tip short circuit that cancels the susceptance component in the first frequency band of the parallel stub 731 in the first frequency band.
- the serial transmission line 72 is connected in series to the main line, and the parallel stub 731 and the parallel stub 381 are connected in parallel to the main line, and the input side blocking circuit 321 is configured.
- the first amplifier circuit 30B includes an output side blocking circuit 331 that blocks the second frequency band signal in the output coupling unit corresponding to the output side of the first amplifier circuit 30B.
- the output side blocking circuit 331 includes a serial transmission line 74 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to the signal in the second frequency band, and a parallel stub 751 for short-circuiting the signal in the second frequency band. And a parallel stub 391 with open end or shorted end that cancels the susceptance component in the first frequency band of the parallel stub 751 in the first frequency band.
- the serial transmission line 74 is connected in series to the main line, the parallel stub 751 and the parallel stub 391 are connected in parallel to the main line, and the output side blocking circuit 331 is configured.
- the second amplifier circuit 40B includes an input side blocking circuit 421 for blocking the first frequency band signal at the input coupling portion thereof.
- the input blocking circuit 421 includes a serial transmission line 82 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to a signal in the first frequency band, and a parallel stub 831 that short-circuits the signal in the first frequency band.
- a parallel stub 481 having a tip open or a tip short circuit that cancels the susceptance component in the second frequency band of the parallel stub 831 in the second frequency band.
- the second amplifier circuit 40B includes an output side blocking circuit 431 that blocks the first frequency band signal at the output coupling unit thereof.
- the output side blocking circuit 431 includes a serial transmission line 84 having a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to the signal in the first frequency band, and a parallel stub 851 that short-circuits the signal in the first frequency band. And a parallel stub 491 having a tip open or a tip short circuit that cancels the susceptance component in the second frequency band of the parallel stub 851 in the second frequency band.
- the first frequency band signal is input to the first amplifier circuit 30B via the input side blocking circuit 321.
- the first frequency band signal amplified by the first amplifier circuit 30B is output from the signal output terminal 4 through the output side blocking circuit 331.
- the impedance when the input side blocking circuit 321 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance of the output side blocking circuit 331 that blocks the second frequency band signal from the output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal is input to the second amplifier circuit 40B via the input side blocking circuit 421 that blocks the first frequency band signal. And amplified.
- the second frequency band signal is output from the signal output terminal 4 of the dual band amplifier via an output side blocking circuit 431 that blocks the first frequency band signal.
- the impedances of the input side blocking circuit 421 and the output side blocking circuit 431 that block the first frequency band signal with respect to the first frequency band from the signal input terminal 3 and the signal output terminal 4 are open.
- the first amplifier circuit 30B includes an FET 31 that is an amplifier element, an input impedance matching circuit 34B disposed on the input side of the FET 31, and an output impedance matching circuit 35B disposed on the output side of the FET 31.
- the input impedance matching circuit 34B and the output impedance matching circuit 35B include an input side blocking circuit 321 and an output side blocking circuit 331 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34B is designed such that the admittance when the signal source side is viewed from the FET 31 is the signal source admittance Y ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35B is designed such that the admittance when the load side is viewed from the FET 31 is the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the admittance Y L1 1 / (50 ⁇ ) is converted into the signal source admittance Y ST1 and the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31, respectively.
- the second amplifier circuit 40B includes an FET 41 that is an amplifier element, an input impedance matching circuit 44B disposed on the input side of the FET 41, and an output impedance matching circuit 45B disposed on the output side of the FET 41.
- the input impedance matching circuit 44B and the output impedance matching circuit 45B are the signal source admittance Y S2 when the input side blocking circuit 421 and the output side blocking circuit 431 blocking the first frequency band signal are viewed from the second amplifier circuit 40B, respectively.
- the present embodiment is characterized in that the design and evaluation of each amplifier circuit is easy because the signal source and the load impedance viewed from each amplifier circuit are 50 ⁇ .
- the parallel stubs 731, 751, 831, 851 for short-circuiting the signal are not limited to a specific line structure such as a transmission line with an open end, a radial line, or the like.
- the parallel stubs 381, 391, 481, and 491 that cancel the susceptance component are not limited to a specific line structure such as an open-ended or short-circuited transmission line, microstrip line, coplanar line, or radial line.
- FIG. 11 is a schematic diagram showing a configuration of an amplifier according to an eleventh embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply abbreviated as “amplifier circuit”). is there. 11, portions having the same configuration as in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.
- the first amplifier circuit 30B includes an input-side blocking circuit 321 that blocks the second frequency band signal at the input coupling portion corresponding to the input side of the first amplifier circuit 30B.
- the input side blocking circuit 321 includes a serial transmission line 72 having a characteristic impedance of 50 ⁇ and a quarter wavelength of the second frequency band signal f 2 (f 2 > f 1 ), A parallel stub 731 that short-circuits signals in the frequency band and a parallel inductor 382 that cancels the susceptance component in the first frequency band f 1 of the parallel stub 731 in the first frequency band are provided.
- the serial transmission line 72 is connected in series, and the parallel stub 731 and the parallel inductor 382 are connected in parallel to form the input side blocking circuit 321.
- the first amplifier circuit 30B includes an output side blocking circuit 331 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30B.
- the output side blocking circuit 331 includes a serial transmission line 74 having a characteristic impedance of 50 ⁇ and a quarter wavelength of the second frequency band signal, and a parallel stub 751 for short-circuiting the second frequency band signal.
- the parallel stub 751 has a parallel inductor 392 that cancels the susceptance component in the first frequency band f 1 in the first frequency band.
- the serial transmission line 74 is connected in series, and the parallel stub 751 and the parallel inductor 392 are connected in parallel to constitute an output side blocking circuit 331.
- the second amplifier circuit 40B includes an input side blocking circuit 421 that blocks the first frequency band signal at the input coupling portion thereof.
- the input-side blocking circuit 421 includes a serial transmission line 82 having a characteristic impedance of 50 ⁇ and a quarter-wavelength with respect to the first frequency band signal f 1 (assuming f 2 > f 1 ), parallel stub 831 for short-circuiting the signal in the frequency band, comprising a parallel capacitor 482 to cancel the second susceptance component in a frequency band f 2 parallel stubs 831 in a second frequency band.
- the second amplifier circuit 40B has, as an output side blocking circuit 431 for blocking the first frequency band signal at its output coupling section, a characteristic impedance of 50 ⁇ and a length with respect to the first frequency band signal f 1 .
- quarter series transmission line 84 having a wavelength of, and parallel stub 851 for short-circuiting a signal of a first frequency band, cancel the second susceptance component in a frequency band f 2 parallel stubs 851 in a second frequency band parallel
- a capacitor 482 is provided.
- the first frequency band signal f 1 is input to the first amplifier circuit 30B via the input side blocking circuit 321.
- the first frequency band signal amplified by the first amplifier circuit 30B is output from the signal output terminal 4 through the output side blocking circuit 331.
- the impedance when the input side blocking circuit 321 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance of the output side blocking circuit 331 that blocks the second frequency band signal from the signal output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal f 2 is second amplified via the input side blocking circuit 421 that blocks the first frequency band signal.
- the signal is input to the circuit 40B and amplified.
- the second frequency band signal f 2 is outputted from the signal output terminal 4 of the dual-band amplifier via the output-side blocking circuit 431 blocks the first frequency band signal.
- the impedances of the input side blocking circuit 421 and the output side blocking circuit 431 that block the first frequency band signal with respect to the first frequency band from the signal input terminal 3 and the signal output terminal 4 are open.
- the first amplifier circuit 30B includes an FET 31 that is an amplifier element, an input impedance matching circuit 34B disposed on the input side of the FET 31, and an output impedance matching circuit 35B disposed on the output side of the FET 31.
- the input impedance matching circuit 34B and the output impedance matching circuit 35B include an input side blocking circuit 321 and an output side blocking circuit 331 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34B is designed such that the admittance when the signal source side is viewed from the FET 31 is the signal source admittance Y ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35B is designed such that the admittance when the load side is viewed from the FET 31 is the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the admittance Y L1 1 / (50 ⁇ ) is converted into a signal source admittance Y ST1 and a load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31, respectively.
- the second amplifier circuit 40B includes an FET 41 that is an amplifier element, an input impedance matching circuit 44B disposed on the input side of the FET 41, and an output impedance matching circuit 45B disposed on the output side of the FET 41.
- the present embodiment is characterized in that the design and evaluation of each amplifier circuit is facilitated because the signal source and load impedance seen by each amplifier circuit are 50 ⁇ .
- the parallel stubs 731, 751, 831, 851 for short-circuiting the signal are not limited to a specific line structure such as a transmission line, a microstrip line, a coplanar line, or a radial line with an open end.
- FIG. 12 is a schematic diagram showing a configuration of an amplifier according to a twelfth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply referred to as “amplifier circuit”). is there. 12, parts having the same configuration as in FIG. 7 are denoted by the same reference numerals and description thereof is omitted.
- the input side blocking circuits 321 and 421 and the output side element circuits 331 and 431 that block the frequency band signals described in FIG. Inductor-capacitor series circuits 732 and 832 and 752 and 852 are used.
- the first amplifier circuit 30B includes an input side blocking circuit 321 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30B.
- the input side blocking circuit 321 includes a serial transmission line 72 having a characteristic impedance of 50 ⁇ and a quarter wavelength of the second frequency band signal f 2 (f 2 > f 1 ), An inductor-capacitor series circuit 732 that short-circuits the signal in the frequency band, and a parallel inductor 383 that cancels the susceptance component in the first frequency band f 1 of the series circuit 732 in the first frequency band.
- the serial transmission line 72 is connected in series, and the series circuit 732 and the parallel inductor 383 are connected in parallel to constitute the input side blocking circuit 321.
- the first amplifier circuit 30B includes an output side blocking circuit 331 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30B.
- the output-side blocking circuit 331 includes a serial transmission line 74 having a characteristic impedance of 50 ⁇ and a quarter wavelength with respect to the second frequency band signal f 2 , an inductor that short-circuits the signal in the second frequency band, and
- the capacitor has a series circuit 752 and a parallel inductor 393 that cancels the susceptance component in the first frequency band f 1 of the series circuit 752 in the first frequency band.
- the serial transmission line 74 is connected in series, and the series circuit 752 and the parallel inductor 393 are connected in parallel to constitute an output side blocking circuit 331.
- the second amplifier circuit 40B includes an input side blocking circuit 421 that blocks the first frequency band signal at the input coupling portion thereof.
- the input side blocking circuit 421 includes a first transmission line 82 having a characteristic impedance of 50 ⁇ and a quarter wavelength of the first frequency band signal f 1 (f 2 > f 1 ), Inductor-capacitor series circuit 832 for short-circuiting a signal in the frequency band, and parallel capacitor 483 for canceling the susceptance component in second frequency band f2 of series circuit 832 in the second frequency band.
- the second amplifier circuit 40B has, as an output side blocking circuit 431 for blocking the first frequency band signal at its output coupling section, a characteristic impedance of 50 ⁇ and a length with respect to the first frequency band signal f 1 .
- quarter series transmission line 84 having a wavelength of, the series circuit 852 of the inductor-capacitor for short-circuiting a signal of a first frequency band, a second frequency susceptance component in a second frequency band f 2 of the series circuit 852
- a parallel capacitor 483 is provided to cancel in the band.
- the first frequency band signal f 1 is input to the first amplifier circuit 30B via the input side blocking circuit 321.
- the first frequency band signal amplified by the first amplifier circuit 30B is output from the signal output terminal 4 through the output side blocking circuit 331.
- the impedance when the input side blocking circuit 321 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance of the output side blocking circuit 331 that blocks the second frequency band signal from the signal output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal f 2 is second amplified via the input side blocking circuit 421 that blocks the first frequency band signal.
- the signal is input to the circuit 40B and amplified.
- Frequency signals f 2 of the second is derived from the signal output terminal 4 of the dual-band amplifier via the output-side blocking circuit 431 blocks the first frequency band signal.
- the impedances of the input side blocking circuit 421 and the output side blocking circuit 431 that block the first frequency band signal with respect to the first frequency band from the signal input terminal 3 and the signal output terminal 4 are open.
- the first amplifier circuit 30B includes an FET 31 that is an amplifier element, an input impedance matching circuit 34B disposed on the input side of the FET 31, and an output impedance matching circuit 35B disposed on the output side of the FET 31.
- the input impedance matching circuit 34B and the output impedance matching circuit 35B include an input side blocking circuit 321 and an output side blocking circuit 331 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34B is designed such that the admittance when the signal source side is viewed from the FET 31 is the signal source admittance Y ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35B is designed such that the admittance when the load side is viewed from the FET 31 is the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the admittance Y L1 1 / (50 ⁇ ) is converted into a signal source admittance Y ST1 and a load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31, respectively.
- the second amplifier circuit 40B includes an FET 41 that is an amplifier element, an input impedance matching circuit 44B disposed on the input side of the FET 41, and an output impedance matching circuit 45B disposed on the output side of the FET 41.
- the present embodiment is characterized in that the design and evaluation of each amplifier circuit is facilitated because the signal source and load impedance seen by each amplifier circuit are 50 ⁇ .
- FIG. 13 is a schematic diagram showing a configuration of an amplifier according to a thirteenth embodiment of the present invention, and is a circuit schematic diagram showing a dual-band amplifier including two transistor amplifier circuits (hereinafter simply referred to as “amplifier circuit”). is there.
- amplifier circuit two transistor amplifier circuits
- the first amplifier circuit 30B includes an input side blocking circuit 321 that blocks the second frequency band signal at the input coupling unit corresponding to the input side of the first amplifier circuit 30B.
- the input-side blocking circuit 321 includes a serial transmission line 72 having a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to the second frequency band signal f 2 (f 2 > f 1 ), Inductor-capacitor series circuit 732 for short-circuiting the signal in the frequency band, and parallel open-ended or short-circuited parallel stub 384 for canceling out the susceptance component in first frequency band f 1 of series circuit 732 in the first frequency band.
- the serial transmission line 72 is connected in series to the main line, and the series circuit 732 and the parallel stub 384 are connected in parallel to the main line to constitute the input side blocking circuit 321.
- the first amplifier circuit 30B includes an output side blocking circuit 331 that blocks the second frequency band signal at the output coupling unit corresponding to the output side of the first amplifier circuit 30B.
- Output blocking circuit 331 a serial transmission line 74 of one wavelength long characteristic impedance for the second frequency band signal f 2 at 50 ⁇ is 4 minutes, inductor for short-circuiting a signal of a second frequency band
- a series circuit 752 of capacitors and a parallel stub 394 with an open end or a shorted end that cancels the susceptance component in the first frequency band f 1 of the series circuit 752 in the first frequency band are provided.
- the serial transmission line 74 is connected in series to the main line, and the series circuit 752 and the parallel stub 394 are connected in parallel to the main line to constitute the output side blocking circuit 331.
- the second amplifier circuit 40B includes an input side blocking circuit 421 that blocks the first frequency band signal at the input coupling portion thereof.
- the input-side blocking circuit 421 includes a serial transmission line 82 having a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to the first frequency band signal f 1 (f 2 > f 1 ),
- An inductor-capacitor series circuit 832 for short-circuiting a signal in the frequency band, and a parallel stub 484 having a tip open or a tip short-circuit for canceling the susceptance component in the second frequency band f 2 of the series circuit 832 in the second frequency band are provided.
- the second amplifier circuit 40B includes an output side blocking circuit 431 that blocks the first frequency band signal at the output coupling unit thereof.
- the output-side blocking circuit 431 includes a series transmission line 84 having a characteristic impedance of 50 ⁇ and a length of a quarter wavelength with respect to the first frequency band signal f 1 , and an inductor that short-circuits the signal in the first frequency band. It comprises a series circuit 852 of the capacitor, the second parallel stub 494 of open-end or short-circuited end of canceling the second frequency band susceptance component in a frequency band f 2 of the series circuit 852.
- the first frequency band signal f 1 is input to the first amplifier circuit 30B via the input side blocking circuit 321.
- the first frequency band signal amplified by the first amplifier circuit 30B is output from the signal output terminal 4 through the output side blocking circuit 331.
- the impedance when the input side blocking circuit 321 for blocking the second frequency band signal with respect to the second frequency band is viewed from the signal input terminal 3 is open. Further, the impedance of the output side blocking circuit 331 that blocks the second frequency band signal from the signal output terminal 4 with respect to the second frequency band is also opened.
- the second frequency band signal f 2 is second amplified via the input side blocking circuit 421 that blocks the first frequency band signal.
- the signal is input to the circuit 40B and amplified.
- the second frequency band signal f 2 is outputted from the signal output terminal 4 of the dual-band amplifier via the output-side blocking circuit 431 blocks the first frequency band signal.
- the impedances of the input side blocking circuit 421 and the output side blocking circuit 431 that block the first frequency band signal with respect to the first frequency band from the signal input terminal 3 and the signal output terminal 4 are open.
- the first amplifier circuit 30B includes an FET 31 that is an amplifier element, an input impedance matching circuit 34B disposed on the input side of the FET 31, and an output impedance matching circuit 35B disposed on the output side of the FET 31.
- the input impedance matching circuit 34B and the output impedance matching circuit 35B include an input side blocking circuit 321 and an output side blocking circuit 331 that block the second frequency band signal, and perform input and output impedance matching with respect to the transistor FET31 that is an amplifying element. To do.
- the input impedance matching circuit 34B is designed such that the admittance when the signal source side is viewed from the FET 31 is the signal source admittance Y ST1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the output impedance matching circuit 35B is designed such that the admittance when the load side is viewed from the FET 31 is the load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31.
- the admittance Y L1 1 / (50 ⁇ ) is converted into a signal source admittance Y ST1 and a load admittance Y LT1 of the FET 31 that realizes the maximum added power efficiency of the FET 31, respectively.
- the second amplifier circuit 40B includes an FET 41 that is an amplifier element, an input impedance matching circuit 44B disposed on the input side of the FET 41, and an output impedance matching circuit 45B disposed on the output side of the FET 41.
- the input impedance matching circuit 44B and the output impedance matching circuit 45B are the signal source admittance Y S2 when the input side blocking circuit 421 and the output side blocking circuit 431 blocking the first frequency band signal are viewed from the second amplifier circuit 40B, respectively.
- the present embodiment is characterized in that the design and evaluation of each amplifier circuit is facilitated because the signal source and load impedance seen by each amplifier circuit are 50 ⁇ .
- the parallel stubs 384, 394, 484, and 494 for short-circuiting the signal are not limited to a specific line structure such as a transmission line having an open end, a microstrip line, a coplanar line, or a radial line.
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Abstract
Description
第nのトランジスタ増幅回路50は、各該当周波数帯に対して、入力結合部及び出力結合部に備えた第n以外の周波数帯を阻止する回路52、53を含めて増幅素子であるトランジスタに対する入力及び出力インピーダンス整合回路を設計する。これにより、各該当周波数帯に対して最適特性を実現することができる。
本発明によれば、複数の周波数帯の信号が単一の増幅回路により同時増幅されることは無いため、単一トランジスタにより増幅される場合の先に述べた問題を生じることは無く、特に、高効率かつ低ひずみのマルチバンド電力増幅器を実現できる。
第nの増幅回路の入力インピーダンス整合回路及び出力インピーダンス整合回路が第nの周波数帯において最適信号入出力特性を実現するトランジスタの信号源インピーダンス及び負荷インピーダンスを備えた
ことを特徴とするマルチバンド増幅器である。
前記第1の増幅回路30はその信号入力結合部及び出力結合部に第2の周波数帯の信号を阻止する第2周波数帯阻止回路32、33を備え、
前記第2の増幅回路40はその信号入力結合部及び出力結合部に第1の周波数帯の信号を阻止する第1周波数帯阻止回路42、43を備えた
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30はその信号入力結合部及び出力結合部に、並列共振周波数が第2の周波数帯にある回路36、37を直列に備えることにより前記第2周波数帯阻止回路を構成し、
前記第2の増幅回路40はその信号入力結合部及び出力結合部に、並列共振周波数が第1の周波数帯にある回路46、47を直列に備えることにより前記第1周波数帯阻止回路を構成した
ことを特徴とするデュアルバンド増幅器である。
第1の増幅回路30Aはその信号入力結合部及び出力結合部に、並列共振周波数が第2の周波数帯にある回路36、37を直列に備え、かつ、該回路36、37の第1の周波数帯における直列リアクタンス成分を第1の周波数帯において打ち消す直列に挿入された回路素子361、371を備えることにより第2周波数帯阻止回路36A、37Aを構成し、
第2の増幅回路40Aはその信号入力結合部及び出力結合部に、並列共振周波数が第1の周波数帯にある回路46、47を直列に備え、かつ、該回路46、47の第2の周波数帯における直列リアクタンス成分を第2の周波数帯において打ち消す直列に挿入された回路素子461、471を備えることにより第1周波数帯阻止回路46A、47Aを構成した
ことを特徴とするデュアルバンド増幅器である。
並列共振周波数が第2の周波数帯にある回路36、37及び並列共振周波数が第1の周波数帯にある回路46、47を、並列に接続されたインダクタ及びキャパシタにより構成した
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30はその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第2の周波数帯の信号に対して長さが4分の1波長の直列伝送線路72、74及び第2の周波数帯の信号を短絡する回路73、75からなる前記第2周波数帯阻止回路32、33を備え、
前記第2の増幅回路40はその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第1の周波数帯の信号に対して長さが4分の1波長の直列伝送線路82、84及び第1の周波数帯の信号を短絡する回路83、85からなる前記第1周波数帯阻止回路42、43を備えた
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Bはその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第2の周波数帯の信号に対して長さが4分の1波長の直列伝送線路72、74及び第2の周波数帯の信号を短絡する回路73、75、該短絡する回路73、75の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路38、39からなる第2周波数帯阻止回路321、331を備え、
前記第2の増幅回路40Bはその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第1の周波数帯の信号に対して長さが4分の1波長の直列伝送線路82、84及び第1の周波数帯の信号を短絡する回路83、85、該短絡する回路83、85の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路48、49からなる第1周波数帯阻止回路421、431を備えた
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Cの信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路を先端開放の並列スタブ731、751により構成して、
前記第2の増幅回路40Cの信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路を先端開放の並列スタブ831、851により構成したことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Dの信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路732、752により構成し、
前記第2の増幅回路40Dの信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路832、852により構成した
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Bの信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路731、751及び該回路731、751の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路381、391を先端開放あるいは先端短絡の並列スタブにより構成し、
前記第2の増幅回路40Bの信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路831、851及び該回路831、851の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路481、491を先端開放あるいは先端短絡の並列スタブにより構成した
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Bの信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路731、751を先端開放の並列スタブにより構成し、該回路731、751の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路382、392をインダクタにより構成し、
前記第2の増幅回路40Bの信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路831、851を先端開放の並列スタブにより構成し、該回路831、851の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路482、492をキャパシタにより構成した
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Bの信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路732、752により構成して、該回路732、752の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路383、393をインダクタにより構成し、
前記第2の増幅回路40Bの信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路832、852により構成して、該回路832、852の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路483、493をキャパシタにより構成した
ことを特徴とするデュアルバンド増幅器である。
前記第1の増幅回路30Bの信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路732、752により構成し、該回路732、752の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路を先端開放あるいは先端短絡の並列スタブ384、394により構成し、
前記第2の増幅回路40Bの信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路832、852により構成し、該回路832、852の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路を先端開放あるいは先端短絡の並列スタブ484、494により構成した
ことを特徴とするデュアルバンド増幅器である。
第1及び第2の増幅回路の入力インピーダンス整合回路34、44及び出力インピーダンス整合回路35、45がそれぞれの第1及び第2の周波数帯において最適信号入出力特性を実現するトランジスタの信号源インピーダンス及び負荷インピーダンスを備えた
ことを特徴とするデュアルバンド増幅器である。
図1は、本発明の第1実施形態によるマルチバンド増幅器の構成を示す概略図である。本実施の形態におけるマルチバンド増幅器は、第1から第N(Nは2以上の自然数)の複数の周波数帯の信号を同時に増幅するマルチバンド増幅器である。
第1の増幅回路10は、増幅回路10の入力側にあたる入力結合部に第1周波数帯以外の周波数帯信号を阻止する入力側阻止回路12を備える。また、増幅回路10は、増幅回路10の出力側にあたる出力結合部に第1周波数帯以外の周波数帯信号を阻止する出力側阻止回路13を備える。
以下同様に、第n(n=3~(N-1))の周波数帯信号のみが増幅回路50に入力され、増幅回路50で増幅されて、信号出力端子2から出力される。また、第Nの周波数帯信号のみが増幅回路70に入力され、増幅回路70で増幅されて、信号出力端子2から出力される。なお、増幅回路10、20・・・50、・・・70で増幅された第1ないし第N周波数帯の多周波数帯信号は、合成されて信号出力端子2から出力される。
第1の増幅回路10は、増幅素子であるFET11を備え、FET11の第1周波数帯信号に対する入力インピーダンス整合及びその第2高調波に対するリアクタンス終端を実現する入力インピーダンス整合回路14が配置される。また、第1の増幅回路10は、FET11の第1周波数帯信号に対する出力インピーダンス整合及びその第2及び第3高調波に対するリアクタンス終端を実現する出力インピーダンス整合回路15が配置される。なお、入力インピーダンス整合回路14が第2高調波に対するリアクタンス終端を行い、出力インピーダンス整合回路15が第2及び第3高調波に対するリアクタンス終端を行うのは一例であり、それぞれより高い高調波までリアクタンス終端を行うようにしてもよい。
同様に、その他の増幅回路20、50、70は、増幅素子であるFET21、51、71を備え、それぞれのFET21、51、71の前段に、入力インピーダンス整合回路14と同様の構成の入力インピーダンス整合回路24、54、74が配置される。また、それぞれのFET21、51、71の後段に、出力インピーダンス整合回路15と同様の構成の出力インピーダンス整合回路25、55、75が配置されている。
なお、入力インピーダンス整合回路14、24、54、74と出力インピーダンス整合回路15、25、55、75は、例えばマイクロストリップ線路などの分布定数回路で形成される。
図2は、本発明の第2実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図2に示すように、デュアルバンド増幅器は、信号入力端子3と信号出力端子4を備える。また、デュアルバンド増幅器は、2個の増幅回路30、40を有する。第1の増幅回路30は、第1の増幅回路30の入力側にあたる入力結合部に第2の周波数帯信号を阻止する入力側阻止回路32を備える。また、第1の増幅回路30は、第1の増幅回路30の出力側にあたる出力結合部に第2の周波数帯信号を阻止する出力側阻止回路33を備える。同様に、第2の増幅回路40はその入力結合部及び出力結合部に、第1の周波数帯信号を阻止する入力側阻止回路42及び出力側阻止回路43をそれぞれ備える。
なお、本実施例はトランジスタ1段増幅回路について説明したが、増幅回路を多段構成にした場合も含むことは言うまでもない。また、トランジスタの増幅動作は、特定のモード(A級、B級、C級、F級、逆F級、E級、高周波リアクタンス終端増幅器、ドハティ増幅器など)に限定されない。
第1の増幅回路30は、第1の周波数帯信号(f1)を増幅し、第2の増幅回路40は、第2の周波数帯信号(f2)を増幅する。ここで、第1の周波数帯信号(f1)は4.5GHzとし、第2の周波数帯信号(f2)は8.5GHzとしている。
図3Aは、第1の周波数帯信号(f1)の出力電力Pout(f1)と第2の周波数帯信号(f2)の出力電力Pout(f2)、第1の周波数帯信号(f1)の電力付加効率PAE(f1)と第2の周波数帯信号(f2)の電力付加効率PAE(f2)、及び第1の周波数帯信号(f1)のドレイン効率ηD(f1)と第2の周波数帯信号(f2)のドレイン効率ηD(f2)を示す。図3Aにおいて、実線は、第1の周波数帯信号(f1)の特性であり、破線は、第2の周波数帯信号(f2)の特性である。
図3Aから分かるように、入力電力Pinに対する出力電力Poutが、第1及び第2の周波数帯信号(f1、f2)で十分なレベルであり、かつ電力付加効率PAE及びドレイン効率ηDについても、良好な特性となっている。
図3Bから分かるように、第1の周波数f1の高調波2f1、3f1、・・・が十分に抑制されており、第2の周波数f2の高調波2f2、・・・についても十分に抑制されている。また、[f2-f1]などの第1の周波数f1と第2の周波数f2の差の周波数成分についても、周波数f1、f2に比べて十分に小さく、相互変調歪についても十分に抑制されていることが分かる。
図4は、本発明の第3実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図4において、図2と同一の構成からなる部分については、同一符号を付して説明を省略する。
図5は、本発明の第4実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図5において、図2と同一の構成からなる部分については、同一符号を付して説明を省略する。
なお、図5以降の各図において、増幅回路30A、40Aなどのように、末尾にA、B、C、またはDの符号を付す回路は、元の回路(増幅回路30、40など)と同一の構成でない場合があるために区別して示す。
本発明の第5実施形態では、第3及び第4実施形態において、並列共振周波数が第2の周波数帯にある入力側阻止回路36及び出力側阻止回路37をそれぞれ、並列に接続されたインダクタ及びキャパシタにより構成した。また、並列共振周波数が第1の周波数帯にある入力側阻止回路46及び出力側阻止回路47をそれぞれ、並列に接続されたインダクタ及びキャパシタにより構成した。
図6は、本発明の第6実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図6において、図2と同一の構成からなる部分については、同一符号を付して説明を省略する。
図7は、本発明の第7実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図7において、図2と同一の構成からなる部分については、同一符号を付して説明を省略する。
また、第2の増幅回路40Bはその出力結合部に、第1の周波数帯信号を阻止する出力側阻止回路431を備える。この出力側阻止回路431は、特性インピーダンスが50Ωで第1の周波数帯の信号に対して長さが4分の1波長の直列伝送線路84と、第1の周波数帯の信号を短絡する並列回路85と、並列回路85の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路49(以下、「打消回路49」という)を備える。
図8は、本発明の第8実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図8において、図6と同一の構成からなる部分については、同一符号を付して説明を省略する。
入力側阻止回路42Cに接続された第2の増幅回路40Cは、増幅素子であるFET41と、FET41の入力側に配置された入力インピーダンス整合回路44Cと、FET41の出力側に配置された出力インピーダンス整合回路45Cを備える。出力インピーダンス整合回路45Cが、出力側阻止回路43Cに接続される。
なお、並列スタブはマイクロストリップ線路、コープレーナ線路、ラジアル線路等の特定の伝送線路に限定されないことは言うまでもない。
図9は、本発明の第9実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図9において、図6と同一の構成からなる部分については、同一符号を付して説明を省略する。
入力側阻止回路32Dに接続された第1の増幅回路30Dは、増幅素子であるFET31と、FET31の入力側に配置された入力インピーダンス整合回路34Dと、FET31の出力側に配置された出力インピーダンス整合回路35Dを備える。出力インピーダンス整合回路35Dが、出力側阻止回路33Dに接続される。
入力側阻止回路42Dに接続された第2の増幅回路40Dは、増幅素子であるFET41と、FET41の入力側に配置された入力インピーダンス整合回路44Dと、FET41の出力側に配置された出力インピーダンス整合回路45Dを備える。出力インピーダンス整合回路45Dが、出力側阻止回路43Dに接続される。
図10は、本発明の第10実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図10において、図7と同一の構成からなる部分については、同一符号を付して説明を省略する。
図11は、本発明の第11実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図11において、図7と同一の構成からなる部分については、同一符号を付して説明を省略する。
図12は、本発明の第12実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図12において、図7と同一の構成からなる部分については、同一符号を付して説明を省略する。
図13は、本発明の第13実施形態による増幅器の構成を示す概略図であり、2個のトランジスタ増幅回路(以下、単に「増幅回路」と略記)から成るデュアルバンド増幅器を示す回路模式図である。図13において、図7と同一の構成からなる部分については、同一符号を付して説明を省略する。
2、4・・・信号出力端子
10、20、30、30A、30B、30C、30D、40、40A、40B、40C、40D、50、60、70・・・増幅回路
11、21、31、41、51、61・・・増幅素子(FET)
12、22、32、42、36、36A、46、46A、52、57、67、321、361、421、461・・・入力側阻止回路
13、23、33、43、37、37A、47、47A、53、59、69、73、331、371、431、471・・・出力側阻止回路
14、24、34、34B、34C、34D、44、44B、44C、44D、54、64・・・入力インピーダンス整合回路
15、25、35、35B、35C、35D、45、45B、45C、45D、55、65・・・出力インピーダンス整合回路
38、39、83、85・・・打消回路
72、74、82、84・・・直列伝送線路
73、75、83、85・・・並列回路
381、384、391、394、481、484、491、494、731、751、831、851・・・並列スタブ
483、493・・・並列キャパシタ
732、752、832、852・・・インダクタ・キャパシタの直列回路
Claims (15)
- 第1乃至第N(Nは2以上の自然数)の周波数帯の信号を同時に増幅するマルチバンド増幅器であって、前記第1乃至第Nの周波数帯の各信号をそれぞれ増幅するN個の増幅回路を備えており、
第n(n=1~Nのいずれか)の周波数帯の信号を増幅する第nの増幅回路の信号入力結合部及び出力結合部に、第nの周波数帯の信号以外の周波数帯の信号を阻止する回路を備えた
ことを特徴とするマルチバンド増幅器。 - 前記各増幅回路は入力及び出力インピーダンス整合回路を有し、
第nの増幅回路の入力及び出力インピーダンス整合回路が第nの周波数帯において最適信号入出力特性を実現するトランジスタの信号源インピーダンス及び負荷インピーダンスを備えた
ことを特徴とする請求項1に記載のマルチバンド増幅器。 - 第1及び第2の周波数帯の信号を同時に増幅するデュアルバンド増幅器であって、前記第1の周波数帯の信号を増幅する第1の増幅回路及び前記第2の周波数帯の信号を増幅する第2の増幅回路を備えており、
前記第1の増幅回路はその信号入力結合部及び出力結合部に第2の周波数帯の信号を阻止する第2周波数帯阻止回路を備え、
前記第2の増幅回路はその信号入力結合部及び出力結合部に第1の周波数帯の信号を阻止する第1周波数帯阻止回路を備えた
ことを特徴とするデュアルバンド増幅器。 - 前記第1の増幅回路はその信号入力結合部及び出力結合部に、並列共振周波数が第2の周波数帯にある回路を直列に備えることにより前記第2周波数帯阻止回路を構成し、
前記第2の増幅回路はその信号入力結合部及び出力結合部に、並列共振周波数が第1の周波数帯にある回路を直列に備えることにより前記第1周波数帯阻止回路を構成した
ことを特徴とする請求項3に記載のデュアルバンド増幅器。 - 前記第1の増幅回路はその信号入力結合部及び出力結合部に、並列共振周波数が第2の周波数帯にある回路を直列に備え、かつ、該回路の第1の周波数帯における直列リアクタンス成分を第1の周波数帯において打ち消す直列に挿入された回路素子を備えることにより前記第2周波数帯阻止回路を構成し、
前記第2の増幅回路はその信号入力結合部及び出力結合部に、並列共振周波数が第1の周波数帯にある回路を直列に備え、かつ、該回路の第2の周波数帯における直列リアクタンス成分を第2の周波数帯において打ち消す直列に挿入された回路素子を備えることにより前記第1周波数帯阻止回路を構成した
ことを特徴とする請求項3に記載のデュアルバンド増幅器。 - 並列共振周波数が第2の周波数帯にある前記回路及び並列共振周波数が第1の周波数帯にある前記回路を、並列に接続されたインダクタ及びキャパシタにより構成した
ことを特徴とする請求項4又は5に記載のデュアルバンド増幅器。 - 前記第1の増幅回路はその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第2の周波数帯の信号に対して長さが4分の1波長の直列伝送線路及び第2の周波数帯の信号を短絡する回路からなる前記第2周波数帯阻止回路を備え、
前記第2の増幅回路はその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第1の周波数帯の信号に対して長さが4分の1波長の直列伝送線路及び第1の周波数帯の信号を短絡する回路からなる前記第1周波数帯阻止回路を備えた
ことを特徴とする請求項3に記載のデュアルバンド増幅器。 - 前記第1の増幅回路はその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第2の周波数帯の信号に対して長さが4分の1波長の直列伝送線路及び第2の周波数帯の信号を短絡する回路、該短絡する回路の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路、からなる第2周波数帯阻止回路を備え、
前記第2の増幅回路はその信号入力結合部及び出力結合部に、特性インピーダンスが50Ωで第1の周波数帯の信号に対して長さが4分の1波長の直列伝送線路及び第1の周波数帯の信号を短絡する回路、該短絡する回路の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路、からなる第1周波数帯阻止回路を備えた
ことを特徴とする請求項3に記載のデュアルバンド増幅器。 - 前記第1の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路を先端開放の並列スタブにより構成して、
前記第2の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路を先端開放の並列スタブにより構成した
ことを特徴とする請求項7に記載のデュアルバンド増幅器。 - 前記第1の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路により構成し、
前記第2の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路により構成した
ことを特徴とする請求項7に記載のデュアルバンド増幅器。 - 前記第1の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路及び該回路の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路を先端開放あるいは先端短絡の並列スタブにより構成し、
前記第2の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路及び該回路の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路を先端開放あるいは先端短絡の並列スタブにより構成した
ことを特徴とする請求項8に記載のデュアルバンド増幅器。 - 前記第1の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路を先端開放の並列スタブにより構成し、該回路の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路をインダクタにより構成し、
前記第2の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路を先端開放の並列スタブにより構成し、該回路の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路をキャパシタにより構成した
ことを特徴とする請求項8に記載のデュアルバンド増幅器。 - 前記第1の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路により構成して、該回路の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路をインダクタにより構成し、
前記第2の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路により構成して、該回路の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路をキャパシタにより構成した
ことを特徴とする請求項8に記載のデュアルバンド増幅器。 - 前記第1の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第2の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路により構成し、該回路の第1の周波数帯におけるサセプタンス成分を第1の周波数帯において打ち消す回路を先端開放あるいは先端短絡の並列スタブにより構成し、
前記第2の増幅回路の信号入力結合部及び出力結合部に設けられた、前記第1の周波数帯の信号を短絡する回路をインダクタ及びキャパシタの直列共振回路により構成し、該回路の第2の周波数帯におけるサセプタンス成分を第2の周波数帯において打ち消す回路を先端開放あるいは先端短絡の並列スタブにより構成した
ことを特徴とする請求項8に記載のデュアルバンド増幅器。 - 前記第1の増幅回路及び前記第2の増幅回路は入力インピーダンス整合回路及び出力インピーダンス整合回路を有し、
前記第1の増幅回路及び前記第2の増幅回路の前記入力インピーダンス整合回路及び前記出力インピーダンス整合回路がそれぞれの第1の周波数帯及び第2の周波数帯において最適信号入出力特性を実現するトランジスタの信号源インピーダンス及び負荷インピーダンスを備えた
ことを特徴とする請求項3~14の何れか1項に記載のデュアルバンド増幅器。
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