Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B29/00—Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents
  • B24B29/02—Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents designed for particular workpieces
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B24—GRINDING; POLISHING
  • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
  • B24B53/00—Devices or means for dressing or conditioning abrasive surfaces
  • B24B53/017—Devices or means for dressing, cleaning or otherwise conditioning lapping tools
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
  • H01L21/02005—Preparing bulk and homogeneous wafers
  • H01L21/02008—Multistep processes
  • H01L21/0201—Specific process step
  • H01L21/02013—Grinding, lapping
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02587—Structure
  • H01L21/0259—Microstructure
  • H01L21/02595—Microstructure polycrystalline
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/32115—Planarisation
  • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/67005—Apparatus not specifically provided for elsewhere
  • H01L21/67011—Apparatus for manufacture or treatment
  • H01L21/67092—Apparatus for mechanical treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
  • H01L22/10—Measuring as part of the manufacturing process
  • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

• This disclosure relates generally to processing semiconductor wafers and more particularly to systems and methods for processing semiconductor wafers including polishing surfaces of semiconductor wafers.
• Semiconductor wafers are used in the production of semiconductor devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency-SOI (RF-SOI) wafers.
• the semiconductor wafers include a high resistivity substrate that can cause formation of a high conductivity inversion accumulation layer, which hinders the performance of the semiconductor devices.
• a layer such as a polycrystalline silicon layer, is deposited onto a surface of the semiconductor wafer to provide a density charge trap and, thereby, inhibit the formation of the high
• the layer can be deposited onto a surface that forms the interface between the high resistivity substrate and a buried oxide (BOX) to hinder the movement of charges across the interface.
• BOX buried oxide
• the layer tends to form a rough surface on the semiconductor wafer. Therefore, the rough surface of the semiconductor wafer needs to be further processed to have characteristics that meet the strict parameters for production of semiconductor devices, such as IC chips, SOI wafers, and RF-SOI wafers.
• CMP chemical- mechanical polishing
• CMP processes may also significantly change the shape of the semiconductor wafer because portions of the semiconductor wafer are removed in unequal amounts and the thickness of the wafer then has variations.
• portions of the wafer may have areas of material that are thicker or thinner than necessary or optimal. These variations can cause waste and
• a method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer.
• the silicon layer has a
• the silicon layer is polished to smooth the silicon layer such that the
• a method of processing a semiconductor wafer includes depositing a silicon layer on the semiconductor wafer.
• the silicon layer includes an inner surface facing the semiconductor wafer and an outer surface opposite the inner surface.
• the silicon layer has a first thickness defined between the inner surface and the outer surface. The first thickness is substantially uniform throughout the silicon layer.
• the semiconductor wafer is positioned in a polishing apparatus.
• polishing apparatus includes a polishing pad having a pad surface.
• the pad surface defines a center area and an edge area. At least one of the center area and the edge area of the pad surface are dressed based on a wafer profile of the semiconductor wafer.
• the outer surface of the silicon layer is contacted with the pad surface. Slurry is applied to the outer surface of the silicon layer.
• the method further includes rotating the pad while the pad surface is in contact with the outer surface of the silicon layer such that a portion of the silicon layer is removed to provide a smooth surface of the silicon layer.
• a second thickness is defined between the inner surface and the smooth surface. The second thickness is substantially uniform throughout the silicon layer.
• Fig. 1 is a side elevation of one embodiment of a wafer polishing system.
• Fig. 2 is a side elevation of one embodiment of a dressing system positioned for dressing the edge of a polishing pad.
• Fig. 3 is a side elevation of the dressing system shown in Fig. 2, positioned for dressing the center of the polishing pad.
• Fig. 4 is a flow diagram showing one embodiment of a method of processing a semiconductor wafer.
• Fig. 5 is an illustration showing changes in wafer shape due to dressing the edges of a polishing pad.
• Fig. 6 is an illustration showing changes in wafer shape due to dressing the center of a polishing pad.
• Figs. 7A-C are a series of cross-sections showing wafer profile shapes before and after polishing according to this disclosure.
• Fig. 8 is a flow diagram showing one embodiment of a method of polishing a semiconductor wafer.
• Fig. 9 is a chart of the method shown in Fig. 8 comparing polish process time to pressure of the polishing pad and slurry concentration.
• Wafer polishing system 100 includes a polishing pad 102 mounted on a pivotable base 104 and a wafer mounting device 106 having a rotatable head 108 for mounting a semiconductor wafer 110 on polishing pad 102.
• Wafer mounting device 106 holds wafer 110 and brings wafer 110 into contact with polishing pad 102 as both wafer 110 and polishing pad 102 are rotated.
• Polishing pad 102 polishes a surface 112 of wafer 110 through abrasion and with chemicals which may be applied to the surface of polishing pad 102.
• a polishing surface 114 of polishing pad 102 is used to polish multiple wafers over many polishing processes, and may become worn during continued use, which can negatively affect the polished surface of wafer 110.
• a pad dressing system 120, shown in Figs. 2 and 3, of wafer polishing system 100 is constructed for dressing (i.e., abrading and compressing) polishing surface 114 of
• polishing pad 102 to facilitate polishing wafer 110 to have a smooth polished surface and a desired post-polishing shape .
• dressing system 120 includes a dressing member 118.
• Dressing member 118 contacts polishing pad 102 as polishing pad 102 rotates to dress portions of polishing surface 114.
• Dressing member 118 may be diamond impregnated. Suitable dressing members are manufactured by Kinik Company of Taiwan.
• a dressing surface 117 of dressing member 118 may have a diameter between about 30 mm and about 10 mm, for example, about 20 mm.
• a small dressing surface provides for more precise dressing of polishing pad 102 to facilitate polishing pad 102 producing smoother and/or more uniform polished wafers having a desired post -polishing shape .
• polishing surface 114 has a larger diameter than wafer 110. Accordingly, only a functional portion of polishing surface 114 polishes wafer 110.
• the diameter of polishing surface 114 e.g., about 546.1 mm (21.5 in)
• the diameter of wafer 110 e.g., about 200 mm (7.87 in)
• dressing system 120 does not need to dress the entire polishing surface 114 and can be configured to dress only the functional portions of polishing surface 114.
• dressing system 120 is
• dressing member 118 configured for selectively dressing polishing surface 114 by positioning dressing member 118.
• Figs. 2 and 3 show dressing system 120 with dressing member 118 positioned for dressing different portions of polishing surface 114.
• dressing member 118 is positioned for dressing an edge area 122 of polishing pad 102.
• dressing member 118 is positioned for dressing a center area 124 of polishing pad 102.
• a controller 126 controls dressing system 120 to dress polishing pad 102, e.g., controller 126 adjusts the amount of force applied to individual radial zones of polishing pad 102 by dressing member 118 according to the instructions given in a preprogrammed recipe. Controller 126 may also control motion of polishing pad 102 (e.g., the rotatable base of the polishing pad), and the wafer mounting device 113 (e.g., the rotatable head of the mounting device) .
• polishing pad 102 e.g., the rotatable base of the polishing pad
• the wafer mounting device 113 e.g., the rotatable head of the mounting device
• Fig. 4 is a flow chart of an example method 200 of processing semiconductor wafers.
• Method 200 generally includes inspecting 202 surface 112 of wafer 110 to determine the wafer thickness profile, based on the inspection, determine whether to dress 204 one of edge area 122 and center area 124 of polishing pad 102 based on the wafer profile, and polishing 206 wafer 110.
• inspecting 202 may be performed, at least in part, by an operator or may be fully automated.
• the wafer profile may be flat (Fig. 7A) , dished (Fig. 7B) , domed (Fig. 7C) , or any other suitable shape.
• the inspected wafer can be an unpolished wafer used to determine an initial shape that will provide a basis for an intended finish shape of the wafer.
• the inspected wafer can be a polished wafer that is inspected to
• the deviations may indicate a wearing of the pad and/or buildup on the pad, which require corrective conditioning.
• inspecting 202 includes inspecting wafer 110 to determine an initial wafer profile.
• the operator, or controller 126 could classify the wafer shape profile and dress polishing pad 102 accordingly.
• the initial wafer profile is determined to be dish-shaped (Fig. 7B)
• polishing pad 102 can be dressed in edge area 122 such that less of edge area 122 is removed.
• the post -polishing wafer profile will be substantially dish-shaped and, thus, match the initial wafer profile.
• the initial wafer profile is determined to be dome-shaped (Fig. 7C)
• polishing pad 102 can be dressed in the center area 124 such that less of center area 124 is removed.
• the post-polishing wafer profile will be substantially dome-shaped and, thus, match the initial wafer profile.
• a polished wafer will be inspected to determine the post-polishing wafer profile.
• the post -polishing wafer profile is compared to the initial wafer profile to determine variations between the profiles.
• the post -polishing wafer profile can be compared against a stored target wafer profile. Based on the variations between the post-polishing wafer profile and the initial wafer profile or target wafer profile, one of center area 124 and edge area 122 of pad surface 114 can be dressed. If the variations between the post-polishing wafer profile and the initial wafer profile of the target wafer profile indicate wafer 110 is worn too much in center area 124, then polishing pad 102 should be dressed in center area 124. If the variations indicate wafer 110 is worn too much in edge area 122, then polishing pad 102 should be dressed in edge area 122.
• Some embodiments of method 200 further include using a wafer measuring device (not shown) , such as an ADE UltraGage 9700, which measures the thickness of a sampled wafer, to assist in determining the wafer profile either before or after polishing.
• the thickness of the wafer is extrapolated through 360 degrees to obtain an average radial two-dimensional profile of the sampled wafer.
• the sampling rate for obtaining the average radial profile of a previously polished wafer may be about 1 wafer from every 25 wafers polished. It is understood that a greater number of wafers may be polished between samplings, or alternatively, fewer wafers may be polished between samplings. Moreover, the sampling rate may change during the life of the polishing pad.
• wafer 110 is analyzed to determine an appropriate dressing process for polishing pad 102.
• deriving a dressing process based on the sampled wafer is easier and more efficient than deriving a dressing process based on polishing surface 114 of the polishing pad 102.
• the radial profile of a wafer can be readily and accurately measured and the radial profile may be analyzed to determine which areas of the polishing pad need to be dressed and to what extent the specific areas need to be dressed.
• controller 126 measures a polished wafer, analyzes the radial profile of the sampled polished wafer and/or chooses the
• a desired area of the polishing pad is selected to be dressed, e.g., either center area 124 or edge area 122 of polishing pad 102.
• dressing member 118 is positioned appropriately to dress edge area (Fig. 2), center area (Fig. 3), and/or other suitable areas of polishing pad 102.
• Fig. 5 and Fig. 6 are illustrations showing the change in wafer shape due to dressing either edge area 122 or center area 124 of polishing pad 102.
• edge area 122 of polishing pad 102 can be dressed when an operator, or controller 126 for an automated process, determines less edge area removal is desired, e.g., the inspected wafer indicates the polishing pad is removing too much of the edge area of the wafer.
• Edge area wafer 110 reaches when wafer 110 is oscillated during polishing. Accordingly, the size of edge area 122 will depend on the size of wafers 110 to be polished and the overall size of polishing pad 102. In the example
• edge area 122 extends radially between about 2.5 cm (1 inch) and about 5 cm (2 inches) from the outer edge of polishing pad 102.
• center area 124 of polishing pad 102 can be dressed when an operator, or controller 126 for an automated process, determines less center area removal is desired, e.g., the inspected wafer indicates the polishing pad is removing too much of the center area of the wafer.
• Center area 124 of polishing pad 102 contacts the middle portion of wafer 110 when wafer 110 is oscillated during polishing. Accordingly, the size of center area 124 will depend on the size of wafer 110 and the overall size of polishing pad 102. In the example embodiment, center area 124 is spaced radially inward from the outer edge of polishing pad 102 between about 15 cm (6 inches) and about 20 cm (8 inches) .
• polishing surface 114 based on the wafer profiles is an accurate way of producing polished wafers with
• shape match polishing generally includes polishing a silicon layer 128 deposited on wafer 110 to smooth wafer 110 such that silicon layer 128 is removed substantially uniformly across wafer 110, i.e., the thickness of silicon layer 128 is removed substantially uniformly throughout wafer 110. Since silicon layer 128 is deposited on wafer 110 with a substantially uniform thickness, silicon layer 128 will still have a substantially uniform thickness after shape match
• wafer 110 will have the same shape after polishing as it did before polishing.
• wafer 110 will have a reduced thickness and enhanced surface characteristics, such as smoothness, after polishing.
• shape match polishing reduces waste during semiconductor wafer processing. For example, in some embodiments, less material will be removed during shape match polishing than during typical semiconductor wafer processing. In example embodiments, between about 0.2 micrometers and about 2 micrometers of the thickness of the material is removed during shape match polishing.
• Figs. 7A-C illustrates some semiconductor wafer shapes before and after shape match polishing.
• Fig. 7A shows a flat-shaped wafer 300, which is substantially level across a top surface 302.
• Fig. 7B shows a dish- shaped wafer 400, which has a greater thickness adjacent its periphery 402 and gradually decreases in thickness radially towards its center 404.
• a surface 406 of dish-shaped wafer 400 is generally concave.
• Fig. 7C shows a dome-shaped wafer 500, which is thinner adjacent its periphery 502 and gradually increases in thickness at its center 504.
• a surface 506 of dome-shaped wafer 500 is generally convex.
• Wafers 300, 400, 500 each include a silicon layer 304, 408, 508, respectively, which covers
• silicon layers 304, 408, 508 have a thickness of between about 1 micrometers and about 5 micrometers, as an example. In other embodiments, silicon layers 304, 408, 508 may have any suitable
• wafers 300, 400, 500 and silicon layers 304, 408, 508 change during shape match polishing, other characteristics such as flatness remain substantially constant. Accordingly, wafers 300, 400, 500 have a post -polishing shape that is substantially similar to their initial shape.
• silicon layers 304, 408, 508, on wafers 300, 400, 500 are polycrystalline silicon layers, which are primarily used as electron charge traps .
• Fig. 8 is a flow chart of an example method 600 of polishing semiconductor wafers. Method 600
• the method generally includes contacting 602 wafer 110 with polishing pad 102, applying 604 a first slurry to wafer 110, rotating 606 polishing pad 102 in contact with wafer 110, and pressing 608 polishing pad 102 against wafer 110 at a first pressure.
• the method also includes pressing 610 polishing pad 102 against wafer 110 at a second pressure and applying 612 a second slurry to wafer 110 as polishing pad 102 is pressed against wafer 110 at the second pressure.
• the method further includes pressing 614 polishing pad 102 against wafer 110 at a third pressure and applying 616 water and diluted slurry to wafer 110 as polishing pad 102 is pressed against wafer 110 at the third pressure.
• Fig. 9 is a diagram of method 600 showing polish process time compared to pressure of polishing pad 102 and slurry concentration. As shown in Fig. 9, during the initial stage, polishing pad 102 is pressed against wafer 110 at the first pressure between about 0 psi and about 5 psi. In the second stage, polishing pad 102 is pressed against wafer 110 at the second pressure between about 5 psi and about 15 psi. In the third stage,
• polishing pad 102 is pressed against wafer 110 at the third pressure between about 0 psi and about 5 psi.
• the first pressure is approximately 1 psi
• the second pressure is approximately 7 psi
• the third pressure is
• polishing pad 102 may be pressed against wafer 110 at any suitable pressures .
• Polishing pad 102 can be pressed against wafer 110 for any suitable amounts of time.
• polishing pad 102 is pressed against wafer 110 at the first pressure for a time period between about 5 and about 20 seconds.
• Polishing pad 102 is pressed against wafer 110 at the second pressure for a time period between about 100 and about 300 seconds.
• Polishing pad 102 is pressed against wafer 110 at the third pressure for a time period between about 10 and about 100 seconds.
• the first slurry containing abrasive particles is applied between polishing pad 102 and wafer 110 to help polish surface 112 of wafer 110.
• the first slurry contains particles having diameters between about 100 nanometers and about 160 nanometers.
• the first slurry includes a strong base agent, e.g., without limitation, potassium hydroxide and sodium hydroxide.
• a strong base agent e.g., potassium hydroxide and sodium hydroxide.
• Conventional slurries such as Nalco DVSTS029 manufactured by Nalco Company of Naperville, IL, are suitable for use in method 600.
• polishing pad 102 When polishing pad 102 is pressed against wafer 110 at the second pressure, the polishing pad works the slurry against surface 112 of wafer 110 to concurrently and uniformly remove material from surface 112 of wafer 110 and help improve the overall smoothness of wafer 110.
• silicon is removed and some minor damage is created on surface 112 by the abrasive action of the slurry.
• the intermediate polishing e.g., without limitation, potassium hydroxide and sodium hydroxide.
• polishing operation preferably removes less than about 1 micrometer of material from surface 112 of wafer 110.
• the minor damage created by the polishing slurry on surface 112 is subsequently removed in final polishing.
• the second slurry containing abrasive particles is applied between polishing pad 102 and wafer 110 to help further polish surface 112 of wafer 110.
• the second slurry contains particles having diameters between about 10 nanometers and about 100 nanometers. More preferably, the particles have diameters between about 20 nanometers and about 80
• the second slurry applied to the second wafer includes a weak base agent, e.g., without limitation, ammonium hydroxide, tetramethylammonium hydroxide, and amine.
• a weak base agent e.g., without limitation, ammonium hydroxide, tetramethylammonium hydroxide, and amine.
• An ammonia stabilized colloidal silica slurry is Glanzox 3900, which is commercially available from Fuj imi Incorporated of Aichi Pref. 452, Japan. Glanzox 3900 has silica content of from about 8 to about 10% and a particle size of from about 0.025 to about 0.035 micrometers.
• the pad is pressed against wafer 110 at the third pressure and water is applied to wafer 110 to provide a final "touch” or “flash” polishing operation to improve sub-micrometer roughness and
• the final polishing also maintains the wafer flatness while imparting a smooth, specular finish to surface 112 of wafer 110 typical for polished wafers and desired by many device manufactures.
• This type of final polish generally removes less than about 1 micrometer of material, preferably between about 0.25 micrometers and about 0.5 micrometers of material from surface 112 of wafer 110.
• the water dilutes the slurry as the water is added. In some embodiments, the slurry is diluted to about one part silica slurry to about 10 parts deionized water.
• Embodiments of the methods and systems described may more efficiently produce semiconductor wafers having improved surface characteristics compared to prior methods and systems.
• the systems and methods described provide an improved polishing system which reduces waste and increases efficiency during wafer polishing.
• the embodiments described provide for polishing a wafer such that an initial wafer profile matches a post-polishing waver profile. The embodiments reduce the material removed during polishing and maintain uniform thickness of layers in the polished wafer .
• the polishing pad is selectively dressed in its center and edge areas. As such, the impacts from variations on the polishing pad as the polishing pad wears and acquires build-up are reduced. Also, selectively dressing the edge area or center area of the polishing pad facilitates polishing a semiconductor wafer to a consistent wafer profile shape.
• the method can reduce the poly grain boundary as compared to a conventional method. For example, when viewed under an atomic force microscope at 2x2 micron view, the poly grain boundary is less
• grain boundary has a number of benefits, including better surface roughness, less re-generated roughness in downstream processes and improved metrology.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Mechanical Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
• Grinding-Machine Dressing And Accessory Apparatuses (AREA)
• Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)

Priority Applications (7)

Applications Claiming Priority (2)

Related Child Applications (2)

Publications (2)

Family

ID=56108731

Family Applications (1)

Country Status (6)

Families Citing this family (3)

Citations (3)

Family Cites Families (25)

• 2016
  • 2016-05-26 US US15/577,515 patent/US10699908B2/en active Active
  • 2016-05-26 EP EP19185015.5A patent/EP3576136A1/en active Pending
  • 2016-05-26 JP JP2017559654A patent/JP6613470B2/ja active Active
  • 2016-05-26 WO PCT/US2016/034428 patent/WO2016196216A1/en active Application Filing
  • 2016-05-26 CN CN201680030931.3A patent/CN107851579B/zh active Active
  • 2016-05-26 CN CN202111316707.XA patent/CN114102269B/zh active Active
  • 2016-05-26 EP EP16727609.6A patent/EP3304580B1/en active Active
  • 2016-05-27 TW TW105116794A patent/TWI714591B/zh active
  • 2016-05-27 TW TW109141370A patent/TWI742938B/zh active
• 2019
  • 2019-10-10 JP JP2019186978A patent/JP6955537B2/ja active Active
• 2020
  • 2020-06-15 US US16/946,283 patent/US11355346B2/en active Active

Patent Citations (3)

Also Published As

Similar Documents

Legal Events