JP6613470B2 - 多結晶仕上げを有する半導体ウエハを処理する方法 - Google Patents
多結晶仕上げを有する半導体ウエハを処理する方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 44
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 238000012545 processing Methods 0.000 title claims description 11
- 238000005498 polishing Methods 0.000 claims description 158
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 239000002002 slurry Substances 0.000 claims description 21
- 239000002245 particle Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 188
- 230000008569 process Effects 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000007517 polishing process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
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- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- -1 without limitation Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 239000008119 colloidal silica Substances 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000011143 downstream manufacturing Methods 0.000 description 1
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- 230000003746 surface roughness Effects 0.000 description 1
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Images
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B29/00—Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents
- B24B29/02—Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents designed for particular workpieces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B53/00—Devices or means for dressing or conditioning abrasive surfaces
- B24B53/017—Devices or means for dressing, cleaning or otherwise conditioning lapping tools
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Grinding-Machine Dressing And Accessory Apparatuses (AREA)
- Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)
Description
本願は、米国仮特許出願(第62/168247号、2015年5月29日出願)の優先権を主張しており、この開示は参照により全体としてここに組み込まれる。
Claims (5)
- シリコン層を半導体ウエハに堆積するステップであって、シリコン層は、半導体ウエハに面する内側表面と、内側表面とは反対の外側表面とを含み、シリコン層は、内側表面と外側表面との間に定義される第1厚さを有し、第1厚さは、シリコン層全体に渡って実質的に均等である、ステップと、
シリコン層の外側表面をパッド表面と接触させる前に、半導体ウエハを検査して、初期ウエハプロファイルを判断するステップと、
初期ウエハプロファイルの形状を分類するステップと、
半導体ウエハを研磨装置に位置決めするステップであって、研磨装置は、パッド表面を有する研磨パッドを含み、パッド表面は、中心エリアおよびエッジエリアを定義する、ステップと、
もし半導体ウエハの初期ウエハプロファイルがドーム形状として分類される場合、パッド表面の中心エリアをドレッシングし、もし半導体ウエハの初期ウエハプロファイルが皿形状として分類される場合、パッド表面のエッジエリアをドレッシングするステップと、
シリコン層の外側表面をパッド表面と接触させるステップと、
スラリーをシリコン層の外側表面に塗布するステップと、
パッド表面がシリコン層の外側表面に接触しつつ、研磨パッドを回転させるステップであって、その結果、シリコン層の一部が除去され、シリコン層の滑らかな表面を提供し、第2厚さが、内側表面と滑らかな表面との間に定義され、第2厚さは、シリコン層全体に渡って実質的に均等である、ステップと、
シリコン層の一部の除去後、半導体ウエハを検査して、研磨後ウエハプロファイルを判断するステップと、
初期ウエハプロファイルを研磨後ウエハプロファイルと比較して、プロファイル間の変動を判断するステップと、
初期ウエハプロファイルと研磨後ウエハプロファイルとの間の変動に基づいて、パッド表面の中心エリアおよびエッジエリアの一方をドレッシングするステップとを含む、
半導体ウエハを処理する方法。 - エッジエリアは、ドレッシングされ、
パッド表面は、円形形状を有し、
エッジエリアは、研磨パッドの外側エッジから2.5cmと5cmの間で放射状に延びている、請求項1記載の方法。 - 中心エリアは、ドレッシングされ、
パッド表面は、円形形状を有し、
中心エリアは、研磨パッドの外側エッジから15cmと20cmの間に内向きに放射状に間隔を空けている、請求項1または2記載の方法。 - シリコン層は、多結晶シリコン層であり、
該層は、研磨後に減少した粗さを有し、
多結晶粒子境界は、研磨によって減少している、請求項1〜3のいずれかに記載の方法。 - スラリーは、研磨粒子および塩基を含む、請求項1〜4のいずれかに記載の方法。
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US201562168247P | 2015-05-29 | 2015-05-29 | |
US62/168,247 | 2015-05-29 | ||
PCT/US2016/034428 WO2016196216A1 (en) | 2015-05-29 | 2016-05-26 | Methods for processing semiconductor wafers having a polycrystalline finish |
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EP (2) | EP3576136A1 (ja) |
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JP6732382B2 (ja) * | 2016-10-12 | 2020-07-29 | 株式会社ディスコ | 加工装置及び被加工物の加工方法 |
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US20150107619A1 (en) * | 2013-10-22 | 2015-04-23 | Taiwan Semiconductor Manufacturing Company Limited | Wafer particle removal |
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US20180151384A1 (en) | 2018-05-31 |
TW202113960A (zh) | 2021-04-01 |
CN107851579B (zh) | 2021-11-09 |
WO2016196216A8 (en) | 2017-12-14 |
US10699908B2 (en) | 2020-06-30 |
TW201705254A (zh) | 2017-02-01 |
TWI714591B (zh) | 2021-01-01 |
EP3304580A1 (en) | 2018-04-11 |
CN114102269A (zh) | 2022-03-01 |
US11355346B2 (en) | 2022-06-07 |
EP3304580B1 (en) | 2019-07-10 |
CN107851579A (zh) | 2018-03-27 |
TWI742938B (zh) | 2021-10-11 |
US20200312671A1 (en) | 2020-10-01 |
WO2016196216A1 (en) | 2016-12-08 |
JP2018518050A (ja) | 2018-07-05 |
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