WO2016194804A1 - アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 - Google Patents
アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 Download PDFInfo
- Publication number
- WO2016194804A1 WO2016194804A1 PCT/JP2016/065696 JP2016065696W WO2016194804A1 WO 2016194804 A1 WO2016194804 A1 WO 2016194804A1 JP 2016065696 W JP2016065696 W JP 2016065696W WO 2016194804 A1 WO2016194804 A1 WO 2016194804A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- active matrix
- gate
- matrix substrate
- pixel electrode
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims description 191
- 239000011159 matrix material Substances 0.000 title claims description 141
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 94
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 238000000034 method Methods 0.000 title description 38
- 239000010410 layer Substances 0.000 claims description 143
- 239000010408 film Substances 0.000 claims description 128
- 239000004065 semiconductor Substances 0.000 claims description 61
- 239000004020 conductor Substances 0.000 claims description 48
- 239000010409 thin film Substances 0.000 claims description 43
- 230000001681 protective effect Effects 0.000 claims description 24
- 238000000059 patterning Methods 0.000 claims description 11
- 230000003071 parasitic effect Effects 0.000 abstract description 32
- 230000008859 change Effects 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 24
- 238000010586 diagram Methods 0.000 description 24
- 229910004205 SiNX Inorganic materials 0.000 description 23
- 230000005684 electric field Effects 0.000 description 22
- 230000004048 modification Effects 0.000 description 20
- 238000012986 modification Methods 0.000 description 20
- 230000008569 process Effects 0.000 description 14
- 230000007547 defect Effects 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 238000005530 etching Methods 0.000 description 11
- 230000007423 decrease Effects 0.000 description 8
- 239000010936 titanium Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- -1 Mo Al Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Definitions
- the present invention relates to a display device, and more particularly to an active matrix substrate, a liquid crystal panel including the same, and a method for manufacturing the active matrix substrate.
- a liquid crystal panel included in a liquid crystal display device has a structure in which an active matrix substrate and a counter substrate are bonded to each other, and a liquid crystal layer is provided between two substrates.
- a plurality of gate lines, a plurality of data lines, a plurality of pixel circuits including thin film transistors (hereinafter referred to as TFTs) and pixel electrodes are formed.
- a vertical electric field method and a horizontal electric field method are known as methods for applying an electric field to a liquid crystal layer of a liquid crystal panel.
- a substantially vertical electric field is applied to a liquid crystal layer using a pixel electrode and a common electrode formed on a counter substrate.
- a horizontal electric field type liquid crystal panel a common electrode is formed on an active matrix substrate together with a pixel electrode, and a substantially horizontal electric field is applied to the liquid crystal layer using the pixel electrode and the common electrode.
- a horizontal electric field type liquid crystal panel has an advantage that a viewing angle is wider than that of a vertical electric field type liquid crystal panel.
- an IPS (In-Plane Switching) mode and an FFS (Fringe Field Switching) mode are known.
- the pixel electrode and the common electrode are each formed in a comb-like shape and are arranged so as not to overlap in a plan view.
- a slit is formed in one of the common electrode and the pixel electrode, and the pixel electrode and the common electrode are disposed so as to overlap with each other through a protective insulating film in plan view.
- the FFS mode liquid crystal panel has an advantage that the aperture ratio is higher than that of the IPS mode liquid crystal panel.
- Patent Documents 1 and 2 A horizontal electric field type liquid crystal panel is described in Patent Documents 1 and 2, for example.
- a common electrode is formed over almost the entire display area (excluding slits and the like).
- the common electrode is formed above the data line via an insulating film.
- the pixel electrode and the drain electrode of the TFT are directly connected without a contact hole formed in the insulating film.
- Patent Documents 1 and 2 also describe a method for manufacturing an active matrix substrate including a step of forming a channel region of a TFT while forming a pixel electrode.
- FIG. 20 is a layout diagram described in FIG.
- FIG. 21 is a layout diagram described in FIG. 20 and FIG. 21, the lower left oblique line portion represents the gate layer pattern, the lower right oblique line portion represents the source layer pattern, and the thick line Ex represents the end of the pixel electrode.
- the description method of FIG. 20 and FIG. 21 is changed from the original drawing.
- the data line 92 has a portion functioning as a source electrode (a portion protruding rightward in the drawing).
- a TFT is formed by providing the drain electrode 93 or the like facing the source electrode.
- the pixel electrode 94 has an extended portion (portion protruding downward in the drawing), and the extended portion of the pixel electrode 94 overlaps the gate line 91.
- the data line 96 has a portion functioning as a source electrode (a portion protruding rightward in the drawing).
- a TFT is formed by providing the drain electrode 97 or the like facing the source electrode.
- the pixel electrode 98 has an extended portion (a portion protruding downward in the drawing), and the extended portion of the pixel electrode 98 overlaps the gate line 95.
- the potential of the pixel electrode decreases by the amount of the pull-in voltage due to the potential of the gate line (TFT gate electrode) changing from a high level to a low level. .
- the pull-in voltage increases as the parasitic capacitance Cgd between the gate and drain of the TFT increases.
- the parasitic capacitance Cgd between the gate and the drain of the TFT increases as the area of the portion where the gate line 91 and the extended portion of the pixel electrode 94 overlap is larger. This is the same in FIG.
- pattern shift When a liquid crystal panel is manufactured, a phenomenon (hereinafter referred to as pattern shift) may occur in which the pattern position of a certain layer is shifted from the correct position (or the pattern position of another layer).
- the pattern shift can be decomposed into a pattern shift in the gate line extending direction (horizontal direction in the drawing) and a pattern shift in the data line extending direction (vertical direction in the drawing).
- the pattern shift in the data line extending direction direction orthogonal to the gate line.
- the pull-in voltage fluctuates, it may not be possible to display with the correct brightness, or flicker may occur. These display defects can be suppressed by a method of adjusting the potential of the common electrode, a method of correcting a potential written to the pixel electrode in advance, or the like. However, it may be difficult to individually perform the adjustment and correction described above for each pixel circuit. For this reason, if the amount of fluctuation of the pull-in voltage differs between the pixel circuits, the display quality of the liquid crystal display device deteriorates.
- a deviation occurs in the exposed portion between a plurality of exposures, and a different pattern deviation occurs for each block. May occur.
- block-like display unevenness occurs on the display screen of the liquid crystal display device.
- the scan exposure method is used in the process of forming the pixel electrode, a slight shift may occur in the exposed portion as the stage of the exposure apparatus moves, and a different pattern shift may occur for each line.
- strip-shaped display unevenness and flicker occur on the display screen of the liquid crystal display device.
- the conventional liquid crystal display device has a problem that the display quality is deteriorated due to the variation in the parasitic capacitance between the gate and the drain of the TFT in the pixel circuit.
- the present invention provides an active matrix substrate, a liquid crystal display device, and a method for manufacturing the active matrix substrate, which prevent deterioration of display quality due to variations in parasitic capacitance between the gate and drain of TFTs in a pixel circuit. With the goal.
- a first aspect of the present invention is an active matrix substrate, A plurality of gate lines extending in a first direction; A plurality of data lines extending in the second direction; A plurality of pixel circuits arranged corresponding to the intersections of the gate lines and the data lines, each including a thin film transistor and a pixel electrode; A protective insulating film formed in an upper layer than the gate line, the data line, the thin film transistor, and the pixel electrode; A common electrode formed in an upper layer of the protective insulating film,
- the thin film transistor includes a gate electrode formed integrally with the gate line, a source electrode formed integrally with the data line, and a drain electrode directly connected to the pixel electrode and having a portion overlapping the gate electrode.
- the pixel electrode has a main body formed on the first side of the gate line, and an extension extending in the second direction and covering an overlapping portion of the gate electrode and the drain electrode,
- the drain electrode is not formed on the second side of the gate line,
- the extended portion of the pixel electrode is also formed on the second side of the gate line.
- the drain electrode is formed inside a region where the gate line and the gate electrode are formed.
- the semiconductor layer of the thin film transistor is formed in a region where the gate line and the gate electrode are formed.
- the gate line penetrates through the pixel circuit;
- the pixel electrode further includes a second body portion formed on the second side of the gate line, The extended portion of the pixel electrode connects a main body portion of the pixel electrode and a second main body portion.
- the common electrode has one or more slits in a region corresponding to the main body and the second main body, At least one of the slits is not formed on the gate line.
- the thin film transistors are alternately formed on both sides of the data line.
- the common electrode has one or more slits corresponding to the pixel circuit.
- a semiconductor layer is formed below the data line, the source electrode, and the drain electrode.
- an active matrix substrate according to any one of the first to eighth aspects of the present invention, A liquid crystal panel comprising a counter substrate facing the active matrix substrate.
- a tenth aspect of the present invention is a method of manufacturing an active matrix substrate including a plurality of pixel circuits each having a thin film transistor and a pixel electrode, Forming a plurality of gate lines extending in a first direction, and forming a gate electrode of the thin film transistor integrally with the gate lines; A semiconductor layer forming step of forming a semiconductor layer of the thin film transistor; A source layer forming step of forming a main conductor portion of a plurality of data lines extending in a second direction and forming a conductor portion that is a source of a drain electrode and a source electrode of the thin film transistor integrally with the main conductor portion; A pixel electrode layer forming step of forming the drain electrode and the source electrode of the thin film transistor by forming the pixel electrode and a sub conductor portion of the data line and patterning the conductor portion; Forming a protective insulating film on the pixel electrode; and Forming a common electrode on an upper layer of the protective insulating film, In the source layer forming
- An eleventh aspect of the present invention is the tenth aspect of the present invention.
- the semiconductor layer forming step is characterized by forming a semiconductor film and patterning the semiconductor film.
- a twelfth aspect of the present invention is the tenth aspect of the present invention.
- the semiconductor layer forming step forms a semiconductor film, In the source layer forming step, the main conductor portion and the conductor portion are formed, and the semiconductor film is patterned.
- the extended portion of the pixel electrode is also formed on the second side of the gate line (the side opposite to the side where the main body of the pixel electrode is disposed), whereby the pixel electrode and the drain electrode are formed.
- the area of the portion where the gate line and the extended portion of the pixel electrode overlap does not change.
- the parasitic capacitance between the gate and the drain of the thin film transistor is substantially equal, and the pull-in voltage is also substantially equal. Accordingly, deterioration in display quality due to variations in parasitic capacitance between the gate and drain of the thin film transistor can be prevented.
- the drain electrode is not formed on the second side of the gate line, it is possible to prevent defects in rubbing treatment, fluctuations in the aperture ratio, and display defects due to the influence of backlight light.
- the drain electrode and the opening of the black matrix formed in the counter substrate are prevented from overlapping, A decrease in the aperture ratio can be prevented. Further, display defects due to the influence of backlight light can be more effectively prevented.
- display defects due to the influence of backlight light can be prevented by forming the semiconductor layer inside the region where the gate line and the gate electrode are formed.
- the magnitude of the parasitic capacitance generated between the gate line and the pixel electrode can be kept substantially constant even when the position of the pixel electrode is shifted to some extent in the second direction.
- the fifth aspect of the present invention in order to widen the viewing angle of the liquid crystal panel including the active matrix substrate by providing a slit in the common electrode in the region corresponding to the main body portion and the second main body portion of the pixel electrode.
- the transverse electric field can be generated. Further, by not providing a slit on the gate line, it is possible to generate a lateral electric field while preventing an electric field due to a voltage applied to the gate line from affecting the alignment of the liquid crystal.
- the sixth aspect of the present invention can be suitably used for a display device that performs dot inversion driving without increasing the load on the data line.
- the seventh aspect of the present invention it is possible to generate a lateral electric field for widening the viewing angle of the liquid crystal panel including the active matrix substrate by providing a slit in the common electrode.
- an active matrix substrate having a semiconductor layer below the source layer pattern can be easily manufactured.
- the ninth aspect of the present invention it is possible to configure a liquid crystal panel that prevents display quality from being deteriorated due to variations in parasitic capacitance between the gate and drain of a thin film transistor.
- the tenth and eleventh aspects of the present invention it is possible to manufacture an active matrix substrate that prevents a reduction in display quality due to variations in parasitic capacitance between the gate and drain of a thin film transistor.
- the drain electrode of the thin film transistor in the pixel electrode layer forming step, the drain electrode can be prevented from becoming larger than necessary, and an increase in parasitic capacitance between the gate and the drain of the thin film transistor can be suppressed.
- an active matrix substrate can be manufactured using a small number of photomasks by patterning the semiconductor layer in the source layer forming step.
- FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device including an active matrix substrate according to a first embodiment of the present invention.
- FIG. 2 is a plan view of the active matrix substrate shown in FIG. 1.
- FIG. 2 is a layout diagram of the liquid crystal panel shown in FIG. 1. It is a figure which shows patterns other than the common electrode of the active matrix substrate shown in FIG. It is a figure which shows the pattern of the common electrode of the active matrix substrate shown in FIG. It is a figure which shows the pattern of the opposing board
- FIG. 5 is an enlarged view of FIG. 4. It is a figure which shows the position of the gate line shown in FIG. 7, a drain electrode, and a pixel electrode.
- FIG. 9A It is a continuation figure of FIG. 9B. It is a continuation figure of FIG. 9C. It is a continuation figure of FIG. 9D. It is a continuation figure of FIG. 9E. It is a continuation figure of FIG. 9F. It is a continuation figure of FIG. 9G. It is a continuation figure of FIG. 9H. It is sectional drawing of the liquid crystal panel shown in FIG. It is a layout diagram of a liquid crystal panel provided with an active matrix substrate according to a comparative example.
- FIG. 10 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a first modification of the first embodiment.
- FIG. 10 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a first modification of the first embodiment.
- FIG. 10 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a second modification example of the first embodiment.
- FIG. 10 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a third modification example of the first embodiment. It is an enlarged view of FIG.
- FIG. 10 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a fourth modification example of the first embodiment.
- FIG. 6 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a second embodiment of the present invention. It is a figure which shows the manufacturing method of the active matrix substrate which concerns on 2nd Embodiment. It is a continuation figure of FIG. 18A. It is a continuation figure of FIG. 18B. It is a continuation figure of FIG. 18C.
- FIG. 1 is a block diagram showing a configuration of a liquid crystal display device including an active matrix substrate according to the first embodiment of the present invention.
- a liquid crystal display device 1 shown in FIG. 1 includes a liquid crystal panel 2, a display control circuit 3, a gate line driving circuit 4, a data line driving circuit 5, and a backlight 6.
- m and n are integers of 2 or more, i is an integer of 1 to m, and j is an integer of 1 to n.
- the liquid crystal panel 2 has a structure in which the active matrix substrate 10 and the counter substrate 40 are bonded together and a liquid crystal layer is provided between the two substrates.
- a black matrix (not shown) or the like is formed on the counter substrate 40.
- m gate lines G1 to Gm, n data lines S1 to Sn, (m ⁇ n) pixel circuits 20, a common electrode 30 (dot pattern portion), and the like are formed on the active matrix substrate 10.
- the gate line driving circuit 4 is integrally formed with the pixel circuit 20 and the like, and a semiconductor chip that functions as the data line driving circuit 5 is mounted.
- FIG. 1 schematically shows the configuration of the liquid crystal display device 1, and the shape of the elements described in FIG. 1 is not accurate.
- gate lines G1 to Gm extend in the row direction and are arranged in parallel to each other.
- the data lines S1 to Sn extend in the column direction and are arranged in parallel to each other.
- the gate lines G1 to Gm and the data lines S1 to Sn intersect at (m ⁇ n) locations.
- the (m ⁇ n) pixel circuits 20 are two-dimensionally arranged corresponding to the intersections of the gate lines G1 to Gm and the data lines S1 to Sn.
- the pixel circuit 20 includes an N-channel TFT 21 and a pixel electrode 22.
- the gate electrode of the TFT 21 included in the pixel circuit 20 in the i-th row and j-th column is connected to the gate line Gi
- the source electrode is connected to the data line Sj
- the drain electrode is connected to the pixel electrode 22.
- a protective insulating film (not shown) is formed above the gate lines G 1 to Gm, the data lines S 1 to Sn, the TFT 21, and the pixel electrode 22.
- the common electrode 30 is formed in the upper layer of the protective insulating film.
- the pixel electrode 22 and the common electrode 30 face each other with a protective insulating film interposed therebetween.
- the backlight 6 is disposed on the back side of the liquid crystal panel 2 and irradiates the back surface of the liquid crystal panel 2 with light.
- a polarizing plate (not shown) is disposed on the surface of the active matrix substrate 10 opposite to the liquid crystal layer and on the surface of the counter substrate 40 opposite to the liquid crystal layer.
- the display control circuit 3 outputs a control signal C1 to the gate line driving circuit 4, and outputs a control signal C2 and a data signal D1 to the data line driving circuit 5.
- the gate line driving circuit 4 drives the gate lines G1 to Gm based on the control signal C1.
- the data line driving circuit 5 drives the data lines S1 to Sn based on the control signal C2 and the data signal D1. More specifically, the gate line driving circuit 4 selects one gate line from the gate lines G1 to Gm in each horizontal period (line period) and applies a high level voltage to the selected gate line.
- the data line driving circuit 5 applies n data voltages corresponding to the data signal D1 to the data lines S1 to Sn in each horizontal period. As a result, n pixel circuits 20 are selected within one horizontal period, and n data voltages are respectively written to the selected n pixel circuits 20.
- FIG. 2 is a plan view of the active matrix substrate 10. As shown in FIG. 2, the active matrix substrate 10 is divided into a facing region 11 facing the facing substrate 40 and a non-facing region 12 not facing the facing substrate 40. A display area 13 for arranging the pixel circuit 20 is set in the counter area 11. A portion obtained by removing the display area 13 from the facing area 11 is referred to as a frame area 14. The frame region 14 is shielded from light by a black matrix (not shown) formed on the counter substrate 40.
- m gate lines 23, n data lines 24, and (m ⁇ n) pixel circuits are formed in the display area 13.
- the m gate lines 23 extend in the row direction in the display region 13.
- the n data lines 24 extend in the column direction in the display area 13.
- the gate line 23 and the data line 24 are formed in different wiring layers.
- the (m ⁇ n) pixel circuits are two-dimensionally arranged in the display area 13.
- the gate line driving circuit 4 is formed in the frame region 14 in two parts. More specifically, a part of the gate line driving circuit 4 (hereinafter referred to as the first gate line driving unit 4a) is arranged along one side (left side in FIG. 2) of the display region 13 in the column direction. The remaining four (hereinafter referred to as second gate line driving unit 4b) are arranged along the other side of the display region 13 in the column direction (the right side in FIG. 2). One end (left end in FIG. 2) of the odd-numbered gate line 23 is connected to the first gate line driving unit 4a, and one end (right end in FIG. 2) of the even-numbered gate line 23 is connected to the second gate line driving unit 4b. Is done. Based on the control signal C1 output from the display control circuit 3, the first gate line driving unit 4a drives the odd-numbered gate lines 23, and the second gate line driving unit 4b drives the even-numbered gate lines 23.
- the first gate line driving unit 4a drives the odd-numbered gate lines 23, and the second gate line driving unit 4b drives the
- the mounting area 15 for mounting the data line driving circuit 5 is set in the non-facing area 12.
- a plurality of external terminals 16 for connection to an external circuit are formed in a portion other than the mounting area 15 of the non-facing area 12.
- the external terminal 16 is connected to the gate line driving circuit 4 via the wiring 17.
- FIG. 3 is a layout diagram of the liquid crystal panel 2.
- the pattern of the active matrix substrate 10 and the pattern of the counter substrate 40 are overlapped.
- FIG. 3 will be described by dividing it into three drawings.
- FIG. 4 is a diagram showing patterns other than the common electrode 30 of the active matrix substrate 10.
- FIG. 5 is a diagram showing a pattern of the common electrode 30 of the active matrix substrate 10.
- FIG. 6 is a diagram showing a pattern of the counter substrate 40.
- the pattern shown in FIG. 4 is indicated by a thin line
- the pattern shown in FIG. 6 is indicated by a thick line
- the pattern shown in FIG. 5 is indicated by an intermediate thickness line. Yes.
- the gate line 23 (lower left oblique line) extends in the row direction.
- the data line 24 (lower right oblique line) extends in the column direction while being refracted near the intersection with the gate line 23.
- the gate line 23 has a portion functioning as a gate electrode of the TFT 21 (a portion protruding upward in the drawing) near the intersection of the gate line 23 and the data line 24.
- the data line 24 has a portion functioning as a source electrode of the TFT 21 (a portion protruding rightward in the drawing) near the intersection of the gate line 23 and the data line 24.
- a drain electrode 25 and a semiconductor layer 26 are formed in the vicinity of the intersection of the gate line 23 and the data line 24.
- the TFT 21 is formed corresponding to the intersection of the gate line 23 and the data line 24.
- a pixel electrode 22 is formed in a region partitioned by the gate line 23 and the data line 24.
- the drain electrode 25 is directly connected to the pixel electrode 22 without passing through a contact hole formed in the insulating film.
- the active matrix substrate 10 includes a plurality of pixel circuits 20 arranged corresponding to the intersections of the gate lines 23 and the data lines 24.
- the common electrode 30 is an upper layer of the TFT 21, the pixel electrode 22, the gate line 23, the data line 24, the drain electrode 25, and a protective insulating film formed in an upper layer than the semiconductor layer 26 (that is, a side closer to the liquid crystal layer). Formed. As shown in FIG. 5, the common electrode 30 is formed so as to cover the entire surface of the display region 13 except for the arrangement positions of the slits 31 and the notches 32. The common electrode 30 has a plurality of slits 31 corresponding to the pixel electrode 22 in order to generate a horizontal electric field applied to the liquid crystal layer together with the pixel electrode 22. In FIG. 5, the common electrode 30 has two slits 31 corresponding to one pixel electrode 22.
- the width of the slit 31 is 2 to 4 ⁇ m, for example, and the interval between the two slits 31 is 2 to 4 ⁇ m, for example.
- the common electrode 30 has a notch 32 corresponding to the TFT 21. By forming the notch 32 in the common electrode 30, it is possible to prevent the common electrode 30 from affecting the operation of the TFT 21.
- the counter substrate 40 is disposed to face the active matrix substrate 10. As shown in FIG. 6, a black matrix 41 having an opening 42 at a position facing the pixel electrode 22 is formed on the counter substrate 40. The black matrix 41 is formed at a position facing a region including the TFT 21, the gate line 23, and the data line 24.
- FIG. 7 is an enlarged view of FIG. FIG. 7 shows a layout near the TFT 21.
- FIG. 8 is a diagram showing the positions of the gate line 23, the drain electrode 25, and the pixel electrode 22 shown in FIG. The three elements shown in FIG. 8 actually overlap.
- the drain electrode 25 is formed above the gate line 23, and the pixel electrode 22 is formed above the drain electrode 25. In FIG. 8, three elements are described so as not to overlap by moving in the row direction.
- the gate line 23 has a portion that functions as the gate electrode of the TFT 21, and the data line 24 has a portion that functions as the source electrode of the TFT 21.
- the gate electrode of the TFT 21 is formed integrally with the gate line 23, and the source electrode of the TFT 21 is formed integrally with the data line 24.
- the drain electrode 25 has a main body portion (portion extending in the column direction) facing the source electrode and a connection portion (portion extending in the row direction) for connecting to the pixel electrode 22.
- the main body of the drain electrode 25 has a portion that overlaps with the gate electrode.
- the pixel electrode 22 covers the connection portion of the drain electrode 25, the main body portion facing the common electrode 30 and the slit 31 formed in the common electrode 30, the column portion extends, and the overlapping portion of the gate electrode and the drain electrode 25 And an extended portion (a portion protruding downward in the drawing).
- a portion of the pixel electrode 22 that transmits backlight and substantially contributes to display is included in the main body.
- the pixel electrode 22 and the common electrode 30 are preferably formed of a transparent conductive film such as IZO (indium zinc oxide) or ITO (indium tin oxide).
- the end closest to the main body of the pixel electrode 22 is the near end En, and the end farthest from the main body of the pixel electrode 22 is far away. It is called end Ef.
- the main body of the drain electrode 25 intersects with the near end En but does not intersect with the far end Ef.
- the main body of the drain electrode 25 does not reach the far end Ef, and ends at a distance L1 before the far end Ef (the main body side of the pixel electrode 22).
- the extended portion of the pixel electrode 22 intersects both the near end En and the far end Ef.
- the extended portion of the pixel electrode 22 ends beyond the far end Ef by a distance L2 beyond the far end Ef (on the side opposite to the main body of the pixel electrode 22).
- the gate line 23 as a reference, when the side on which the body part of the pixel electrode 22 is disposed is the first side and the opposite side is the second side, the body part of the pixel electrode 22 is formed on the first side of the gate line 23.
- the drain electrode 25 is formed on the first side of the gate line 23, but is not formed on the second side of the gate line 23.
- the extended portion of the pixel electrode 22 is formed on the first side of the gate line 23 and is also formed on the second side of the gate line 23.
- FIGS. 9A to 9I show the process of forming the gate line 23, the data line 24, and the TFT 21, respectively.
- the thicknesses of various films formed on the substrate are suitably determined according to the function and material of the film.
- the thickness of the film is, for example, about 10 nm to 1 ⁇ m.
- an example of the film thickness is shown.
- a Ti film having a thickness of 25 to 35 nm, an Al film having a thickness of 180 to 220 nm, and a Ti film having a thickness of 90 to 110 nm are sequentially formed.
- an SiNx film 121 having a thickness of 360 to 450 nm, an amorphous Si film 122 having a thickness of 100 to 200 nm, and an n + amorphous Si film 123 having a thickness of 30 to 80 nm are successively formed.
- a MoNb film having a thickness of 180 to 220 nm is formed, and in the fourth step, an IZO film 141 having a thickness of 50 to 80 nm is formed.
- a lower SiNx film 151 having a thickness of 220 to 280 nm and an upper SiNx film 152 having a thickness of 450 to 550 nm are formed.
- an IZO film having a thickness of 110 to 140 nm is formed.
- gate layer pattern (FIG. 9A) Ti (titanium), Al (aluminum), and Ti are sequentially formed on the glass substrate 101 by sputtering. Subsequently, the gate layer is patterned using photolithography and etching to form the gate line 23, the gate electrode 111 of the TFT 21, and the like.
- patterning using a photolithography method and etching refers to the following processing. First, a photoresist is applied to the substrate. Next, the substrate is exposed with a photomask having a desired pattern, thereby leaving the photoresist in the same pattern as the photomask on the substrate. Next, the substrate is etched using the remaining photoresist as a mask to form a pattern on the surface of the substrate. Finally, the photoresist is peeled off.
- FIG. 9B An SiNx (silicon nitride) film 121, an amorphous Si (amorphous silicon) film 122, and an n + amorphous Si film 123 doped with phosphorus are formed on the substrate shown in FIG. 9A by a CVD (Chemical Vapor Deposition) method. Are continuously formed. Subsequently, the semiconductor layer is patterned using a photolithography method and etching, and a semiconductor layer composed of an amorphous Si film 122 and an n + amorphous Si film 123 is formed on the gate electrode 111 of the TFT 21 in an island shape.
- CVD Chemical Vapor Deposition
- Source layer pattern formation (FIG. 9C) A MoNb (molybdenum niobium) film is formed on the substrate shown in FIG. 9B by sputtering. Subsequently, the source layer is patterned using a photolithography method and etching to form the main conductor portion 131 of the data line 24, the conductor portion 132 of the TFT 21, and the like. The conductor portion 132 of the TFT 21 is formed at the position of the source electrode, the drain electrode, and the channel region of the TFT 21. When the third step is completed, the source electrode, the drain electrode, and the channel region of the TFT 21 are formed integrally with the main conductor portion 131 of the data line 24.
- FIG. 9D Formation of Pixel Electrode
- An IZO film 141 to be the pixel electrode 22 is formed on the substrate shown in FIG. 9C by sputtering. Subsequently, the pixel electrode layer is patterned using photolithography and etching. In the fourth step, a photomask that leaves the photoresist 142 at the position of the pixel electrode 22 and the position of the source layer pattern (except for the position of the channel region of the TFT 21) is used. For this reason, after exposure, the photoresist 142 remains at the position of the pixel electrode 22 and the position of the source layer pattern excluding the position of the channel region of the TFT 21 (FIG. 9D).
- the IZO film 141 and the conductor portion 132 existing at the channel region of the TFT 21 are first etched by wet etching, and then the n + amorphous Si film existing at the channel region of the TFT 21 by dry etching. 123 is etched (FIGS. 9E and 9F).
- FIG. 9E shows the substrate when the etching of the conductor portion 132 is completed.
- FIG. 9F shows the substrate at the time when the etching of the n + amorphous Si film 123 is completed.
- the film thickness of the amorphous Si film 122 existing in the channel region of the TFT 21 is reduced by dry etching.
- the photoresist 142 is removed to obtain the substrate shown in FIG. 9G.
- the channel region of the TFT 21 is formed, and the source electrode 143 and the drain electrode 25 of the TFT 21 are separated from each other.
- the IZO film 141 remains on the main conductor 131 of the data line 24, the source electrode 143 of the TFT 21, and the drain electrode 25 of the TFT 21.
- the data line 24 is formed by the main conductor portion 131 and the IZO film 141 on the upper layer.
- FIG. 9H Formation of protective insulating film
- Two layers of SiNx films 151 and 152 to be protective insulating films are sequentially formed on the substrate shown in FIG. 9G by a CVD method.
- the deposition conditions for the lower SiNx film 151 and the deposition conditions for the upper SiNx film 152 are different.
- a thin film with a high film density formed under a high temperature condition is used for the lower SiNx film 151
- a thick film with a low film density formed under a low temperature condition is used for the upper SiNx film 152.
- the two-layered SiNx films 151 and 152 formed in the fifth process and the SiNx film 121 formed in the second process are patterned using photolithography and etching. 9H to 9C, the protective insulating film is not subjected to specific patterning such as contact holes. The protective insulating film is patterned in order to form a contact hole or the like for connecting the gate layer or the source layer and the common electrode layer in the frame region 14 or the non-facing region 12.
- the active matrix substrate 10 having the cross-sectional structure shown in FIG. 9I can be manufactured.
- a photolithography method is executed using different photomasks in the first to sixth steps.
- the total number of photomasks used in the manufacturing method according to this embodiment is six.
- the shapes of the pixel electrode 22, the gate line 23 (including the gate electrode), the data line 24 (including the source electrode), the drain electrode 25, and the semiconductor layer 26 illustrated in FIG. 7 are used in the first to fourth steps. Determined by the photomask. Therefore, by using a photomask corresponding to the layout pattern shown in FIG. 7, the drain electrode 25 is not formed on the second side of the gate line 23, and the extended portion of the pixel electrode 22 is on the second side of the gate line 23. Can also be formed.
- a transparent conductive film such as ITO may be used instead of IZO.
- a single-layer SiNx film may be formed instead of the two-layer SiNx film.
- a SiOx (silicon oxide) film, a SiON (silicon nitride oxide) film, or a laminated film thereof may be used.
- the counter substrate 40 is formed by forming a black matrix 41 having openings 42 on a glass substrate, forming a color filter layer and an overcoat layer thereon, and providing column spacers (not shown) at predetermined positions. Is done. Further, a horizontal alignment film (not shown) is provided on the surface of the active matrix substrate 10 on the liquid crystal layer side and on the surface of the counter substrate 40 on the liquid crystal layer side to set the initial alignment direction of the liquid crystal molecules. Surface treatment is performed. By arranging the active matrix substrate 10 and the counter substrate 40 to face each other and providing a liquid crystal layer between the two substrates, the liquid crystal panel 2 can be configured.
- FIG. 10 is a cross-sectional view of the liquid crystal panel 2.
- FIG. 10 shows a cross section taken along line A-A 'of FIG.
- the active matrix substrate 10 has the following configuration on the A-A ′ line.
- a gate electrode 111 of the TFT 21 is formed at a predetermined position on the glass substrate 101.
- a SiNx film 121 that functions as a gate insulating film is formed on the glass substrate 101 and the gate electrode 111.
- the data line 24 including the main conductor 131 and the IZO film 141 is formed on the A side (left side in the drawing) of the gate electrode 111.
- the IZO film 141 is formed on the upper layer of the main conductor 131 together with the pixel electrode 22 in the fourth step.
- a semiconductor layer 26 is formed at a predetermined position on the SiNx film 121, and a source electrode 143 and a drain electrode 25 are formed at a predetermined position on the semiconductor layer 26.
- the pixel electrode 22 is formed so as to cover the drain electrode 25.
- Two layers of SiNx films 151 and 152 functioning as a protective insulating film are formed on the pixel electrode 22 and the data line 24.
- the common electrode 30 is formed at a predetermined position on the upper SiNx film 152.
- the drain electrode 25 is not formed on the second side of the gate line 23, and the extended portion of the pixel electrode 22 is also formed on the second side of the gate line 23.
- the terminal end (right end) of the drain electrode 25 is in the range of the gate electrode 111 (on the left side of the right end of the gate electrode 111) in plan view.
- the end (right end) of the pixel electrode 22 is outside the range of the gate electrode 111 (on the right side of the right end of the gate electrode 111) in plan view.
- a black matrix 41 is formed on one surface of the glass substrate 102 of the counter substrate 40.
- a color filter layer 43 and an overcoat layer 44 are formed on the surface of the glass substrate 102 on which the black matrix 41 is formed.
- the active matrix substrate 10 and the counter substrate 40 are arranged to face each other, and a liquid crystal layer 45 is provided between the two substrates. In FIG. 10, the horizontal alignment film is omitted.
- FIG. 11 is a layout diagram of a liquid crystal display device including an active matrix substrate according to a comparative example. 11, the shapes of the gate line 23, the data line 24, the drain electrode 25, and the semiconductor layer 26 are the same as those in FIG. 7, and the shape of the pixel electrode 82 is different from that in FIG. In FIG. 11, the extended portion of the pixel electrode 82 ends at the same position as the main body portion of the drain electrode 25.
- the extended portion of the pixel electrode 82 is not formed on the second side of the gate line 23. For this reason, when the positions of the pixel electrode 82 and the drain electrode 25 are slightly shifted upward, the area of the portion where the gate line 23 and the main body of the drain electrode 25 overlap is reduced, and the parasitic capacitance between the gate and drain of the TFT is reduced. Cgd decreases and the pull-in voltage decreases. Further, when the positions of the pixel electrode 82 and the drain electrode 25 are slightly shifted downward, the area where the gate line 23 and the main body of the drain electrode 25 overlap increases, and the parasitic capacitance Cgd between the gate and the drain of the TFT is increased. Increases and the pull-in voltage increases.
- the liquid crystal display device including the active matrix substrate according to the comparative example variation occurs in the parasitic capacitance Cgd between the gate and drain of the TFT due to the pattern shift. Therefore, if the amount of fluctuation in the pull-in voltage differs between the pixel circuits, the display quality is improved. Decreases. For example, when pixel electrodes and gate lines are formed using the step-and-repeat method, block-like display unevenness occurs on the display screen, and when pixel electrodes and gate lines are formed using the scan exposure method , Band-like display unevenness and flickering occur on the display screen.
- the extended portion of the pixel electrode 22 is also formed on the second side of the gate line 23.
- the positions of the pixel electrode 22 and the drain electrode 25 are shifted upward or downward by a predetermined amount or less, even if the area of the portion where the gate line 23 and the body of the drain electrode 25 overlap changes, The area where the line 23 and the extended portion of the pixel electrode 22 overlap does not change. Therefore, the parasitic capacitance Cgd between the gate and the drain of the TFT 21 is substantially equal between the pixel circuits 20, and the pull-in voltage is substantially equal. Therefore, according to the liquid crystal display device including the active matrix substrate 10, it is possible to prevent the display quality from being deteriorated due to variations in the parasitic capacitance Cgd between the gate and the drain of the TFT 21.
- the extended portion of the pixel electrode 22 is also formed on the second side of the gate line 23, but the drain electrode 25 is not formed on the second side of the gate line 23. For this reason, as will be described below, it is possible to prevent defects in rubbing processing, fluctuations in the aperture ratio, and display defects due to the influence of backlight light.
- a rubbing process is performed to set the initial alignment of liquid crystal molecules.
- the rubbing treatment is performed in a direction substantially perpendicular to the direction in which the slits of the common electrode extend (horizontal direction in FIG. 3; the extending direction of the gate line 23). This is done so that the long axes of the molecules are aligned.
- the rubbing process is such that the major axes of the liquid crystal molecules are arranged in the direction in which the slits of the common electrode extend (vertical direction in FIG. 3, the extending direction of the data line 24). To be done. If the level difference is large in the vicinity of the TFT, the rubbing process is liable to occur. In the active matrix substrate 10, the level difference is small in the vicinity of the TFT 21, so that the rubbing process is less likely to occur.
- the drain electrode 25 is formed up to the second side of the gate line 23, the main body portion of the drain electrode 25 and the opening 42 of the black matrix 41 are overlapped when the substrate is displaced and the aperture ratio is reduced.
- the drain electrode 25 is formed of an opaque metal material such as MoNb.
- the opaque drain electrode 25 is not formed on the second side of the gate line 23, and a transparent conductive film such as IZO is formed on the second side of the gate line 23.
- the aperture ratio is unlikely to fluctuate even when a deviation occurs. Further, when the liquid crystal display device 1 is used outdoors, display defects due to reflection of external light by the drain electrode 25 are unlikely to occur.
- the backlight light may be reflected on the back surface (the side where the backlight is disposed) of the drain electrode and enter the channel region of the TFT.
- the backlight light When the backlight light is incident on the channel region of the TFT, charge may be lost through the TFT within a period in which the voltage applied to the liquid crystal layer should be maintained, and display defects may occur.
- the drain electrode 25 since the drain electrode 25 is not formed on the second side of the gate line 23, display defects due to the influence of the backlight light can be prevented.
- a channel region of the TFT 21 by patterning the conductor portion 132 and the semiconductor layer of the TFT 21 using a photomask for forming the pixel electrode 22 in the fourth step.
- a design margin positional displacement in the photolithography process, etching, or the like is formed between the pattern of the pixel electrode layer and the pattern for forming the TFT channel region. It is necessary to provide a margin for variations in the finished width in the process.
- the parasitic capacitance Cgd between the gate and drain of the TFT increases, and the load (capacitance) of the gate line increases. growing.
- the drain electrode 25 is not enlarged more than necessary, and an increase in the parasitic capacitance Cgd between the gate and the drain of the TFT 21 can be suppressed.
- the active matrix substrate 10 includes a plurality of gate lines 23 extending in the first direction (row direction) and a plurality of data lines 24 extending in the second direction (column direction).
- a plurality of pixel circuits 20 arranged corresponding to the intersections of the gate line 23 and the data line 24, each including a thin film transistor (TFT 21) and a pixel electrode 22, a gate line 23, a data line 24, a thin film transistor, and a pixel electrode.
- the protective insulating films (SiNx films 151 and 152) formed above the protective insulating film 22 and the common electrode 30 formed above the protective insulating film are provided.
- the thin film transistor includes a gate electrode formed integrally with the gate line 23, a source electrode formed integrally with the data line 24, and a drain electrode 25 directly connected to the pixel electrode 22 and having a portion overlapping with the gate electrode. .
- the pixel electrode 22 has a main body portion formed on the first side (upper side) of the gate line 23 and an extension portion extending in the second direction and covering the overlapping portion of the gate electrode and the drain electrode 25.
- the drain electrode 25 is not formed on the second side (lower side) of the gate line 23, and the extended portion of the pixel electrode 22 is also formed on the second side of the gate line 23.
- the positions of the pixel electrode 22 and the drain electrode 25 are only in a certain extent in the second direction. Even in the case of deviation, the area of the portion where the gate line 23 and the extended portion of the pixel electrode 22 overlap does not change. For this reason, the parasitic capacitance Cgd between the gate and drain of the thin film transistor is substantially equal between the pixel circuits 20, and the pull-in voltage is substantially equal. Accordingly, it is possible to prevent display quality from being deteriorated due to variations in the parasitic capacitance Cgd between the gate and the drain of the thin film transistor. In addition, since the drain electrode 25 is not formed on the second side of the gate line 23, it is possible to prevent display defects due to a rubbing treatment defect, an aperture ratio variation, and influence of backlight light.
- the common electrode 30 has one or more (two) slits 31 corresponding to the pixel circuit 20. Thereby, a lateral electric field for widening the viewing angle of the liquid crystal panel 2 including the active matrix substrate 10 can be generated.
- the liquid crystal panel 2 according to this embodiment includes an active matrix substrate 10 and a counter substrate 40 that faces the active matrix substrate 10. Thus, a liquid crystal panel can be configured in which display quality is prevented from being deteriorated due to variations in the parasitic capacitance Cgd between the gate and drain of the thin film transistor.
- a plurality of gate lines 23 extending in the first direction (row direction) are formed, and a gate electrode of the thin film transistor (TFT 21) is formed integrally with the gate lines 23 ( A first step), a semiconductor layer forming step (second step) for forming the semiconductor layer 26 of the thin film transistor, a main conductor portion 131 of the plurality of data lines 24 extending in the second direction (column direction), and A source layer forming step (third step) for forming the drain electrode 25 of the thin film transistor and the conductor portion 132 that is the source of the source electrode integrally with the main conductor portion 131, the sub-conductor portion of the pixel electrode 22 and the data line 24 (
- the thin film transistor A pixel electrode layer forming step (fourth step) for forming the rain electrode 25 and the source electrode, a step (fifth step) for forming a protective insul
- the drain electrode 25 is formed so as to have a portion overlapping with the gate electrode.
- the pixel electrode layer forming step includes a main body portion formed on the first side (upper side) of the gate line 23 and an extension portion extending in the second direction and covering an overlapping portion of the gate electrode and the drain electrode 25. 22 is formed in direct connection to the drain electrode 25.
- the drain electrode 25 is not formed on the second side of the gate line 23, and in the pixel electrode layer formation step, the extended portion of the pixel electrode 22 is formed on the second side of the gate line 23. Also formed.
- semiconductor films (amorphous Si film 122 and n + amorphous Si film 123) are formed, and the semiconductor film is patterned.
- the active matrix substrate 10 in which display quality is prevented from being deteriorated due to variations in the parasitic capacitance Cgd between the gate and drain of the thin film transistor.
- the drain electrode 25 of the thin film transistor in the pixel electrode layer forming step, the drain electrode 25 is not made larger than necessary, and an increase in parasitic capacitance between the gate and the drain of the thin film transistor can be suppressed.
- FIG. 12 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a first modification.
- a drain electrode 51 having a main body portion and no connection portion is used.
- the drain electrode 51 does not intersect with both the near end En and the far end Ef of the gate line 23.
- the drain electrode 51 is not formed on the first side or the second side of the gate line 23, and is formed inside the region where the gate line 23 and the gate electrode are formed.
- the active matrix substrate according to the first modification prevents the substrate from being bonded and prevents the drain electrode and the black matrix opening from overlapping even when the black matrix opening is formed close to the TFT. In addition, it is possible to prevent a decrease in the aperture ratio. Further, display defects due to the influence of backlight light can be more effectively prevented.
- FIG. 13 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a second modification.
- a semiconductor layer 52 smaller than the semiconductor layer 26 is used instead of the semiconductor layer 26 shown in FIG.
- the semiconductor layer 52 is formed inside the region where the gate line 23 and the gate electrode are formed. Thereby, display failure due to the influence of the backlight light can be prevented.
- the active matrix substrate according to the second modification since the positional deviation when forming the semiconductor layer in the second step has a great influence on the TFT characteristics, it is necessary to increase the area of the gate electrode in advance. .
- the accuracy of the exposure apparatus the brightness of the backlight, the design of the pixel circuit (such as the size of the auxiliary capacity that can be secured), the output voltage of the drive circuit, etc. are taken into consideration in FIG. It may be determined which of the layout shown and the layout shown in FIG.
- FIG. 14 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a third modification.
- the active matrix substrate according to the third modification has a larger pixel size than the active matrix substrate shown in FIGS. 4, 12, and 13.
- the pixel size in FIGS. 4, 12, and 13 is 21 ⁇ 63 ⁇ m
- the pixel size in FIG. 14 is 42 ⁇ 126 ⁇ m.
- FIG. 15 is an enlarged view of FIG. FIG. 15 shows patterns other than the common electrode of the active matrix substrate according to the third modification.
- the gate line 53 penetrates through the pixel circuit, and the pixel circuit is divided into two by the gate line 53.
- the pixel electrode 54 is connected to the first main body portion 54a formed on the first side and the second side.
- the formed second main body portion 54b and an extension portion 54c extending in the column direction, covering the overlapping portion of the gate electrode and the drain electrode 51, and connecting the first main body portion 54a and the second main body portion 54b (see FIG. 15).
- the common electrode has five slits 55a formed on the first side and five slits 55b formed on the second side corresponding to one pixel circuit.
- the black matrix has an opening 56a formed on the first side and an opening 56b formed on the second side corresponding to one pixel circuit.
- the slit 55a and the slit 55b can be formed as a continuous slit.
- the electric field due to the voltage applied to the gate line 53 may affect the alignment of the liquid crystal.
- a configuration in which no slit is formed on the gate line 53 is preferable.
- the common electrode has one or more slits in a region corresponding to the first main body portion 54 a and the second main body portion 54 b, it is preferable that at least one of the slits is not formed on the gate line 53. Thereby, it is possible to generate a horizontal electric field for widening the viewing angle of the liquid crystal panel including the active matrix substrate while preventing the electric field due to the voltage applied to the gate line 53 from affecting the alignment of the liquid crystal. .
- the gate line 53 and the pixel electrode 54 do not overlap, but a parasitic capacitance is generated between the gate line 53 and the pixel electrode 54 due to an oblique electric field.
- the parasitic capacitance generated between the gate line 53 and the pixel electrode 54 is a first capacitance generated between the gate line 53 and the first main body 54a (capacitance generated in the Pa portion in FIG. 15), This is the total of the second capacitance generated between the gate line 53 and the second main body portion 54b (capacitance generated at the Pb portion in FIG. 15).
- the active matrix substrate according to the third modification when the position of the pixel electrode 54 is shifted upward, the first main body 54 a is far from the gate line 53, and the second main body 54 b is close to the gate line 53. The first capacity is small and the second capacity is large. Conversely, when the position of the pixel electrode 54 is shifted downward, the first main body 54a is close to the gate line 53 and the second main body 54b is far from the gate line 53. Capacity is reduced. Therefore, in the active matrix substrate according to the third modification, even when the position of the pixel electrode 54 is deviated from the position of the gate line 53, the magnitude of the parasitic capacitance generated between the gate line 53 and the pixel electrode 54 is substantially constant. Can be kept in.
- the parasitic capacitance generated between the gate line 53 and the pixel electrode 54 is larger than in the configuration in which the second main body portion is not formed on the second side. Therefore, when designing an active matrix substrate, it may be determined whether or not to select the layout shown in FIG. 14 in consideration of the accuracy of the exposure apparatus.
- FIG. 16 is a layout diagram of a liquid crystal panel including an active matrix substrate according to a fourth modification.
- the data line 57 has a portion that functions as a source electrode of the TFT in the vicinity of the intersection of the gate line 23 and the data line 57.
- the source electrodes are alternately formed on both sides of the data line 57. Therefore, the TFTs are alternately formed on both sides of the data line 57.
- the active matrix substrate according to the fourth modification can be suitably used for a liquid crystal display device that performs dot inversion driving without increasing the load on the data line 57.
- FIG. 17 is a layout diagram of a liquid crystal panel including an active matrix substrate according to the second embodiment of the present invention.
- the shape of the pixel electrode 22, the gate line 23, the data line 24, and the drain electrode 51 is the same as that in FIG. 12, and the shape of the semiconductor layer 61 is different from that in FIG.
- the semiconductor layer 61 is formed between the source electrode formed integrally with the data line 24 and the drain electrode 51.
- the semiconductor layer 61 is formed in substantially the same shape as the source layer pattern below the source layer pattern. Specifically, the semiconductor layer 61 is also formed below the data line 24, the TFT source electrode, and the drain electrode 51.
- the first process described in the first embodiment is performed, then the second and third processes described below are performed, and then the second process described in the first embodiment is performed. Steps 4 to 6 are executed.
- the second and third steps of the manufacturing method according to the present embodiment will be described with reference to FIGS. 18A to 18D. Note that the same elements as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
- a MoNb film 171 is formed on the substrate shown in FIG. 18A by sputtering. Subsequently, the source layer and the semiconductor layer are patterned using photolithography and etching to form the main conductor portion 131 of the data line 24, the conductor portion 132 of the TFT 21, and the like. The conductor portion 132 of the TFT 21 is formed at the position of the source electrode, the drain electrode, and the channel region of the TFT 21. In the third step, a photomask that leaves the photoresist 172 in positions such as the main conductor 131 and the conductor 132 is used.
- the photoresist 172 remains at positions such as the main conductor 131 and the conductor 132 (FIG. 18B).
- the MoNb film 171 formed in the third step is first etched, and then the n + amorphous Si film 123 and the amorphous Si film 122 formed in the second step are successively etched (FIG. 18C).
- the amorphous Si film 122 and the n + amorphous Si film 123 are patterned in substantially the same shape as the source layer.
- the photoresist 172 is removed to obtain the substrate shown in FIG. 18D. In the substrate shown in FIG.
- the MoNb film 171 remaining without being etched becomes the main conductor portion 131 of the data line 24, the conductor portion 132 of the TFT 21, and the like.
- the substrate shown in FIG. 18D corresponds to the substrate shown in FIG. 9C.
- the substrate shown in FIG. 18D is different from the substrate shown in FIG. 9C in that an amorphous Si film 122 and an n + amorphous Si film 123 exist below the main conductor portion 131 of the data line 24.
- An active matrix substrate having the cross-sectional structure shown in FIG. 18E can be manufactured by performing the fourth to sixth steps described in the first embodiment on the substrate shown in FIG. 18D.
- the liquid crystal panel according to the present embodiment can be configured.
- the gate line 23 in the first step and forming the main conductor 131 of the data line 24 in the third step Cu, Mo Al, Ti, alloys thereof, or a laminated film of these metals may be used.
- a transparent conductive film such as ITO may be used.
- a single SiNx film may be formed, or a SiOx film, a SiON film, or a laminated film thereof may be used.
- FIG. 19 is a cross-sectional view of the liquid crystal panel according to the present embodiment.
- FIG. 19 shows a cross section taken along line B-B ′ of FIG. 17.
- the active matrix substrate 70 according to this embodiment is the same as that of the first embodiment in that the semiconductor layer 26 including the amorphous Si film 122 and the n + amorphous Si film 123 exists below the main conductor 131 of the data line 24. This is different from the active matrix substrate 10. For this reason, in the active matrix substrate 70, the thickness of the data line 24 is increased by the semiconductor layer 26.
- the photolithography method is executed using different photomasks in the first and third to sixth steps, and the photolithography method is not executed in the second step.
- the total number of photomasks used in the manufacturing method according to this embodiment is five. Therefore, according to the manufacturing method according to the present embodiment, the number of photomasks to be used can be reduced by one as compared with the manufacturing method according to the first embodiment, and the manufacturing cost can be reduced.
- the semiconductor layer forming step (second step) is to form the semiconductor films (amorphous Si film 122 and n + amorphous Si film 123) and to form the source layer.
- the main conductor 131 of the data line 24, the drain electrode 25 of the thin film transistor, and the conductor 132 serving as the source electrode are formed, and the semiconductor film is patterned. In this manner, by patterning the semiconductor layer in the source layer forming step, the active matrix substrate 70 can be manufactured using a small number of photomasks.
- the semiconductor layer 61 is formed below the data line 24, the source electrode of the thin film transistor, and the drain electrode 25.
- Such an active matrix substrate 70 can be easily manufactured using the manufacturing method described above.
- an active matrix substrate 70 having substantially the same layout configuration as that of the active matrix substrate (FIG. 13) according to the second modification of the first embodiment is manufactured using five photomasks.
- an active matrix substrate having substantially the same layout configuration as that of the active matrix substrate according to the first embodiment or another modification of the first embodiment may be manufactured using five photomasks. .
- an active matrix substrate having a specific layout configuration has been described.
- the present invention can also be applied to active matrix substrates having other layout configurations.
- the shape of the gate electrode, drain electrode, source electrode, and semiconductor layer of the TFT included in the active matrix substrate, the shape of the gate line and the data line, the direction in which the slit of the common electrode extends, and the like are described above. It is not limited to that.
- the drain electrode is not formed on the second side of the gate line (the side opposite to the side where the main body of the pixel electrode is disposed), and the pixel electrode is expanded.
- the portion also on the second side of the gate line it is possible to prevent display quality from being deteriorated due to variations in parasitic capacitance between the gate and drain of the TFT in the pixel circuit.
- the active matrix substrate of the present invention has a feature that it can prevent deterioration in display quality due to variations in parasitic capacitance between the gate and drain of TFTs in a pixel circuit. It can be used for a display unit or the like.
Abstract
Description
第1方向に延伸する複数のゲート線と、
第2方向に延伸する複数のデータ線と、
前記ゲート線と前記データ線の交点に対応して配置され、それぞれが薄膜トランジスタおよび画素電極を含む複数の画素回路と、
前記ゲート線、前記データ線、前記薄膜トランジスタ、および、前記画素電極よりも上層に形成された保護絶縁膜と、
前記保護絶縁膜の上層に形成された共通電極とを備え、
前記薄膜トランジスタは、前記ゲート線と一体に形成されたゲート電極と、前記データ線と一体に形成されたソース電極と、前記画素電極に直接接続され、前記ゲート電極と重なる部分を有するドレイン電極とを有し、
前記画素電極は、前記ゲート線の第1側に形成された本体部と、前記第2方向に延伸し、前記ゲート電極と前記ドレイン電極の重なり部分を覆う拡張部とを有し、
前記ドレイン電極は、前記ゲート線の第2側には形成されておらず、
前記画素電極の拡張部は、前記ゲート線の第2側にも形成されていることを特徴とする。
前記ドレイン電極は、前記ゲート線および前記ゲート電極が形成された領域の内部に形成されていることを特徴とする。
前記薄膜トランジスタの半導体層は、前記ゲート線および前記ゲート電極が形成された領域の内部に形成されていることを特徴とする。
前記ゲート線は、前記画素回路内を貫通し、
前記画素電極は、前記ゲート線の第2側に形成された第2本体部をさらに有し、
前記画素電極の拡張部は、前記画素電極の本体部と第2本体部を接続することを特徴とする。
前記共通電極は、前記本体部および前記第2本体部に対応する領域に1以上のスリットを有し、
前記スリットのうち少なくとも1つは、前記ゲート線上には形成されていないことを特徴とする。
前記薄膜トランジスタは、前記データ線の両側に交互に形成されていることを特徴とする。
前記共通電極は、前記画素回路に対応して1以上のスリットを有することを特徴とする。
前記データ線、前記ソース電極、および、前記ドレイン電極の下層には、半導体層が形成されていることを特徴とする。
前記アクティブマトリクス基板に対向する対向基板とを備えた、液晶パネルである。
第1方向に延伸する複数のゲート線を形成すると共に、前記ゲート線と一体に前記薄膜トランジスタのゲート電極を形成するステップと、
前記薄膜トランジスタの半導体層を形成する半導体層形成ステップと、
第2方向に延伸する複数のデータ線の主導体部を形成すると共に、前記主導体部と一体に、前記薄膜トランジスタのドレイン電極とソース電極の元になる導体部を形成するソース層形成ステップと、
前記画素電極と、前記データ線の副導体部とを形成すると共に、前記導体部をパターニングすることにより、前記薄膜トランジスタのドレイン電極とソース電極を形成する画素電極層形成ステップと、
前記画素電極の上層に保護絶縁膜を形成するステップと、
前記保護絶縁膜の上層に共通電極を形成するステップとを備え、
前記ソース層形成ステップと前記画素電極層形成ステップは、前記ドレイン電極を前記ゲート電極と重なる部分を有するように形成し、
前記画素電極層形成ステップは、前記画素電極として、前記ゲート線の第1側に形成された本体部と、前記第2方向に延伸し、前記ゲート電極と前記ドレイン電極の重なり部分を覆う拡張部とを有する電極を、前記ドレイン電極に直接接続して形成し、
前記ソース層形成ステップと前記画素電極層形成ステップは、前記ドレイン電極を前記ゲート線の第2側には形成せず、
前記画素電極層形成ステップは、前記画素電極の拡張部を前記ゲート線の第2側にも形成することを特徴とする。
前記半導体層形成ステップは、半導体膜を成膜し、前記半導体膜をパターニングすることを特徴とする。
前記半導体層形成ステップは、半導体膜を成膜し、
前記ソース層形成ステップは、前記主導体部と前記導体部とを形成すると共に、前記半導体膜をパターニングすることを特徴とする。
図1は、本発明の第1の実施形態に係るアクティブマトリクス基板を備えた液晶表示装置の構成を示すブロック図である。図1に示す液晶表示装置1は、液晶パネル2、表示制御回路3、ゲート線駆動回路4、データ線駆動回路5、および、バックライト6を備えている。以下、mおよびnは2以上の整数、iは1以上m以下の整数、jは1以上n以下の整数であるとする。
ガラス基板101上にスパッタリング法によって、Ti(チタン)、Al(アルミニウム)、および、Tiを順次成膜する。続いて、フォトリソグラフィ法とエッチングを用いてゲート層をパターニングし、ゲート線23、TFT21のゲート電極111などを形成する。ここで、フォトリソグラフィ法とエッチングを用いたパターニングとは、以下の処理をいう。まず、基板にフォトレジストを塗布する。次に、所望のパターンを有するフォトマスクを被せて基板を露光することにより、基板上にフォトマスクと同じパターンにフォトレジストを残す。次に、残したフォトレジストをマスクとして基板をエッチングすることにより、基板の表面にパターンを形成する。最後に、フォトレジストを剥離する。
図9Aに示す基板にCVD(Chemical Vapor Deposition )法によって、ゲート絶縁膜となるSiNx(窒化シリコン)膜121と、アモルファスSi(アモルファスシリコン)膜122と、リンがドープされたn+アモルファスSi膜123とを連続して成膜する。続いて、フォトリソグラフィ法とエッチングを用いて半導体層をパターニングし、TFT21のゲート電極111上に島状にアモルファスSi膜122とn+アモルファスSi膜123からなる半導体層を形成する。
図9Bに示す基板にスパッタリング法によって、MoNb(モリブデンニオブ)膜を成膜する。続いて、フォトリソグラフィ法とエッチングを用いてソース層をパターニングし、データ線24の主導体部131、TFT21の導体部132などを形成する。TFT21の導体部132は、TFT21のソース電極、ドレイン電極、および、チャネル領域の位置に形成される。第3工程完了時点では、TFT21のソース電極、ドレイン電極、および、チャネル領域は、データ線24の主導体部131と一体に形成されている。
図9Cに示す基板にスパッタリング法によって、画素電極22となるIZO膜141を成膜する。続いて、フォトリソグラフィ法とエッチングを用いて画素電極層をパターニングする。第4工程では、画素電極22の位置とソース層パターンの位置(ただし、TFT21のチャネル領域の位置を除く)にフォトレジスト142を残すフォトマスクが使用される。このため露光後には、画素電極22の位置、および、ソース層パターンの位置からTFT21のチャネル領域の位置を除いた位置にフォトレジスト142が残る(図9D)。フォトレジスト142をマスクとして、まずウェットエッチングによってIZO膜141とTFT21のチャネル領域の位置に存在する導体部132とをエッチングし、続いてドライエッチングによってTFT21のチャネル領域の位置に存在するn+アモルファスSi膜123をエッチングする(図9E、図9F)。図9Eには、導体部132のエッチングが完了した時点の基板が記載されている。図9Fには、n+アモルファスSi膜123のエッチングが完了した時点の基板が記載されている。図9Fに示すように、ドライエッチングによって、TFT21のチャネル領域に存在するアモルファスSi膜122の膜厚は薄くなる。最後にフォトレジスト142を剥離することにより、図9Gに示す基板が得られる。図9Gに示す基板では、TFT21のチャネル領域が形成され、TFT21のソース電極143とドレイン電極25は分離された状態になる。データ線24の主導体部131、TFT21のソース電極143、および、TFT21のドレイン電極25の上層には、IZO膜141が残る。主導体部131とその上層のIZO膜141とによって、データ線24が形成される。
図9Gに示す基板にCVD法によって、保護絶縁膜となる2層のSiNx膜151、152を順次成膜する。下層SiNx膜151の成膜条件と上層SiNx膜152の成膜条件は異なる。例えば、下層SiNx膜151には高温条件で成膜した膜密度が高い薄膜が使用され、上層SiNx膜152には低温条件で成膜した膜密度が低い厚膜が使用される。続いて、フォトリソグラフィ法とエッチングを用いて、第5工程で成膜された2層のSiNx膜151、152、および、第2工程で成膜されたSiNx膜121をパターニングする。なお、図9H(a)から(c)において、保護絶縁膜にはコンタクトホールなどの特定のパターニングは行われていない。保護絶縁膜のパターニングは、額縁領域14や非対向領域12において、ゲート層またはソース層と共通電極層とを接続するためのコンタクトホールなどを形成するために行われる。
図9Hに示す基板にスパッタリング法によって、共通電極30となるIZO膜を成膜する。続いて、フォトリソグラフィ法とエッチングを用いて共通電極層をパターニングし、共通電極30を形成する。
第2の実施形態では、第1の実施形態とは異なる方法で製造されたアクティブマトリクス基板について説明する。図17は、本発明の第2の実施形態に係るアクティブマトリクス基板を備えた液晶パネルのレイアウト図である。図17において、画素電極22、ゲート線23、データ線24、および、ドレイン電極51の形状は図12と同じであり、半導体層61の形状は図12とは異なる。半導体層61は、データ線24と一体に形成されたソース電極と、ドレイン電極51との間に形成されている。これに加えて、半導体層61は、ソース層パターンの下層にソース層パターンとほぼ同じ形状で形成されている。具体的には、半導体層61は、データ線24、TFTのソース電極、および、ドレイン電極51の下層にも形成される。
図9Aに示す基板にCVD法によって、ゲート絶縁膜となるSiNx膜121と、アモルファスSi膜122と、リンがドープされたn+アモルファスSi膜123とを連続して成膜する。第1の実施形態とは異なり、本実施形態では半導体層のパターニングを行わない。半導体層のパターニングは、ソース層のパターニングと共に第3工程で行われる。
図18Aに示す基板にスパッタリング法によって、MoNb膜171を成膜する。続いて、フォトリソグラフィ法とエッチングを用いてソース層と半導体層をパターニングし、データ線24の主導体部131、および、TFT21の導体部132などを形成する。TFT21の導体部132は、TFT21のソース電極、ドレイン電極、および、チャネル領域の位置に形成される。第3工程では、主導体部131および導体部132などの位置にフォトレジスト172を残すフォトマスクが使用される。このため露光後には、主導体部131および導体部132などの位置にフォトレジスト172が残る(図18B)。フォトレジスト172をマスクとして、まず第3工程で成膜したMoNb膜171をエッチングし、次に第2工程で成膜したn+アモルファスSi膜123とアモルファスSi膜122とを連続してエッチングする(図18C)。これにより、アモルファスSi膜122とn+アモルファスSi膜123は、ソース層とほぼ同じ形状にパターニングされる。最後にフォトレジスト172を剥離することにより、図18Dに示す基板が得られる。図18Dに示す基板では、エッチングされずに残ったMoNb膜171が、データ線24の主導体部131、TFT21の導体部132などになる。図18Dに示す基板は、図9Cに示す基板に対応する。図18Dに示す基板は、データ線24の主導体部131の下層にアモルファスSi膜122とn+アモルファスSi膜123が存在する点で、図9Cに示す基板と相違する。
2…液晶パネル
3…表示制御回路
4…ゲート線駆動回路
5…データ線駆動回路
6…バックライト
10、70…アクティブマトリクス基板
11…対向領域
12…非対向領域
20…画素回路
21…TFT
22、54…画素電極
23、53…ゲート線
24、57…データ線
25、51…ドレイン電極
26、52、61…半導体層
30…共通電極
31、55…スリット
40…対向基板
Claims (12)
- 第1方向に延伸する複数のゲート線と、
第2方向に延伸する複数のデータ線と、
前記ゲート線と前記データ線の交点に対応して配置され、それぞれが薄膜トランジスタおよび画素電極を含む複数の画素回路と、
前記ゲート線、前記データ線、前記薄膜トランジスタ、および、前記画素電極よりも上層に形成された保護絶縁膜と、
前記保護絶縁膜の上層に形成された共通電極とを備え、
前記薄膜トランジスタは、前記ゲート線と一体に形成されたゲート電極と、前記データ線と一体に形成されたソース電極と、前記画素電極に直接接続され、前記ゲート電極と重なる部分を有するドレイン電極とを有し、
前記画素電極は、前記ゲート線の第1側に形成された本体部と、前記第2方向に延伸し、前記ゲート電極と前記ドレイン電極の重なり部分を覆う拡張部とを有し、
前記ドレイン電極は、前記ゲート線の第2側には形成されておらず、
前記画素電極の拡張部は、前記ゲート線の第2側にも形成されていることを特徴とする、アクティブマトリクス基板。 - 前記ドレイン電極は、前記ゲート線および前記ゲート電極が形成された領域の内部に形成されていることを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記薄膜トランジスタの半導体層は、前記ゲート線および前記ゲート電極が形成された領域の内部に形成されていることを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記ゲート線は、前記画素回路内を貫通し、
前記画素電極は、前記ゲート線の第2側に形成された第2本体部をさらに有し、
前記画素電極の拡張部は、前記画素電極の本体部と第2本体部を接続することを特徴とする、請求項1に記載のアクティブマトリクス基板。 - 前記共通電極は、前記本体部および前記第2本体部に対応する領域に1以上のスリットを有し、
前記スリットのうち少なくとも1つは、前記ゲート線上には形成されていないことを特徴とする、請求項4に記載のアクティブマトリクス基板。 - 前記薄膜トランジスタは、前記データ線の両側に交互に形成されていることを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記共通電極は、前記画素回路に対応して1以上のスリットを有することを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 前記データ線、前記ソース電極、および、前記ドレイン電極の下層には、半導体層が形成されていることを特徴とする、請求項1に記載のアクティブマトリクス基板。
- 請求項1~8のいずれかに記載のアクティブマトリクス基板と、
前記アクティブマトリクス基板に対向する対向基板とを備えた、液晶パネル。 - それぞれが薄膜トランジスタおよび画素電極を有する複数の画素回路を含むアクティブマトリクス基板の製造方法であって、
第1方向に延伸する複数のゲート線を形成すると共に、前記ゲート線と一体に前記薄膜トランジスタのゲート電極を形成するステップと、
前記薄膜トランジスタの半導体層を形成する半導体層形成ステップと、
第2方向に延伸する複数のデータ線の主導体部を形成すると共に、前記主導体部と一体に、前記薄膜トランジスタのドレイン電極とソース電極の元になる導体部を形成するソース層形成ステップと、
前記画素電極と、前記データ線の副導体部とを形成すると共に、前記導体部をパターニングすることにより、前記薄膜トランジスタのドレイン電極とソース電極を形成する画素電極層形成ステップと、
前記画素電極の上層に保護絶縁膜を形成するステップと、
前記保護絶縁膜の上層に共通電極を形成するステップとを備え、
前記ソース層形成ステップと前記画素電極層形成ステップは、前記ドレイン電極を前記ゲート電極と重なる部分を有するように形成し、
前記画素電極層形成ステップは、前記画素電極として、前記ゲート線の第1側に形成された本体部と、前記第2方向に延伸し、前記ゲート電極と前記ドレイン電極の重なり部分を覆う拡張部とを有する電極を、前記ドレイン電極に直接接続して形成し、
前記ソース層形成ステップと前記画素電極層形成ステップは、前記ドレイン電極を前記ゲート線の第2側には形成せず、
前記画素電極層形成ステップは、前記画素電極の拡張部を前記ゲート線の第2側にも形成することを特徴とする、アクティブマトリクス基板の製造方法。 - 前記半導体層形成ステップは、半導体膜を成膜し、前記半導体膜をパターニングすることを特徴とする、請求項10に記載のアクティブマトリクス基板の製造方法。
- 前記半導体層形成ステップは、半導体膜を成膜し、
前記ソース層形成ステップは、前記主導体部と前記導体部とを形成すると共に、前記半導体膜をパターニングすることを特徴とする、請求項10に記載のアクティブマトリクス基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201680031955.0A CN107615156A (zh) | 2015-06-05 | 2016-05-27 | 有源矩阵基板、液晶面板以及有源矩阵基板的制造方法 |
JP2017521896A JP6501879B2 (ja) | 2015-06-05 | 2016-05-27 | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 |
US15/579,576 US10330994B2 (en) | 2015-06-05 | 2016-05-27 | Active matrix substrate, liquid crystal panel, and method for manufacturing active matrix substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015114598 | 2015-06-05 | ||
JP2015-114598 | 2015-06-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016194804A1 true WO2016194804A1 (ja) | 2016-12-08 |
Family
ID=57442393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2016/065696 WO2016194804A1 (ja) | 2015-06-05 | 2016-05-27 | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10330994B2 (ja) |
JP (1) | JP6501879B2 (ja) |
CN (1) | CN107615156A (ja) |
WO (1) | WO2016194804A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6753885B2 (ja) * | 2018-04-16 | 2020-09-09 | シャープ株式会社 | アクティブマトリクス基板、表示装置およびアクティブマトリクス基板の欠陥修正方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003021845A (ja) * | 2001-05-31 | 2003-01-24 | Hyundai Display Technology Inc | フリンジフィールドスイッチング液晶表示装置及びその製造方法 |
US20150062477A1 (en) * | 2013-08-28 | 2015-03-05 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4785229B2 (ja) * | 2000-05-09 | 2011-10-05 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR100475108B1 (ko) * | 2001-12-22 | 2005-03-10 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 및 그 제조 방법 |
JP4584332B2 (ja) * | 2006-02-24 | 2010-11-17 | シャープ株式会社 | アクティブマトリクス基板、表示装置、テレビジョン受像機 |
KR101035737B1 (ko) * | 2006-03-15 | 2011-05-20 | 샤프 가부시키가이샤 | 액티브 매트릭스 기판, 표시 장치 및 텔레비전 수상기 |
KR101300184B1 (ko) * | 2006-08-03 | 2013-08-26 | 삼성디스플레이 주식회사 | 액정 표시 장치 |
KR101294232B1 (ko) | 2007-06-08 | 2013-08-07 | 엘지디스플레이 주식회사 | 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판 및이의 제조 방법 |
WO2009125532A1 (ja) * | 2008-04-11 | 2009-10-15 | シャープ株式会社 | アクティブマトリクス基板及び液晶表示装置 |
JP5646162B2 (ja) | 2009-01-23 | 2014-12-24 | 三菱電機株式会社 | 薄膜トランジスタアレイ基板、その製造方法、及び液晶表示装置 |
JP5612399B2 (ja) * | 2010-08-31 | 2014-10-22 | 株式会社ジャパンディスプレイ | 液晶表示装置 |
CN103761944B (zh) * | 2013-12-25 | 2017-01-25 | 合肥京东方光电科技有限公司 | 一种栅极驱动电路、显示装置及驱动方法 |
-
2016
- 2016-05-27 WO PCT/JP2016/065696 patent/WO2016194804A1/ja active Application Filing
- 2016-05-27 CN CN201680031955.0A patent/CN107615156A/zh active Pending
- 2016-05-27 US US15/579,576 patent/US10330994B2/en active Active
- 2016-05-27 JP JP2017521896A patent/JP6501879B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003021845A (ja) * | 2001-05-31 | 2003-01-24 | Hyundai Display Technology Inc | フリンジフィールドスイッチング液晶表示装置及びその製造方法 |
US20150062477A1 (en) * | 2013-08-28 | 2015-03-05 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
Also Published As
Publication number | Publication date |
---|---|
JPWO2016194804A1 (ja) | 2018-03-15 |
JP6501879B2 (ja) | 2019-04-17 |
US20180173063A1 (en) | 2018-06-21 |
CN107615156A (zh) | 2018-01-19 |
US10330994B2 (en) | 2019-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4619997B2 (ja) | 液晶表示装置とその製造方法 | |
US7751021B2 (en) | Liquid crystal display and fabricating method thereof | |
JP5392670B2 (ja) | 液晶表示装置及びその製造方法 | |
JP4395130B2 (ja) | 液晶表示装置およびその製造方法 | |
US20110304787A1 (en) | Array substrate, liquid crystal panel, liquid crystal display and driving method thereof | |
US20120161140A1 (en) | Tft array substrate and manufacturing method thereof | |
US9761613B2 (en) | TFT array substrate and manufacturing method thereof | |
JP2006338008A (ja) | 開口率が向上したアレイ基板、その製造方法及びそれを含む表示装置。 | |
JP6218949B2 (ja) | アクティブマトリクス基板および液晶パネル | |
US20090166633A1 (en) | Array substrate and method for manufacturing the same | |
JP2006023744A5 (ja) | ||
WO2016021319A1 (ja) | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 | |
JP4881475B2 (ja) | アクティブマトリクス基板及び液晶表示装置 | |
JP4011557B2 (ja) | 液晶表示装置および液晶表示装置の製造方法 | |
JP4682295B2 (ja) | 液晶表示装置 | |
KR101946927B1 (ko) | 액정표시장치용 어레이기판 및 이의 제조방법 | |
JP2009151285A (ja) | 液晶表示装置及びその製造方法 | |
JP6501879B2 (ja) | アクティブマトリクス基板、液晶パネル、および、アクティブマトリクス基板の製造方法 | |
KR102410396B1 (ko) | 수평 전계형 액정 표시장치 및 그 제조방법 | |
JP2007272255A (ja) | 液晶表示装置 | |
KR102085857B1 (ko) | 액정표시장치 및 그 제조방법 | |
KR101977238B1 (ko) | 박막트랜지스터 어레이 기판 및 그 제조 방법 | |
KR102056687B1 (ko) | 액정표시장치 및 그 제조방법 | |
JP2007305641A (ja) | アクティブマトリクス基板および液晶表示パネル | |
CN110596975A (zh) | 有源矩阵基板及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16803239 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2017521896 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15579576 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16803239 Country of ref document: EP Kind code of ref document: A1 |