WO2016192275A1 - 一种像素驱动电路及方法、阵列基板和显示装置 - Google Patents

一种像素驱动电路及方法、阵列基板和显示装置 Download PDF

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Publication number
WO2016192275A1
WO2016192275A1 PCT/CN2015/092660 CN2015092660W WO2016192275A1 WO 2016192275 A1 WO2016192275 A1 WO 2016192275A1 CN 2015092660 W CN2015092660 W CN 2015092660W WO 2016192275 A1 WO2016192275 A1 WO 2016192275A1
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Prior art keywords
transistor
unit
driving
electrode
control
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PCT/CN2015/092660
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English (en)
French (fr)
Inventor
段立业
王俪蓉
李重君
钟杰兴
林俊杰
Original Assignee
京东方科技集团股份有限公司
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Priority to US15/307,788 priority Critical patent/US10467956B2/en
Publication of WO2016192275A1 publication Critical patent/WO2016192275A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a pixel driving circuit and method, an array substrate, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the Organic Light Emitting Diode (OLED) in AMOLED can be driven by a driving current generated by a Thin Film Transistor (TFT).
  • TFT Thin Film Transistor
  • the threshold voltage of the TFT may change, causing the same voltage to be input to the TFT, but the driving current generated by the TFT is inconsistent, which in turn causes the brightness of each OLED to be different, and the brightness of the AMOLED composed of multiple OLEDs is not Uniform, affecting the display of the entire image.
  • Embodiments of the present invention provide a pixel driving circuit and method, an array substrate, and a display device.
  • an embodiment of the present invention provides a pixel driving circuit for driving an organic light emitting diode to emit light, including:
  • the first end of the charge storage unit is connected to a power voltage signal
  • a driving unit wherein a control end of the driving unit is connected to the second end of the charge storage unit, and is configured to generate the organic light emitting when a voltage of the second end of the charge storage unit is greater than a threshold voltage of the driving unit The driving current of the diode light;
  • a reset unit coupled to the second end of the charge storage unit, for writing a voltage of an initial voltage signal to a second end of the charge storage unit during a reset phase
  • a data writing unit connected to the second end of the charge storage unit, for writing a voltage of the data voltage signal and a threshold voltage of the driving unit to the second end of the charge storage unit in a data writing phase; as well as
  • the driving unit includes a driving transistor, and a control end of the driving transistor is connected to a second end of the charge storage unit, and a first electrode of the driving transistor is connected to the power supply voltage through the light emitting control unit a second electrode of the driving transistor is connected to the organic light emitting diode through the light emitting control unit.
  • the reset unit includes a first transistor, a control end of the first transistor is connected to a reset switch signal, and a first electrode of the first transistor is connected to the initial voltage signal, and the first transistor is A second electrode is coupled to the second end of the charge storage unit.
  • the data writing unit includes a second transistor and a third transistor, and a control end of the second transistor and a control end of the third transistor respectively input a first control signal, and the second transistor An electrode is connected to the control end of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, and a first electrode of the third transistor is connected to the data voltage signal. A second electrode of the third transistor is coupled to the first electrode of the drive transistor.
  • the light emission control unit includes a fourth transistor and a fifth transistor, and a control end of the fourth transistor and a control end of the fifth transistor respectively input a second control signal, and the first of the fourth transistor
  • the electrode is connected to the power voltage signal
  • the second electrode of the fourth transistor is connected to the first electrode of the driving transistor
  • the first electrode of the fifth transistor is connected to the second electrode of the driving transistor
  • the fifth A second electrode of the transistor is coupled to the organic light emitting diode.
  • the driving transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all thin film transistors.
  • the pixel driving unit further includes:
  • a potential compensation unit connected to the control end of the driving unit for providing leakage compensation for the control end of the driving unit during the lighting phase.
  • the potential compensation unit includes a leakage prevention transistor, and a control end of the leakage prevention transistor is connected to a third control signal, and a first electrode of the leakage prevention transistor is connected to the power supply voltage signal, and the leakage prevention A second electrode of the transistor is coupled to the control terminal of the drive transistor.
  • the third control signal is in phase with the second control signal.
  • the initial voltage signal is a signal of constant level.
  • the initial voltage signal is inverted from the second control signal.
  • an embodiment of the present invention provides a pixel driving method, which is applied to the above pixel driving circuit, and includes:
  • the reset switch signal turns on the reset unit, and the reset unit writes the voltage of the initial voltage signal into the charge storage unit;
  • the first control signal turns on the data writing unit, and the data writing unit writes a voltage of the data voltage signal and a threshold voltage of the driving unit to the charge storage unit, the driving unit Generating a driving current for driving the organic light emitting diode to emit light when a voltage written to the charge storage unit is greater than a threshold voltage of the driving unit;
  • the second control signal turns on the illumination control unit, and the illumination control unit controls the supply voltage signal to be written to the drive unit to generate the drive current.
  • the pixel driving method further includes:
  • the third control signal turns on the potential compensation unit, and the potential compensation unit provides leakage compensation for the control end of the driving unit.
  • the third control signal is in phase with the second control signal.
  • the initial voltage signal is a signal of constant level.
  • the initial voltage signal is inverted from the second control signal.
  • an embodiment of the present invention provides an array substrate, including any of the above pixel compensation circuits.
  • an embodiment of the present invention provides a display device including any of the above array substrates.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a specific implementation circuit of a pixel driving circuit according to an embodiment of the present invention Schematic;
  • FIG. 4 is a schematic diagram of a current path in a reset phase according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a current path of an illuminating phase according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of leakage generation according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of another specific implementation circuit of a pixel driving circuit according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of leakage prevention according to an embodiment of the present invention.
  • FIG. 11 is a flowchart of a pixel driving method according to an embodiment of the present invention.
  • Embodiments of the present invention provide a pixel driving circuit for driving an organic light emitting diode to emit light, as shown in FIG.
  • the pixel driving circuit includes:
  • the reset unit 3 is connected to the second end of the charge storage unit 1 for writing the voltage of the initial voltage signal INIT to the second end of the charge storage unit 1 in the reset phase;
  • the illumination control unit 5 is connected to the driving unit 2 for controlling the power supply voltage signal to be written into the driving unit 2 to generate a driving current during the lighting phase.
  • the threshold voltage of the driving unit 2 is the voltage required for the driving unit 2 to be turned on.
  • the control terminal of the reset unit 3 is connected to the reset switch signal RES, and the reset switch signal RES controls whether the reset unit 3 is turned on.
  • the control terminal of the data writing unit 4 is connected to the first control signal GATE, the first control signal GATE is a scan signal, and the first control signal GATE controls whether the data writing unit 4 is turned on.
  • the control terminal of the illumination control unit 5 is connected to the second control signal EM, the second control signal EM is an illumination control signal, and the second control signal EM controls whether the illumination control unit 5 is turned on.
  • the data writing unit 4 writes the voltage of the data voltage signal DATA and the threshold voltage of the driving unit 2 to the second end of the charge storage unit 1 in the data writing phase.
  • the driving unit 2 generates a driving current for driving the organic light emitting diode OLED to emit light when the voltage of the second end of the charge storage unit 1 is greater than the threshold voltage of the driving unit 2. Therefore, in the light-emitting phase, the threshold voltage included in the voltage of the control terminal of the driving unit 2 is canceled by the threshold voltage that is turned on by the driving unit 2, and the driving current generated by the driving unit 2 is not affected by the threshold voltage of the driving unit 2, and is driven.
  • the current can be kept consistent, the brightness of each organic light emitting diode OLED is the same, and the display effect of the entire image is good.
  • the charge storage unit 1 may be a capacitor.
  • the charge storage unit 1 may include a storage capacitor Cst
  • the drive unit 2 may include a drive transistor VT0
  • the reset unit 3 may include a first transistor VT1
  • the data write unit 4 may include a second transistor VT2 and a
  • the three transistor VT3 the light emission control unit 5 may include a fourth transistor VT4 and a fifth transistor VT5.
  • the first plate of the storage capacitor Cst is connected to the power supply voltage signal VDD.
  • the gate of the driving transistor VT0 is connected to the second plate of the storage capacitor Cst, the drain of the driving transistor VT0 is connected to the organic light emitting diode OLED through the light emitting control unit 5, and the source of the driving transistor VT0 is connected to the power supply voltage through the light emitting control unit 5.
  • Signal VDD is connected to the second plate of the storage capacitor Cst, the drain of the driving transistor VT0 is connected to the organic light emitting diode OLED through the light emitting control unit 5, and the source of the driving transistor VT0 is connected to the power supply voltage through the light emitting control unit 5.
  • the gate of the first transistor VT1 is connected to the reset switch signal RES, the second electrode of the first transistor VT1 is connected to the second plate of the storage capacitor Cst, and the first electrode of the first transistor VT1 is connected to the initial voltage signal INIT.
  • the gate of the second transistor VT2 and the gate of the third transistor VT3 are both connected to the first control signal GATE, the first electrode of the second transistor VT2 is connected to the gate of the driving transistor VT0, and the second electrode of the second transistor VT2 is The drain of the driving transistor VT0 is connected, the first electrode of the third transistor VT3 is connected to the data voltage signal DATA, and the second electrode of the third transistor VT3 is connected to the source of the driving transistor VT0.
  • the gates of the fourth transistor VT4 and the fifth transistor VT5 are both connected to the second control signal EM, the first electrode and the second electrode of the fourth transistor VT4 are connected in series between the power supply voltage signal VDD and the source of the driving transistor VT0, and the first electrode and the second electrode of the fifth transistor VT5 are connected in series to the drain of the driving transistor VT0. And between the organic light emitting diode OLED.
  • the first electrode of the fourth transistor VT4 is connected to the power supply voltage signal VDD
  • the second electrode of the fourth transistor VT4 is connected to the first electrode of the driving transistor VT0
  • the first electrode of the fifth transistor VT5 is connected to the second electrode of the driving transistor VT0.
  • the second electrode of the fifth transistor VT5 is connected to the organic light emitting diode OLED.
  • the driving transistor VT0, the first transistor VT1, the second transistor VT2, the third transistor VT3, the fourth transistor VT4, and the fifth transistor VT5 may all be thin film transistors, which have small volume, low power consumption, and convenient and accurate control.
  • the first to fifth transistors VT1 - VT5 may be one or more of a Junction Field Effect Transistor (JFET), an enhancement MOSFET, a depletion MOSFET, and a BJT, respectively.
  • JFET Junction Field Effect Transistor
  • enhancement MOSFET an enhancement MOSFET
  • depletion MOSFET a depletion MOSFET
  • the first to fifth transistors VT1 - VT5 may each be a P-type transistor or an N-type transistor.
  • the first electrode is a source and the second electrode is a drain;
  • the first to fifth transistors VT1 - VT5 are N-type transistors, the first electrode is The drain and the second electrode are sources.
  • FIG. 3 is a timing diagram of control signals of a pixel driving circuit according to an embodiment of the present invention. It should be noted that the timing chart shown in FIG. 3 is exemplified by the fact that each transistor is a P-type transistor, and the present invention is not limited thereto.
  • the timing of the control signal of the pixel compensation circuit includes three stages of a reset phase T11, a data writing phase T12, and an illumination phase T13.
  • 4 is a schematic diagram of a current path in a reset phase
  • FIG. 5 is a schematic diagram of a current path in a data writing phase
  • FIG. 6 is a schematic diagram of a current path in a light emitting phase.
  • the paths of the currents in each stage are indicated by arrows in Fig. 4-6, and the active components are indicated by solid lines, and the inactive components are indicated by broken lines.
  • the reset switch signal RES is at a low level, and the first transistor VT1 controlled by the reset switch signal RES is turned on.
  • Storage capacitor Cst A plate inputs a power supply voltage signal VDD, and a second plate of the storage capacitor Cst inputs an initial voltage signal INIT.
  • the storage capacitor Cst is charged due to a voltage difference between the first plate and the second plate being increased.
  • the initial voltage signal INIT The voltage is written to the second plate of the storage capacitor Cst.
  • the potential at point A coincides with the initial voltage signal INIT, and point A is the connection point between the gate of the drive transistor VT0 and the second plate of the storage capacitor Cst.
  • the first control signal GATE is at a high level, and the second transistor VT2 and the third transistor VT3 controlled by the first control signal GATE are turned off.
  • the second control signal EM and the third control signal VL are at a high level, and the fourth transistor VT4 and the fifth transistor VT5 controlled by the second control signal EM and the leakage preventing transistor VT6 controlled by the third control signal VL are turned off.
  • the reset switch signal RES is at a high level, and the first transistor VT1 controlled by the reset switching signal RES is turned off.
  • the first control signal GATE is at a low level, and the second transistor VT2 and the third transistor VT3 controlled by the first control signal GATE are turned on.
  • the second transistor VT2 is turned on, and is short-circuited by the gate and the drain of the driving transistor VT0 connected to the first electrode and the second electrode of the second transistor VT2, respectively.
  • the driving transistor VT0 has only the PN between the gate and the source thereof. The junction is active and the drive transistor VT0 is in diode connection.
  • the third transistor VT3 is turned on, and the data voltage signal DATA accessed by the first electrode of the third transistor VT3 is transmitted to the source of the driving transistor VT0 connected to the second electrode of the third transistor VT3.
  • the potential at point B coincides with the data voltage signal DATA
  • point B is the connection point of the source of the drive transistor VT0. Since the driving transistor VT0 has only the PN junction between its gate and source, the potential at point A becomes VDATA+Vth, VDATA is the potential of the data voltage signal DATA, Vth is the threshold voltage of the PN junction, and the storage capacitor Cst Discharges due to a small voltage difference between the first plate and the second plate.
  • the second control signal EM and the third control signal VL are still at a high level, and the fourth transistor VT4 and the fifth transistor VT5 controlled by the second control signal EM and the leakage preventing transistor VT6 controlled by the third control signal VL are still turned off.
  • the reset switch signal RES and the first control signal GATE are at a high level, the first transistor VT1 controlled by the reset switch signal RES, the second transistor VT2 controlled by the first control signal GATE, and The third transistor VT3 is turned off.
  • the second control signal EM is at a low level, and the fourth transistor VT4 and the fifth transistor VT5 controlled by the second control signal EM are turned on.
  • the potential at point A is maintained at VDATA+Vth, and the driving transistor VT0 is turned on and operates in the saturation region, so the fourth transistor VT4, the driving transistor VT0, the fifth transistor VT5, and the organic light emitting diode OLED form a via, and the driving transistor VT0 generates a driving current.
  • the potential at the point C is VOLED
  • the point C is the connection point of the drain of the driving transistor VT0
  • the VOLED is the illuminating voltage of the organic light emitting diode OLED.
  • the pixel driving circuit provided by the embodiment of the present invention can compensate for the driving current deviation caused by the threshold voltage drift, and the uniformity is generated. The driving current ensures the uniformity of brightness of each OLED in the AMOLED.
  • the charge stored in the storage capacitor Cst is leaked through the first transistor VT1 and the second transistor VT2 (the leakage direction is as shown by the arrow in FIG. 7), and the charge stored in the capacitor Cst is stored.
  • the potential of the second terminal of the storage capacitor Cst is lowered, the gate potential of the driving transistor VT0 is lowered, the voltage difference between the gate and the source of the driving transistor VT0 is increased, and the driving current generated by the driving transistor VT0 is increased, and the OLED is increased.
  • the illuminating becomes strong, and in severe cases, the problem of not being able to write the correct display data is caused.
  • the pixel driving circuit can further include:
  • the potential compensation circuit 6 is connected to the control terminal of the driving unit 2 for providing leakage compensation for the control terminal of the driving unit during the lighting phase.
  • the potential compensation unit 6 may include a leakage preventing transistor VT6.
  • the gate of the leakage preventing transistor VT6 is connected to the third control signal VL, and the first electrode of the leakage preventing transistor VT6 is connected to the power supply voltage signal VDD, and the leakage preventing transistor VT6 is The two electrodes are connected to the gate of the driving transistor VT0.
  • the leakage preventing transistor VT6 communicates the power supply voltage signal VDD with the control terminal of the driving unit 2 in the light emitting phase, effectively compensating and balancing the control terminal of the driving unit 2 due to leakage of the path between the charge storage unit 1 and the driving unit 2.
  • the reduced potential allows the potential of the control terminal of the driving unit 2 to be consistent with the data voltage, ensuring correct writing of data, and the OLED is normally illuminated.
  • the charge storage unit 1 can select a capacitor having a smaller capacity, reducing the volume of the charge storage unit 1 (capacitor The volume is proportional to the capacity, which effectively reduces the area of the pixel, which increases the number of pixels per unit area and improves the image resolution of the entire panel.
  • the leakage preventing transistor VT6 may be any one of a JFET, an enhancement MOSFET, a depletion MOSFET, and a BJT.
  • the leakage preventing transistor VT6 may be a P-type transistor or an N-type transistor.
  • the leakage preventing transistor VT6 is a P-type transistor, the first electrode is a source and the second electrode is a drain; when the leakage preventing transistor VT6 is an N-type transistor, the first electrode is a drain and the second electrode is a source.
  • the third control signal VL may be in phase with the second control signal EM.
  • the third control signal VL and the second control signal EM have the same waveform and can be provided by the same signal line, and do not need to be implemented by using a complicated process, thereby saving cost on the one hand and reducing the design difficulty of the circuit on the other hand.
  • the initial voltage signal INIT may also be inverted from the second control signal EM.
  • the second control signal EM is at a low level
  • the initial voltage signal INIT is at a high level (inverted from the second control signal EM)
  • the leakage current of the gate of VT0 balances and compensates for the leakage current consumed by the second transistor VT2, and also suppresses the leakage current from the gate of the driving transistor VT0 to the initial voltage signal INIT of the input, further enhancing the retention.
  • the effect of the potential of the gate of the driving transistor VT0 is constant, ensuring correct writing of data, and the OLED is normally illuminated.
  • the initial voltage signal INIT is inverted from the second control signal EM, and the initial voltage signal INIT is obtained by inverting the second control signal EM, which does not need to be implemented by a complicated process, thereby saving cost on the one hand and reducing the cost on the other hand.
  • the design difficulty of the circuit is not required to be implemented by a complicated process.
  • the voltage of the data voltage signal and the threshold voltage of the driving unit are written into the second end of the charge storage unit by the data writing unit in the data writing phase, and the voltage at the second end of the charge storage unit is greater than the threshold of the driving unit.
  • a driving current for driving the organic light emitting diode to emit light is generated. Therefore, in the light emitting phase, the threshold voltage included in the voltage of the control terminal of the driving unit is cancelled by the threshold voltage that is turned on by the driving unit, and the driving current generated by the driving unit is not driven.
  • the influence of the threshold voltage of the unit, the drive current can be guaranteed Consistently, the brightness of each organic light-emitting diode is the same, and the overall image display effect is good.
  • FIG. 9 takes each transistor as a P-type transistor as an example
  • the initial voltage signal INIT is inverted with the second control signal EM, and the initial voltage signal INIT is at a high level in the light-emitting phase, resulting in a slave
  • the leakage current of the initial voltage signal INIT connected to the gate of the driving transistor VT0 balances and compensates for the leakage current consumed by the second transistor VT2, and also suppresses the slave driving transistor VT0.
  • the drain current of the gate to the initial voltage signal INIT is kept, and the potential of the gate of the driving transistor VT0 is kept unchanged, effectively compensating and balancing the gate of the driving transistor VT0 due to the connection between the storage capacitor Cst and the driving transistor VT0
  • the potential of the path leakage is reduced, so that the gate potential of the driving transistor VT0 can be kept consistent with the data voltage, the correct writing of the data is ensured, the OLED is normally illuminated, and no component needs to be added.
  • the storage capacitor with a smaller capacity can be selected, and the volume of the storage capacitor is reduced (the volume of the storage capacitor is proportional to the capacity), thereby effectively reducing the area of the pixel, thereby increasing the number of pixels per unit area, thereby increasing the number of pixels.
  • the image resolution of the entire panel Further, the initial voltage signal INIT is inverted from the second control signal EM, and the initial voltage signal INIT is obtained by inverting the second control signal EM, which does not need to be implemented by a complicated process, thereby saving cost and reducing on the other hand.
  • the design difficulty of the circuit is provided.
  • the voltage of the data voltage signal and the threshold voltage of the driving unit are written into the second end of the charge storage unit by the data writing unit in the data writing phase, and the voltage at the second end of the charge storage unit is greater than the threshold of the driving unit.
  • a driving current for driving the organic light emitting diode to emit light is generated. Therefore, in the light emitting phase, the threshold voltage included in the voltage of the control terminal of the driving unit is cancelled by the threshold voltage that is turned on by the driving unit, and the driving current generated by the driving unit is not driven.
  • the influence of the threshold voltage of the unit, the driving current can be kept consistent, the brightness of each organic light emitting diode is the same, and the display effect of the entire image is good.
  • An embodiment of the present invention provides a pixel driving method, which is applied to the above pixel driving circuit. Referring to FIG. 11, the method includes:
  • Step S11 In the reset phase, the reset switch signal turns on the reset unit, and the reset unit writes the voltage of the initial voltage signal to the charge storage unit.
  • the reset switch signal RES controls the first transistor VT1 to be turned on
  • the first control signal GATE controls the second transistor VT2 and the third transistor VT3 to be turned off
  • the second control signal EM controls the fourth transistor VT4.
  • the fifth transistor VT5 is turned off.
  • Step S12 In the data writing phase, the first control signal turns on the data writing unit, and the data writing unit writes the voltage of the data voltage signal and the threshold voltage of the driving unit to the charge storage unit, and the driving unit writes the charge storage.
  • the voltage of the cell is greater than the threshold voltage of the driving unit, a driving current for driving the organic light emitting diode to emit light is generated.
  • the reset switch signal RES controls the first transistor VT1 to be turned off
  • the first control signal GATE controls the second transistor VT2 and the third transistor VT3 to be turned on
  • the second control signal EM controls the fourth.
  • the transistor VT4 and the fifth transistor VT5 are turned off.
  • Step S13 In the lighting stage, the second control signal turns on the lighting control unit, and the lighting control unit controls the power voltage signal to be written into the driving unit to generate a driving current.
  • the reset switch signal RES controls the first transistor VT1 to be turned off
  • the first control signal GATE controls the second transistor VT2 and the third transistor VT3 to be turned off
  • the second control signal EM controls the fourth transistor VT4 and The fifth transistor VT5 is turned on.
  • the pixel driving method may further include:
  • the third control signal turns on the potential compensation unit, and the potential compensation unit provides leakage compensation for the control terminal of the driving unit.
  • the third control signal VL controls the anti-leakage transistor VT6 to be turned on.
  • the third control signal VL may be in phase with the second control signal EM.
  • the initial voltage signal INIT may be inverted from the second control signal EM.
  • the initial voltage signal INIT may be inverted from the second control signal EM.
  • the pixel driving method provided by the embodiment of the present invention has the corresponding technical features of any of the above pixel compensation circuits, the same technical problem can be solved, and the same technical effect is produced.
  • An embodiment of the present invention provides an array substrate.
  • the array substrate includes Any of the above pixel compensation circuits.
  • FIG. 12 is an array substrate including a pixel compensation circuit including a leakage preventing transistor VT6.
  • the array substrate may also be composed of a pixel compensation circuit that does not include a potential compensation unit.
  • the array substrate provided by the embodiment of the present invention has the same technical features as any of the above pixel compensation circuits, the same technical problem can be solved, and the same technical effect is produced.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种像素补偿电路、阵列基板和显示装置，属于半导体技术领域。所述像素补偿电路包括电荷存储单元（1），第一端接入电源电压信号；驱动单元（2），控制端与电荷存储单元（1）的第二端连接，用于在电荷存储单元（1）的第二端的电压大于驱动单元（2）的阈值电压时产生驱动OLED发光的驱动电流；复位单元（3），与电荷存储单元（1）的第二端连接，用于在复位阶段将初始电压信号的电压写入电荷存储单元（1）的第二端；数据写入单元（4），与电荷存储单元（1）的第二端连接，用于在数据写入阶段将数据电压信号的电压与驱动单元（2）的阈值电压写入电荷存储单元（1）的第二端；发光控制单元（5），与驱动单元（2）连接，用于在发光阶段控制电源电压信号写入驱动单元（2）产生驱动电流。从而保证了数据的正确写入。

Description

一种像素驱动电路及方法、阵列基板和显示装置 技术领域
本发明涉及半导体技术领域，特别涉及一种像素驱动电路及方法、阵列基板和显示装置。
背景技术
有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，简称AMOLED)显示技术是一种应用于电视和移动设备中的显示技术，以其低功耗、低成本、大尺寸的特点在对功耗敏感的便携式电子设备中有着广阔的应用前景。
AMOLED中的有机发光二极管(Organic Light Emitting Diode，简称OLED)能够发光是由薄膜晶体管(Thin Film Transistor，简称TFT)产生的驱动电流驱动的。但是随着时间的变化，TFT的阈值电压可能会变化，造成向TFT输入相同的电压，但TFT产生的驱动电流不一致的问题，进而导致各个OLED的亮度不同，多个OLED组成的AMOLED的亮度不均匀，影响整个图像的显示效果。
发明内容
本发明实施例提供了一种像素驱动电路及方法、阵列基板和显示装置。
一方面，本发明实施例提供了一种像素驱动电路，用于驱动有机发光二极管发光，包括：
电荷存储单元，所述电荷存储单元的第一端接入电源电压信号；
驱动单元，所述驱动单元的控制端与所述电荷存储单元的第二端连接，用于在所述电荷存储单元的第二端的电压大于所述驱动单元的阈值电压时产生驱动所述有机发光二极管发光的驱动电流；
复位单元，与所述电荷存储单元的第二端连接，用于在复位阶段将初始电压信号的电压写入所述电荷存储单元的第二端；
数据写入单元，与所述电荷存储单元的第二端连接，用于在数据写入阶段将数据电压信号的电压与所述驱动单元的阈值电压写入所述电荷存储单元的第二端；以及
发光控制单元，与所述驱动单元连接，用于在发光阶段控制所述电源电压信号写入所述驱动单元以产生所述驱动电流。
具体地，所述驱动单元包括驱动晶体管，所述驱动晶体管的控制端与所述电荷存储单元的第二端连接，所述驱动晶体管的第一电极通过所述发光控制单元接入所述电源电压信号，所述驱动晶体管的第二电极通过所述发光控制单元与所述有机发光二极管连接。
具体地，所述复位单元包括第一晶体管，所述第一晶体管的控制端接入复位开关信号，所述第一晶体管的第一电极接入所述初始电压信号，所述第一晶体管的第二电极与所述电荷存储单元的第二端连接。
具体地，所述数据写入单元包括第二晶体管和第三晶体管，所述第二晶体管的控制端和所述第三晶体管的控制端均接入第一控制信号，所述第二晶体管的第一电极与所述驱动晶体管的控制端连接，所述第二晶体管的第二电极与所述驱动晶体管的第二电极连接，所述第三晶体管的第一电极接入所述数据电压信号，所述第三晶体管的第二电极与所述驱动晶体管的第一电极连接。
具体地，所述发光控制单元包括第四晶体管和第五晶体管，所述第四晶体管的控制端和所述第五晶体管的控制端均接入第二控制信号，所述第四晶体管的第一电极连接所述电源电压信号，所述第四晶体管的第二电极连接所述驱动晶体管的第一电极，所述第五晶体管的第一电极连接所述驱动晶体管的第二电极，所述第五晶体管的第二电极连接所述有机发光二极管。
可选地，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为薄膜晶体管。
在本发明一种可能的实现方式中，所述像素驱动单元还包括：
电位补偿单元，与所述驱动单元的控制端连接，用于在所述发光阶段为所述驱动单元的控制端提供漏电补偿。
可选地，所述电位补偿单元包括防漏电晶体管，所述防漏电晶体管的控制端接入第三控制信号，所述防漏电晶体管的第一电极接入所述电源电压信号，所述防漏电晶体管的第二电极与所述驱动晶体管的控制端连接。
可选地，所述第三控制信号与所述第二控制信号同相。
可选地，所述初始电压信号为电平恒定的信号。
在本发明另一种可能的实现方式中，所述初始电压信号与所述第二控制信号反相。
另一方面，本发明实施例提供了一种像素驱动方法，应用于上述像素驱动电路，包括：
在复位阶段，复位开关信号将复位单元导通，所述复位单元将初始电压信号的电压写入电荷存储单元；
在数据写入阶段，第一控制信号将所述数据写入单元导通，所述数据写入单元将数据电压信号的电压与驱动单元的阈值电压写入所述电荷存储单元，所述驱动单元在写入所述电荷存储单元的电压大于所述驱动单元的阈值电压时产生驱动有机发光二极管发光的驱动电流；以及
在发光阶段，第二控制信号将发光控制单元导通，所述发光控制单元控制所述电源电压信号写入所述驱动单元以产生所述驱动电流。
在本发明一种可能的实现方式中，所述像素驱动方法还包括：
在所述发光阶段，第三控制信号将所述电位补偿单元导通，所述电位补偿单元为所述驱动单元的控制端提供漏电补偿。
可选地，所述第三控制信号与所述第二控制信号同相。
可选地，所述初始电压信号为电平恒定的信号。
在本发明另一种可能的实现方式中，所述初始电压信号与所述第二控制信号反相。
又一方面，本发明实施例提供了一种阵列基板，包括上述任一种像素补偿电路。
又一方面，本发明实施例提供了一种显示装置，包括上述任一种阵列基板。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本发明的一些实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种像素驱动电路的结构示意图；
图2是本发明实施例提供的像素驱动电路的一种具体实现电路的 结构示意图；
图3是本发明实施例提供的像素驱动电路的一种控制信号的时序图；
图4是本发明实施例提供的复位阶段的电流通路示意图；
图5是本发明实施例提供的数据写入阶段的电流通路示意图；
图6是本发明实施例提供的发光阶段的电流通路示意图；
图7是本发明实施例提供的漏电产生的结构示意图；
图8是本发明实施例提供的像素驱动电路的另一种具体实现电路的结构示意图；
图9是本发明实施例提供的像素驱动电路的另一种控制信号的时序图；
图10是本发明实施例提供的防漏电的结构示意图；
图11是本发明实施例提供的一种像素驱动方法的流程图；
图12是本发明实施例提供的一种阵列基板的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明实施例提供了一种像素驱动电路，用于驱动有机发光二极管发光，参见图1。该像素驱动电路包括：
电荷存储单元1，电荷存储单元1的第一端接入电源电压信号；
驱动单元2，驱动单元2的控制端与电荷存储单元1的第二端连接，用于在电荷存储单元1的第二端的电压大于驱动单元1的阈值电压时产生驱动有机发光二极管OLED发光的驱动电流；
复位单元3，与电荷存储单元1的第二端连接，用于在复位阶段将初始电压信号INIT的电压写入电荷存储单元1的第二端；
数据写入单元4，与电荷存储单元1的第二端连接，用于在数据写入阶段将数据电压信号DATA的电压与驱动单元2的阈值电压写入电荷存储单元1的第二端；以及
发光控制单元5，与驱动单元2连接，用于在发光阶段控制电源电压信号写入驱动单元2产生驱动电流。
其中，驱动单元2的阈值电压为驱动单元2导通所需达到的电压。
复位单元3的控制端接入复位开关信号RES，复位开关信号RES控制复位单元3是否导通。数据写入单元4的控制端接入第一控制信号GATE，第一控制信号GATE为扫描信号，第一控制信号GATE控制数据写入单元4是否导通。发光控制单元5的控制端接入第二控制信号EM，第二控制信号EM为发光控制信号，第二控制信号EM控制发光控制单元5是否导通。
可以理解地，数据写入单元4在数据写入阶段将数据电压信号DATA的电压与驱动单元2的阈值电压写入电荷存储单元1的第二端。驱动单元2在电荷存储单元1的第二端的电压大于驱动单元2的阈值电压时产生驱动有机发光二极管OLED发光的驱动电流。因此在发光阶段，驱动单元2的控制端的电压中所包含的阈值电压与驱动单元2导通而降低的阈值电压抵消，驱动单元2产生的驱动电流不受驱动单元2的阈值电压的影响，驱动电流可以保持一致，各个有机发光二极管OLED的亮度相同，整个图像的显示效果好。
具体地，电荷存储单元1可以为电容器。
更具体地，参见图2，电荷存储单元1可以包括存储电容器Cst，驱动单元2可以包括驱动晶体管VT0，复位单元3可以包括第一晶体管VT1，数据写入单元4可以包括第二晶体管VT2和第三晶体管VT3，发光控制单元5可以包括第四晶体管VT4和第五晶体管VT5。
存储电容器Cst的第一极板接入电源电压信号VDD。
驱动晶体管VT0的栅极与存储电容器Cst的第二极板连接，驱动晶体管VT0的漏极通过发光控制单元5与有机发光二极管OLED连接，驱动晶体管VT0的源极通过发光控制单元5接入电源电压信号VDD。
第一晶体管VT1的栅极接入复位开关信号RES，第一晶体管VT1的第二电极与存储电容器Cst的第二极板连接，第一晶体管VT1的第一电极接入初始电压信号INIT。
第二晶体管VT2的栅极和第三晶体管VT3的栅极均接入第一控制信号GATE，第二晶体管VT2的第一电极与驱动晶体管VT0的栅极连接，第二晶体管VT2的第二电极与驱动晶体管VT0的漏极连接，第三晶体管VT3的第一电极接入数据电压信号DATA，第三晶体管VT3的第二电极与驱动晶体管VT0的源极连接。
第四晶体管VT4和第五晶体管VT5的栅极均接入第二控制信号 EM，第四晶体管VT4的第一电极和第二电极串联在电源电压信号VDD和驱动晶体管VT0的源极之间，第五晶体管VT5的第一电极和第二电极串联在驱动晶体管VT0的漏极和有机发光二极管OLED之间。具体地，第四晶体管VT4的第一电极连接电源电压信号VDD，第四晶体管VT4的第二电极连接驱动晶体管VT0的第一电极，第五晶体管VT5的第一电极连接驱动晶体管VT0的第二电极，第五晶体管VT5的第二电极连接有机发光二极管OLED。
进一步地，驱动晶体管VT0、第一晶体管VT1、第二晶体管VT2、第三晶体管VT3、第四晶体管VT4和第五晶体管VT5可以均为薄膜晶体管，其体积小、功耗低、控制方便准确。
可选地，驱动晶体管VT0可以为P沟道增强型金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor，简称MOSFET)，也可以为P型双极结型晶体管(Bipolar Junction Transistor，简称BJT)。
可选地，第一至第五晶体管VT1-VT5可以分别为结型场效应晶体管(Junction Field Effect Transistor，简称JFET)、增强型MOSFET、耗尽型MOSFET和BJT中的一种或多种。
可选地，第一至第五晶体管VT1-VT5均可以为P型晶体管，也可以为N型晶体管。当第一至第五晶体管VT1-VT5为P型晶体管时，第一电极为源极，第二电极为漏极；当第一至第五晶体管VT1-VT5为N型晶体管时，第一电极为漏极，第二电极为源极。
图3是本发明实施例提供的像素驱动电路的控制信号的时序图。需要说明的是，图3所示的时序图以各晶体管均为P型晶体管为例，本发明并不限制于此。
如图3所示，该像素补偿电路的控制信号的时序包括复位阶段T11、数据写入阶段T12、发光阶段T13三个阶段。图4为复位阶段的电流通路示意图，图5为数据写入阶段的电流通路示意图，图6为发光阶段的电流通路示意图。为了说明方便，图4-图6中用箭头标出了各阶段电流的通路，并将起作用的元器件用实线标示，不起作用的元器件用虚线标示。
在复位阶段T11，参见图3和图4，复位开关信号RES为低电平，复位开关信号RES控制的第一晶体管VT1导通。存储电容器Cst的第 一极板输入电源电压信号VDD，存储电容器Cst的第二极板输入初始电压信号INIT，存储电容器Cst由于第一极板和第二极板之间的电压差变大而充电，初始电压信号INIT的电压写入存储电容器Cst的第二极板。此时，A点的电位与初始电压信号INIT一致，A点为驱动晶体管VT0的栅极与存储电容器Cst的第二极板的连接点。
第一控制信号GATE为高电平，第一控制信号GATE控制的第二晶体管VT2、第三晶体管VT3截止。第二控制信号EM和第三控制信号VL为高电平，第二控制信号EM控制的第四晶体管VT4和第五晶体管VT5、第三控制信号VL控制的防漏电晶体管VT6截止。
在数据写入阶段T12，参见图3和图5，复位开关信号RES为高电平，复位开关信号RES控制的第一晶体管VT1截止。
第一控制信号GATE为低电平，第一控制信号GATE控制的第二晶体管VT2、第三晶体管VT3导通。第二晶体管VT2导通，分别与第二晶体管VT2的第一电极和第二电极连接的驱动晶体管VT0的栅极和漏极连通而短路，驱动晶体管VT0只有其栅极和源极之间的PN结有效，驱动晶体管VT0处于二极管连接方式。第三晶体管VT3导通，第三晶体管VT3的第一电极接入的数据电压信号DATA，传输至与第三晶体管VT3的第二电极连接的驱动晶体管VT0的源极。此时，B点的电位与数据电压信号DATA一致，B点为驱动晶体管VT0的源极的连接点。由于驱动晶体管VT0只有其栅极和源极之间的PN结有效，此时A点的电位变为VDATA+Vth，VDATA为数据电压信号DATA的电位，Vth为PN结的阈值电压，存储电容器Cst由于第一极板和第二极板之间的电压差变小而放电。
第二控制信号EM和第三控制信号VL仍为高电平，第二控制信号EM控制的第四晶体管VT4和第五晶体管VT5、第三控制信号VL控制的防漏电晶体管VT6依然截止。
在发光阶段T13，参见图3和图6，复位开关信号RES和第一控制信号GATE为高电平，复位开关信号RES控制的第一晶体管VT1、第一控制信号GATE控制的第二晶体管VT2和第三晶体管VT3截止。
第二控制信号EM为低电平，第二控制信号EM控制的第四晶体管VT4、第五晶体管VT5导通。加上此时A点的电位维持为VDATA+Vth，驱动晶体管VT0导通且工作在饱和区，所以第四晶体管 VT4、驱动晶体管VT0、第五晶体管VT5、有机发光二极管OLED形成通路，驱动晶体管VT0产生驱动电流。此时，C点的电位为VOLED，C点为驱动晶体管VT0的漏极的连接点，VOLED为有机发光二极管OLED的发光电压。驱动电流Id＝F(Vgs)＝F(驱动晶体管栅极电位-驱动晶体管源极电位)＝F(驱动晶体管栅极电位-(驱动晶体管漏极电位+驱动晶体管源极与漏极之间的电压差))＝F(A点电位-(C点电位+驱动晶体管源极与漏极之间的电压差))＝F(VDATA+Vth-VOLED-Vth)＝F(VDATA-VOLED)，F(*)表示以*为变量的函数，Vgs为栅极与源极之间的电压。从公式Id＝F(VDATA-VOLED)可以看出，驱动电流的大小与PN结的阈值电压无关，本发明实施例提供的像素驱动电路可以补偿阈值电压漂移而造成的驱动电流偏差，产生一致的驱动电流，保证AMOLED中各OLED亮度的均匀性。
需要说明的是，如图7所示，在发光阶段，存储电容器Cst存储的电荷会通过第一晶体管VT1和第二晶体管VT2漏电(漏电方向如图7箭头所示)，存储电容器Cst存储的电荷量减少，存储电容器Cst的第二端的电位降低，驱动晶体管VT0的栅极电位降低，驱动晶体管VT0的栅极和源极之间的电压差增大，驱动晶体管VT0产生的驱动电流增大，OLED发光变强，严重时会导致不能写入正确的显示数据的问题。
本实施例可以解决上述问题，如图2所示，该像素驱动电路还可以包括：
电位补偿电路6，与驱动单元2的控制端连接，用于在发光阶段为驱动单元的控制端提供漏电补偿。
具体地，电位补偿单元6可以包括防漏电晶体管VT6，防漏电晶体管VT6的栅极接入第三控制信号VL，防漏电晶体管VT6的第一电极接入电源电压信号VDD，防漏电晶体管VT6的第二电极与驱动晶体管VT0的栅极连接。
可以理解地，防漏电晶体管VT6在发光阶段将电源电压信号VDD与驱动单元2的控制端连通，有效弥补和平衡了驱动单元2的控制端由于电荷存储单元1和驱动单元2之间的通路漏电而降低的电位，使驱动单元2的控制端的电位可以与数据电压保持一致，保证了数据的正确写入，OLED正常发光。另外，由于平衡了漏电，电荷存储单元1可以选择容量较小的电容器，降低电荷存储单元1的体积(电容器的 体积与容量成正比)，进而有效减小像素的面积，使得单位面积的像素数量增多，提升了整个面板的图像分辨率。
可选地，防漏电晶体管VT6可以为JFET、增强型MOSFET、耗尽型MOSFET和BJT中的任一种。
可选地，防漏电晶体管VT6可以为P型晶体管，也可以为N型晶体管。当防漏电晶体管VT6为P型晶体管时，第一电极为源极，第二电极为漏极；当防漏电晶体管VT6为N型晶体管时，第一电极为漏极，第二电极为源极。
可选地，如图3所示，第三控制信号VL可以与第二控制信号EM同相。
可以理解地，第三控制信号VL和第二控制信号EM波形相同，可以采用同一信号线提供，不需要使用复杂的工艺实现，一方面节约了成本，另一方面也降低了电路的设计难度。
具体地，如图3所示，初始电压信号INIT可以为电平恒定的信号。
在其它实现中，初始电压信号INIT也可以与第二控制信号EM反相。
可以理解地，在发光阶段，第二控制信号EM为低电平，初始电压信号INIT为高电平(与第二控制信号EM反相)，可以产生从接入的初始电压信号INIT到驱动晶体管VT0的栅极的漏电流，平衡和弥补了通过第二晶体管VT2消耗的漏电流，同时也抑制了从驱动晶体管VT0的栅极到接入的初始电压信号INIT消耗的漏电流，进一步加强了保持驱动晶体管VT0的栅极的电位不变的效果，保证了数据的正确写入，OLED正常发光。而且，初始电压信号INIT与第二控制信号EM反相，通过将第二控制信号EM反相得到初始电压信号INIT，不需要使用复杂的工艺实现，一方面节约了成本，另一方面也降低了电路的设计难度。
本发明实施例通过数据写入单元在数据写入阶段将数据电压信号的电压与驱动单元的阈值电压写入电荷存储单元的第二端，在电荷存储单元的第二端的电压大于驱动单元的阈值电压时产生驱动有机发光二极管发光的驱动电流，因此在发光阶段，驱动单元的控制端的电压中所包含的阈值电压与驱动单元导通而降低的阈值电压抵消，驱动单元产生的驱动电流不受驱动单元的阈值电压的影响，驱动电流可以保 持一致，各个有机发光二极管的亮度相同，整个图像的显示效果好。
本发明实施例提供了另一种像素驱动电路，与图2所示的像素驱动电路的不同之处在于，如图8所示，该像素驱动电路不需要设置电位补偿电路，只需要初始电压信号INIT与第二控制信号EM反相(详见图9)。
可以理解地，如图9所示(图9以各晶体管为P型晶体管为例)，初始电压信号INIT与第二控制信号EM反相，初始电压信号INIT在发光阶段为高电平，产生从接入的初始电压信号INIT到驱动晶体管VT0的栅极的漏电流(电流方向如图10箭头所示)，平衡和弥补了通过第二晶体管VT2消耗的漏电流，同时也抑制了从驱动晶体管VT0的栅极到接入的初始电压信号INIT消耗的漏电流，保持驱动晶体管VT0的栅极的电位不变，有效弥补和平衡了驱动晶体管VT0的栅极由于存储电容器Cst与驱动晶体管VT0之间的通路漏电而降低的电位，使驱动晶体管VT0的栅极电位可以与数据电压保持一致，保证了数据的正确写入，OLED正常发光，并且不需要增加任何元器件。另外，由于平衡了漏电，可以选择容量较小的存储电容器，降低存储电容器的体积(存储电容器的体积与容量成正比)，进而有效减小像素的面积，使得单位面积的像素数量增多，提升了整个面板的图像分辨率。进一步地，初始电压信号INIT与第二控制信号EM反相，通过将第二控制信号EM反相得到初始电压信号INIT，不需要使用复杂的工艺实现，一方面节约了成本，另一方面也降低了电路的设计难度。
本发明实施例通过数据写入单元在数据写入阶段将数据电压信号的电压与驱动单元的阈值电压写入电荷存储单元的第二端，在电荷存储单元的第二端的电压大于驱动单元的阈值电压时产生驱动有机发光二极管发光的驱动电流，因此在发光阶段，驱动单元的控制端的电压中所包含的阈值电压与驱动单元导通而降低的阈值电压抵消，驱动单元产生的驱动电流不受驱动单元的阈值电压的影响，驱动电流可以保持一致，各个有机发光二极管的亮度相同，整个图像的显示效果好。
本发明实施例提供了一种像素驱动方法，应用于上述的像素驱动电路，参见图11，包括：
步骤S11：在复位阶段，复位开关信号将复位单元导通，复位单元将初始电压信号的电压写入电荷存储单元。
具体地，结合图2，在复位阶段，复位开关信号RES控制第一晶体管VT1导通，第一控制信号GATE控制第二晶体管VT2和第三晶体管VT3截止，第二控制信号EM控制第四晶体管VT4和第五晶体管VT5截止。
步骤S12：在数据写入阶段，第一控制信号将数据写入单元导通，数据写入单元将数据电压信号的电压与驱动单元的阈值电压写入电荷存储单元，驱动单元在写入电荷存储单元的电压大于驱动单元的阈值电压时产生驱动有机发光二极管发光的驱动电流。
具体地，结合图2，在数据写入阶段，复位开关信号RES控制第一晶体管VT1截止，第一控制信号GATE控制第二晶体管VT2和第三晶体管VT3导通，第二控制信号EM控制第四晶体管VT4和第五晶体管VT5截止。
步骤S13：在发光阶段，第二控制信号将发光控制单元导通，发光控制单元控制电源电压信号写入驱动单元产生驱动电流。
具体地，结合图2，在发光阶段，复位开关信号RES控制第一晶体管VT1截止，第一控制信号GATE控制第二晶体管VT2和第三晶体管VT3截止，第二控制信号EM控制第四晶体管VT4和第五晶体管VT5导通。
在本实施例的一种实现方式中，该像素驱动方法还可以包括：
在发光阶段，第三控制信号将电位补偿单元导通，电位补偿单元为驱动单元的控制端提供漏电补偿。
具体地，结合图2，在发光阶段，第三控制信号VL控制防漏电晶体管VT6导通。
可选地，第三控制信号VL可以与第二控制信号EM同相。
可选地，初始电压信号INIT也可以为电平恒定的信号。
可选地，初始电压信号INIT可以与第二控制信号EM反相。
在本实施例的另一种实现方式中，初始电压信号INIT可以与第二控制信号EM反相。
由于本发明实施例提供的像素驱动方法与上述任一种像素补偿电路具有相应的技术特征，所以也能解决同样的技术问题，产生相同的技术效果。
本发明实施例提供了一种阵列基板，参见图12，该阵列基板包括 上述任一种像素补偿电路。
需要说明的是，图12是以包括防漏电晶体管VT6的像素补偿电路为例的阵列基板，在实际应用中，阵列基板也可以由不包括电位补偿单元的像素补偿电路组成。
由于本发明实施例提供的阵列基板与上述任一种像素补偿电路具有相同的技术特征，所以也能解决同样的技术问题，产生相同的技术效果。
本发明实施例还提供了一种显示装置，该显示装置包括上述任一种阵列基板。该显示装置可以为：电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于本发明实施例提供的显示装置与上述任一种阵列基板具有相同的技术特征，所以也能解决同样的技术问题，产生相同的技术效果。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (18)

  1. 一种像素驱动电路，用于驱动有机发光二极管发光，包括：
    电荷存储单元，所述电荷存储单元的第一端接入电源电压信号；
    驱动单元，所述驱动单元的控制端与所述电荷存储单元的第二端连接，用于在所述电荷存储单元的第二端的电压大于所述驱动单元的阈值电压时产生驱动所述有机发光二极管发光的驱动电流；
    复位单元，与所述电荷存储单元的第二端连接，用于在复位阶段将初始电压信号的电压写入所述电荷存储单元的第二端；
    数据写入单元，与所述电荷存储单元的第二端连接，用于在数据写入阶段将数据电压信号的电压与所述驱动单元的阈值电压写入所述电荷存储单元的第二端；以及
    发光控制单元，与所述驱动单元连接，用于在发光阶段控制所述电源电压信号写入所述驱动单元以产生所述驱动电流。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动单元包括驱动晶体管，所述驱动晶体管的控制端与所述电荷存储单元的第二端连接，所述驱动晶体管的第一电极通过所述发光控制单元接入所述电源电压信号，所述驱动晶体管的第二电极通过所述发光控制单元与所述有机发光二极管连接。
  3. 根据权利要求2所述的像素驱动电路，其中，所述复位单元包括第一晶体管，所述第一晶体管的控制端接入复位开关信号，所述第一晶体管的第一电极接入所述初始电压信号，所述第一晶体管的第二电极与所述电荷存储单元的第二端连接。
  4. 根据权利要求3所述的像素驱动电路，其中，所述数据写入单元包括第二晶体管和第三晶体管，所述第二晶体管的控制端和所述第三晶体管的控制端均接入第一控制信号，所述第二晶体管的第一电极与所述驱动晶体管的控制端连接，所述第二晶体管的第二电极与所述驱动晶体管的第二电极连接，所述第三晶体管的第一电极接入所述数据电压信号，所述第三晶体管的第二电极与所述驱动晶体管的第一电极连接。
  5. 根据权利要求4所述的像素驱动电路，其中，所述发光控制单元包括第四晶体管和第五晶体管，所述第四晶体管的控制端和所述第 五晶体管的控制端均接入第二控制信号，所述第四晶体管的第一电极连接所述电源电压信号，所述第四晶体管的第二电极连接所述驱动晶体管的第一电极，所述第五晶体管的第一电极连接所述驱动晶体管的第二电极，所述第五晶体管的第二电极连接所述有机发光二极管。
  6. 根据权利要求5所述的像素驱动电路，其中，所述驱动晶体管、所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管和所述第五晶体管均为薄膜晶体管。
  7. 根据权利要求5所述的像素驱动电路，其中，所述像素驱动单元还包括：
    电位补偿单元，与所述驱动单元的控制端连接，用于在所述发光阶段为所述驱动单元的控制端提供漏电补偿。
  8. 根据权利要求7所述的像素驱动电路，其中，所述电位补偿单元包括防漏电晶体管，所述防漏电晶体管的控制端接入第三控制信号，所述防漏电晶体管的第一电极接入所述电源电压信号，所述防漏电晶体管的第二电极与所述驱动晶体管的控制端连接。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第三控制信号与所述第二控制信号同相。
  10. 根据权利要求1所述的像素驱动电路，其中，所述初始电压信号为电平恒定的信号。
  11. 根据权利要求5所述的像素驱动电路，其中，所述初始电压信号与所述第二控制信号反相。
  12. 一种像素驱动方法，应用于如权利要求1-11任一项所述的像素驱动电路，包括：
    在复位阶段，复位开关信号将复位单元导通，所述复位单元将初始电压信号的电压写入电荷存储单元；
    在数据写入阶段，第一控制信号将所述数据写入单元导通，所述数据写入单元将数据电压信号的电压与驱动单元的阈值电压写入所述电荷存储单元，所述驱动单元在写入所述电荷存储单元的电压大于所述驱动单元的阈值电压时产生驱动有机发光二极管发光的驱动电流；以及
    在发光阶段，第二控制信号将发光控制单元导通，所述发光控制单元控制所述电源电压信号写入所述驱动单元以产生所述驱动电流。
  13. 根据权利要求12所述的像素驱动方法，其中，所述像素驱动电路还包括与所述驱动单元的控制端连接的电位补偿单元，所述像素驱动方法还包括：
    在所述发光阶段，第三控制信号将所述电位补偿单元导通，所述电位补偿单元为所述驱动单元的控制端提供漏电补偿。
  14. 根据权利要求13所述的像素驱动方法，其中，所述第三控制信号与所述第二控制信号同相。
  15. 根据权利要求12所述的像素驱动方法，其中，所述初始电压信号为电平恒定的信号。
  16. 根据权利要求12所述的像素驱动方法，其中，所述初始电压信号与所述第二控制信号反相。
  17. 一种阵列基板，包括如权利要求1-11任一项所述的像素驱动电路。
  18. 一种显示装置，包括如权利要求17所述的阵列基板。
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