WO2016176949A1 - 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 - Google Patents

薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 Download PDF

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WO2016176949A1
WO2016176949A1 PCT/CN2015/089995 CN2015089995W WO2016176949A1 WO 2016176949 A1 WO2016176949 A1 WO 2016176949A1 CN 2015089995 W CN2015089995 W CN 2015089995W WO 2016176949 A1 WO2016176949 A1 WO 2016176949A1
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substrate
shielding layer
thin film
layer
film transistor
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PCT/CN2015/089995
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English (en)
French (fr)
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宋萍
李红敏
薛伟
董职福
古宏刚
李小和
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/034,827 priority Critical patent/US20170115540A1/en
Publication of WO2016176949A1 publication Critical patent/WO2016176949A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
    • G02F1/133723—Polyimide, polyamide-imide
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133788—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by light irradiation, e.g. linearly polarised light photo-polymerisation

Definitions

  • Embodiments of the present disclosure relate to a thin film transistor, a method of fabricating the same, an array substrate, a method of fabricating the same, a display panel, and a display device.
  • the TFT substrate Thin Film Transistor Liquid Crystal Display
  • the CF substrate Color Filer substrate
  • Alignment film (PI) printing and alignment treatment are separately required.
  • the commonly used PI alignment processing method is a rubbing rubbing process, which is aligned by a rubbing process, and the alignment of the liquid crystal molecules is controlled by the alignment film to ensure that the liquid crystal molecules can be aligned in the correct direction.
  • the friction process is gradually being replaced by photo-alignment technology.
  • Light alignment uses ultraviolet light to optically align the alignment material with high light sensitivity and good stability, and has the advantages of high opening, high contrast, fast response, etc., and can effectively prevent electrostatic discharge (ESD) in the friction process. Poor, reduced PI's various stripes and poor particles.
  • ESD electrostatic discharge
  • the active layer characteristics of the TFT device in the pixel structure are affected, resulting in a large leakage current, which affects the characteristics of the TFT, resulting in crosstalk and the like.
  • At least one embodiment of the present disclosure provides a thin film transistor including an active layer on a substrate, and an ultraviolet shielding layer on a side of the active layer facing away from the substrate And a projection of the active layer on the substrate is located within a projection of the ultraviolet shielding layer on the substrate.
  • the active layer is completely covered by the ultraviolet shielding layer in a direction perpendicular to the substrate, and the ultraviolet shielding layer blocks the ultraviolet light, and the ultraviolet shielding layer can be effectively used in the optical alignment process. Eliminating the influence of ultraviolet light on the active layer of the thin film transistor, thereby ensuring that the performance of the thin film transistor is not affected by ultraviolet light.
  • the performance of the above thin film transistor is not affected by the ultraviolet light irradiation during the photoalignment process.
  • the thin film transistor further includes a source/drain electrode on a side of the active layer facing away from the substrate substrate, the ultraviolet light shielding layer being located at the source/drain electrode facing away from the lining One side of the base substrate.
  • At least one embodiment of the present disclosure provides an array substrate including a substrate substrate, further including any of the above thin film transistors.
  • the material of the ultraviolet shielding layer is an ultraviolet light absorbing material.
  • the ultraviolet light absorbing material is indium tin oxide.
  • the array substrate further includes a pixel electrode located on a side of the thin film transistor from which the source and drain electrodes face away from the substrate, and when the ultraviolet shielding layer is located at the source and drain electrodes
  • the ultraviolet shielding layer is disposed in the same layer as the pixel electrode when facing away from a side of the substrate substrate; or
  • the array substrate further includes a common electrode on a side of the thin film transistor from which the source and drain electrodes face away from the substrate, and when the ultraviolet shielding layer is located on a side of the source and drain electrodes facing away from the substrate
  • the ultraviolet shielding layer is disposed in the same layer as the common electrode.
  • a display panel comprising any of the above array substrates.
  • a display device comprising any of the above display panels.
  • a method of preparing a thin film transistor comprising:
  • the method further includes:
  • a source/drain electrode is formed on a side of the active layer facing away from the base substrate.
  • a method for preparing an array substrate comprising the method for preparing a thin film transistor according to any one of the above aspects.
  • the material of the ultraviolet shielding layer is an ultraviolet light absorbing material.
  • the material of the ultraviolet shielding layer is indium tin oxide.
  • the array substrate further includes a pixel electrode located at a side of the thin film transistor with a source/drain electrode facing away from the substrate substrate, and the ultraviolet light shielding layer and the When the pixel electrode is disposed in the same layer, the ultraviolet shielding layer is formed on a side of the active layer facing away from the substrate, and specifically includes:
  • a pixel electrode layer is formed on a side of the thin film transistor whose source and drain electrodes face away from the base substrate, and a pattern of the pixel electrode and a pattern of the ultraviolet light shielding layer are formed by one patterning process.
  • the array substrate further includes a common electrode on a side of the thin film transistor whose source and drain electrodes face away from the substrate, and the ultraviolet light shielding layer is the same as the common electrode When the layer is disposed, the ultraviolet shielding layer is formed on a side of the active layer facing away from the substrate, and includes:
  • a common electrode layer is formed on a side of the thin film transistor whose source and drain electrodes face away from the base substrate, and a pattern of the common electrode and a pattern of the ultraviolet light shielding layer are formed by one patterning process.
  • FIG. 1 is a partial structural schematic view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a partial cross-sectional structural view of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic flow chart of a method of fabricating a thin film transistor according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a thin film transistor 2 including an active layer 21 on a substrate 1 and a side of the active layer 21 facing away from the substrate 1.
  • the active layer 21 is completely covered by the ultraviolet light shielding layer 3, and the ultraviolet light shielding layer 3 can block ultraviolet light, so that the ultraviolet light shielding layer 3 can effectively avoid the ultraviolet light to the active layer during the light alignment process.
  • the influence of 21, thereby ensuring that the performance of the thin film transistor 2 is not affected by ultraviolet light. Therefore, the performance of the above thin film transistor 2 is not affected by the ultraviolet light irradiation during the photoalignment process.
  • the thin film transistor 2 may further include a source/drain electrode 23 on the side of the active layer 21 facing away from the substrate 1, and the ultraviolet shielding layer 3 is located at the source and drain electrodes. 23 faces away from the side of the base substrate 1.
  • the thin film transistor 2 may further include a gate electrode 22 and a gate insulating layer 24 disposed between the active layer 21 and the base substrate 1.
  • the ultraviolet shielding layer 3 may be made of an ultraviolet light absorbing material.
  • the ultraviolet light absorbing material blocks the ultraviolet light by absorbing ultraviolet light.
  • the ultraviolet light absorbing material may be indium tin oxide.
  • the material of the ultraviolet shielding layer 3 is not limited to the above ultraviolet light absorbing material, and may be an ultraviolet light reflecting material such as a metal material.
  • an embodiment of the present disclosure further provides an array substrate including the thin film transistor 2 in any of the above embodiments.
  • the array substrate may further include a pixel electrode 4 on the side of the source/drain electrode 23 of the thin film transistor 2 facing away from the substrate 1 , and a source/drain electrode 23 and a pixel.
  • a passivation layer 25 is formed between the electrodes 4; since the pixel electrode 4 in the array substrate can be made of an indium tin oxide material, when the ultraviolet shielding layer 3 is located on the side of the source/drain electrode 23 facing away from the substrate 1
  • the ultraviolet shielding layer 3 can be disposed in the same layer as the pixel electrode 4.
  • the array substrate may include, in addition to the pixel electrode 4 on the side of the source/drain electrode 23 of the thin film transistor 2 facing away from the substrate 1 , and may also be located on the side of the pixel electrode 4 facing away from the substrate 1 .
  • the common electrode is formed with an insulating layer between the pixel electrode 4 and the common electrode; since the common electrode in the array substrate can also be made of indium tin oxide, when the ultraviolet shielding layer 3 is located at the source/drain electrode 23 away from the substrate 1 On one side, the ultraviolet shielding layer 3 can be disposed in the same layer as the common electrode.
  • the ultraviolet shielding layer is made of indium tin oxide
  • the ultraviolet shielding layer 3 is disposed in the same layer as the pixel electrode 4 or the common electrode in the array substrate, which simplifies the preparation process and can avoid ultraviolet rays.
  • the light affects the electrical conductivity of the conductive structure such as the active layer 21, the gate 22, the source 231, and the drain 232 in the thin film transistor 2, so that the influence on the performance of the thin film transistor 2 can be avoided.
  • the ultraviolet shielding layer 3 can also be formed between the active layer 21 of the thin film transistor 2 and the source and drain electrodes 23; when the ultraviolet shielding layer 3 is formed between the active layer 21 of the thin film transistor 2 and the source and drain electrodes 23
  • the material of the ultraviolet shielding layer 3 may be a non-conductive material to avoid affecting the performance of the thin film transistor 2.
  • At least one embodiment of the present disclosure also provides a display panel comprising the array substrate of any of the above embodiments.
  • the array substrate in the display panel is not damaged by ultraviolet light, and the performance is stable and reliable.
  • At least one embodiment of the present disclosure also provides a display device including the display panel in the above embodiment.
  • the performance of the array substrate in the display device is stable and reliable, and it is possible to avoid problems such as crosstalk.
  • a method for preparing any of the above thin film transistors includes:
  • Step S101 forming an active layer 21 on the base substrate 1;
  • step S102 an ultraviolet shielding layer 3 is formed on a side of the active layer 21 facing away from the substrate 1; wherein the projection of the active layer 21 on the substrate 1 is located on the ultraviolet shielding layer 3 on the substrate 1. Inside the projection.
  • the active layer 21 is completely covered by the ultraviolet light shielding layer 3, and the ultraviolet light shielding layer 3 can block ultraviolet light, so that the ultraviolet light shielding layer 3 can effectively eliminate ultraviolet light during the light alignment process.
  • the influence on the active layer 21 can thereby ensure that the performance of the thin film transistor 2 is not affected by ultraviolet light irradiation.
  • the source and drain electrodes may be formed on a side of the active layer 21 facing away from the substrate 1.
  • the material of the ultraviolet shielding layer 3 may be an ultraviolet light absorbing material.
  • the ultraviolet light absorbing material acts to block ultraviolet light by absorbing ultraviolet light.
  • the ultraviolet light absorbing material may be indium tin oxide.
  • the material of the ultraviolet shielding layer 3 is not limited to the ultraviolet light absorbing material in the above embodiment. It can also be a UV light reflecting material such as a metal.
  • a method of preparing any of the above array substrates comprising the method of preparing a thin film transistor as described in any of the above embodiments.
  • the array substrate further includes a pixel electrode 4 located on a side of the thin film transistor 2 from which the source and drain electrodes 23 face away from the substrate 1
  • the ultraviolet shielding layer 3 is disposed in the same layer as the pixel electrode 4, in step S102, the ultraviolet shielding layer 3 is formed on the side of the active layer 21 facing away from the substrate 1 , which may include:
  • the array substrate further includes a common electrode located on a side of the thin film transistor 2 from which the source and drain electrodes 23 face away from the base substrate 1, and the ultraviolet light shielding layer 3 and the When the common electrode is disposed in the same layer, in step S102, the ultraviolet shielding layer 3 is formed on the side of the active layer 21 facing away from the substrate 1 , which may include:
  • a pixel electrode 4 is formed on a side of the thin film transistor 2 from which the source/drain electrode 23 faces away from the base substrate 1, an insulating layer is formed on a side of the pixel electrode 4 facing away from the base substrate 1, and a common electrode layer is formed on the insulating layer
  • the pattern of the common electrode and the pattern of the ultraviolet shielding layer 3 are formed by one patterning process.

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  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种薄膜晶体管(2)及其制备方法。所述薄膜晶体管(2)包括位于衬底基板(1)上的有源层(21)，还包括位于所述有源层(21)背离所述衬底基板(1)一侧的紫外光遮挡层(3)，且所述有源层(21)在所述衬底基板(1)上的投影位于所述紫外光遮挡层(3)在所述衬底基板(1)上的投影内。所述有源层(21)被所述紫外光遮挡层(3)完全覆盖，在光配向过程中，紫外光遮挡层(3)可以有效消除紫外光对薄膜晶体管(2)的有源层(21)的影响，保证薄膜晶体管(2)的性能不受紫外光照射的影响。

Description

薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 技术领域
本公开的实施例涉及一种薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板、显示装置。
背景技术
在TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)成盒工艺前需要在TFT基板(Thin Film Transistor substrate，薄膜晶体管基板)以及CF基板(Color Filer substrate，彩膜基板)上分别进行配向膜(PI)印刷以及进行配向处理。目前常用的PI配向处理方法是拓印摩擦(Rubbing)工艺，通过摩擦工艺进行配向，通过配向膜控制液晶分子的配向，保证液晶分子能够沿着正确的方向排列。随着分辨率和开口率以及对比度的需求越来越高，摩擦工艺逐渐被光配向技术取代。光配向使用紫外光对光敏感度高、稳定性好的配向材料进行光配向，具有高开口、高对比度、快速响应等优点，同时可以有效防止摩擦工艺中的静电释放(Electro Static Discharge,ESD)高发不良、降低PI的各种条纹和颗粒不良。
但是，光配向过程使用紫外光照射时，会影响像素结构中TFT器件的有源层特性，导致漏电流变大，从而影响TFT特性，导致产生串扰等不良。
发明内容
本公开的至少一个实施例提供了一种薄膜晶体管，所述薄膜晶体管包括位于衬底基板上的有源层，还包括位于所述有源层背离所述衬底基板一侧的紫外光遮挡层，且所述有源层在所述衬底基板上的投影位于所述紫外光遮挡层在所述衬底基板上的投影内。
上述薄膜晶体管中，有源层在垂直于衬底基板的方向上被所述紫外光遮挡层完全覆盖，紫外光遮挡层对紫外光有遮挡作用，在光配向过程中，紫外光遮挡层可以有效消除紫外光对薄膜晶体管有源层的影响，从而可以保证薄膜晶体管的性能不会受到紫外光照射的影响。
因此，上述薄膜晶体管的性能不会受到光配向过程中紫外光照射的影响。
在本公开的一个实施例中，所述薄膜晶体管还包括位于所述有源层背离所述衬底基板一侧的源漏电极，所述紫外光遮挡层位于所述源漏电极背离所述衬底基板的一侧。
本公开的至少一个实施例提供了一种阵列基板，包括衬底基板，还包括上述任一种薄膜晶体管。
在本公开的一个实施例中，所述紫外光遮挡层的材料为紫外光吸收材料。
在本公开的一个实施例中，所述紫外光吸收材料为氧化铟锡。
在本公开的一个实施例中，所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的像素电极，且当所述紫外光遮挡层位于所述源漏电极背离所述衬底基板的一侧时，所述紫外光遮挡层与所述像素电极同层设置；或者，
所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的公共电极，且当所述紫外光遮挡层位于所述源漏电极背离所述衬底基板的一侧时，所述紫外光遮挡层与所述公共电极同层设置。
一种显示面板，包括上述任一种阵列基板。
一种显示装置，包括上述任一种显示面板。
一种薄膜晶体管的制备方法，包括：
在衬底基板上形成有源层；
在有源层背离衬底基板的一侧形成紫外光遮挡层；其中，所述有源层在所述衬底基板上的投影位于所述紫外光遮挡层在所述衬底基板上的投影内。
在本公开的一个实施例中，在衬底基板上形成有源层之后，以及在有源层背离衬底基板的一侧形成紫外光遮挡层之前，还包括：
在所述有源层背离所述衬底基板的一侧形成源漏电极。
一种阵列基板的制备方法，包括如上述任一技术方案中所述的薄膜晶体管的制备方法。
在本公开的一个实施例中，所述紫外光遮挡层的材料为紫外光吸收材料。
在本公开的一个实施例中，所述紫外光遮挡层的材料为氧化铟锡。
在本公开的一个实施例中，当所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的像素电极、且所述紫外光遮挡层与所述 像素电极同层设置时，所述在有源层背离衬底基板的一侧形成紫外光遮挡层，具体包括：
在所述薄膜晶体管的源漏电极背离所述衬底基板的一侧形成像素电极层，通过一次构图工艺形成所述像素电极的图形和所述紫外光遮挡层的图形。
在本公开的一个实施例中，当所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的公共电极、且所述紫外光遮挡层与所述公共电极同层设置时，所述在有源层背离衬底基板的一侧形成紫外光遮挡层，包括：
在所述薄膜晶体管的源漏电极背离所述衬底基板的一侧形成公共电极层，通过一次构图工艺形成所述公共电极的图形和所述紫外光遮挡层的图形。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为根据本公开的一个实施例的一种阵列基板的部分结构示意图；
图2为根据本公开的一个实施例的一种阵列基板的部分截面结构示意图；以及
图3为根据本公开的一个实施例的一种薄膜晶体管的制备方法流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1和图2所示，本公开的一个实施例提供了一种薄膜晶体管2，包括位于衬底基板1上的有源层21，还包括位于有源层21背离衬底基板1一侧的紫外光遮挡层3，且有源层21在衬底基板1上的投影位于紫外光遮挡层 3在衬底基板1上的投影内。
上述薄膜晶体管2中，有源层21被紫外光遮挡层3完全覆盖，紫外光遮挡层3可以遮挡紫外光，因此在光配向过程中，紫外光遮挡层3可以有效避免紫外光对有源层21的影响，从而可以保证薄膜晶体管2的性能不会受到紫外光照射的影响。因此，上述薄膜晶体管2的性能不会受到光配向过程中紫外光照射的影响。
如图1和图2所示，在本公开的一个实施例，薄膜晶体管2还可以包括位于有源层21背离衬底基板1一侧的源漏电极23，紫外光遮挡层3位于源漏电极23背离衬底基板1的一侧。如图2所示，薄膜晶体管2还可以包括设置在有源层21与衬底基板1之间的栅极22和栅绝缘层24。
在本公开的一个实施例，紫外光遮挡层3可以紫外光吸收材料制成。紫外光吸收材料通过对紫外光的吸收起到遮挡紫外光的作用。
在本公开的一个实施例，上述紫外光吸收材料可以为氧化铟锡。
当然，紫外光遮挡层3的材料并不限于上述紫外光吸收材料，也可以为紫外光反射材料，例如金属材料。
如图1和图2所示，本公开的一个实施例还提供了一种阵列基板，该阵列基板包括上述任一实施例中的薄膜晶体管2。
如图1和图2所示，在本公开的一个实施例，上述阵列基板还可以包括位于薄膜晶体管2的源漏电极23背离衬底基板1一侧的像素电极4，源漏电极23与像素电极4之间形成有钝化层25；由于阵列基板中的像素电极4可以采用氧化铟锡材料制成，因此，当紫外光遮挡层3位于源漏电极23背离衬底基板1的一侧时，紫外光遮挡层3可以与像素电极4同层设置。
在本公开的一个实施例中，阵列基板除了可以包括位于薄膜晶体管2的源漏电极23背离衬底基板1一侧的像素电极4，还可以包括位于像素电极4背离衬底基板1一侧的公共电极，像素电极4与公共电极之间形成有绝缘层；由于阵列基板中的公共电极也可以采用氧化铟锡制成，因此，当紫外光遮挡层3位于源漏电极23背离衬底基板1的一侧时，紫外光遮挡层3可以与公共电极同层设置。
当紫外光遮挡层由氧化铟锡制成时，紫外光遮挡层3与阵列基板中的像素电极4或者公共电极同层设置，可以使制备过程简化，并且可以避免紫外 光对薄膜晶体管2中的有源层21、栅极22、源极231和漏极232等导电结构的导电性能产生影响，从而可以避免对薄膜晶体管2的性能产生影响。
当然，紫外光遮挡层3也可以形成于薄膜晶体管2的有源层21与源漏电极23之间；当紫外光遮挡层3形成于薄膜晶体管2的有源层21与源漏电极23之间时，紫外光遮挡层3的材料可以为不导电材料，以避免对薄膜晶体管2的性能产生影响。
本公开的至少一个实施例还提供一种显示面板，包括上述任一实施例中的阵列基板。该显示面板中的阵列基板不会由于受到紫外光的照射而产生不良，性能稳定可靠。
本公开的至少一个实施例还提供一种显示装置，包括上述实施例中的显示面板。该显示装置中的阵列基板的性能稳定可靠，可以避免产生串扰等不良。
如图1、图2和图3所示，一种制备上述任一薄膜晶体管的方法，包括：
步骤S101，在衬底基板1上形成有源层21；
步骤S102，在有源层21背离衬底基板1的一侧形成紫外光遮挡层3；其中，有源层21在衬底基板1上的投影位于紫外光遮挡层3在衬底基板1上的投影内。
上述制备方法形成的薄膜晶体管2中，有源层21被紫外光遮挡层3完全覆盖，紫外光遮挡层3可以遮挡紫外光，因此在光配向过程中，紫外光遮挡层3可以有效消除紫外光对有源层21的影响，从而可以保证薄膜晶体管2的性能不会受到紫外光照射的影响。
如图1和图2所示，在上述实施例的基础上，在本公开的一个改进实施例中，在衬底基板1上形成有源层21之后，以及在有源层21背离衬底基板1的一侧形成紫外光遮挡层3之前，还可以包括：在有源层21背离衬底基板1的一侧形成源漏电极。
在上述实施例的基础上，在本公开的一个改进实施例中，紫外光遮挡层3的材料可以为紫外光吸收材料。紫外光吸收材料通过吸收紫外光起到遮挡紫外光的作用。
在本公开的一个实施例中，上述紫外光吸收材料可以为氧化铟锡。
当然，紫外光遮挡层3的材料并不限于上述实施例中的紫外光吸收材料， 也可以为紫外光反射材料，例如金属。
一种制备上述任一阵列基板的方法，包括如上述任一实施例中所述的薄膜晶体管的制备方法过程。
在本公开的一个实施例中，如图1和图2所示，当所述阵列基板还包括位于所述薄膜晶体管2的源漏电极23背离所述衬底基板1一侧的像素电极4、且所述紫外光遮挡层3与所述像素电极4同层设置时，步骤S102，在有源层21背离衬底基板1的一侧形成紫外光遮挡层3，可以包括：
在所述薄膜晶体管2的源漏电极23背离所述衬底基板1的一侧形成钝化层25，在钝化层25上形成像素电极层，通过一次构图工艺形成所述像素电极4的图形和所述紫外光遮挡层3的图形。
在本公开的一个实施例中，当所述阵列基板还包括位于所述薄膜晶体管2的源漏电极23背离所述衬底基板1一侧的公共电极、且所述紫外光遮挡层3与所述公共电极同层设置时，步骤S102，在有源层21背离衬底基板1的一侧形成紫外光遮挡层3，可以包括：
在所述薄膜晶体管2的源漏电极23背离所述衬底基板1的一侧形成像素电极4，在像素电极4背离衬底基板1的一侧形成绝缘层，在绝缘层上形成公共电极层，通过一次构图工艺形成所述公共电极的图形和所述紫外光遮挡层3的图形。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。
本申请要求于2015年5月6日递交的中国专利申请第201510227721.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种薄膜晶体管，包括位于衬底基板上的有源层，其中，所述薄膜晶体管还包括位于所述有源层背离所述衬底基板一侧的紫外光遮挡层，且所述有源层在所述衬底基板上的投影位于所述紫外光遮挡层在所述衬底基板上的投影内。
  2. 如权利要求1所述的薄膜晶体管，其还包括位于所述有源层背离所述衬底基板一侧的源漏电极，其中，所述紫外光遮挡层位于所述源漏电极背离所述衬底基板的一侧。
  3. 一种阵列基板，包括衬底基板，其还包括如权利要求1或2所述的薄膜晶体管。
  4. 如权利要求3所述的阵列基板，其中，所述紫外光遮挡层的材料为紫外光吸收材料。
  5. 如权利要求4所述的阵列基板，其中，所述紫外光吸收材料为氧化铟锡。
  6. 如权利要求3至5中任何一项所述的阵列基板，其中，
    所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的像素电极，且当所述紫外光遮挡层位于所述源漏电极背离所述衬底基板的一侧时，所述紫外光遮挡层与所述像素电极同层设置；或者，
    所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的公共电极，且当所述紫外光遮挡层位于所述源漏电极背离所述衬底基板的一侧时，所述紫外光遮挡层与所述公共电极同层设置。
  7. 一种显示面板，其包括如权利要求3-6中任何一项所述的阵列基板。
  8. 一种显示装置，其包括如权利要求7所述的显示面板。
  9. 一种薄膜晶体管的制备方法，包括：
    在衬底基板上形成有源层；
    在有源层背离衬底基板的一侧形成紫外光遮挡层；其中，所述有源层在所述衬底基板上的投影位于所述紫外光遮挡层在所述衬底基板上的投影内。
  10. 如权利要求9所述的制备方法，其中，在衬底基板上形成有源层之后，以及在有源层背离衬底基板的一侧形成紫外光遮挡层之前，所述制备方 法还包括：
    在所述有源层背离所述衬底基板的一侧形成源漏电极。
  11. 一种阵列基板的制备方法，其包括如权利要求9或10所述的薄膜晶体管的制备方法。
  12. 如权利要求11所述的制备方法，其中，所述紫外光遮挡层的材料为紫外光吸收材料。
  13. 如权利要求12所述的制备方法，其中，所述紫外光遮挡层的材料为氧化铟锡。
  14. 如权利要求13所述的制备方法，其中，
    当所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的像素电极、且所述紫外光遮挡层与所述像素电极同层设置时，所述在有源层背离衬底基板的一侧形成紫外光遮挡层，包括：
    在所述薄膜晶体管的源漏电极背离所述衬底基板的一侧形成像素电极层，通过一次构图工艺形成所述像素电极的图形和所述紫外光遮挡层的图形。
  15. 如权利要求13所述的制备方法，其中，
    当所述阵列基板还包括位于所述薄膜晶体管的源漏电极背离所述衬底基板一侧的公共电极、且所述紫外光遮挡层与所述公共电极同层设置时，所述在有源层背离衬底基板的一侧形成紫外光遮挡层，包括：
    在所述薄膜晶体管的源漏电极背离所述衬底基板的一侧形成公共电极层，通过一次构图工艺形成所述公共电极的图形和所述紫外光遮挡层的图形。
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