WO2016173520A1 - Ldmos可控硅结构的静电保护器件 - Google Patents

Ldmos可控硅结构的静电保护器件 Download PDF

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WO2016173520A1
WO2016173520A1 PCT/CN2016/080590 CN2016080590W WO2016173520A1 WO 2016173520 A1 WO2016173520 A1 WO 2016173520A1 CN 2016080590 W CN2016080590 W CN 2016080590W WO 2016173520 A1 WO2016173520 A1 WO 2016173520A1
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Prior art keywords
source
well
drain
ldmos
electrostatic protection
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French (fr)
Inventor
孙俊
林中瑀
汪广羊
孙贵鹏
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/80—PNPN diodes, e.g. Shockley diodes or break-over diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/151—LDMOS having built-in components

Definitions

  • the present invention relates to an electrostatic discharge (ESD) protection device, and more particularly to an electrostatic protection device for a laterally diffused metal oxide semiconductor (LDMOS) thyristor structure.
  • ESD electrostatic discharge
  • LDMOS laterally diffused metal oxide semiconductor
  • SCR thyristor
  • a disadvantage of a conventional LDMOS-SCR electrostatic protection structure is that the drain terminal, that is, the P+ of the anode and the high-voltage P-well of the source terminal, that is, the cathode, are easily penetrated, which easily affects the internal circuit, resulting in a drop in breakdown voltage (BV), which cannot satisfy the original Designed operating voltage.
  • BV breakdown voltage
  • An electrostatic protection device for an LDMOS thyristor structure comprising a P-type substrate, an N-well, a P-well on the substrate, a gate that overlaps the P-well and extends to an edge of the N-well, a first N+ structure and a first P+ structure disposed in the N well, a second N+ structure and a second P+ structure disposed in the P well, the first N+ structure being a drain N+ structure,
  • the first P+ structure is a drain P+ structure
  • the second N+ structure is a source N+ structure
  • the second P+ structure is a source P+ structure
  • a distance of the drain P+ structure to the gate is greater than the The distance from the drain N+ structure to the gate.
  • An electrostatic protection device for an LDMOS thyristor structure comprising: a substrate, a P-type epitaxial layer on the substrate, an N-well and a P-well on the P-type epitaxial layer, overlapping the P-well and extending to a gate of the N-well edge, a first N+ structure and a first P+ structure disposed in the N-well, a second N+ structure and a second P+ structure disposed in the P-well, the first N+ The structure is a drain N+ structure, the first P+ structure is a drain P+ structure, the second N+ structure is a source N+ structure, the second P+ structure is a source P+ structure, and the drain P+ structure is The distance of the gate is greater than the distance from the drain N+ structure to the gate.
  • the distance from the drain P+ structure to the gate is larger than the distance from the drain N+ structure to the gate, and the punch-through is not easily formed, thereby ensuring that the breakdown voltage BV is maintained at the design level.
  • FIG. 1 is a layout of an LDMOS-SCR electrostatic protection structure device in an embodiment
  • Figure 2 is a cross-sectional view of the LDMOS-SCR electrostatic protection structure device of Figure 1 taken along line AA;
  • FIG. 3 is a layout of an LDMOS-SCR electrostatic protection structure device in still another embodiment
  • Figure 4 is a cross-sectional view of the LDMOS-SCR electrostatic protection structure device of Figure 3 taken along line BB;
  • Figure 5 is a layout of an LDMOS-SCR electrostatic protection structure device in another embodiment
  • Figure 6 is a cross-sectional view of the LDMOS-SCR electrostatic protection structure device of Figure 5 taken along line CC;
  • FIG. 7 is a schematic view showing a case where the LDMOS-SCR source of the common source structure has a three-column extraction structure
  • Fig. 8 is a schematic view showing a case where the LDMOS-SCR source of the common source structure is extremely segmented and taken out.
  • the distance from the P+ to the polysilicon gate of the drain (ie, the anode) is closer than the distance from the N+ to the polysilicon gate of the drain, and the BV (breakdown voltage) is affected because the high-voltage N-well is the total consumption.
  • the distance from the drain P+ to the polysilicon gate is the same as or closer to the distance from the drain N+ to the polysilicon gate, the punch-through will be formed and the BV will drop, failing to meet the original design operating voltage.
  • FIG. 1 is a layout of an LDMOS-SCR electrostatic protection structure device in an embodiment
  • FIG. 2 is a cross-sectional view of the LDMOS-SCR electrostatic protection structure device of FIG. 1 taken along line AA.
  • the LDMOS thyristor structure has a common drain structure, including an N well 320, a drain N+ structure 322, and a drain P+ structure 324 disposed in the middle, and a P disposed on both sides of the N well 320.
  • the two sides of the N-well 320 are respectively connected to the P-well 330 through a gate 340 and extend to the edge of the source N+ structure 332 of the side.
  • the drain N+ structure 322 has a drain P+ in the horizontal direction.
  • Structure 324 is surrounded by four sides.
  • N-well 320 is a high voltage N-well and P-well 330 is a high voltage P-well.
  • the N well 320 and the P well 330 may be formed in the P-type epitaxial layer, that is, the position of the P-type substrate 310 in FIG. 2 is a P-type epitaxial layer.
  • the distance from the drain P+ structure 324 to the gate 340 is greater than the distance from the drain N+ structure 322 to the gate 340, and the drain P+ structure 324 of the anode is not easily formed with the P well 330, so Ensure that the breakdown voltage (BV) remains at the design level. .
  • the drain P+ structure 324 in the N well 320 is taken out as an anode through the contact hole, and the drain N+ structure 322 in the N well 320 is not taken out, as shown in FIG.
  • the conventional technique is to simultaneously extract the N+ and P+ of the drain, which is equivalent to paralleling an NPN.
  • This NPN is equivalent to the parasitic NPN of the common high voltage NLDMOS, and the final capability of the ESD is limited to the parasitic NPN.
  • Parasitic NPN has a poor ESD capability, so the device's ESD capability is also poor.
  • the structure in this embodiment only draws the drain P+ structure 324 without drawing the drain N+ structure 322, so that the parasitic NPN is cut off, and only the SCR of the PNPN structure is retained, so the ESD capability is stronger.
  • the source N+ structure 332 and the source P+ structure 334 in the two P wells 330 are all taken out through the contact holes, and these leads are electrically connected together.
  • the two gates 340 are also electrically connected through the contact holes, and are electrically connected together with the extraction of the source N+ structure 332 and the extraction of the source P+ structure 334 as a cathode.
  • FIG. 3 is a layout of an LDMOS-SCR electrostatic protection structure device in still another embodiment
  • FIG. 4 is a cross-sectional view of the LDMOS-SCR electrostatic protection structure device of FIG. 3 taken along line BB.
  • the LDMOS thyristor structure is a common source structure, including a P well 530, a source N+ structure 532, and a source P+ structure 534 disposed in the middle, and a N disposed on both sides of the P well 530.
  • the source N+ structure 532 is disposed on both sides of the source P+ structure 534, separated by the source P+ structure 534, and the two N wells 520 on both sides of the P well 530 are respectively connected to the P well 530 through a gate 540 and Extending to the side edge of source N+ structure 532.
  • the drain P+ structures 524 in each of the N wells 520 on both sides of the P well 530 are taken out through the contact holes and electrically connected to each other as an anode, and in each of the N wells 520 on both sides of the P well 530. Neither the drain N+ structure 522 is drawn.
  • the source P+ structure 534 in the P well 530 is taken out through the contact hole, and the source N+ structure 532 in the P well 530 is electrically connected through the contact hole, and the two gates 540 are electrically connected through the contact hole. Together, they are electrically connected to the extraction of the source N+ structure 532 and the extraction of the source P+ structure 534 as a cathode.
  • the drain N+ structure 522 surrounds the drain P+ structure 524 in all directions in the horizontal direction.
  • the N well 520 and the P well 530 may also be formed in the P-type epitaxial layer, that is, the position of the P-type substrate 510 in FIG. 4 is a P-type epitaxial layer.
  • FIG. 5 is a layout of an LDMOS-SCR electrostatic protection structure device in another embodiment
  • FIG. 6 is a cross-sectional view of the LDMOS-SCR electrostatic protection structure device of FIG. 5 taken along line CC.
  • the LDMOS thyristor structure is also a common source structure, including a P well 730, a source N+ structure 732, and a source P+ structure 734 disposed in the middle, and an N well disposed on both sides of the P well 730.
  • 720, one drain N+ structure 722 and one drain P+ structure 724 is the main difference between the embodiment shown in FIG. 5 and the embodiment shown in FIG. 3
  • the drain N+ structure 722 of the embodiment shown in FIG. 5 only surrounds the drain P+ structure 724 in three directions in the horizontal direction, and the drain P+ structure 724 is far away.
  • the source side is in direct contact with the N-well 720.
  • the source shown in Figures 3 and 5 is extremely three-column (3-stripe shape Pickup structure, as shown in Figure 7, N+, P+ and N+ are each taken as a column. Note that the value of the width a is adjusted according to the actual needs of the device.
  • the source may also be a segmented extraction of N+, P+ as shown in FIG. 8 spaced apart in the longitudinal direction (ie, a direction perpendicular to the direction of the line connecting the N wells on both sides of the intermediate P well) ( Multi-segment Shape pickup structure, this structure needs to pay attention to the ratio of the length X and Y of N+ and P+ in the longitudinal direction.
  • the P-type substrate 710 can be replaced with a P-type epitaxial layer.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种LDMOS可控硅结构的静电保护器件，包括P型衬底（310），所述衬底上N阱（320）、P阱（330），搭接于所述P阱（330）上且延伸至所述N阱（320）边缘的栅极（340），设于所述N阱（320）内的第一N+结构和第一P+结构，设于所述P阱（330）内的第二N+结构和第二P+结构，所述第一N+结构为漏极N+结构（322），所述第一P+结构为漏极P+结构（324），所述第二N+结构为源极N+结构（332），所述第二P+结构为源极P+结构（334），所述漏极P+结构（324）到所述栅极（340）的距离大于所述漏极N+结构（322）到所述栅极（340）的距离。

Description

LDMOS可控硅结构的静电保护器件
【技术领域】
本发明涉及一种静电释放（ESD）保护器件，特别是涉及一种横向扩散金属氧化物半导体（LDMOS）可控硅结构的静电保护器件。
【背景技术】
随着高压器件在集成电路中的应用越来越广泛，对其抗静电能力的要求也越来越高。传统的外挂抗静电器件大部分使用可控硅（SCR）的结构来实现，而这种结构根据不同的工艺其特性也是随之变化的。
一种传统的LDMOS-SCR静电保护结构的缺点是漏端、即阳极的P+容易和源端、即阴极的高压P阱穿通，容易影响内部电路，导致击穿电压（BV）下降，满足不了原先设计的工作电压。
【发明内容】
基于此，有必要提供一种能够确保较高的击穿电压的LDMOS可控硅结构的静电保护器件。
一种LDMOS可控硅结构的静电保护器件，包括P型衬底，所述衬底上的N阱、P阱，搭接于所述P阱上且延伸至所述N阱边缘的栅极，设于所述N阱内的第一N+结构和第一P+结构，设于所述P阱内的第二N+结构和第二P+结构，所述第一N+结构为漏极N+结构，所述第一P+结构为漏极P+结构，所述第二N+结构为源极N+结构，所述第二P+结构为源极P+结构，所述漏极P+结构到所述栅极的距离大于所述漏极N+结构到所述栅极的距离。
一种LDMOS可控硅结构的静电保护器件，包括衬底、衬底上的P型外延层，所述P型外延层上的N阱、P阱，搭接于所述P阱上且延伸至所述N阱边缘的栅极，设于所述N阱内的第一N+结构和第一P+结构，设于所述P阱内的第二N+结构和第二P+结构，所述第一N+结构为漏极N+结构，所述第一P+结构为漏极P+结构，所述第二N+结构为源极N+结构，所述第二P+结构为源极P+结构，所述漏极P+结构到所述栅极的距离大于所述漏极N+结构到所述栅极的距离。
上述LDMOS可控硅结构的静电保护器件，漏极P+结构到栅极的距离大于漏极N+结构到栅极的距离，不易形成穿通，因此可以确保击穿电压BV保持在设计水平。
【附图说明】
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1是一实施例中LDMOS-SCR静电保护结构器件的版图；
图2是图1的LDMOS-SCR静电保护结构器件沿AA线的剖视图；
图3是再一实施例中LDMOS-SCR静电保护结构器件的版图；
图4是图3的LDMOS-SCR静电保护结构器件沿BB线的剖视图；
图5是另一实施例中LDMOS-SCR静电保护结构器件的版图；
图6是图5的LDMOS-SCR静电保护结构器件沿CC线的剖视图；
图7是共源极结构的LDMOS-SCR源极为三列引出结构时的示意图；
图8是共源极结构的LDMOS-SCR源极为分段引出结构时的示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
传统技术中漏极（也就是阳极）的P+到多晶硅栅的距离比漏极的N+到多晶硅栅的距离更近，这时BV（击穿电压）就会受到影响，因为高压N阱是全耗尽的，所以当漏极的P+到多晶硅栅的距离和漏极的N+到多晶硅栅的距离一样或者更近，会形成穿通，BV就会下降，满足不了原先的设计工作电压。
图1是一实施例中LDMOS-SCR静电保护结构器件的版图，图2是图1的LDMOS-SCR静电保护结构器件沿AA线的剖视图。
在本实施例中，LDMOS可控硅结构为共漏极结构，包括设于中间的N阱320、漏极N+结构322及漏极P+结构324，以及设于N阱320两侧的各一个P阱330、各一个源极N+结构332及各一个源极P+结构334。N阱320两侧分别通过一个栅极340搭接至P阱330上并延伸至该侧的源极N+结构332边缘，如图1所示，漏极N+结构322在水平方向上将漏极P+结构324四面包围。在本实施例中，N阱320为高压N阱，P阱330为高压P阱。
在其他实施例中，也可以是在P型外延层内形成N阱320和P阱330，也就是图2中P型衬底310的位置为P型外延层。
上述LDMOS-SCR静电保护结构器件，漏极P+结构324到栅极340的距离大于漏极N+结构322到栅极340的距离，阳极的漏极P+结构324不易与P阱330形成穿通，因此可以确保击穿电压（BV）保持在设计水平。。
在本实施例中，N阱320中的漏极P+结构324通过接触孔引出作为阳极，N阱320中的漏极N+结构322不引出，如图1所示。而传统技术是将漏极的N+与P+同时引出，这样就相当于并联了一个NPN，这个NPN相当于普通高压NLDMOS的寄生NPN，ESD的最终能力被限制在了这个寄生的NPN上，由于该寄生NPN的ESD能力较差，因此器件的ESD能力也较差。而本实施例中的结构只引出漏极P+结构324而不引出漏极N+结构322，这样就把这个寄生的NPN给切掉了，只保留一个PNPN结构的SCR，因此ESD能力更强。
在本实施例中，两个P阱330中的源极N+结构332和源极P+结构334均通过接触孔引出，且这些引出均电性连接在一起。两个栅极340也通过接触孔引出后电性连接在一起，并与源极N+结构332的引出、源极P+结构334的引出电性连接在一起作为阴极。
图3是再一实施例中LDMOS-SCR静电保护结构器件的版图，图4是图3的LDMOS-SCR静电保护结构器件沿BB线的剖视图。
在本实施例中，LDMOS可控硅结构为共源极结构，包括设于中间的P阱530、源极N+结构532及源极P+结构534，以及设于P阱530两侧的各一个N阱520、各一个漏极N+结构522及各一个漏极P+结构524。源极N+结构532设于源极P+结构534的两边，被源极P+结构534分隔开，P阱530两侧的两个N阱520分别通过一个栅极540搭接至P阱530上并延伸至源极N+结构532的该侧边缘。
在本实施例中，P阱530两侧的各一个N阱520中的漏极P+结构524均通过接触孔引出并相互电性连接作为阳极，P阱530两侧的各一个N阱520中的漏极N+结构522均不引出。P阱530中的源极P+结构534通过接触孔引出，P阱530中的源极N+结构532通过接触孔引出后电性连接在一起，且两个栅极540通过接触孔引出后电性连接在一起，并与源极N+结构532的引出、源极P+结构534的引出电性连接后作为阴极。
参见图3，在本实施例中，漏极N+结构522在水平方向上将漏极P+结构524四面包围。
在其他实施例中，也可以是在P型外延层内形成N阱520和P阱530，也就是图4中P型衬底510的位置为P型外延层。
图5是另一实施例中LDMOS-SCR静电保护结构器件的版图，图6是图5的LDMOS-SCR静电保护结构器件沿CC线的剖视图。本实施例中LDMOS可控硅结构也为共源极结构，包括设于中间的P阱730、源极N+结构732及源极P+结构734，以及设于P阱730两侧的各一个N阱720、各一个漏极N+结构722及各一个漏极P+结构724。图5所示实施例与图3所示实施例的主要区别在于图5所示实施例的漏极N+结构722在水平方向上只是将漏极P+结构724三面包围，漏极P+结构724在远离源极那一侧直接与N阱720接触。
图3和图5所示的源极为三列引出（3-stripe shape pickup）结构，如图7所示，N+、P+及N+各作为一列引出，注意根据器件的实际需求对宽度a的值进行调整。在其他实施例中，源极也可以为图8所示的N+、P+在纵向（即与中间的P阱两侧的N阱的连线方向相垂直的方向）上间隔分布的分段引出（multi-segment shape pickup）结构，这种结构需要注意N+、P+在纵向上的长度X与Y的比值。
同样的，在其他实施例中，P型衬底710可以替换为P型外延层。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种LDMOS可控硅结构的静电保护器件，包括P型衬底，所述衬底上的N阱、P阱，搭接于所述P阱上且延伸至所述N阱边缘的栅极，设于所述N阱内的第一N+结构和第一P+结构，设于所述P阱内的第二N+结构和第二P+结构，所述第一N+结构为漏极N+结构，所述第一P+结构为漏极P+结构，所述第二N+结构为源极N+结构，所述第二P+结构为源极P+结构，所述漏极P+结构到所述栅极的距离大于所述漏极N+结构到所述栅极的距离。
  2. 根据权利要求1所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述漏极N+结构将所述漏极P+结构至少在水平方向上三面包围。
  3. 根据权利要求2所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述LDMOS可控硅结构为共漏极结构，包括设于中间的所述N阱、所述漏极N+结构及漏极P+结构，以及设于所述N阱两侧的各一个所述P阱、各一个所述源极N+结构及各一个所述源极P+结构，N阱的两侧分别通过一个所述栅极搭接至该侧P阱上并延伸至该侧的源极N+结构边缘，所述漏极N+结构在水平方向上将所述漏极P+结构四面包围。
  4. 根据权利要求3所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述N阱中的漏极P+结构通过接触孔引出，所述N阱中的漏极N+结构不引出。
  5. 根据权利要求3所述的LDMOS可控硅结构的静电保护器件，其特征在于，两个所述P阱中的源极N+结构和源极P+结构均通过接触孔引出，两个所述栅极通过接触孔引出，且两个所述P阱中的源极N+结构和源极P+结构的引出、两个所述栅极的引出电性连接在一起。
  6. 根据权利要求2所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述LDMOS可控硅结构为共源极结构，包括设于中间的所述P阱、所述源极N+结构及源极P+结构，以及设于所述P阱两侧的各一个所述N阱、各一个所述漏极N+结构及各一个所述漏极P+结构，所述源极N+结构设于所述源极P+结构的两边，P阱两侧的两个N阱分别通过一个所述栅极搭接至P阱上并延伸至源极N+结构边缘。
  7. 根据权利要求6所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述P阱两侧的各一个N阱中的漏极P+结构均通过接触孔引出并相互电性连接，所述P阱两侧的各一个N阱中的漏极N+结构均不引出。
  8. 根据权利要求6所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述P阱中的源极P+结构通过接触孔引出，所述P阱中的源极N+结构通过接触孔引出，两个所述栅极通过接触孔引出，且所述源极P+结构的引出、所述源极N+结构的引出、两个所述栅极的引出电性连接在一起。
  9. 根据权利要求8所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述源极N+结构和源极P+结构为NPN的三列引出结构，N+、P+及N+各作为一列引出。
  10. 根据权利要求6所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述源极N+结构和源极P+结构为在纵向上间隔分布的分段引出结构。
  11. 根据权利要求1所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述LDMOS为N沟道LDMOS。
  12. 一种LDMOS可控硅结构的静电保护器件，包括衬底、衬底上的P型外延层，所述P型外延层上的N阱、P阱，搭接于所述P阱上且延伸至所述N阱边缘的栅极，设于所述N阱内的第一N+结构和第一P+结构，设于所述P阱内的第二N+结构和第二P+结构，所述第一N+结构为漏极N+结构，所述第一P+结构为漏极P+结构，所述第二N+结构为源极N+结构，所述第二P+结构为源极P+结构，所述漏极P+结构到所述栅极的距离大于所述漏极N+结构到所述栅极的距离。
  13. 根据权利要求12所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述漏极N+结构将所述漏极P+结构至少在水平方向上三面包围。
  14. 根据权利要求13所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述LDMOS可控硅结构为共漏极结构，包括设于中间的所述N阱、所述漏极N+结构及漏极P+结构，以及设于所述N阱两侧的各一个所述P阱、各一个所述源极N+结构及各一个所述源极P+结构，N阱的两侧分别通过一个所述栅极搭接至该侧P阱上并延伸至该侧的源极N+结构边缘，所述漏极N+结构在水平方向上将所述漏极P+结构四面包围。
  15. 根据权利要求14所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述N阱中的漏极P+结构通过接触孔引出，所述N阱中的漏极N+结构不引出。
  16. 根据权利要求14所述的LDMOS可控硅结构的静电保护器件，其特征在于，两个所述P阱中的源极N+结构和源极P+结构均通过接触孔引出，两个所述栅极通过接触孔引出，且两个所述P阱中的源极N+结构和源极P+结构的引出、两个所述栅极的引出电性连接在一起。
  17. 根据权利要求13所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述LDMOS可控硅结构为共源极结构，包括设于中间的所述P阱、所述源极N+结构及源极P+结构，以及设于所述P阱两侧的各一个所述N阱、各一个所述漏极N+结构及各一个所述漏极P+结构，所述源极N+结构设于所述源极P+结构的两边，P阱两侧的两个N阱分别通过一个所述栅极搭接至P阱上并延伸至源极N+结构边缘。
  18. 根据权利要求17所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述P阱两侧的各一个N阱中的漏极P+结构均通过接触孔引出并相互电性连接，所述P阱两侧的各一个N阱中的漏极N+结构均不引出。
  19. 根据权利要求17所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述P阱中的源极P+结构通过接触孔引出，所述P阱中的源极N+结构通过接触孔引出，两个所述栅极通过接触孔引出，且所述源极P+结构的引出、所述源极N+结构的引出、两个所述栅极的引出电性连接在一起。
  20. 根据权利要求19所述的LDMOS可控硅结构的静电保护器件，其特征在于，所述源极N+结构和源极P+结构为NPN的三列引出结构，N+、P+及N+各作为一列引出。
PCT/CN2016/080590 2015-04-29 2016-04-29 Ldmos可控硅结构的静电保护器件 Ceased WO2016173520A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN106206561B (zh) * 2015-04-29 2019-05-10 无锡华润上华科技有限公司 Ldmos可控硅结构的静电保护器件
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1433083A (zh) * 2002-01-18 2003-07-30 罗姆股份有限公司 双重扩散型mosfet及其半导体装置
CN1841744A (zh) * 2005-03-31 2006-10-04 株式会社理光 具有稳定静电放电保护能力的半导体器件
CN101339956A (zh) * 2007-07-03 2009-01-07 台湾积体电路制造股份有限公司 半导体装置
CN103258814A (zh) * 2013-05-15 2013-08-21 电子科技大学 一种集成电路芯片esd防护用ldmos scr器件
CN103617996A (zh) * 2013-12-09 2014-03-05 江南大学 一种具有高维持电流的环形vdmos结构的esd保护器件
CN103681660A (zh) * 2013-12-13 2014-03-26 江南大学 一种双重抗闩锁的环形ldmos-scr结构的高压esd保护器件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080110680A (ko) * 2006-04-14 2008-12-18 엔엑스피 비 브이 전자 디바이스와, 이 전자 디바이스를 포함하는 기지국 및 이동 전화기
US8088656B2 (en) * 2009-08-14 2012-01-03 International Business Machines Corporation Fabricating ESD devices using MOSFET and LDMOS
CN102110686B (zh) * 2010-12-17 2012-11-28 无锡华润上华半导体有限公司 一种基于scr的集成电路静电保护器件
CN106206561B (zh) * 2015-04-29 2019-05-10 无锡华润上华科技有限公司 Ldmos可控硅结构的静电保护器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1433083A (zh) * 2002-01-18 2003-07-30 罗姆股份有限公司 双重扩散型mosfet及其半导体装置
CN1841744A (zh) * 2005-03-31 2006-10-04 株式会社理光 具有稳定静电放电保护能力的半导体器件
CN101339956A (zh) * 2007-07-03 2009-01-07 台湾积体电路制造股份有限公司 半导体装置
CN103258814A (zh) * 2013-05-15 2013-08-21 电子科技大学 一种集成电路芯片esd防护用ldmos scr器件
CN103617996A (zh) * 2013-12-09 2014-03-05 江南大学 一种具有高维持电流的环形vdmos结构的esd保护器件
CN103681660A (zh) * 2013-12-13 2014-03-26 江南大学 一种双重抗闩锁的环形ldmos-scr结构的高压esd保护器件

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