WO2016161729A1 - 阵列基板及其驱动方法、显示装置 - Google Patents

阵列基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2016161729A1
WO2016161729A1 PCT/CN2015/086448 CN2015086448W WO2016161729A1 WO 2016161729 A1 WO2016161729 A1 WO 2016161729A1 CN 2015086448 W CN2015086448 W CN 2015086448W WO 2016161729 A1 WO2016161729 A1 WO 2016161729A1
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sub
line
additional
pixel
row
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PCT/CN2015/086448
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English (en)
French (fr)
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李文波
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京东方科技集团股份有限公司
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Priority to EP15834628.8A priority Critical patent/EP3282312B1/en
Priority to BR112016028110-1A priority patent/BR112016028110B1/pt
Priority to US14/907,782 priority patent/US9858881B2/en
Priority to MX2017000369A priority patent/MX360797B/es
Priority to RU2016146517A priority patent/RU2693559C2/ru
Publication of WO2016161729A1 publication Critical patent/WO2016161729A1/zh

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    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H—ELECTRICITY
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a driving method thereof, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the ground is used in the field of high performance display.
  • the TFT-LCD display device includes an effective display area (Active Area, abbreviated as AA area) and a non-display area.
  • AA area an effective display area
  • non-display area a plurality of horizontally and vertically intersecting gate lines (G1, G2, G3, ..., Gi... Gn) and data lines (D1, D2, D3, ..., Dj...Dm) intersect to define a plurality of matrix arrangements.
  • Subpixel 10 In the non-display area other than the AA area, the timing controller 11, the gate driver 12, and the source driver 13 are provided.
  • the timing controller 11 is configured to output an STV (Gate Driver Start Signal) to the gate driver 12, and sequentially shift the received STV signal through the shift register 120 to output a scan signal.
  • the level shifter 121 receives the scan signal and determines whether to output a scan signal to the gate line (for example, Gi) with reference to OE (Output Enable).
  • the timing controller 11 outputs STH (Source Driver Start Signal), DD (Digital Data) and LP (Latch Input) to the source driver 13, and the STH signal is
  • the latch 130 latches the DD signal in the corresponding channel, and then determines whether to output a DD signal to the data line (for example, Dj) according to the LP signal, and the DD signal is converted into the data signal Vdata by the digital-to-analog converter 131.
  • the data signal Vdata is input to the corresponding data lines, thereby realizing display of images.
  • the gate lines (G1, G2, G3, ..., Gi... Gn) turn on a row of sub-pixels 10 that are later in the process of row-by-row, and receive the data lines (D1, D2, D3, ..., Dj...Dm).
  • the time of the input data signal Vdata is delayed. Thereby reducing the response speed of the display, affecting the display quality of the high PPI display.
  • Embodiments of the present disclosure provide an array substrate, a driving method thereof, and a display device, which can solve the problem that a sub-pixel receiving data signal with a late opening time is delayed due to a gate line being turned on line by line.
  • An aspect of an embodiment of the present disclosure provides an array substrate including a plurality of gate lines and data lines, and a plurality of sub-pixels defined by the gate lines and the data lines being intersected, wherein
  • At least one additional line for providing an additional data signal is disposed, and the sub-pixels of the same column correspond to at least one additional line;
  • At least one of the sub-pixels of the same column is driven by the additional line corresponding to the sub-pixel.
  • a display device comprising any of the array substrates described above.
  • a further aspect of the embodiments of the present disclosure provides a driving method of an array substrate, including:
  • the data line inputs a data signal to a sub-pixel controlled by the one of the gate lines;
  • At least one additional line inputs additional data signals to the remaining sub-pixels controlled by the gate lines.
  • Embodiments of the present disclosure provide an array substrate, a driving method thereof, and a display device.
  • the array substrate comprises a plurality of gate lines and data lines, and a plurality of sub-pixels defined by the intersection of the gate lines and the data lines.
  • at least one sub-pixel of the same column in which at least one additional line for providing additional data signals is disposed between adjacent two columns of sub-pixels corresponds to at least one additional line, and at least one sub-pixel of the sub-pixels of the same column is used by the sub-pixel Corresponding additional line drive.
  • the gate driver can scan a plurality of gate lines at the same time, so that the sub-pixels of different rows respectively connected with the data lines and the additional lines are simultaneously turned on, and respectively receive the data signals input by the data lines and the additional signals.
  • Additional data signal for line input is increased.
  • FIG. 1 is a schematic structural view of a display device provided by the prior art
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • Figure 5a is an enlarged schematic view showing a partial structure of A in Figure 4.
  • Figure 5b is an enlarged schematic view showing another partial structure of A in Figure 4.
  • FIG. 6 is a flow chart of a method for driving an array substrate as shown in FIG. 2;
  • FIG. 7 is a flow chart of a method for driving an array substrate as shown in FIG. 3;
  • Figure 8 is a flow chart of a method for driving an array substrate as shown in Figure 4.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIG. 2, which may include a plurality of gate lines (G1, G2, G3, ..., Gi...Gn) and data lines (D1, D2, D3, ..., Dj...Dm), and
  • the plurality of sub-pixels 10 are defined by the above-described gate lines (G1, G2, G3, ..., Gi... Gn) and the data lines (D1, D2, D3, ..., Dj, ... Dm).
  • i and j are integers greater than or equal to 0, and n and m are integers greater than or equal to 1; the above “multiple” may be at least one, and “multiple” may be at least one.
  • At least one additional line L for providing the additional data signal Add_Vdata is disposed between the adjacent two columns of sub-pixels 10 and sub-pixels 10', and the sub-pixels 10 of the same column correspond to at least one additional line L.
  • At least one of the sub-pixels 10 of the same column of sub-pixels 10 is driven by an additional line L corresponding to the sub-pixel 10.
  • the function of the additional line L is the same as that of the data lines (D1, D2, D3, ..., Dm) shown in FIG. 1 , and is used for receiving as shown in FIG. 1 .
  • the signal output from the source driver 13 is shown for displaying an image. Therefore, the above-described additional data signals Add_Vdata and data signal Vdata are both the signals for displaying an image described above.
  • the gate lines G1 and G2 since at least one row of sub-pixels 10 is driven by the additional line L, it is possible to scan the gate lines G1 and G2 without progressively, and to simultaneously input scan signals to the gate lines G1 and G2, so that A row of sub-pixels 10 and a second row of sub-pixels 10 are simultaneously turned on.
  • the first row of sub-pixels 10 receives the data signal Vdata input by the data line D1
  • the second row of sub-pixels 10 receives the additional data signal Add_Vdata input by the additional line L. Since the gate line G1 and the gate line G2 are simultaneously scanned, the probability of occurrence of signal delay when a part of the sub-pixel receives the source driver output signal is reduced, and the response speed of the display is improved.
  • the above “column” may be the extending direction of the data line, and the above “row” may be the gate line Extend the direction.
  • the extension line direction of the additional line L is substantially the same as the extension line direction of the data lines (D1, D2, D3, ..., Dj, ..., Gn).
  • the additional line L can be parallel to the data lines (D1, D2, D3...Dj...Gn), so that the additional line L and the data lines (D1, D2, D3...Dj) can be avoided.
  • a crossover causes a short circuit or an overlap that causes the coupling capacitance to increase.
  • the additional line L may be partially or entirely disposed in the same material as the data lines (D1, D2, D3, ..., Dj), so that the manufacturing process can be simplified.
  • Embodiments of the present disclosure provide an array substrate including a plurality of gate lines and data lines, and a plurality of sub-pixels defined by intersections of gate lines and data lines.
  • at least one sub-pixel of the same column in which at least one additional line for providing additional data signals is disposed between adjacent two columns of sub-pixels corresponds to at least one additional line
  • at least one sub-pixel of the sub-pixels of the same column is corresponding to the sub-pixel.
  • Additional line drive is provided.
  • the gate driver can scan a plurality of gate lines at the same time, so that the sub-pixels of different rows respectively connected with the data lines and the additional lines are simultaneously turned on, and respectively receive the data signals input by the data lines and the additional signals.
  • Additional data signal for line input Thereby, the transmission speed of the data signal or the additional data signal for displaying the image is improved, so that the ability to drive the display for display is doubled, and the response speed of the display is improved.
  • the structure of the array substrate is also different.
  • the structure of the array substrate corresponding to different numbers of additional lines L will be described in detail by way of a specific embodiment.
  • An additional line L is disposed between each adjacent two columns of sub-pixels 10 and sub-pixels 10'.
  • the sub-pixels 10 of the same column correspond to one data line and one additional line.
  • the sub-pixel 10 of the first column in FIG. 3 corresponds to the left side.
  • the switching unit of the sub-pixel 10 of the 2i+1th row, for example, the TFT is connected to the data lines (D1, D2, D3, ..., Dj...Dm) corresponding to the sub-pixel 10.
  • the TFT of the sub-pixel 10 of the 2i+2th row is connected to the additional line L corresponding to the sub-pixel 10.
  • the TFTs of the odd-line sub-pixels 10 are connected to the data lines (D1, D2, D3, ..., Dj...Dm); the TFTs of the even-line sub-pixels 10 are connected to the additional lines L.
  • the gate driver 12 can simultaneously input scan signals to the 2i+1th row and the 2i+2th row gate lines G2i+1 and G2i+2 so that the 2i+1th row and the 2i+2th row are sub-
  • the pixels 10 are simultaneously turned on, in which case the source driver 13 can simultaneously input the data signal Vdata to the data lines (D1, D2, D3 ... Dj ... Dm), and input the additional data signal Add_Vdata to each additional line L for Display the image.
  • the sub-pixels on the 2i+2th gate line G2i+2 and the sub-pixels 10 on the 2i+1th gate line G2i+1 can simultaneously receive the output of the source driver 13.
  • a signal for displaying an image when the gate line G2i+1 and the gate line G2i+2 are scanned row by row, the gate line G2i+2 is caused by the gate line G2i+2 being turned on later than the gate line G2i+1.
  • the sub-pixel 10 on which it is received receives the delay of the output signal of the source driver 13. Therefore, the signal delay is reduced, and the response speed of the display device is improved.
  • Two additional lines L are disposed between each adjacent two columns of sub-pixels 10 and sub-pixels 10'.
  • the sub-pixels 10 of the same column correspond to one data line and two additional lines L, and the two additional lines are respectively the first
  • the additional line L1 and the second additional line L2 for example, the sub-pixel 10 of the first column in FIG. 4 correspond to the left data line D1 and the right first additional line L1 and the second additional line L2.
  • the TFT of the 3i+1th row sub-pixel 10 is connected to the data lines (D1, D2, D3, ... Dj...Dm) corresponding to the sub-pixel 10.
  • the TFT of the sub-pixel 10 of the 3i+2th row is connected to the first additional line L1 corresponding to the sub-pixel 10.
  • the TFT of the sub-pixel 10 of the 3i+3th row is connected to the second additional line L2 corresponding to the sub-pixel 10.
  • the TFTs of the first row and the fourth row of sub-pixels 10 are connected to the data lines (D1, D2, D3, ..., Dj...Dm); the TFTs of the second row and the fifth row of sub-pixels 10 are The first additional lines L1 are connected; the TFTs of the third and sixth rows of sub-pixels 10 are connected to the second additional line L2.
  • the gate driver 12 can simultaneously input scan signals to the 3i+1th row, the 3i+2th row, and the 3i+3th row gate line G3i+1, the gate lines G3i+2, and G3i+3, so that the first The sub-pixels 10 of 3i+1, 3i+2, and 3i+3 are simultaneously turned on, in which case the source driver 13 can simultaneously input data to the data lines (D1, D2, D3...Dj...Dm).
  • the signal Vdata, the first additional data signal Add_Vdata1 is input to each of the first additional lines L1 and to the second additional lines L2, respectively.
  • a second additional data signal Add_Vdata2 for displaying an image.
  • the first additional data signal Add_Vdata1 and the second additional data signal Add_Vdata2 may be the same or different depending on the actual image display.
  • the sub-pixel 10 on the 3i+3th gate line G3i+3, the sub-pixel 10 on the 3i+2th gate line G3i+2, and the 3i+1th row gate The sub-pixel 10 on the line G3i+1 can simultaneously receive the signal output from the source driver 13 for displaying an image. Therefore, in the prior art, when the gate line G3i+1 and the gate line G3i+2 are scanned row by row, the gate line G3i+2 is caused by the gate line G3i+2 being turned on later than the gate line G3i+1.
  • the sub-pixel 10 on which it is received receives a delay in the output signal of the source driver 13. Therefore, the signal delay is reduced, and the response speed of the display device is improved.
  • the second embodiment is different from the first embodiment. Since the number of gate lines opened in the second embodiment is large, the faster the transmission speed of the output signal of the source driver 13 is, the faster the response speed of the constructed display is. However, since the number of additional lines L provided in the second embodiment is large, the data lines (D1, D2, D3, ..., Dj... in the solution provided in the second embodiment are the same as in the first embodiment. Dm) and the additional line L have a narrow line width, which requires high manufacturing process and precision.
  • the embodiments of the present disclosure are merely illustrative of the specific structure of the array substrate provided with one and two additional lines. The array substrate having other numbers of additional lines will not be further described herein, but all should belong to the protection of the present disclosure. range.
  • the data lines (D1, D2, D3, ..., Dj... Dm) or the additional lines L of the sub-pixels controlled by the odd-numbered gate lines are connected with the sub-pixels controlled by the even rows. instruction of.
  • the solution provided by the present disclosure is not limited to the above connection manner, the gate line where the sub-pixel 10 connected to the additional line L is located and the gate where the sub-pixel 10 connected to the data line (D1, D2, D3, ... Dj...Dm) is located.
  • the line is not limited, as long as the signal lines for providing data signals to the respective gate lines that are simultaneously turned on are different.
  • the sub-pixel 10 controlled by the gate line G1 can be connected to the data lines (D1, D2, D3, ..., Dj...Dm), and the sub-pixel 10 controlled by the gate line G4 can be connected to the additional line.
  • the sub-pixel 10 controlled by the gate line G2 can be connected to the data lines (D1, D2, D3, ..., Dj...Dm), and the sub-pixel 10 controlled by the gate line G7. Can connect the first additional line L1, the gate line G10 The controlled sub-pixel 10 can be connected to the second additional line L2.
  • Other connection methods are equally available and will not be described here.
  • the first additional line L1 is disposed between the sub-pixel 10 and the second additional line L2;
  • the first via 30 is disposed on the source 20 of the TFT of the sub-pixel 10 in the 3i+3 row (for example, the third row);
  • a second via 31 is provided on the second additional line L2.
  • the source 20 of the TFT of the sub-pixel 10 passes through the first lap electrode layer 21 that penetrates the first via hole 30 and the second via hole 31, respectively, and the second additional line L2.
  • the electrodes are connected such that the TFTs of the i+2th row sub-pixel 10 can be connected to the second additional line L2.
  • the first lap electrode layer 21 may be made of a transparent conductive material, such as indium tin oxide or indium zinc oxide, or may be prepared by using a gate metal layer constituting the TFT gate 22 .
  • the line width a of the portion overlapping the first additional line L1 and the first lap electrode layer 21 may be smaller than the line width b of the first additional line L1.
  • the line width of the portion overlapping the first lap electrode layer 21 and the first additional line L1 may be smaller than the line width of the first lap electrode layer 21. In this way, by reducing the area of the upper and lower substrates constituting the coupling capacitance between the first additional line L1 and the first lap electrode layer 21, the purpose of reducing the coupling capacitance can be achieved.
  • the line width c of the portion of the second additional line L2 on which the second via hole 31 is provided is larger than the line width b of the second additional line L2.
  • the line width of the portion overlapping the first lap electrode layer 21 and the second additional line L2 is larger than the line width of the first lap electrode layer 21. In this way, by increasing the local line width of the first lap electrode layer 21 or the second additional line L2, the yield of the electrical connection at the position of the second via 31 on the second additional line L2 can be increased.
  • a contact electrode for connecting the first lap electrode layer 21 and the second additional line L2 is formed (at Other In the embodiment, there may be other additional lines, such as the first attachment line L1).
  • the contact electrode is small, so those skilled in the art can reduce the size of the via hole by ensuring that the array substrate has a certain electrical connection yield according to actual needs. The purpose of contacting the electrodes.
  • the first additional line L1 is disposed between the sub-pixel 10 and the second additional line L2;
  • the first additional line L1 is divided into upper and lower portions at the junction of the second additional line L2 and the source 20 of the TFT.
  • the upper and lower portions of the first additional line L1 are respectively provided with a fourth via hole 33, and the second overlapping electrode layer 34 can electrically connect the upper and lower portions of the first additional line L1 through the fourth via hole 33.
  • the optional source 3 of the TFT of the sub-pixel 10 of the 3i+3th row may be disposed in the same material as the second additional line L2, thereby simplifying the manufacturing process.
  • the upper and lower portions of the first additional line L1 are electrically connected by the second lap electrode layer 34, thereby preventing the first via 30 from being formed on the source 20 of the TFT.
  • a process error has a bad influence on the TFT region, for example, causing a short circuit or a short circuit.
  • the length of the second lap electrode layer 34 is relatively shorter than the length of the first lap electrode layer 21, so the fourth embodiment is advantageous for increasing the transmission speed of the signal with respect to the third embodiment.
  • a gate line layer is formed on a substrate.
  • a thin film layer composed of a gate metal layer is deposited on a transparent substrate by sputtering deposition on a glass substrate.
  • the gate metal layer may be a simple metal of any one of metallic copper Cu, aluminum Al, molybdenum Mo, titanium Ti, chromium Cr or tungsten W, or an alloy composed of the above-mentioned metal simple substance.
  • the above gate metal layer may be a single layer structure, or may be a multilayer structure, such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Ti ⁇ Cu.
  • the substrate on which the gate metal layer is deposited is coated with a photoresist, and the gate line layer includes a gate line (G1, G2, G3, ..., Gi) and a gate electrode 22 through an exposure development and etching process.
  • a gate line G1, G2, G3, ..., Gi
  • Gi gate line
  • a common electrode line not shown
  • a gate insulating layer is formed.
  • a gate insulating layer is deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition), and the gate insulating layer may be formed of silicon nitride.
  • an active layer pattern is formed.
  • a-Si is deposited by PECVD, or IGZO (indium gallium zinc oxide) is deposited by sputtering.
  • the photoresist is then coated, and a pattern of the active layer is formed by an exposure development and etching process.
  • a data line layer is formed.
  • a data line metal layer is deposited by a sputtering process, and the data line metal layer may be any of metallic copper Cu, aluminum Al, molybdenum Mo, titanium Ti, chromium Cr or tungsten W.
  • a metal element or an alloy composed of the above-mentioned metal is coated, and data lines (D1, D2, D3, ..., Dj...Dm), a first additional line L1, a second additional line L2, and a source 20 and a drain 23 of the TFT are formed by an exposure and development and etching process.
  • a passivation layer is formed.
  • silicon nitride or a resin layer is deposited by PECVD, and then a photoresist is applied, and the first via 30, the second via 31, and the corresponding are formed by exposure development and etching processes.
  • a pixel electrode is formed.
  • a transparent conductive layer such as indium tin oxide (ITO) is formed by a sputtering process.
  • a photoresist is coated, and the pixel electrode 14 and the first lap electrode layer 21 are formed by an exposure development and etching process.
  • the pixel electrode 14 and the drain electrode 23 are connected through the third via hole 32, and the source electrode 20 is connected to the second additional line L2 through the first via hole 20 and the second via hole 31.
  • the above steps are only one of the ways of fabricating the array substrate, and other methods such as a gate insulating layer, the active layer and the data line layer may be formed in one patterning process.
  • the pixel electrode 14 may be formed first, and after the pixel electrode 14 is deposited, the first lap electrode layer 21 is formed by an exposure development and etching process. At this time, the first lap electrode layer 21 and the drain 22 are made of the same material.
  • the first lap electrode layer 21 is made of a metal material which is more conductive than the transparent conductive material.
  • the first lap electrode layer 21 and the pixel electrode layer 14 cannot be formed at the same time, but need to be separately formed by two steps, so that the fabrication process is relatively complicated. In summary, those skilled in the art can select the above manufacturing method according to actual needs.
  • the above fabrication process is merely an example of the fabrication process of the array substrate provided in the second embodiment.
  • the array substrate of other structures is similarly available, and will not be further described herein.
  • Embodiments of the present disclosure provide a display device including any of the array substrates described above. It has the same structure and advantageous effects as the array substrate provided by the foregoing embodiments. Since the structure and beneficial effects of the array substrate have been described in detail in the foregoing embodiments, details are not described herein again.
  • the display device may specifically include a liquid crystal display device.
  • the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • the embodiment of the present disclosure provides a method for driving an array substrate, which may include a method for driving any one of the above array substrates. As shown in FIG. 6, the method may further include:
  • the data line inputs a data signal to a sub-pixel where the TFT connected to the sub-pixel controlled by one row of the gate line is located.
  • the at least one additional line inputs an additional data signal to at least one of the remaining gate lines of the remaining gate lines.
  • steps S102 and S103 can be performed simultaneously.
  • Embodiments of the present disclosure provide a driving method of an array substrate, including first, simultaneously inputting a scan signal to at least two rows of gate lines; and then inputting data to a sub-pixel where a TFT connected to a sub-pixel controlled by one row of gate lines is located. a signal; at least one additional line inputs an additional data signal to at least one of the remaining gate lines of the remaining gate lines.
  • the gate driver can simultaneously scan a plurality of gate lines, so that the sub-pixels of different rows connected with the data lines and the additional lines are simultaneously turned on, and respectively receive the data signals input by the data lines and the additional lines. Additional data signals entered. Thereby, the transmission speed of the data signal or the additional data signal for displaying the image is improved, so that the ability to drive the display for display is doubled, and the response speed of the display is improved.
  • the structure of the array substrate is also different, and thus the above driving method is also different.
  • the driving method of the array substrate corresponding to the different number of additional lines L will be described in detail by way of a specific embodiment.
  • an additional line L is disposed between each adjacent two columns of sub-pixels 10 and sub-pixels 10'; the TFTs of the 2i+1-th row sub-pixels 10 and the data lines corresponding to the sub-pixels 10 (D1) , D2, D3, ... Dj...Dm) are connected; the TFT of the 2i+2th row of sub-pixels 10 is attached to the sub-pixel 10
  • the above driving method is as shown in FIG. 7, and may include:
  • the timing controller 11 outputs the STV signal to the gate driver 12, and shifts the received STV signal step by step through the shift register 120 to output a scan signal.
  • the level shifter 121 receives the scan signal and refers to the OE signal to output a scan signal to the 2i+1th row and the 2i+2th row gate line.
  • the data lines (D1, D2, D3, ..., Dj, ... Dn) input the data signal Vdata to the sub-pixel 10 located in the 2i+1th row.
  • the timing controller 11 outputs the STH signal, the DD signal, and the LP signal to the source driver 13, and the STH signal latches the DD signal in the corresponding channel in the latch 130, and then follows the LP signal to the data line (D1).
  • D2, D3 ... Dj ... Dn) output a DD signal which is converted into data lines (D1, D2, D3 ... Dj ... Dn) by the digital-to-analog converter 131 to input data to the sub-pixel 10 located in the 2i+1th row.
  • Signal Vdata the timing controller 11 outputs the STH signal, the DD signal, and the LP signal to the source driver 13, and the STH signal latches the DD signal in the corresponding channel in the latch 130, and then follows the LP signal to the data line (D1).
  • D2, D3 ... Dj ... Dn output a DD signal which is converted into data lines (D1, D2, D3 ... Dj ... Dn) by the digital-to-analog converter
  • the additional line L inputs the additional data signal Add_Vdata to the sub-pixel 10 located in the 2i+2th row.
  • steps S202 and S203 can be performed simultaneously.
  • the subpixels on the 2i+1th row gate line G2i+2 and the 2i+1th row gate line G2i+1 The upper sub-pixel 10 can simultaneously receive a signal output from the source driver 13 for displaying an image. Therefore, in the prior art, when the gate line G2i+1 and the gate line G2i+2 are scanned row by row, the gate line G2i+2 is caused by the gate line G2i+2 being turned on later than the gate line G2i+1.
  • the sub-pixel 10 on which it is received receives a delay in the output signal of the source driver 13. Therefore, the signal delay is reduced, and the response speed of the display device is improved.
  • the sub-pixels 10 of the same column correspond to one data line and two additional lines, and the two additional lines are respectively the first The additional line L1 and the second additional line L2;
  • the TFT of the 3i+1th row sub-pixel 10 is connected to the data line (D1, D2, D3...Dj...Dm) corresponding to the sub-pixel 10;
  • the TFT of 10 is connected to the first additional line L1 corresponding to the sub-pixel 10; when the TFT of the 3i+3-row sub-pixel 10 is connected to the second additional line L2 corresponding to the sub-pixel 10, the driving method is as shown in FIG. 8. As shown, it can include:
  • the data lines (D1, D2, D3, ..., Dj, ... Dm) input the data signal Vdata to the sub-pixel 10 located in the 3i+1th row.
  • the first additional line L1 inputs the first additional data signal Add_Vdata1 to the sub-pixel 10 located in the 3i+2th row.
  • the second additional line L2 inputs the second additional data signal Add_Vdata2 to the sub-pixel 10 located in the 3i+3th row.
  • steps S302, S303 and S304 can be performed simultaneously.
  • the sub-pixels 10 and 3i on the 3i+3th row gate line G3i+3 can simultaneously receive the signal output from the source driver 13 for displaying an image. Therefore, in the prior art, when the gate line G3i+1 and the gate line G3i+2 are scanned row by row, the gate line G3i+2 is caused by the gate line G3i+2 being turned on later than the gate line G3i+1.
  • the sub-pixel 10 on which it is received receives a delay in the output signal of the source driver 13. Therefore, the signal delay is reduced, and the response speed of the display device is improved.
  • Embodiment 6 With respect to the fifth embodiment, since the number of gate lines opened in the sixth embodiment is large, the faster the transmission speed of the output signal of the source driver 13, the faster the response speed of the constructed display.
  • the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

一种阵列基板及其驱动方法、显示装置，所述阵列基板包括多条栅线（G1、G2、G3…Gi…Gn）和数据线（D1、D2、D3…Dj…Dm），以及由栅线（G1、G2、G3…Gi…Gn）和数据线（D1、D2、D3…Dj…Dm）交叉界定的多个亚像素(10)，相邻两列亚像素(10,10')之间设置有至少一条用于提供附加数据信号的附加线(L)，同一列的亚像素(10)对应至少一条附加线(L)；同一列的所述亚像素(10)中至少一个亚像素(10)由该亚像素(10)对应的所述附加线(L)驱动。

Description

阵列基板及其驱动方法、显示装置
相关申请的交叉引用
本申请主张在2015年4月8日在中国提交的中国专利申请号No.201510163454.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其驱动方法、显示装置。
背景技术
TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管-液晶显示器)作为一种平板显示装置，因其具有体积小、功耗低、无辐射以及制作成本相对较低等特点，而越来越多地被应用于高性能显示领域当中。
TFT-LCD显示装置，如图1所示，包括有效显示区域(Active Area，简称AA区)和非显示区域。其中，在AA区内，多条横纵交叉的栅线(G1、G2、G3…Gi…Gn)和数据线(D1、D2、D3…Dj…Dm)交叉界定出多个呈矩阵形式排列的亚像素10。在除了AA区以外的非显示区域内，设置有时序控制器11、栅极驱动器12以及源极驱动器13。
其中，时序控制器11用于将STV(Gate Driver Start Signal，栅极驱动器起始信号)输出至栅极驱动器12，通过移位寄存器120将所接收的STV信号逐级移位，以便输出扫描信号。电平移位器121接收扫描信号并参照OE(Output Enable，使能信号)决定是否向栅线(例如Gi)输出扫描信号。同时，时序控制器11向源极驱动器13输出STH(Source Driver Start Signal，源极驱动器起始信号)、DD(Digital Data，数字显示数据)与LP(Latch Input，锁存信号)，STH信号在锁存器130中把DD信号锁存在对应的通道中，再依照LP信号决定是否向数据线(例如Dj)输出DD信号，该DD信号经数字模拟转换器131转换为数据信号Vdata。当上述栅线逐行打开时，所述数据信号Vdata会输入至对应的数据线，从而实现显示图像。
然而现有技术中，对于高PPI(Pixels Per Inch，每英寸所拥有的像素数目)的显示器而言，由于亚像素10的数量较多，从而使得栅线的数量较多。 在此情况下，栅线(G1、G2、G3…Gi…Gn)在逐行开启的过程中，开启时间较晚的一行亚像素10，接收数据线(D1、D2、D3…Dj…Dm)输入的数据信号Vdata的时间会有所延迟。从而降低了显示器的响应速度，影响了高PPI显示器的显示品质。
发明内容
本公开的实施例提供一种阵列基板及其驱动方法、显示装置，能够解决由于栅线在逐行开启的过程中，开启时间较晚的亚像素接收数据信号有所延迟的问题。
为达到上述目的，本公开的实施例采用如下技术方案：
本公开实施例的一方面，提供一种阵列基板，包括多条栅线和数据线，以及由所述栅线和所述数据线交叉界定的多个亚像素，其中，
相邻两列所述亚像素之间设置有至少一条用于提供附加数据信号的附加线，同一列的所述亚像素对应至少一条附加线；
同一列的所述亚像素中至少一个亚像素由该亚像素对应的所述附加线驱动。
本公开实施例的另一方面，提供一种显示装置包括如上所述的任意一种阵列基板。
本公开实施例的又一方面，提供一种阵列基板的驱动方法，包括：
同时对至少两行栅线输入扫描信号；
数据线向其中一行所述栅线控制的亚像素输入数据信号；
至少一条附加线向其余的所述栅线控制的亚像素输入附加数据信号。
本公开实施例提供一种阵列基板及其驱动方法、显示装置。其中所述阵列基板包括多条栅线和数据线，以及由栅线和数据线交叉界定的多个亚像素。此外，相邻两列亚像素之间设置有至少一条用于提供附加数据信号的附加线同一列的亚像素对应至少一条附加线，同一列的所述亚像素中至少一个亚像素由该亚像素对应的附加线驱动。这样一来，通过设置上述附加线，栅极驱动器可以同时扫描多条栅线，使得分别连接有数据线和附加线的不同行的亚像素同时开启，并分别接收数据线输入的数据信号以及附加线输入的附加数据信号。从而提高了用于显示图像的数据信号或附加数据信号的传输速度， 使得驱动显示器进行显示的能力倍增，提升了显示器的响应速度。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种显示装置的结构示意图；
图2为本公开实施例提供的一种阵列基板的结构示意图；
图3为本公开实施例提供的另一种阵列基板的结构示意图；
图4为本公开实施例提供的又一种阵列基板的结构示意图；
图5a为图4中的A处一种局部结构放大示意图；
图5b为图4中的A处另一种局部结构放大示意图；
图6为一种用于驱动如图2所示的阵列基板的方法流程图；
图7为一种用于驱动如图3所示的阵列基板的方法流程图；
图8为一种用于驱动如图4所示的阵列基板的方法流程图。
附图标记：
10、10’-亚像素；11-时序控制器；12-栅极驱动器；120-移位寄存器；121-电平移位器；13-源极驱动器；130-锁存器；131-数字模拟转换器；G1、G2、G3…Gi…Gn-栅线；D1、D2、D3…Dj…Dm-数据线；L-附加线；L1-第一附加线；L2-第二附加线；14-像素电极；20-源极；21-第一搭接电极层；22-栅极；23-漏极；30-第一过孔；31-第二过孔；32-第三过孔；33-第四过孔；34-第二搭接电极层；a-第一附加线上与第一搭接电极层之间重叠部分的线宽；b-第一附加线的线宽；c-第二附加线上设置有第二过孔的部分的线宽。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领 域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开实施例提供一种阵列基板，如图2所示，可以包括多条栅线(G1、G2、G3…Gi…Gn)和数据线(D1、D2、D3…Dj…Dm)，以及由上述栅线(G1、G2、G3…Gi…Gn)和数据线(D1、D2、D3…Dj…Dm)交叉界定的多个亚像素10。其中，i、j为大于等于0的整数，n和m为大于等于1的整数；上述“多个”可以是至少一个，“多条”可以是至少一条。
此外，相邻两列亚像素10和亚像素10’之间设置有至少一条用于提供附加数据信号Add_Vdata的附加线L，同一列的亚像素10对应至少一条附加线L。
同一列的亚像素10中至少一个亚像素10由该亚像素10对应的附加线L驱动。
需要说明的是，第一、本公开实施例中的附加线L的作用与如图1所示的数据线(D1、D2、D3…Dm)的作用相同，均是用于接收如图1所示的源极驱动器13输出的用于显示图像的信号。因此，上述附加数据信号Add_Vdata与数据信号Vdata均是上述用于显示图像的信号。
如图2所示，由于至少一行亚像素10由附加线L驱动，这样一来，可以无需逐行扫描栅线G1和G2，而可以同时向栅线G1和栅线G2输入扫描信号，使得第一行亚像素10和第二行亚像素10同时打开。第一行亚像素10接收数据线D1输入的数据信号Vdata，第二行亚像素10接收附加线L输入的附加数据信号Add_Vdata。由于栅线G1和栅线G2同时扫描，因此减小了部分亚像素接收源极驱动器输出信号时，出现信号延迟的现象的几率，提高了显示器的响应速度。
其中，上述“列”可以是数据线的延伸方向，上述“行”可以是栅线的 延伸方向。
上述附加线L的延长线方向与数据线(D1、D2、D3…Dj…Gn)的延长线方向大致相同。当然可选的，附加线L可以与数据线(D1、D2、D3…Dj…Gn)相平行，这样一来，可以使得避免附加线L与数据线(D1、D2、D3…Dj)之间出现交叉而导致信号短路，或出现重叠而导致耦合电容增加。
此外，上述附加线L可以部分或全部与所述数据线(D1、D2、D3…Dj)同层同材料设置，从而可以简化制作工艺。
本公开实施例提供一种阵列基板，包括多条栅线和数据线，以及由栅线和数据线交叉界定的多个亚像素。此外，相邻两列亚像素之间设置有至少一条用于提供附加数据信号的附加线同一列的亚像素对应至少一条附加线，同一列的亚像素中至少一个亚像素由该亚像素对应的附加线驱动。这样一来，通过设置上述附加线，栅极驱动器可以同时扫描多条栅线，使得分别连接有数据线和附加线的不同行的亚像素同时开启，并分别接收数据线输入的数据信号以及附加线输入的附加数据信号。从而提高了用于显示图像的数据信号或附加数据信号的传输速度，使得驱动显示器进行显示的能力倍增，提升了显示器的响应速度。
由于在阵列基板上，附加线L的数量不同，阵列基板的结构也不尽相同。以下，通过具体的实施例对不同数量的附加线L对应的阵列基板的结构进行详细的举例说明。
实施例一
每相邻两列亚像素10与亚像素10’之间设置有一条附加线L，同一列的亚像素10对应一条数据线和一条附加线，例如图3中第一列的亚像素10对应左边的数据线D1和右边的附加线L。
第2i+1行亚像素10的开关单元，例如TFT与该亚像素10对应的数据线(D1、D2、D3…Dj…Dm)相连接。
第2i+2行亚像素10的TFT与该亚像素10对应的附加线L相连接。
其中，i≥0，且为整数。
具体的，如图3所示，奇数行亚像素10的TFT与数据线(D1、D2、D3…Dj…Dm)相连接；偶数行亚像素10的TFT与附加线L相连接。
这样一来，栅极驱动器12可以同时向第2i+1行和第2i+2行栅线G2i+1和G2i+2输入扫描信号，以使得第2i+1行和第2i+2行的亚像素10同时打开，在此情况下，源极驱动器13可以同时向数据线(D1、D2、D3…Dj…Dm)输入数据信号Vdata，以及向每一条附加线L输入附加数据信号Add_Vdata，用于显示图像。
由于两行栅线同时被扫描，因此第2i+2行栅线G2i+2上的亚像素与第2i+1行栅线G2i+1上的亚像素10可以同时接收源极驱动器13输出的用于显示图像的信号。从而避免了现有技术中，逐行对栅线G2i+1和栅线G2i+2进行扫描时，由于栅线G2i+2打开时间晚于栅线G2i+1，而导致的栅线G2i+2上所在的亚像素10接收源极驱动器13输出信号的延迟。因此，减小了信号延时，提升了显示器件的响应速度。
实施例二
每相邻两列亚像素10与亚像素10’之间设置有两条附加线L，同一列的亚像素10对应一条数据线和两条附加线L，所述两条附加线分别为第一附加线L1和第二附加线L2，例如图4中第一列的亚像素10对应左边的数据线D1和右边的第一附加线L1和第二附加线L2。
第3i+1行亚像素10的TFT与该亚像素10对应的数据线(D1、D2、D3…Dj…Dm)相连接。
第3i+2行亚像素10的TFT与该亚像素10对应的第一附加线L1相连接。
第3i+3行亚像素10的TFT与该亚像素10对应的第二附加线L2相连接。
其中，i≥0，且为整数。
具体的，如图4所示，第一行、第四行亚像素10的TFT与数据线(D1、D2、D3…Dj…Dm)相连接；第二行、第五行亚像素10的TFT与第一附加线L1相连接；第三行、第六行亚像素10的TFT与第二附加线L2相连接。
这样一来，栅极驱动器12可以同时向第3i+1行、第3i+2行以及第3i+3行栅线G3i+1、栅线G3i+2以及G3i+3输入扫描信号，以使得第3i+1行、第3i+2行以及第3i+3行的亚像素10同时打开，在此情况下，源极驱动器13可以同时向数据线(D1、D2、D3…Dj…Dm)输入数据信号Vdata、向每一条第一附加线L1以及向第二附加线L2分别输入第一附加数据信号Add_Vdata1 和第二附加数据信号Add_Vdata2，用于显示图像。其中，根据实际图像显示的需要，上述第一附加数据信号Add_Vdata1和第二附加数据信号Add_Vdata2可以相同，也可以不同。
由于上述三行栅线同时被扫描，因此第3i+3行栅线G3i+3上的亚像素10、第3i+2行栅线G3i+2上的亚像素10，以及第3i+1行栅线G3i+1上的亚像素10可以同时接收源极驱动器13输出的用于显示图像的信号。从而避免了现有技术中，逐行对栅线G3i+1和栅线G3i+2进行扫描时，由于栅线G3i+2打开时间晚于栅线G3i+1，而导致的栅线G3i+2上所在的亚像素10接收源极驱动器13输出信号有所延迟。因此，减小了信号延时，提升了显示器件的响应速度。
实施例二相对于实施例一而言，由于实施例二打开的栅线的数量较多，因此源极驱动器13输出信号的传输速度越快，构成的显示器的响应速度也越快。然而，由于实施例二设置的附加线L的数量较多，因此相对于实施例一而言，如果布线区域相同，那么实施例二提供给的方案中数据线(D1、D2、D3…Dj…Dm)和附加线L的线宽较窄，从而对制作工艺和精度的要求较高。
综上所述，同时打开的栅线越多，需要设置的附加线的条数越多，信号的延时率越低，显示器件的响应速度越高，然而制作工艺和精度的要求也越高。本公开实施例仅仅是对设置有一条和两条附加线的阵列基板的具体结构进行了说明，具有其它数目的附加线的阵列基板在此不再一一赘述，但都应当属于本公开的保护范围。此外，实施例一和实施例二均是以奇数行栅线控制的亚像素与偶数行控制的亚像素连接不同的数据线(D1、D2、D3…Dj…Dm)或附加线L为例进行的说明。当然，本公开提供的方案不仅限于上述连接方式，对与附加线L连接的亚像素10所在的栅线和与数据线(D1、D2、D3…Dj…Dm)连接的亚像素10所在的栅线不做限定，只要向同时打开的各行栅线提供数据信号的信号线不同即可。例如需要同时打开栅线G1和栅线G4，那么栅线G1控制的亚像素10可以连接数据线(D1、D2、D3…Dj…Dm)，栅线G4控制的亚像素10可以连接附加线。或者，需要同时打开栅线G2、栅线G7和栅线G10，那么栅线G2控制的亚像素10可以连接数据线(D1、D2、D3…Dj…Dm)，栅线G7控制的亚像素10可以连接第一附加线L1，栅线G10 控制的亚像素10可以连接第二附加线L2。其他连接方式同理可得，此处不再赘述。
以下通过具体的实施例，对实施例二提供的阵列基板中，第一附加线L和第二附加线L2的设置方式进行详细的说明：
实施例三
如图4或图5a所示，第一附加线L1设置于亚像素10与第二附加线L2之间；
第3i+3行(例如第三行)亚像素10的TFT的源极20上设置有第一过孔30；
第二附加线L2上设置有第二过孔31。
第3i+3行(例如第三行)亚像素10的TFT的源极20，通过分别贯通第一过孔30和第二过孔31的第一搭接电极层21，与第二附加线L2相连接，从而使得第i+2行亚像素10的TFT能够与第二附加线L2相连接。其中，所述第一搭接电极层21可以采用透明导电材料构成，例如氧化铟锡或氧化铟锌，还可以采用构成TFT栅极22的栅极金属层进行制备。
其中，第一附加线L1上与第一搭接电极层21之间重叠部分的线宽a，可以小于第一附加线L1的线宽b。
或者，还可以将第一搭接电极层21上与第一附加线L1之间重叠部分的线宽，小于上述第一搭接电极层21的线宽。这样一来，通过减小构成第一附加线L1与第一搭接电极层21之间耦合电容上、下基板的面积，可以达到减小耦合电容的目的。
此外，第二附加线L2上设置有第二过孔31的部分的线宽c，大于所述第二附加线L2的线宽b。
或，第一搭接电极层21上与第二附加线L2之间重叠部分的线宽，大于第一搭接电极层21的线宽。这样一来，通过增加第一搭接电极层21或第二附加线L2的局部线宽，从而可以增加第二附加线L2上第二过孔31位置处的电气连接的良率。
并且，在第一过孔30和第二过孔31内，在形成第一搭接电极层21的同时，形成用于连接第一搭接电极层21与第二附加线L2的接触电极(在其他 实施例中，可能为其他的附加线，如第一附件线L1)。当过孔较小时，上述接触电极较小，因此本领域技术人员，可以根据实际需要在确保阵列基板具有一定的电气连接良率的情况下，减小上述过孔的尺寸，已达到减小上述接触电极的目的。
实施例四
如图5b所示，第一附加线L1设置于亚像素10与第二附加线L2之间；
第一附加线L1在第二附加线L2和TFT的源极20相连接处被分成上、下两部分。第一附加线L1的上、下两部分分别设置有第四过孔33，第二搭接电极层34可以通过第四过孔33将第一附加线L1的上、下两部分电连接。
此外，可选的第3i+3行(例如第三行)亚像素10的TFT的源极20可以与第二附加线L2同层同材料设置，从而可以简化制作工序。
这样一来，相对于实施例三而言，通过第二搭接电极层34将第一附加线L1的上、下两部分电连接，可以避免在TFT的源极20上制作第一过孔30时，由于工艺误差对TFT区域产生不良的影响，例如造成短路或短路。此外，第二搭接电极层34的长度相对与第一搭接电极层21的长度而言较短，因此实施例四相对于实施例三而言，有利于提升信号的传输速度。
以实施例二提供的阵列基板为例，对上述阵列基板的具体制作方法进行详细的描述。
首先，在基板上形成栅线层。例如玻璃基板上通过溅射沉积的方法，在透明基板上沉积有栅极金属层构成的薄膜层。其中，所述栅极金属层可以是金属铜Cu、铝Al、钼Mo、钛Ti、铬Cr或钨W中的任意一种金属单质，或由上述金属单质构成的合金。当然上述栅极金属层可以是单层结构，还可以是多层结构，例如Mo\Al\Mo，Ti\Cu\Ti，Mo\Ti\Cu。
对沉积有栅极金属层的基板涂覆光刻胶，通过曝光显影、刻蚀工艺，栅线层包括形成栅线(G1、G2、G3…Gi)、栅极22。当然，还可以包括形成公共电极线(图中未示出)的图案。
然后，形成栅极绝缘层。例如采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法)沉积栅极绝缘层，该栅极绝缘层可以有氮化硅构成。
接下来，形成有源层图案。在形成有栅极绝缘层的基板表面，采用PECVD沉积a-Si，或者采用溅射的方法沉积IGZO(indium gallium zinc oxide，铟镓锌氧化物)。之后涂覆光刻胶，通过曝光显影、刻蚀工艺形成有源层的图案。
接下来，形成数据线层。例如在形成有有源层图案的基板表面，通过溅射工艺沉积数据线金属层，该数据线金属层可以是金属铜Cu、铝Al、钼Mo、钛Ti、铬Cr或钨W中的任意一种金属单质，或由上述金属单只构成的合金。然后涂覆光刻胶，通过曝光显影、刻蚀工艺形成数据线(D1、D2、D3…Dj…Dm)、第一附加线L1、第二附加线L2以及TFT的源极20和漏极23的图形。
接下来，形成钝化层。例如在形成有上述结构的基板表面，采用PECVD沉积氮化硅或涂覆树脂层，然后涂覆光刻胶，通过曝光显影、刻蚀工艺形成第一过孔30、第二过孔31以及对应于漏极23位置的第三过孔32。其中，第一过孔30的底部露出源极20，第二过孔31露出第二附加线L2，第三过孔32露出漏极23。
最后，形成像素电极。在形成有上述结构的基板表面，通过溅射工艺形成透明导电层，例如氧化铟锡(ITO)。然后涂覆光刻胶，通过曝光显影、刻蚀工艺形成像素电极14和第一搭接电极层21。其中，像素电极14与漏极23通过第三过孔32相连接，源极20通过第一过孔20和第二过孔31与第二附加线L2相连接。
需要说明的是，上述步骤仅是制作阵列基板的方式之一，还可以采用其他方法，例如栅极绝缘层，有源层和数据线层可以在一次构图工艺中形成。
在上述步骤还可以首先形成像素电极14，而在像素电极14之后沉积栅极金属层，通过曝光显影、刻蚀工艺形成上述第一搭接电极层21。这时，该第一搭接电极层21与漏极22的同材料制成。在该方法中，第一搭接电极层21采用金属材料，其相对于透明导电材料而言，其导电性能更好。但是，采用该方法时，第一搭接电极层21与像素电极层14不能同时形成，而需要通过两个步骤分别形成，因此制作程序上相对复杂。综上所述，本领域技术人员，可以根据实际需要，对上述制作方法进行选择。
上述制作过程，仅仅是对实施例二提供的阵列基板的制作过程进行的举例说明，其它结构的阵列基板同理可得，在此不再一一赘述。
本公开实施例提供一种显示装置，包括如上所述的任意一种阵列基板。具有与前述实施例提供的阵列基板相同的结构和有益效果。由于前述实施例中已经对阵列基板的结构和有益效果进行了详细的描述，此处不再赘述。
其中，在本公开实施例中，显示装置具体可以包括液晶显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本公开实施例提供一种阵列基板的驱动方法，可以包括用于驱动上述任意一种阵列基板的方法，如图6所示，还可以包括：
S101、同时对至少两行栅线输入扫描信号。
S102、数据线向与其一行栅线控制的亚像素相连接的TFT所在的亚像素输入数据信号。
S103、至少一条附加线向其余的栅线中至少一行栅线控制的亚像素输入附加数据信号。
其中，步骤S102和S103可以同时进行。
本公开实施例提供一种阵列基板的驱动方法，包括首先，同时对至少两行栅线输入扫描信号；然后，数据线向与其一行栅线控制的亚像素相连接的TFT所在的亚像素输入数据信号；至少一条附加线向其余的栅线中至少一行栅线控制的亚像素输入附加数据信号。这样一来，通过设置上述附加线，栅极驱动器可以同时扫描多条栅线，使得连接有数据线和附加线的不同行的亚像素同时开启，并分别接收数据线输入的数据信号以及附加线输入的附加数据信号。从而提高了用于显示图像的数据信号或附加数据信号的传输速度，使得驱动显示器进行显示的能力倍增，提升了显示器的响应速度。
由于在阵列基板上，附加线L的数量不同，阵列基板的结构也不尽相同，因此上述驱动方法也有所差异。以下，通过具体的实施例对不同数量的附加线L对应的阵列基板的驱动方法进行详细的举例说明。
实施例五
如图3所示，当每相邻两列亚像素10与亚像素10’之间设置有一条附加线L；第2i+1行亚像素10的TFT与该亚像素10对应的数据线(D1、D2、D3…Dj…Dm)相连接；第2i+2行亚像素10的TFT与该亚像素10对应的附 加线L相连接时，上述驱动方法如图7所示，可以包括：
S201、同时对第2i+1行和第2i+2行栅线输入扫描信号。
具体的，时序控制器11将STV信号输出至栅极驱动器12，通过移位寄存器120将所接收的STV信号逐级移位，以便输出扫描信号。电平移位器121接收扫描信号并参照OE信号，向第2i+1行和第2i+2行栅线输出扫描信号。
S202、数据线(D1、D2、D3…Dj…Dn)向位于第2i+1行的亚像素10输入数据信号Vdata。
具体的，时序控制器11向源极驱动器13输出STH信号、DD信号与LP信号，STH信号在锁存器130中把DD信号锁存在对应的通道中，再依照LP信号，向数据线(D1、D2、D3…Dj…Dn)输出DD信号，该DD信号经数字模拟转换器131转换为数据线(D1、D2、D3…Dj…Dn)向位于第2i+1行的亚像素10输入数据信号Vdata。
S203、附加线L向位于第2i+2行的亚像素10输入附加数据信号Add_Vdata。
其中，步骤S202和S203可以同时进行。
由于两行栅线(第2i+1行和第2i+2行栅线)同时被扫描，因此第2i+1行栅线G2i+2上的亚像素与第2i+1行栅线G2i+1上的亚像素10可以同时接收源极驱动器13输出的用于显示图像的信号。从而避免了现有技术中，逐行对栅线G2i+1和栅线G2i+2进行扫描时，由于栅线G2i+2打开时间晚于栅线G2i+1，而导致的栅线G2i+2上所在的亚像素10接收源极驱动器13输出信号有所延迟。因此，减小了信号延时，提升了显示器件的响应速度。
实施例六
如图4所示，当每相邻两列亚像素10之间设置有两条附加线，同一列的亚像素10对应一条数据线和两条附加线，所述两条附加线分别为第一附加线L1和第二附加线L2；第3i+1行亚像素10的TFT与该亚像素10对应的数据线(D1、D2、D3…Dj…Dm)相连接；第3i+2行亚像素10的TFT与该亚像素10对应的第一附加线L1相连接；第3i+3行亚像素10的TFT与该亚像素10对应的第二附加线L2相连接时，上述驱动方法如图8所示，可以包括：
S301、同时对第3i+1行、第3i+2行以及第3i+3行栅线输入扫描信号。
S302、数据线(D1、D2、D3…Dj…Dm)向位于第3i+1行的亚像素10输入数据信号Vdata。
S303、第一附加线L1向位于第3i+2行的亚像素10输入第一附加数据信号Add_Vdata1。
S304、第二附加线L2向位于第3i+3行的亚像素10输入第二附加数据信号Add_Vdata2。
其中，步骤S302、S303和S304可以同时进行。
由于上述三行栅线(第3i+1行、第3i+2行以及第3i+3行栅线)同时被扫描，因此第3i+3行栅线G3i+3上的亚像素10、第3i+2行栅线G3i+2上的亚像素10，以及第3i+1行栅线G3i+1上的亚像素10可以同时接收源极驱动器13输出的用于显示图像的信号。从而避免了现有技术中，逐行对栅线G3i+1和栅线G3i+2进行扫描时，由于栅线G3i+2打开时间晚于栅线G3i+1，而导致的栅线G3i+2上所在的亚像素10接收源极驱动器13输出信号有所延迟。因此，减小了信号延时，提升了显示器件的响应速度。
实施例六相对于实施例五而言，由于实施例六打开的栅线的数量较多，因此源极驱动器13输出信号的传输速度越快，构成的显示器的响应速度也越快。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种阵列基板，包括多条栅线和数据线，以及由所述栅线和所述数据线交叉界定的多个亚像素，其中，
    相邻两列所述亚像素之间设置有至少一条用于提供附加数据信号的附加线，同一列的所述亚像素对应至少一条附加线；
    同一列的所述亚像素中至少一个亚像素由该亚像素对应的所述附加线驱动。
  2. 根据权利要求1所述的阵列基板，其中，相邻两列所述亚像素之间设置有一条所述附加线，同一列的所述亚像素对应一条数据线和一条附加线；
    第2i+1行所述亚像素的开关单元与该亚像素对应的所述数据线相连接；
    第2i+2行所述亚像素的开关单元与该亚像素对应的所述附加线相连接；
    其中，i≥0，且为整数。
  3. 根据权利要求1所述的阵列基板，其中，每相邻两列所述亚像素之间设置有两条所述附加线，同一列的所述亚像素对应一条数据线和两条附加线，所述两条附加线分别为第一附加线和第二附加线；
    第3i+1行所述亚像素的开关单元与该亚像素对应的所述数据线相连接；
    第3i+2行所述亚像素的开关单元与该亚像素对应的所述第一附加线相连接；
    第3i+3行所述亚像素的开关单元与该亚像素对应的所述第二附加线相连接；
    其中，i≥0，且为整数。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一附加线设置于所述亚像素与所述第二附加线之间；
    所述第3i+3行所述亚像素的开关单元的源极上设置有第一过孔；
    所述第二附加线上设置有第二过孔；
    所述第3i+3行所述亚像素的开关单元的源极，通过分别贯通所述第一过孔和所述第二过孔的第一搭接电极层，与所述第二附加线相连接。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第一附加线上与所述第一搭接电极层之间重叠部分的线宽，小于所述第一附加线的线宽；
    或，所述第一搭接电极层上与所述第一附加线之间重叠部分的线宽，小于所述第一搭接电极层的线宽。
  6. 根据权利要求4所述的阵列基板，其中，
    所述第二附加线上设置有所述第二过孔的部分的线宽，大于所述第二附加线的线宽；
    或，所述第一搭接电极层上与所述第二附加线之间重叠部分的线宽，大于所述第一搭接电极层的线宽。
  7. 根据权利要求3所述的阵列基板，其中，
    所述第一附加线设置于所述亚像素与所述第二附加线之间；
    所述第一附加线在所述第二附加线和所述开关单元的源极相连接处被分成上、下两部分，所述第一附加线的上、下两部分分别设置有一个第四过孔，第二搭接电极层通过两个所述第四过孔将所述第一附加线的上、下两部分电连接。
  8. 根据权利要求1所述的阵列基板，其中，
    所述附加线的方向与数据线的方向大致相同。
  9. 根据权利要求1所述的阵列基板，其中，
    所述附加线部分或全部与所述数据线同层同材料设置。
  10. 一种显示装置，包括如权利要求1-9任一项所述的阵列基板。
  11. 一种阵列基板的驱动方法，包括：
    同时对至少两行栅线输入扫描信号；
    数据线向其中一行所述栅线控制的亚像素输入数据信号；
    至少一条附加线向其余的所述栅线控制的亚像素输入附加数据信号。
  12. 根据权利要求11所述的一种阵列基板的驱动方法，其中，当第2i+1行所述亚像素的开关单元与该亚像素对应的所述数据线相连接；第2i+2行所述亚像素的开关单元与该亚像素对应的所述附加线相连接时，所述驱动方法包括：
    同时对第2i+1行和第2i+2行栅线输入扫描信号；
    所述数据线向位于第2i+1行的所述亚像素输入所述数据信号；
    所述附加线向位于第2i+2行的所述亚像素输入所述附加数据信号；
    其中，i≥0，且为整数。
  13. 根据权利要求11所述的一种阵列基板的驱动方法，其中，当每相邻两列所述亚像素之间设置有两条所述附加线，同一列的所述亚像素对应一条数据线和两条附加线，所述两条附加线分别为第一附加线和第二附加线，第3i+1行所述亚像素的开关单元与该亚像素对应的所述数据线相连接；第3i+2行所述亚像素的开关单元与该亚像素对应的所述第一附加线相连接；第3i+3行所述亚像素的开关单元与该亚像素对应的所述第二附加线相连接时，所述驱动方法包括：
    同时对第3i+1行、第3i+2行以及第3i+3行栅线输入扫描信号；
    所述数据线向位于第3i+1行的所述亚像素输入所述数据信号；
    第一附加线向位于第3i+2行的所述亚像素输入第一附加数据信号；
    第二附加线向位于第3i+3行的所述亚像素输入第二附加数据信号，
    其中，i≥0，且为整数。
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CN104730791A (zh) 2015-06-24
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BR112016028110A2 (zh) 2017-08-22
RU2693559C2 (ru) 2019-07-03
BR112016028110B1 (pt) 2022-10-25
EP3282312A1 (en) 2018-02-14
US20170039972A1 (en) 2017-02-09
RU2016146517A3 (zh) 2019-05-08
EP3282312A4 (en) 2019-01-23
CN104730791B (zh) 2018-09-21
RU2016146517A (ru) 2019-05-08
US9858881B2 (en) 2018-01-02
MX2017000369A (es) 2017-04-27

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