WO2016161726A1 - 移位寄存器单元、栅极驱动装置以及显示装置 - Google Patents

移位寄存器单元、栅极驱动装置以及显示装置 Download PDF

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Publication number
WO2016161726A1
WO2016161726A1 PCT/CN2015/085993 CN2015085993W WO2016161726A1 WO 2016161726 A1 WO2016161726 A1 WO 2016161726A1 CN 2015085993 W CN2015085993 W CN 2015085993W WO 2016161726 A1 WO2016161726 A1 WO 2016161726A1
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Prior art keywords
pull
module
shift register
control node
signal
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PCT/CN2015/085993
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English (en)
French (fr)
Inventor
王峥
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/913,331 priority Critical patent/US9947281B2/en
Publication of WO2016161726A1 publication Critical patent/WO2016161726A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and more particularly to a shift register unit, and a gate driving device and a display device using the same.
  • the GOA circuit generally includes a plurality of cascaded shift register units, each shift register unit being respectively connected to a shift register unit of an adjacent row, each shift register unit corresponding to a row of gate lines, each shift register The unit supplies the output signal to the next shift register unit while outputting the gate drive signal to ensure that the next shift register unit realizes the output of the gate drive signal in the next clock cycle.
  • a small-sized LCD generally adopts a one-sided GOA structure.
  • the current shift register unit is reset only when there is a signal output at the signal output end of the next shift register unit, so that the signal output end of the current shift register unit is pulled down to a low level. .
  • this design makes it difficult to ensure the voltage at the far end of the driver circuit.
  • An object of the present disclosure is to provide a shift register unit, and a gate driving device and a display device using the same, to overcome the above disadvantages.
  • a shift register unit including a pull-up module, an input module, a pull-down control module, a pull-down module, a reset discharge module, a voltage dividing module, a holding module, and a remote pull-down module; Connecting a first clock signal port, a pull-up control node, and a signal output end, for pulling up a signal outputted by the signal output terminal to a high level according to a potential of the pull-up control node and a clock signal input by the first clock signal port,
  • the pull-up control node is a connection point between the pull-up module and the input module; the input module is connected to the signal input end, the second clock signal port, and the pull-up control node, and is configured to input the signal according to the signal input end and the second clock signal port.
  • the clock signal controls the potential of the pull-up control node;
  • the pull-down control module connects the second clock signal port, the pull-down control intermediate point and the lower
  • the pull control node is configured to control the potential of the pull-down control node according to the potential of the second clock signal and the pull-down control intermediate point, wherein the pull-down control intermediate point is a connection point of the pull-down control module and the voltage dividing module, and the pull-down control node is a pull-down control module and The connection point of the pull-down module; the pull-down module is connected to the pull-down control node, the pull-up control node, the low-level signal, and the signal output end, and is used to pull down the potential of the pull-up control node and the signal of the signal output terminal to be low according to the potential of the pull-down control node.
  • the reset discharge module is connected to the reset signal terminal, the pull-up control node, and the low-level signal for pulling down the potential of the pull-up control node to a low level according to the signal input from the reset signal terminal;
  • the voltage divider module is connected to the pull-down control intermediate a point, a pull-down control node, a pull-up control node, and a low-level signal for controlling the potential of the intermediate point and the potential of the pull-down control node according to the potential of the pull-up control node; maintaining the module connected to the second clock signal port, low power Flat signal and signal output for signal input according to the second clock signal port The output signal of the output terminal is kept low;
  • the remote pull-down module is connected to the far end of the signal output end, the first clock signal port and the second clock signal port, and is used for input according to the first clock signal port and the second clock signal port. A signal is used to maintain the potential of the far end of the signal output low.
  • the shift register unit adopts a split design to perform pull-down compensation of the output signal at the far end, which saves the low-voltage signal at the far end, thereby saving space and making the design more convenient.
  • the shift register unit may further include a state clearing module for clearing a state of the pull-down control module.
  • a gate driving apparatus including a plurality of the shift register units, wherein the plurality of shift register units are cascaded with each other except for a first shift register unit and Outside the last shift register unit, the signal output terminals of each of the other shift register units are connected to the input terminal of the next shift register unit adjacent thereto and the reset signal terminal of the previous shift register unit adjacent thereto.
  • the signal input end of the first shift register unit inputs a frame start signal
  • the signal output end is connected to a signal input end of the second shift register unit
  • the signal output end of the last shift register unit Connect the reset signal terminal of the previous shift register unit adjacent to it.
  • the clock signals input by the first clock signal port of the adjacent two-stage shift register unit are inverted with each other, and the clock signals input by the second clock signal port are inverted with each other.
  • a display device which includes the above The gate drive device described.
  • FIG. 1 illustrates a schematic diagram of a shift register unit in accordance with one embodiment of the present disclosure
  • FIG. 2 illustrates a schematic structural diagram of a shift register unit in accordance with one embodiment of the present disclosure
  • FIG. 3 illustrates a signal timing diagram of a shift register unit in accordance with one embodiment of the present disclosure
  • FIG. 4 illustrates a schematic structural diagram of a gate driving device according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics.
  • the source and drain of each transistor can be used interchangeably, so for convenience of description, one of them is referred to as a first pole and the other is referred to as a second pole.
  • FIG. 1 illustrates a schematic diagram of a shift register unit in accordance with one embodiment of the present disclosure.
  • the shift register unit 100 includes a pull-up module 101, an input module 102, a pull-down control module 103, a pull-down module 104, a reset discharge module 105, a voltage dividing module 106, a holding module 107, and a remote pull-down module. 108.
  • the pull-up module 101 is connected to the first clock signal port CLK1, the pull-up control node (PU), and the signal output terminal OUTPUT_N (take the Nth shift register unit in the cascade structure as an example) for the pull-up control.
  • the potential of the node and the clock signal input by the first clock signal port pull up a signal outputted by the signal output terminal, and the pull-up control node is a connection point between the pull-up module and the input module.
  • the input module 102 is connected to the signal input terminal INPUT_N (which is usually connected to the signal output port OUTPUT_N-1 of the previous shift register unit), the second clock signal port CLK2, and the pull-up control node (PU) for the signal input terminal.
  • the pull-down control module 103 is connected to the second clock signal port, the pull-down control intermediate point (PD_CN) and the pull-down control node (PD) for controlling the potential of the pull-down control node according to the potential of the second clock signal and the pull-down control intermediate point,
  • the pull-down control intermediate point is the connection point of the pull-down control module and the voltage dividing module 106
  • the pull-down control node is the connection point of the pull-down control module and the pull-down module 104.
  • the pull-down module 104 is connected to the pull-down control node, the pull-up control node, the low-level signal VSS, and the signal output terminal for pulling down the potential of the pull-up control node and the signal output terminal to a low level according to the potential of the pull-down control node.
  • the reset discharge module 105 is connected to the reset signal terminal RST_N (which is usually connected to the signal output port OUTPUT_N+1 of the next shift register unit), the pull-up control node, and the low-level signal for pulling up the signal according to the input signal of the reset signal terminal. The potential of the control node is pulled low.
  • the voltage dividing module 106 is connected to the pull-down control intermediate point, the pull-down control node, the pull-up control node, and the low level signal for controlling the potential of the intermediate point and the potential of the pull-down control node according to the potential of the pull-up control node.
  • the holding module 107 is connected to the second clock signal port, the low level signal and the signal output terminal for maintaining the signal outputted by the output terminal at a low level according to the signal input by the second clock signal port.
  • the remote pull-down module 108 is connected to the remote end OUTPUT_N' of the signal output end, the first clock signal port and the second clock signal port for connecting the far end of the signal output end according to the signal input by the first clock signal port and the second clock signal port Maintain low.
  • the shift register unit may further include a state clearing module 109 connected to the pull-down control intermediate point for clearing the state of the pull-down control module 103.
  • FIG. 2 illustrates a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • the pull-up module includes: a first transistor M1 having a gate connected to the pull-up control node PU, a first pole connected to the first clock signal port CLK1, and a second pole connected to the signal output terminal OUTPUT_N;
  • a capacitor C1 has one end connected to the pull-up control node and the other end connected to the signal output terminal.
  • the input module includes a second transistor M2 having a gate coupled to the signal input, a first pole coupled to the second clock signal port CLK2, and a second pole coupled to the pull up control node.
  • the second capacitor C2 may be further included, and one end of the second capacitor is connected to the pull-up control node, and the other end is connected to the second clock signal port for coupling the clock signal of the second clock signal port to the PU point and the first The coupling of the clock signal of the clock signal port to the PU point cancels out.
  • the pull-down control module includes: a third transistor M3 having a gate and a first pole connected to the second clock signal port, a second pole connected to the pull-down control intermediate point PD_CN, and a fourth transistor M4 whose gate is connected to the pull-down control intermediate point The first pole is connected to the second clock signal port, and the second pole is connected to the pull-down control node.
  • the pull-down module includes: a fifth transistor M5 whose gate is connected to the pull-down control node, the first stage is connected to the pull-up control node, the second pole is connected to the low-level signal, and the sixth transistor M6 is connected to the pull-down control Node, the first stage is connected to the signal output, and the second stage is connected to the low level signal.
  • the reset discharge module includes a seventh transistor M7 whose gate is connected to the reset signal terminal, the first pole is connected to the pull-up control node, and the second pole is connected to the low-level signal.
  • the voltage dividing module comprises: an eighth transistor M8 whose gate is connected to the pull-up control node, the first pole is connected to the low level signal, the second pole is connected to the pull-down control intermediate point; the ninth transistor M9 is connected to the gate Pull-up control node, the first pole is connected to the pull-down control node, and the second pole is connected to the low-level signal.
  • the holding module includes a tenth transistor M10 whose gate is connected to the second clock signal port, the first pole is connected to the signal output end, and the second pole is connected to the low level signal.
  • the remote pull-down module includes an eleventh transistor M11 whose gate is connected to the second clock signal port, the first pole is connected to the far end of the signal output end, and the second pole is connected to the first clock signal port.
  • the shift register unit may further include a state clearing module, and the state clearing module may include a twelfth transistor M12 whose gate is connected to the first clock signal port, and the first pole is connected to the pull-down control intermediate point, The two poles are connected to the second clock signal port.
  • FIG. 2 The circuit structure shown in FIG. 2 is described by taking a P-type transistor as an example. However, based on the description and teaching of the implementation of the P-type transistor herein, those skilled in the art can easily think of adopting N without requiring creative labor. The implementation of the transistor, all of which are covered by the scope of the present invention. Therefore, it should be noted that the structures of the various modules described above are merely exemplary and not limiting, and any structure that can implement the functions of the modules described above is contemplated.
  • FIG. 3 illustrates a signal timing of a shift register unit according to an embodiment of the present disclosure. Sequence diagram. In order to make the description of the present disclosure more thorough, the description will now be made in conjunction with the exemplary structural diagram of FIG.
  • the clock signals input from the first clock signal port CLK1 and the second clock signal port CLK2 are inverted from each other.
  • CLK1 is low
  • CLK2 is high
  • signal input INPUT_N has signal input (ie, port appears high)
  • reset signal RST_N has no signal input (port is low) .
  • the signal input INPUT_N is usually connected to the signal output (OUTPUT_N-1) of the previous shift register unit.
  • the second transistor M2 is turned on to charge the first capacitor C1, so that the potential of the PU point is controlled to a high level.
  • M8 and M9 in the voltage divider circuit causes M8 and M9 in the voltage divider circuit to be turned on, so that the potentials of the pull-down control intermediate point (PD_CN) and the pull-down control node (PD) are controlled to be low, thereby making the pull-down control module inoperative (M4 cut-off) and pull-down The module does not work (M5 and M6 are off).
  • M10 in the hold module is turned on due to a signal input at the CKL2 terminal, so that the signal output from the signal output terminal is kept at a low level.
  • M11 in the remote pull-down module is also turned on, so that the potential of the far end of the signal output is maintained at a low level.
  • the CLK1 terminal has a high level
  • the CLK2 terminal has a low level
  • the signal input terminal has no signal input
  • the reset signal terminal has no signal input.
  • the potential of the PU point is at a high level, causing the first transistor M1 of the pull-up module to be turned on, so that the signal output from the signal output terminal is pulled up to a high level.
  • the signal output can be connected to the gate of the pixel region to provide a gate drive signal thereto.
  • the CLK1 terminal is low level
  • the CLK2 terminal is high level
  • the reset signal terminal has a signal input. This is because the signal output terminal of the adjacent next shift register unit (OUTPUT_N+1) has a signal output.
  • M7 in the reset discharge module is turned on, which causes the left end of C1 to be discharged, and the potential of the PU point becomes a low level, so that the voltage dividing module does not function (M8 and M9 are turned off).
  • the M3 of the pull-down control module is turned on, so that the pull-down control intermediate point (PD_CN) becomes a high level, so that M4 is also turned on, thereby causing the potential of the pull-down control node (PD) to become a high level.
  • the pull-down module operates (M5 and M6 are turned on), discharging both ends of C1, so that the potential of the pull-up control node and the signal at the signal output become low.
  • far The terminal pull-down module maintains the potential of the far end of the signal output terminal at a low level to keep the circuit stable.
  • the CLK1 terminal and the CLK2 terminal alternately appear high level, the signal input terminal and the reset signal terminal of the shifter register unit have no signal input, and the signal output terminal has no signal output until there is a new signal input terminal.
  • the above ac phase is repeated.
  • the input module may further include a second capacitor C2, one end of which is connected to the pull-up control node PU, and the other end of which is connected to the second clock signal port CLK2, which can make the clock signal of the CLK1 terminal to the PU.
  • the coupling of the points cancels the coupling of the clock signal at the CLK2 terminal to the PU point. In this way, the stability of the shift register unit circuit is greatly enhanced.
  • the remote pull-down module pulls the remote potential of the signal output terminal to a low level, thereby maintaining the remote potential low. level. This allows the low level at the far end of the driver circuit to be guaranteed, and does not require additional Vss signals at the far end, making the circuit design simpler and more efficient.
  • the potential of the PD point and the PD_CN point is also high, and the pull-down module acts to pull the signal output low to keep the circuit stable.
  • the state clearing module can set the high level of the PD_CN point to a low level when the high level of the CLK1 terminal (at this time, M12 is turned on).
  • M4 is turned off, extending its life without affecting the realization of the function of the circuit.
  • FIG. 4 illustrates a schematic structural diagram of a gate driving device according to an embodiment of the present disclosure.
  • the gate driving device 400 includes a plurality of shift register units 100_1, ..., 100_N, each of which may have the same structure as the shift register unit of FIG.
  • the plurality of shift register units are cascaded with each other, except for the first shift register unit 100_1 and the last shift register unit 100_N, the signal output ends of each of the shift register units are connected to the next adjacent one An input terminal of the shift register unit and a reset signal terminal connected to a previous shift register unit adjacent thereto.
  • the signal input end of the first shift register unit inputs a frame start signal STV, and the signal output end is connected to a signal input end of the second shift register unit.
  • the last shift The signal output terminal of the bit register unit is connected to the reset signal terminal of the previous shift register unit adjacent thereto.
  • the first voltage source CLK and the second voltage source CLKB shown in FIG. 4 are mutually inverted, so that the clock signals input to the first clock signal port of the adjacent two-stage shift register unit are inverted with each other, and the second clock The clock signals input to the signal port are inverted from each other.
  • a display device that includes a gate driving device as described above.

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Abstract

一种移位寄存器单元包括上拉模块（101）、输入模块（102）、下拉控制模块（103）、下拉模块（104）、复位放电模块（105）、分压模块（106）、保持模块（107）以及远端下拉模块（108）。该移位寄存器单元采用分体式设计以便在远端对输出信号进行下拉补偿，节省了远端的低电压信号，从而节省了空间并使得设计更加方便。还提供了使用该移位寄存器单元的栅极驱动装置以及显示装置。

Description

移位寄存器单元、栅极驱动装置以及显示装置 技术领域
本公开涉及显示技术的领域，更具体地涉及一种移位寄存器单元、以及使用该移位寄存器单元的栅极驱动装置以及显示装置。
背景技术
作为与现有的液晶显示装置的驱动电路相关的技术，本领域已经开发出GOA(Gate-driver on Array)技术。GOA电路通常包括多个级联的移位寄存器单元，每一个移位寄存器单元分别与相邻行的移位寄存器单元相连接，每一个移位寄存器单元均对应一行栅线，每一个移位寄存器单元在输出栅极驱动信号的同时会将输出信号提供给下一个移位寄存器单元，以保证下一个移位寄存器单元在下一个时钟周期内实现栅极驱动信号的输出。
但在目前的GOA技术中，小尺寸LCD一般采用单边GOA结构。而在单边GOA结构中，仅在下一个移位寄存器单元的信号输出端有信号输出时，对当前移位寄存器单元的进行复位，进而使当前移位寄存器单元的信号输出端下拉为低电平。然而，这种设计导致驱动器电路远端的电压很难得到保证。
发明内容
本公开的目标是提供一种移位寄存器单元、以及使用该移位寄存器单元的栅极驱动装置以及显示装置来克服上述缺点。
根据本发明的一个方面，提供了一种移位寄存器单元，包括上拉模块、输入模块、下拉控制模块、下拉模块、复位放电模块、分压模块、保持模块以及远端下拉模块；上拉模块连接第一时钟信号端口、上拉控制节点以及信号输出端，用于根据上拉控制节点的电位和第一时钟信号端口输入的时钟信号将信号输出端输出的信号上拉为高电平，所述上拉控制节点为上拉模块与输入模块的连接点；输入模块连接信号输入端、第二时钟信号端口以及上拉控制节点，用于根据信号输入端输入的信号和第二时钟信号端口的时钟信号控制上拉控制节点的电位；下拉控制模块连接第二时钟信号端口、下拉控制中间点和下 拉控制节点，用于根据第二时钟信号和下拉控制中间点的电位来控制下拉控制节点的电位，下拉控制中间点为下拉控制模块与分压模块的连接点，下拉控制节点为下拉控制模块与下拉模块的连接点；下拉模块连接下拉控制节点、上拉控制节点、低电平信号以及信号输出端，用于根据下拉控制节点的电位将上拉控制节点的电位和信号输出端的信号下拉为低电平；复位放电模块连接复位信号端、上拉控制节点以及低电平信号，用于根据复位信号端输入的信号将上拉控制节点的电位下拉为低电平；分压模块连接下拉控制中间点、下拉控制节点、上拉控制节点以及低电平信号，用于根据上拉控制节点的电位控制下拉控制中间点的电位和下拉控制节点的电位；保持模块连接第二时钟信号端口、低电平信号和信号输出端，用于根据第二时钟信号端口输入的信号将输出端输出的信号保持为低电平；远端下拉模块连接信号输出端的远端、第一时钟信号端口和第二时钟信号端口，用于根据第一时钟信号端口和第二时钟信号端口输入的信号来将信号输出端的远端的电位维持为低电平。
所述移位寄存器单元采用分体式设计以便在远端对输出信号进行下拉补偿，节省了远端的低电压信号，从而节省了空间并使得设计更加方便。
在实施例中，所述移位寄存器单元还可以包括状态清除模块，用于清除下拉控制模块的状态。
根据本公开的另一个方面，提供了一种栅极驱动装置，包括多个所述的移位寄存器单元，其中所述多个移位寄存器单元相互级联，除第一个移位寄存器单元和最后一个移位寄存器单元外，其余每个移位寄存器单元的信号输出端都连接与其相邻的下一个移位寄存器单元的输入端以及连接与其相邻的上一个移位寄存器单元的复位信号端；其中所述第一个移位寄存器单元的信号输入端输入帧起始信号，信号输出端与第二个移位寄存器单元的信号输入端连接，所述最后一个移位寄存器单元的信号输出端连接与其相邻的上一个移位寄存器单元的复位信号端。
在实施例中，相邻两级移位寄存器单元的第一时钟信号端口输入的时钟信号互为反相，第二时钟信号端口输入的时钟信号互为反相。
根据本发明的又一个方面，提供了一种显示装置，其包括如上所 述的栅极驱动装置。
本发明内容被提供来以简化形式引入在下面在具体实施方式中被进一步描述的构思的选择。本发明内容不旨在识别所要求保护的主题的关键特征或必要特征，它也不旨在用来帮助确定所要求保护的主题的范围。
附图说明
现将参考示出本发明的实施例的附图更详细地描述本发明的上述和其它方面。
图1图示了根据本公开的一个实施例的移位寄存器单元的示意图；
图2图示了根据本公开的一个实施例的移位寄存器单元的一个示意性结构图；
图3图示了根据本公开的一个实施例的移位寄存器单元的信号时序图；以及
图4图示了根据本公开的一个实施例的栅极驱动装置的示意性结构图。
具体实施方式
下面的实施例作为例子被提供使得本公开内容将是彻底的且完整的，并且将完全地将本发明的范围传达给本领域的技术人员。本公开内容在代表性实施例的上下文中被阐述，代表性实施例在任何方面不旨在为限制性的。
本发明的所有实施例中采用的晶体管可以是薄膜晶体管或场效应管或者其它具有相同特性的器件。在本发明的实施中，每个晶体管的源极和漏极可以互换地使用，因此为了描述方便，将其中的一个称为第一极，另一个称为第二极。
图1图示了根据本公开的一个实施例的移位寄存器单元的示意图。如图1所示，所述移位寄存器单元100包括上拉模块101、输入模块102、下拉控制模块103、下拉模块104、复位放电模块105、分压模块106、保持模块107以及远端下拉模块108。所述上拉模块101连接第一时钟信号端口CLK1、上拉控制节点(PU)以及信号输出端OUTPUT_N(以级联结构中的第N个移位寄存器单元为例)，用于根据上拉控制 节点的电位和所述第一时钟信号端口输入的时钟信号将信号输出端输出的信号上拉为高电平，所述上拉控制节点为上拉模块与输入模块的连接点。所述输入模块102连接信号输入端INPUT_N(其通常连接上一个移位寄存器单元的信号输出端口OUTPUT_N-1)、第二时钟信号端口CLK2以及上拉控制节点(PU)，用于根据信号输入端输入的信号和第二时钟信号端口的时钟信号控制上拉控制节点的电位。所述下拉控制模块103连接第二时钟信号端口、下拉控制中间点(PD_CN)和下拉控制节点(PD)，用于根据第二时钟信号和下拉控制中间点的电位来控制下拉控制节点的电位，下拉控制中间点为下拉控制模块与分压模块106的连接点，下拉控制节点为下拉控制模块与下拉模块104的连接点。下拉模块104连接下拉控制节点、上拉控制节点、低电平信号VSS以及信号输出端，用于根据下拉控制节点的电位将上拉控制节点的电位和信号输出端的信号下拉为低电平。复位放电模块105连接复位信号端RST_N(其通常连接下一个移位寄存器单元的信号输出端口OUTPUT_N+1)、上拉控制节点以及低电平信号，用于根据复位信号端输入的信号将上拉控制节点的电位下拉为低电平。分压模块106连接下拉控制中间点、下拉控制节点、上拉控制节点以及低电平信号，用于根据上拉控制节点的电位控制下拉控制中间点的电位和下拉控制节点的电位。保持模块107连接第二时钟信号端口、低电平信号和信号输出端，用于根据第二时钟信号端口输入的信号将输出端输出的信号保持为低电平。远端下拉模块108连接信号输出端的远端OUTPUT_N’、第一时钟信号端口和第二时钟信号端口，用于根据第一时钟信号端口和第二时钟信号端口输入的信号来将信号输出端的远端维持为低电平。此外，所述移位寄存器单元还可以包括状态清除模块109，其连接到下拉控制中间点，用于清除下拉控制模块103的状态。
图2图示了根据本公开的一个实施例的移位寄存器单元的一个示意性结构图。如图2所示，上拉模块包括：第一晶体管M1，其栅极连接到上拉控制节点PU，第一极连接到第一时钟信号端口CLK1，第二极连接到信号输出端OUTPUT_N；第一电容C1，其一端连接到上拉控制节点，另一端连接到信号输出端。
输入模块包括第二晶体管M2，其栅极连接信号输入端，第一极连接到第二时钟信号端口CLK2，第二极连接到上拉控制节点。输入模块 还可以包括第二电容C2，第二电容的一端连接到上拉控制节点，另一端连接到第二时钟信号端口，用于将第二时钟信号端口的时钟信号对PU点的耦合作用与第一时钟信号端口的时钟信号对PU点的耦合作用相抵消。
下拉控制模块包括：第三晶体管M3，其栅极和第一极连接到第二时钟信号端口，第二极连接到下拉控制中间点PD_CN；第四晶体管M4，其栅极连接到下拉控制中间点，第一极连接到第二时钟信号端口，第二极连接到下拉控制节点。
下拉模块包括：第五晶体管M5，其栅极连接到下拉控制节点，第一级连接到上拉控制节点，第二极连接到低电平信号；第六晶体管M6，其栅极连接到下拉控制节点，第一级连接到信号输出端，第二极连接到低电平信号。
复位放电模块包括第七晶体管M7，其栅极连接到复位信号端，第一极连接到上拉控制节点，第二极连接到低电平信号。
分压模块包括：第八晶体管M8，其栅极连接到上拉控制节点，第一极连接到低电平信号，第二极连接到下拉控制中间点；第九晶体管M9，其栅极连接到上拉控制节点，第一极连接到下拉控制节点，第二极连接到低电平信号。
保持模块包括第十晶体管M10，其栅极连接第二时钟信号端口，第一极连接信号输出端，第二极连接低电平信号。
远端下拉模块包括第十一晶体管M11，其栅极连接第二时钟信号端口，第一极连接信号输出端的远端，第二极连接第一时钟信号端口。
此外，所述移位寄存器单元还可以包括状态清除模块，所述状态清除模块可以包括第十二晶体管M12，其栅极连接到第一时钟信号端口，第一极连接到下拉控制中间点，第二极连接到第二时钟信号端口。
图2所示电路结构均以P型晶体管为例进行说明，但是本领域普通技术人员基于本文对P型晶体管实现方式的描述和教导，在不需要付出创造性劳动的前提下也能够容易想到采用N型晶体管的实现方式，所有这些实现方式都涵盖在本发明的保护范围内。因此，应当指出，上面所描述的各模块的结构仅仅是示例性的而不是限制性的，任何可以实施上面所述描述的模块的功能的结构都被设想。
图3图示了根据本公开的一个实施例的移位寄存器单元的信号时 序图。为了使对本公开内容的描述更加透彻，现结合图2的示例性结构图进行描述。
如图3所示，第一时钟信号端口CLK1和第二时钟信号端口CLK2输入的时钟信号互为反相。在a阶段，CLK1端为低电平，CLK2端出现高电平，并且信号输入端INPUT_N有信号输入(即，端口出现高电平)，复位信号端RST_N无信号输入(端口为低电平)。应当指出，信号输入端INPUT_N通常与上一个移位寄存器单元的信号输出端(OUTPUT_N-1)连接。此时，第二晶体管M2导通，对第一电容C1进行充电，因此PU点的电位被控制成为高电平。这导致分压电路中M8和M9导通，使得下拉控制中间点(PD_CN)和下拉控制节点(PD)的电位被控制成为低电平，进而使得下拉控制模块不起作用(M4截止)并且下拉模块不起作用(M5和M6截止)。此时，保持模块中的M10由于CKL2端有信号输入而导通，使得信号输出端输出的信号保持为低电平。远端下拉模块中的M11也导通，使信号输出端的远端的电位维持为低电平。
在b阶段，CLK1端出现高电平，CLK2端为低电平，信号输入端无信号输入，复位信号端也无信号输入。此时，由于a阶段第一电容C1已充电，PU点的电位为高电平，导致上拉模块的第一晶体管M1导通，从而使得信号输出端输出的信号被上拉为高电平。信号输出端可以连接像素区的栅极，以便为其提供栅极驱动信号。需要指出，由于电容的耦合作用，PU点的电位将继续升高，由此可以使得下拉控制中间点(PD_CN)和下拉控制节点(PD)的电位仍然为低电平，下拉控制模块和下拉模块继续不起作用。
在c阶段，CLK1端为低电平，CLK2端出现高电平，并且信号输入端无信号输入，而复位信号端有信号输入，这是因为相邻的下一个移位寄存器单元的信号输出端(OUTPUT_N+1)有信号输出。此时，复位放电模块中的M7导通，进而导致C1的左端被放电，PU点的电位变为低电平，从而使得分压模块不起作用(M8和M9截止)。同时，下拉控制模块的M3导通，使得下拉控制中间点(PD_CN)变为高电平，进而使得M4也导通，从而导致下拉控制节点(PD)的电位变为高电平。这样，下拉模块工作(M5和M6导通)，将C1的两端放电，使得上拉控制节点的电位和信号输出端的信号成为低电平。此时，远 端下拉模块使信号输出端的远端的电位维持为低电平，保持电路的稳定。
在之后的各个阶段中，CLK1端和CLK2端交替出现高电平，该移位器寄存器单元的信号输入端和复位信号端无信号输入，信号输出端无信号输出，直到在信号输入端有新的信号到来，则重复上述a-c阶段。
此外，考虑到电容C1的存在，输入模块还可以包括有第二电容C2，其一端连接到上拉控制节点PU，另一端连接到第二时钟信号端口CLK2，这可以使得CLK1端的时钟信号对PU点的耦合作用抵消CLK2端的时钟信号对PU点的耦合作用。通过这种方式，该移位寄存器单元电路的稳定性被极大地增强。
在信号输入端无新的信号到来的情况下，每当CLK2端出现高电平时，远端下拉模块就将信号输出端的远端电位下拉为低电平，从而将远端的电位维持为低电平。这使得驱动器电路远端的低电平能够得到保证，并且在远端不需要额外增加Vss信号，使得电路设计更为简单有效。与此同时，PD点和PD_CN点的电位也是高电平，下拉模块起作用来将信号输出端下拉为低电平，保持电路稳定。事实上，在此后阶段中，因为PD点和PD_CN点的电位并未被置为低电平，其将一直保持为高电平，因此下拉控制模块中的M4将一直处于导通的状态并且下拉模块一直保持起作用的状态，直到在信号输入端有新的信号到来为止。为了降低此时M4的高功耗所带来的寿命缩短的问题，状态清除模块可以在CLK1端出现高电平的时候(此时，M12导通)将PD_CN点的电位置为低电平，从而使M4截止，延长其寿命，而不会影响电路的功能的实现。
图4图示了根据本公开的一个实施例的栅极驱动装置的示意性结构图。如图4所示，栅极驱动装置400包括多个移位寄存器单元100_1，...，100_N，它们中的每一个都可以与图1中的移位寄存单元具有相同的结构。所述多个移位寄存器单元相互级联，除第一个移位寄存器单元100_1和最后一个移位寄存器单元100_N外，其余每个移位寄存器单元的信号输出端都连接与其相邻的下一个移位寄存器单元的输入端以及连接与其相邻的上一个移位寄存器单元的复位信号端。所述第一个移位寄存器单元的信号输入端输入帧起始信号STV，信号输出端与第二个移位寄存器单元的信号输入端连接。所述最后一个移 位寄存器单元的信号输出端连接与其相邻的上一个移位寄存器单元的复位信号端。在图4中所示的第一电压源CLK和第二电压源CLKB互为反相，因此相邻两级移位寄存器单元的第一时钟信号端口输入的时钟信号互为反相，第二时钟信号端口输入的时钟信号互为反相。
同样，一种显示装置被公开，其包括如上面所述的栅极驱动装置。
鉴于所公开的发明的原理可以被应用于的许多可能的实施例，应认识到，所图示的实施例仅是本发明的优选例子，并且不应该被视为限制本发明的范围。相反地，本发明的范围由以下权利要求来定义。我们因此要求落入这些权利要求和它们的等同物的范围内的全部作为我们的发明。

Claims (15)

  1. 一种移位寄存器单元，包括上拉模块、输入模块、下拉控制模块、下拉模块、复位放电模块、分压模块、保持模块以及远端下拉模块；
    上拉模块连接第一时钟信号端口、上拉控制节点以及信号输出端，用于根据上拉控制节点的电位和第一时钟信号端口输入的时钟信号将信号输出端输出的信号上拉为高电平，所述上拉控制节点为上拉模块与输入模块的连接点；
    输入模块连接信号输入端、第二时钟信号端口以及上拉控制节点，用于根据信号输入端输入的信号和第二时钟信号端口的时钟信号控制上拉控制节点的电位；
    下拉控制模块连接第二时钟信号端口、下拉控制中间点和下拉控制节点，用于根据第二时钟信号和下拉控制中间点的电位来控制下拉控制节点的电位，下拉控制中间点为下拉控制模块与分压模块的连接点，下拉控制节点为下拉控制模块与下拉模块的连接点；
    下拉模块连接下拉控制节点、上拉控制节点、低电平信号以及信号输出端，用于根据下拉控制节点的电位将上拉控制节点的电位和信号输出端的信号下拉为低电平；
    复位放电模块连接复位信号端、上拉控制节点以及低电平信号，用于根据复位信号端输入的信号将上拉控制节点的电位下拉为低电平；
    分压模块连接下拉控制中间点、下拉控制节点、上拉控制节点以及低电平信号，用于根据上拉控制节点的电位控制下拉控制中间点的电位和下拉控制节点的电位；
    保持模块连接第二时钟信号端口、低电平信号和信号输出端，用于根据第二时钟信号端口输入的信号将输出端输出的信号保持为低电平；
    远端下拉模块连接信号输出端的远端、第一时钟信号端口和第二时钟信号端口，用于根据第一时钟信号端口和第二时钟信号端口输入的信号来将信号输出端的远端的电位维持为低电平。
  2. 根据权利要求1的移位寄存器单元，所述上拉模块包括：
    第一晶体管，其栅极连接到上拉控制节点，第一极连接到第一时钟信号端口，第二极连接到信号输出端；
    第一电容，其一端连接到上拉控制节点，另一端连接到信号输出端。
  3. 根据权利要求1的移位寄存器单元，所述输入模块包括第二晶体管，其栅极连接信号输入端，第一极连接到第二时钟信号端口，第二极连接到上拉控制节点。
  4. 根据权利要求1的移位寄存器单元，所述下拉控制模块包括：
    第三晶体管，其栅极和第一极连接到第二时钟信号端口，第二极连接到下拉控制中间点；
    第四晶体管，其栅极连接到下拉控制中间点，第一极连接到第二时钟信号端口，第二极连接到下拉控制节点。
  5. 根据权利要求1的移位寄存器单元，所述下拉模块包括：
    第五晶体管，其栅极连接到下拉控制节点，第一级连接到上拉控制节点，第二极连接到低电平信号；
    第六晶体管，其栅极连接到下拉控制节点，第一级连接到信号输出端，第二极连接到低电平信号。
  6. 根据权利要求1的移位寄存器单元，所述复位放电模块包括第七晶体管，其栅极连接到复位信号端，第一极连接到上拉控制节点，第二极连接到低电平信号。
  7. 根据权利要求1的移位寄存器单元，所述分压模块包括：
    第八晶体管，其栅极连接到上拉控制节点，第一极连接到低电平信号，第二极连接到下拉控制中间点；
    第九晶体管，其栅极连接到上拉控制节点，第一极连接到下拉控制节点，第二极连接到低电平信号。
  8. 根据权利要求1的移位寄存器单元，所述保持模块包括第十晶体管，其栅极连接第二时钟信号端口，第一极连接信号输出端，第二极连接低电平信号。
  9. 根据权利要求1的移位寄存器单元，所述远端下拉模块包括第十一晶体管，其栅极连接第二时钟信号端口，第一极连接信号输出端的远端，第二极连接第一时钟信号端口。
  10. 根据权利要求1或3的移位寄存器单元，所述输入模块包括第 二电容，第二电容的一端连接到上拉控制节点，另一端连接到第二时钟信号端口。
  11. 根据权利要求1的移位寄存器单元，还包括状态清除模块，其连接到下拉控制中间点，用于清除下拉控制模块的状态。
  12. 根据权利要求10的移位寄存器单元，所述状态清除模块包括第十二晶体管，其栅极连接到第一时钟信号端口，第一极连接到下拉控制中间点，第二极连接到第二时钟信号端口。
  13. 一种栅极驱动装置，包括多个根据权利要求1-12中任意一项所述的移位寄存器单元，
    其中所述多个移位寄存器单元相互级联，除第一个移位寄存器单元和最后一个移位寄存器单元外，其余每个移位寄存器单元的信号输出端都连接与其相邻的下一个移位寄存器单元的输入端以及连接与其相邻的上一个移位寄存器单元的复位信号端；
    其中所述第一个移位寄存器单元的信号输入端输入帧起始信号，信号输出端与第二个移位寄存器单元的信号输入端连接，所述最后一个移位寄存器单元的信号输出端连接与其相邻的上一个移位寄存器单元的复位信号端。
  14. 根据权利要求13所述的栅极驱动装置，其中相邻两级移位寄存器单元的第一时钟信号端口输入的时钟信号互为反相，第二时钟信号端口输入的时钟信号互为反相。
  15. 一种显示装置，其包括如权利要求13-14中任意一项所述的栅极驱动装置。
PCT/CN2015/085993 2015-04-09 2015-08-04 移位寄存器单元、栅极驱动装置以及显示装置 Ceased WO2016161726A1 (zh)

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