WO2016157935A1 - Procédé de fabrication d'un dispositif à semi-conducteurs de puissance - Google Patents

Procédé de fabrication d'un dispositif à semi-conducteurs de puissance Download PDF

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WO2016157935A1
WO2016157935A1 PCT/JP2016/051013 JP2016051013W WO2016157935A1 WO 2016157935 A1 WO2016157935 A1 WO 2016157935A1 JP 2016051013 W JP2016051013 W JP 2016051013W WO 2016157935 A1 WO2016157935 A1 WO 2016157935A1
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semiconductor substrate
semiconductor device
power semiconductor
concentration
center
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PCT/JP2016/051013
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English (en)
Japanese (ja)
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明 清井
政幸 田中
忠玄 湊
政良 多留谷
和豊 高野
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三菱電機株式会社
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Priority to JP2016546111A priority Critical patent/JP6109432B2/ja
Publication of WO2016157935A1 publication Critical patent/WO2016157935A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for manufacturing a power semiconductor device that performs power control and the like.
  • Bipolar power semiconductor devices include IGBTs (Insulated gate Bipolar Transistors), diodes, thyristors, GTOs (Gate Turn-Off Thyristors), and the like.
  • IGBTs Insulated gate Bipolar Transistors
  • diodes diodes
  • thyristors thyristors
  • GTOs Gate Turn-Off Thyristors
  • the carrier recombination lifetime in the drift layer may be shortened. This is because the carriers accumulated in the drift layer at the time of switching can be quickly eliminated by shortening the recombination lifetime.
  • recombination levels such as crystal defects are formed in the drift layer. Conventionally, there are the following two methods for forming a recombination level.
  • Patent Document 1 a metal film such as platinum (Pt) having a relatively large diffusion coefficient is generally formed on a semiconductor substrate, and then the metal such as platinum is diffused into the semiconductor substrate by heating the semiconductor substrate.
  • the metal diffused throughout the semiconductor substrate is replaced with silicon (Si) atoms, whereby recombination levels are formed in the silicon band gap. This recombination level shortens the carrier recombination lifetime.
  • the charged particle beam in this method is an electron beam, a high energy hydrogen ion (proton), or a high energy helium nucleus.
  • This method of irradiating a charged particle beam is disclosed in, for example, Non-Patent Document 1, and lattice defects, composite defects, and impurity defects are formed in the semiconductor substrate by the interaction between the semiconductor substrate and the charged particles.
  • the lattice defect means interstitial silicon, vacancies, and interstitial silicon or vacancies bonded together.
  • a composite defect refers to a combination of impurity atoms present in a semiconductor substrate and lattice defects.
  • an impurity defect means that an electrically neutral impurity present in a semiconductor substrate is electrically activated by irradiation with a charged particle beam.
  • the recombination lifetime of the carriers is shortened by the recombination level due to these defects. This method is disclosed in, for example, Patent Document 3 and Patent Document 4.
  • the power semiconductor is used by using any one of the first method and the second method described above, or by using the first method and the second method in combination.
  • the switching speed of the device is improved.
  • the conventional method for manufacturing a power semiconductor device has a problem that the switching characteristics are not sufficiently stable.
  • that the switching characteristics are stable means that the switching characteristics do not change when the power semiconductor device is energized for a long time.
  • the present invention has been made as part of its development, and an object of the present invention is to provide a method of manufacturing a power semiconductor device capable of obtaining stable switching characteristics.
  • the method for manufacturing a power semiconductor device includes the following steps.
  • the silicon having a region having a carbon concentration of 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less and an oxygen concentration of 1 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less.
  • a power semiconductor device is formed on a semiconductor substrate.
  • the semiconductor substrate is irradiated with an electron beam.
  • the semiconductor substrate is heat-treated under a temperature condition of 250 ° C. or higher and 400 ° C. or lower.
  • the semiconductor substrate has the prescribed carbon concentration and oxygen concentration, respectively, thereby eliminating defects with low heat resistance and high heat resistance.
  • the C center can be efficiently left. As a result, the switching speed can be improved and the switching characteristics can be stabilized.
  • FIG. 10 is a cross-sectional view showing a step of a method for manufacturing the power semiconductor device in the embodiment.
  • FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment.
  • FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment.
  • FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment.
  • FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment.
  • it is a graph which shows the evaluation result of the relation between the oxygen concentration in a semiconductor substrate, and the concentration of C center. In the same embodiment, it is a graph which shows the evaluation result of the relationship between the oxygen concentration in a semiconductor substrate, and the density
  • FIG. 4 is a graph showing a relationship between a thickness direction of a semiconductor substrate and an oxygen concentration and a relationship between a thickness direction of the semiconductor substrate and a C center concentration in the same embodiment.
  • FIG. 4 is a cross-sectional view of a power semiconductor device in which a diode is formed as the power semiconductor device in the embodiment.
  • a power semiconductor device in this specification is a semiconductor device (power semiconductor device) that controls or supplies power. For example, convert AC to DC, reduce voltage to 5V or 3V, drive motor, charge battery, operate microcomputer (Central processing Unit) or LSI (Large Scale Integrated circuit), etc.
  • the semiconductor device used for this purpose is not a microcomputer or an LSI used for a memory or the like.
  • a semiconductor substrate used for a power semiconductor device contains carbon and oxygen as impurities, and it is necessary to set the carbon concentration and the oxygen concentration to specified values, respectively.
  • carbon does not have an appropriate diffusion source in the treatment after crystal growth of the semiconductor substrate. Therefore, here, when the semiconductor substrate is crystal-grown, a semiconductor substrate containing a prescribed concentration of carbon is used by controlling the growth atmosphere.
  • a silicon semiconductor substrate (silicon wafer) grown by an FZ (Floating-Zone) method is used as the crystal growth method.
  • a silicon semiconductor substrate is a semiconductor substrate containing silicon as a main component, and this semiconductor substrate contains a predetermined impurity or the like that defines a conductivity type.
  • oxygen is added to a semiconductor substrate that has been previously containing carbon.
  • oxygen is diffused into the semiconductor substrate.
  • a power semiconductor device such as an IGBT is formed on the semiconductor substrate.
  • defects are formed in the semiconductor substrate by irradiating the semiconductor substrate with an electron beam.
  • the semiconductor substrate is subjected to a heat treatment to eliminate a part of the defects or to inactivate the defects.
  • FIG. 2 corresponds to the first step S1.
  • a silicon oxide film 2 is formed on the surface of the semiconductor substrate 1 by subjecting the semiconductor substrate 1 to heat treatment (about 1100 ° C.) in an air atmosphere.
  • heat treatment (about 1100 ° C.) is performed on the semiconductor substrate 1 on which the silicon oxide film 2 is formed in a nitrogen atmosphere, thereby diffusing oxygen 3 in the silicon oxide film 2 into the semiconductor substrate 1.
  • the heat treatment is controlled so that the concentration of oxygen in the semiconductor substrate 1 is 1 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less.
  • FIGS. 3, 4 and 5 correspond to the second step S2.
  • an IGBT is taken as an example of a power semiconductor device and its manufacturing process will be described.
  • p + body regions 5 are formed on one surface side by diffusing p-type impurities such as boron from one surface and the other surface of the semiconductor substrate 1, respectively.
  • a p + collector region 4 is formed on the surface side of the substrate. At this time, the region of the semiconductor substrate 1 sandwiched between the p + collector region 4 and the p + body region 5 becomes the n ⁇ drift layer 6.
  • a resist mask (not shown) is formed on one surface side of the semiconductor substrate 1, and the semiconductor substrate 1 is dry-etched using the resist mask as an etching mask, as shown in FIG. Then, the trench groove 7 is formed. Thereafter, the resist mask is removed.
  • another resist mask (not shown) is formed on one surface side of the semiconductor substrate 1, and the resist mask is used as an etching mask, for example, n-type impurities such as phosphorus are formed on the side of the trench groove 7.
  • the n + emitter region 10 is formed by selective diffusion and heat treatment. Thereafter, the other resist mask is removed.
  • the gate oxide film 8 is formed by selectively oxidizing the bottom and side walls of the trench groove 7.
  • a gate electrode 9 is formed on the gate oxide film 8 by a physical film formation method such as sputtering.
  • an emitter electrode 11 is formed so as to be in contact with the n + emitter region 10 by a physical film formation method such as sputtering.
  • a field insulating film 12 is formed on the entire surface of one surface of the semiconductor substrate 1 so as to cover the emitter electrode 11.
  • the collector electrode 13 is formed so as to be in contact with the p + collector region 4 by using a physical film formation method such as sputtering.
  • an IGBT 21 is formed on the semiconductor substrate 1 as an example of the power semiconductor device 20.
  • a general IGBT manufacturing process has been described as an example.
  • a manufacturing method for example, an ion implantation method may be used instead of the diffusion method.
  • a vapor deposition method may be used instead of the sputtering method, and the method for manufacturing the IGBT is not limited to the method described above.
  • FIG. 6 corresponds to the third step S3.
  • the electron beam 14 is irradiated to one surface side of the semiconductor substrate 1.
  • the incident energy is about 250 keV to 3 MeV
  • the irradiation amount is about 1 ⁇ 10 13 cm ⁇ 2 to 1 ⁇ 10 15 cm ⁇ 2 .
  • incident energy and irradiation amount are changed according to the standard (switching speed, on-resistance) of the target power semiconductor device.
  • the values of the incident energy and the irradiation amount of the electron beam are set high.
  • the range of the incident energy of the electron beam is limited by the depth dependency of the absorbed dose of the electron beam with respect to silicon (semiconductor substrate). That is, the upper limit value and the lower limit value of the incident energy are set in order to reduce the difference in the amount of absorption of the electron beam between the front surface and the back surface of the semiconductor substrate.
  • the temperature rise of the sample (semiconductor substrate, etc.) when irradiated with the electron beam is about several tens of degrees Celsius. For this reason, it is not particularly necessary to control the temperature of the sample when irradiating the electron beam. For example, a process of irradiating at room temperature may be performed.
  • a process of irradiating at room temperature may be performed.
  • lattice defects, composite defects, and impurity defects are generated in the semiconductor substrate 1.
  • a composite defect for example, an E center that is attributed to a vacancy-group V element pair is generated.
  • the impurity defect for example, a G center attributed to a carbon-carbon pair or a C center attributed to an oxygen-carbon pair is generated.
  • the E center recombination level is Ec ⁇ 0.43 eV
  • the G center recombination level is Ev + 0.17 eV
  • the C center recombination level is Ev + 0.33 eV.
  • Ec is the energy at the lower end of the conduction band
  • Ev is the energy at the upper end of the valence band.
  • Defects generated in the semiconductor substrate have the effect of shortening the recombination lifetime of carriers, and in particular, in the band gap (1.11 eV) of silicon (semiconductor substrate), a defect level is formed near the center of the band gap. It is said that the defects possessed have a high effect of shortening the recombination lifetime of the carriers.
  • the C center is preferable to the G center as a defect.
  • the E center is not desirable because it has a level close to the mid gap of silicon and causes reverse bias leakage. Therefore, in the power semiconductor device according to the embodiment, the C center is positively used as a defect in order to shorten the recombination lifetime of the carriers accumulated in the drift layer.
  • lattice defects or composite defects remain in the semiconductor substrate 1. These defects are low in heat resistance and disappear due to current or heat generated when the power semiconductor device is energized with a high current density. For example, characteristics when a power semiconductor device is energized for a long time with a high current density. Will change.
  • the semiconductor substrate 1 is subjected to heat treatment for several hours at a temperature of 250 ° C. or higher and 400 ° C. or lower, preferably 300 ° C. or higher and 400 ° C. or lower. It has been found that the majority of complex defects can be extinguished or made electrically inactive.
  • the time for performing the heat treatment depends on the impurity concentration in the semiconductor substrate and the dose of the electron beam irradiated on the semiconductor substrate. For example, when the impurity concentration is high, impurity defects are easily formed, and lattice defects or composite defects are reduced. Therefore, the heat treatment time is set short. On the other hand, when the electron beam irradiation amount is large, the number of lattice defects or composite defects increases, so the heat treatment time is set longer.
  • the heat treatment is preferably performed in an inert gas such as nitrogen in order to suppress oxidation of the electrode material of the power semiconductor device.
  • the carriers accumulated in the drift layer in the power semiconductor device can be obtained by efficiently remaining the C center.
  • the recombination lifetime can be shortened, and the speed of the power semiconductor device can be increased.
  • the first effect is that a high generation efficiency of the C center can be obtained.
  • the C center is more effective in reducing the lifetime by recombining the carriers as compared with the G center. Therefore, it is desired to increase the generation efficiency of the C center.
  • the generation efficiency is the ratio of the C center to the electron beam irradiation dose, and means to increase this ratio. By increasing the generation efficiency, the amount of electron beam irradiation can be reduced, which can contribute to simplification of the manufacturing process.
  • the inventors evaluated the relationship between the C center concentration and the oxygen concentration in the semiconductor substrate, and the relationship between the G center concentration and the oxygen concentration in the semiconductor substrate, respectively. The evaluation will be described.
  • the carbon concentration is set to a substantially constant concentration (about 3 ⁇ 10 14 cm ⁇ 3 to 9 ⁇ 10 14 cm ⁇ 3 ), and the oxygen concentration is set to 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm.
  • a semiconductor substrate distributed within a range of about ⁇ 3 was used.
  • the semiconductor substrate was irradiated with an electron beam under irradiation conditions of an irradiation energy of 750 keV and an irradiation amount of 1 ⁇ 10 14 cm ⁇ 2, and the C center concentration and the G center concentration in each semiconductor substrate.
  • PL Photoluminescence
  • FIG. 7 shows the relationship between the C center concentration and the oxygen concentration in the semiconductor substrate.
  • FIG. 8 shows the relationship between the concentration of the G center and the oxygen concentration in the semiconductor substrate.
  • FIG. 7 it can be seen that the higher the oxygen concentration in the semiconductor substrate is, the higher the concentration of the C center is, and the generation of the C center is promoted.
  • FIG. 8 it can be seen that the higher the oxygen concentration in the semiconductor substrate, the lower the concentration of the G center, and the generation of the G center is suppressed. From this, it was found that impurity defects (G center and C center) can be controlled by defining the carbon concentration and the oxygen concentration in the semiconductor substrate.
  • the higher the oxygen concentration in the semiconductor substrate the better.
  • the oxygen concentration is It has been found that it is desirable to specify 2 ⁇ 10 18 cm ⁇ 3 (upper limit) or less.
  • the carbon concentration is excessively small, the C center is not generated in the semiconductor substrate. Therefore, in order to surely generate the C center, it is desirable to define the carbon concentration to be 1 ⁇ 10 14 cm ⁇ 3 or more. all right.
  • the upper limit value of the carbon concentration is preferably 1 ⁇ 10 16 cm ⁇ 3 . If the carbon concentration exceeds this upper limit, the generation of the G center is promoted more than the C center. Therefore, it was found that the carbon concentration range is preferably specified to be 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less.
  • the second effect is that the heat resistance of the C center can be increased.
  • the inventors further evaluated the relationship between the C center concentration and the heat treatment temperature (annealing temperature). The evaluation will be described. First, as in the evaluation described above, a semiconductor substrate having a substantially constant carbon concentration and an oxygen concentration distributed within a predetermined range is used as the semiconductor substrate, and the semiconductor substrate is subjected to predetermined irradiation conditions. And irradiated with an electron beam. The semiconductor substrate was subjected to a heat treatment for 20 minutes by distributing the temperature (maximum temperature to 500 ° C.) in the air atmosphere, and the concentration of C center in each semiconductor substrate was measured by the PL method.
  • FIG. 9 shows the relationship between the C center concentration and the annealing temperature.
  • FIG. 10 shows the relationship between the concentration of the G center and the annealing temperature.
  • FIG. 9 it can be seen that when the heat treatment at about 250 ° C. is performed, the concentration of the C center does not decrease in any of the semiconductor substrates. It can also be seen that the semiconductor substrate with a higher oxygen concentration is less likely to decrease the C center concentration even by heat treatment at a higher temperature. This means that the thermal resistance of the C center can be improved by defining the impurity concentration in the semiconductor substrate.
  • By increasing the heat resistance of the C center it is possible to suppress changes during energization of the semiconductor device, set the temperature of the heat treatment in the fourth step high, and eliminate unnecessary defects in a short time.
  • the lower limit value of the oxygen concentration in the semiconductor substrate capable of exhibiting this effect is defined as 1 ⁇ 10 16 cm ⁇ 3 . Therefore, the oxygen concentration in the semiconductor substrate is specified to be 1 ⁇ 10 16 cm ⁇ 3 or more and 2 ⁇ 10 18 cm ⁇ 3 or less together with the upper limit of the oxygen concentration described above.
  • the rate of change is defined as follows. First, let the collector-emitter voltage value be A (initial value) when the inspection gate voltage and emitter voltage flow, respectively, and then load test gate-emitter voltage and collector current flow respectively. When the collector-emitter voltage value is B, the rate of change is represented by (BA) / A.
  • the stability of the switching characteristics was indirectly evaluated using this rate of change. That is, the smaller the rate of change of the saturated emitter-collector voltage, the more stable the power semiconductor device.
  • oxygen has a small diffusion coefficient, so that nonuniformity or non-reproduction of the oxygen concentration in the semiconductor substrate surface is unlikely to occur. Moreover, since the defect is formed by irradiating with an electron beam, the recombination lifetime can be controlled with high accuracy. Further, among lattice defects, composite defects and impurity defects caused by electron beam irradiation, impurity defects having high heat resistance are left to remain, and the remaining lattice defects or composite defects are extinguished or electrically inactive. Can be in a state.
  • the C center has higher heat resistance than lattice defects or composite defects. Furthermore, the heat resistance of the C center is improved when the semiconductor substrate having the above-described oxygen concentration and carbon concentration is used as compared with the case where a semiconductor substrate having a low impurity concentration applied to a normal power semiconductor device is used. I found out that
  • a silicon semiconductor substrate grown by the CZ (Czochralski) method or the MCZ (Magnetic-Field Applied Czochralski) method may be used.
  • CZ Czochralski
  • MCZ Magnetic-Field Applied Czochralski
  • a supplementary description will be given of the difference between a semiconductor substrate grown by the FZ method and a semiconductor substrate grown by the CZ method or the MCZ method.
  • the oxygen concentration distribution decreases as the distance from the diffusion surface increases.
  • the oxygen concentration changes from about 2 ⁇ 10 18 cm ⁇ 3 to about 1 ⁇ 10 15 cm ⁇ 3 at maximum.
  • the change in the thickness direction of the semiconductor substrate is less than about 10%. Become. The result is shown in the upper graph of FIG.
  • the change of the carbon concentration in the thickness direction of the semiconductor substrate is within about 10% for both the semiconductor substrate grown by the FZ method and the semiconductor substrate grown by the CZ method or MCZ method.
  • the C center concentration has almost the same concentration distribution as the oxygen concentration. The result is shown in the lower graph of FIG.
  • the concentration distribution of the C center in the thickness direction of the semiconductor substrate differs between the semiconductor substrate grown by the FZ method and the semiconductor substrate grown by the CZ method or the MCZ method.
  • the loss during switching be small. That is, it is desirable that the switching speed is fast.
  • the switching speed is faster when the C center is distributed over the entire area (thickness direction) of the semiconductor substrate. Therefore, the manufacturing method shown in FIG. 12 using a semiconductor substrate grown by the CZ method or the MCZ method is desirable.
  • the manufacturing method shown in FIG. 1 using a semiconductor substrate grown by the FZ method is desirable.
  • the first modification by using a semiconductor substrate grown by the CZ method or the MCZ method, a power semiconductor device having stable switching characteristics can be manufactured, and the first step is omitted as a manufacturing process. Can contribute to the reduction of the manufacturing process.
  • the power semiconductor device is not limited to the IGBT, and a diode may be formed in addition to the IGBT as shown in FIG.
  • the second step S2 simply replaces the step of forming the IGBT with the step of forming the diode.
  • the diode formed in this way is shown in FIG.
  • a p + layer 34, an n ⁇ drift layer 35 and an n + layer 36 are formed on a semiconductor substrate 31.
  • an anode electrode 32 and a field insulating film 33 are formed so as to be in contact with the p + layer 34.
  • a cathode electrode 37 is formed so as to be in contact with the n + layer 36.
  • This diode 30 can also be stabilized while increasing the switching characteristics as in the case of the IGBT.
  • a power semiconductor device such as a thyristor or GTO may be formed.
  • the present invention is effectively used in a method of manufacturing a power semiconductor device such as an IGBT that performs power control and the like.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne tout d'abord la formation, dans une première étape (S1), d'un substrat semi-conducteur ayant une concentration en carbone qui n'est pas inférieure à 1×1014 cm-3 mais qui n'est pas supérieure à 1×1016cm-3, et une concentration en oxygène qui n'est pas inférieure à 1×1016cm-3 mais qui n'est pas supérieure à 2×1018 cm-3. Puis, dans une deuxième étape (S2), par exemple, un transistor bipolaire à porte isolée (IGBT) est formé sur le substrat semi-conducteur. Ensuite, dans une troisième étape (S3), le substrat semi-conducteur est irradié à l'aide d'un faisceau d'électrons. Enfin, dans une quatrième étape (S4), le substrat semi-conducteur est soumis à un traitement thermique dans les conditions de température de 250 à 400 °C.
PCT/JP2016/051013 2015-04-02 2016-01-14 Procédé de fabrication d'un dispositif à semi-conducteurs de puissance WO2016157935A1 (fr)

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JPWO2020217683A1 (ja) * 2019-04-26 2021-10-14 富士電機株式会社 半導体装置および製造方法
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