WO2016155214A1 - 导电结构及其制作方法、阵列基板、显示装置 - Google Patents
导电结构及其制作方法、阵列基板、显示装置 Download PDFInfo
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- WO2016155214A1 WO2016155214A1 PCT/CN2015/087879 CN2015087879W WO2016155214A1 WO 2016155214 A1 WO2016155214 A1 WO 2016155214A1 CN 2015087879 W CN2015087879 W CN 2015087879W WO 2016155214 A1 WO2016155214 A1 WO 2016155214A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 177
- 239000002184 metal Substances 0.000 claims abstract description 177
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 36
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- 229910052750 molybdenum Inorganic materials 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 8
- 241001239379 Calophysus macropterus Species 0.000 claims description 7
- 229910016024 MoTa Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 171
- 239000010936 titanium Substances 0.000 description 21
- 239000010949 copper Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 3
- 229910001257 Nb alloy Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- ZZUFCTLCJUWOSV-UHFFFAOYSA-N furosemide Chemical compound C1=C(Cl)C(S(=O)(=O)N)=CC(C(O)=O)=C1NCC1=CC=CO1 ZZUFCTLCJUWOSV-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Definitions
- Embodiments of the present invention relate to a conductive structure, a method of fabricating the same, an array substrate, and a display device.
- the low temperature poly-silicon (LTPS) thin film transistor display device is different from the conventional amorphous silicon thin film transistor display device, and its electron mobility can reach 50-200 cm 2 /vs, which can effectively reduce the channel area. Thereby, the area of the thin film transistor device is reduced, and the purpose of increasing the aperture ratio and the integration degree is achieved, thereby reducing the power consumption while improving the brightness of the display.
- LTPS low temperature poly-silicon
- each signal line is generally made of metal aluminum (Al) which is low in cost, high in conductivity, and very small in metal ion diffusibility.
- Al metal aluminum
- the pure Al having a higher thickness is very prone to hillock phenomenon on the surface in the case where the grain directions are relatively uniform, thereby Great impact on the contact of the signal line and subsequent optical inspection work.
- the conductive structure and the manufacturing method thereof, the array substrate and the display device provided by the embodiments of the present invention can suppress the small protrusion phenomenon generated when the conductive structure on the array substrate is heated.
- At least one embodiment of the present invention provides a conductive structure including a plurality of first metal layers made of aluminum, and a second metal layer disposed between each adjacent two first metal layers.
- the two metal layers are made of a metal other than aluminum.
- the density of the first metal layers of two adjacent layers is different.
- the thickness of the second metal layer of each layer is from 1 nm to 8 nm.
- the first metal layer of each layer has a thickness of from 200 angstroms to 2800 angstroms.
- the electrically conductive structure comprises 2 to 4 layers of the first metal layer.
- a third metal layer made of Ti or Mo and a fourth metal layer made of Ti or Mo are further included, and each of the first metal layer and each of the second metal layers are located at the Between the three metal layers and the fourth metal layer.
- the material of the second metal layer is any one or more of the following: Ag, Cu, MoTa, MoNb, Ti.
- At least one embodiment of the present invention further provides an array substrate including a gate line, a data line, a source, a drain, and a gate, the gate line, the data line, the source, the drain, At least one of the gates is the conductive structure described above.
- At least one embodiment of the present invention also provides a display device including the above array substrate.
- At least one embodiment of the present invention also provides a method of fabricating a conductive structure, comprising: fabricating a plurality of first metal layers on a substrate using aluminum, and using aluminum between each adjacent two first metal layers The metal is made of a second metal layer.
- the substrate before the second metal layer is made of aluminum on the substrate, and the second metal layer is made of metal other than aluminum between each adjacent two first metal layers, the substrate is included:
- the third metal layer is made of Ti or Mo;
- the first metal layer is made of aluminum on the substrate, and the second metal layer is made of metal other than aluminum between each adjacent two first metal layers.
- FIG. 1 is a schematic diagram of a conductive structure according to an embodiment of the present invention.
- FIG. 2 is a schematic diagram of a conductive structure according to another embodiment of the present invention.
- FIG. 3 is a partial schematic view of an array substrate according to an embodiment of the invention.
- FIG. 4 is a partial plan view of an array substrate according to an embodiment of the invention.
- At least one embodiment of the present invention provides a conductive structure including a plurality of first metal layers made of aluminum, and a second metal layer disposed between each adjacent two first metal layers.
- the second metal layer is made of a metal other than aluminum.
- At least one embodiment of the present invention provides a conductive structure by providing a plurality of first metal layers made of aluminum and providing a second metal layer between each adjacent two first metal layers for blocking, thereby reducing single
- the continuous length of the grains in the first metal layer of the layer in turn, can reduce the small protrusion phenomenon of the conductive structure when heated without reducing the overall thickness of the conductive structure.
- the first metal layer is an aluminum film made of pure aluminum
- the material of the second metal layer may be Ag (silver), Cu (copper), MoTa (molybdenum-niobium alloy), One or more of MoNb (molybdenum-niobium alloy) and Ti (titanium).
- the second metal layer may be Ag, or other layers such as Cu, MoTa, MoNb, Ti, etc. which are in good contact with Al may be selected, and for the convenience of process, the second metal The layer can be Ti.
- the number of the first metal layer and the second metal layer may be set according to actual conditions.
- the conductive structure may include 2 to 4 layers of the first metal layer (or 1 to 3 layers of the second metal layer), each of which The thickness of the first metal layer of the layer may range from 200 angstroms to 2800 angstroms.
- the thickness of each first metal layer may be from 2000 angstroms to 2800 angstroms, for example, may be 2300 angstroms, 2600 angstroms, etc.; if the conductive structure includes four The first metal layer of the layer may have a thickness of 200 angstroms to 800 angstroms per layer of the first metal layer, for example, 300 angstroms, 600 angstroms, or the like.
- the thickness of the second metal layer of each layer may be from 1 nm to 8 nm, thereby not only avoiding the adverse effect on the overall conductivity of the conductive structure, but also etching the pattern to form a pattern. Has a good etching effect.
- the thickness of the second metal layer may be 3 nm, 5 nm, 7 nm, or the like.
- the density of the first metal layers of the adjacent two layers may be different, so that the crystal grains in the first metal layer on both sides of the same second metal layer may be inconsistent, thereby further suppressing A small protrusion phenomenon that occurs when the conductive structure is heated.
- the conductive structure further includes a third metal layer made of Ti or Mo and a fourth metal layer made of Ti or Mo, and each layer of the first metal layer and each layer of the second metal layer Both are located between the third metal layer and the fourth metal layer.
- the third metal layer is formed on the conductive
- the lowermost portion of the structure serves as a barrier layer for blocking the outward diffusion of aluminum atoms in the first metal layer.
- a conductive structure (such as a gate or a source/drain) is formed over the semiconductor active layer, so that the third The metal layer is disposed between the first metal layer and the semiconductor amorphous silicon layer, so that the aluminum atoms in the first metal layer can be blocked from diffusing to the semiconductor active layer; and the fourth metal layer is disposed on the uppermost layer of the conductive structure, Since Mo and Ti do not easily cause small protrusions on the surface under high temperature conditions, and the hardness of both is higher than Al, the release of stress of the first metal layer can be suppressed, so that the surface of the first metal layer of the uppermost layer can be further suppressed. The production of small protrusions.
- FIG. 1 is a schematic diagram of a conductive structure according to an embodiment of the present invention.
- the conductive structure includes a third metal layer 30 made of Ti or Mo, and a fourth metal layer 40 made of Ti or Mo. Between the metal layer 30 and the fourth metal layer 40, two first metal layers 10 made of aluminum and a second metal layer 20 between the two first metal layers 10 are disposed.
- the two first metal layers are aluminum films made of pure aluminum, and the deposition density of the two first metal layers is different.
- the second metal layer is a metal film made of Ag, Cu, MoTa, MoNb or Ti, two layers.
- the first metal layer and the second metal layer are disposed to overlap each other, and the second metal layer is disposed between the two first metal layers and is in close contact with the two first metal layers on both sides, and the second metal layer is The two first metal layers are isolated, so that the continuous length of the crystal grains in the first metal layer of each layer can be reduced, and the small protrusion phenomenon generated when the conductive structure is heated is effectively reduced.
- FIG. 2 is a schematic diagram of a conductive structure according to another embodiment of the present invention.
- the conductive structure includes a third metal layer 30 made of Ti or Mo, and a fourth metal layer 40 made of Ti or Mo.
- a third metal layer 10 made of pure aluminum is further disposed between the three metal layers 30 and the fourth metal layer 40, and a second metal layer 20 is further disposed between each adjacent two first metal layers 10.
- the layers are overlapped and the adjacent layers are in close contact.
- the deposition density of the three first metal layers is different from each other.
- the density of the three first metal layers may gradually increase from the third metal layer to the fourth metal layer, and the material of the second metal layer 20 may be adopted.
- a metal film made of Ag, Cu, MoTa, MoNb or Ti The three first metal layers are separated from each other by the two second metal layers, so that the continuous length of the crystal grains in the first metal layer of each layer can be reduced, and the small protrusion phenomenon generated when the conductive structure is heated is effectively reduced.
- At least one embodiment of the present invention further provides an array substrate including a gate line, a data line, a source, a drain, and a gate, wherein the gate line, the data line, and the source At least one of the pole, the drain, and the gate is the conductive structure described above.
- FIG. 3 is a partial schematic view of an array substrate according to an embodiment of the present invention.
- the array substrate includes a substrate substrate 1, and a buffer layer 2, a semiconductor active layer 3, and a gate sequentially disposed on the substrate substrate 1.
- FIG. 4 is a partial schematic plan view of an array substrate according to an embodiment of the present invention. 4 shows only a portion corresponding to one pixel structure including gate lines 51 and data lines 71 crossing each other, wherein the gate lines 51 are connected to the gate 5, and the data lines 71 are connected to the source 7.
- a pixel electrode 8 is further included, which is electrically connected to the drain 7 of the thin film transistor.
- the gate electrode 5 and the source and drain electrodes 7 in the array substrate can adopt the above-mentioned conductive structure, taking the source and drain electrodes 7 as an example, wherein the third metal layer is located at the lowermost layer of the source and drain electrodes to be in contact with the substrate, and the multilayer layer A metal layer and a second metal layer are overlapped to form a surface of the third metal layer, and the fourth metal layer is located at the uppermost layer as a surface layer structure as a source and a drain, and when performing the hydrogenation process, the first metal of any two adjacent layers
- the layer can be blocked by the second metal layer, thereby reducing the continuous length of the crystal grains in the first metal layer of each layer, effectively reducing the small protrusion phenomenon of the conductive structure when heated, and through the third metal layer,
- the diffusion of aluminum atoms in the first metal layer in the source drain is blocked to the semiconductor active layer, preventing adverse effects on the semiconductor active layer.
- the fourth metal layer the release of stress when the first metal layer is heated can be suppresse
- the embodiment according to the present invention is not limited thereto, wherein the gate line, the data line, the source, the drain, and the gate are not limited thereto.
- At least one of the poles may be fabricated from a conductive structure in accordance with an embodiment of the present invention.
- the array substrate provided by at least one embodiment of the present invention is configured by disposing each electrode and signal line in the array substrate into a plurality of layers of a first metal layer made of aluminum, and in each adjacent two layers of the first metal layer.
- a second metal layer is disposed between the barriers to further reduce the small protrusion phenomenon of the conductive structure when heated without affecting the electrical resistance of each conductive structure.
- the respective conductive structures in the array substrate can be increased from the current 300-400 nm to 1000 nm or even thicker, and the signal is reduced in the case where the signal line width is small.
- the resistance of the line has a good effect.
- At least one embodiment of the present invention also provides a display device including the above array substrate.
- the display device provided by the embodiment of the present invention may be any product or component having a display function, such as a notebook computer display screen, a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, and the like.
- At least one embodiment of the present invention further provides a method for fabricating a conductive structure, comprising: fabricating a plurality of first metal layers on a substrate using aluminum, and using aluminum between each adjacent two first metal layers The metal other than the metal is made of a second metal layer.
- Each of the second metal layers may have a thickness of 1 nm to 8 nm, and each of the first metal layers may have a thickness of 200 angstroms to 2800 angstroms, and the second metal layer may be made of Ag or Cu. , MoTa, MoNb or Ti.
- the first metal layer of 2 to 4 layers may be formed.
- the density of the first metal layers of the adjacent two layers is different.
- the method further includes: on the substrate A third metal layer is formed using Ti or Mo.
- the method further includes: using Ti or Mo The fourth metal layer.
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Abstract
Description
Claims (11)
- 一种导电结构,包括至少两层由铝制作的第一金属层,且在每相邻的两层第一金属层之间还设置有第二金属层,所述第二金属层由铝之外的金属制成。
- 根据权利要求1所述的导电结构,其中,相邻两层的第一金属层的密度不同。
- 根据权利要求1或2所述的导电结构,其中,每一层所述第二金属层的厚度为1nm~8nm。
- 根据权利要求1-3任一项所述的导电结构,其中,每一层所述第一金属层的厚度为200埃米~2800埃米。
- 根据权利要求1-4任一项所述的导电结构,其中,所述导电结构包括2~4层的所述第一金属层。
- 根据权利要求1-5任一项所述的导电结构,还包括由Ti或Mo制作的第三金属层以及由Ti或Mo制作的第四金属层,且每一层第一金属层和每一层第二金属层均位于所述第三金属层与所述第四金属层之间。
- 根据权利要求1-6任一所述的导电结构,其中,所述第二金属层的材料为以下的任意一种或多种:Ag、Cu、MoTa、MoNb、Ti。
- 一种阵列基板,包括栅线、数据线、源极、漏极、栅极,所述栅线、所述数据线、所述源极、所述漏极、所述栅极中至少一者为权利要求1-7任一项所述的导电结构。
- 一种显示装置,包括如权利要求8所述的阵列基板。
- 一种导电结构的制作方法,包括:在基板上采用铝制作多层第一金属层,并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层。
- 根据权利要求10所述的导电结构的制作方法,还包括:在所述基板上采用铝制作多层第一金属层,并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之前,在所述基板上采用Ti或Mo制作第三金属层;在基板上采用铝制作多层第一金属层,并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之后,采用Ti或Mo制作第四金属层。
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US14/907,778 US9837502B2 (en) | 2015-04-03 | 2015-08-24 | Conductive structure and manufacturing method thereof, array substrate, display device |
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CN201510158811.9A CN104867904B (zh) | 2015-04-03 | 2015-04-03 | 导电结构及其制作方法、阵列基板、显示装置 |
CN201510158811.9 | 2015-04-03 |
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CN106932956A (zh) * | 2017-05-22 | 2017-07-07 | 厦门天马微电子有限公司 | 阵列基板、显示面板及显示装置 |
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US9837502B2 (en) | 2017-12-05 |
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