WO2016155214A1 - 导电结构及其制作方法、阵列基板、显示装置 - Google Patents

导电结构及其制作方法、阵列基板、显示装置 Download PDF

Info

Publication number
WO2016155214A1
WO2016155214A1 PCT/CN2015/087879 CN2015087879W WO2016155214A1 WO 2016155214 A1 WO2016155214 A1 WO 2016155214A1 CN 2015087879 W CN2015087879 W CN 2015087879W WO 2016155214 A1 WO2016155214 A1 WO 2016155214A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal layer
metal
conductive structure
layers
layer
Prior art date
Application number
PCT/CN2015/087879
Other languages
English (en)
French (fr)
Inventor
田宏伟
马凯葓
徐文清
左岳平
许晓伟
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/907,778 priority Critical patent/US9837502B2/en
Publication of WO2016155214A1 publication Critical patent/WO2016155214A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present invention relate to a conductive structure, a method of fabricating the same, an array substrate, and a display device.
  • the low temperature poly-silicon (LTPS) thin film transistor display device is different from the conventional amorphous silicon thin film transistor display device, and its electron mobility can reach 50-200 cm 2 /vs, which can effectively reduce the channel area. Thereby, the area of the thin film transistor device is reduced, and the purpose of increasing the aperture ratio and the integration degree is achieved, thereby reducing the power consumption while improving the brightness of the display.
  • LTPS low temperature poly-silicon
  • each signal line is generally made of metal aluminum (Al) which is low in cost, high in conductivity, and very small in metal ion diffusibility.
  • Al metal aluminum
  • the pure Al having a higher thickness is very prone to hillock phenomenon on the surface in the case where the grain directions are relatively uniform, thereby Great impact on the contact of the signal line and subsequent optical inspection work.
  • the conductive structure and the manufacturing method thereof, the array substrate and the display device provided by the embodiments of the present invention can suppress the small protrusion phenomenon generated when the conductive structure on the array substrate is heated.
  • At least one embodiment of the present invention provides a conductive structure including a plurality of first metal layers made of aluminum, and a second metal layer disposed between each adjacent two first metal layers.
  • the two metal layers are made of a metal other than aluminum.
  • the density of the first metal layers of two adjacent layers is different.
  • the thickness of the second metal layer of each layer is from 1 nm to 8 nm.
  • the first metal layer of each layer has a thickness of from 200 angstroms to 2800 angstroms.
  • the electrically conductive structure comprises 2 to 4 layers of the first metal layer.
  • a third metal layer made of Ti or Mo and a fourth metal layer made of Ti or Mo are further included, and each of the first metal layer and each of the second metal layers are located at the Between the three metal layers and the fourth metal layer.
  • the material of the second metal layer is any one or more of the following: Ag, Cu, MoTa, MoNb, Ti.
  • At least one embodiment of the present invention further provides an array substrate including a gate line, a data line, a source, a drain, and a gate, the gate line, the data line, the source, the drain, At least one of the gates is the conductive structure described above.
  • At least one embodiment of the present invention also provides a display device including the above array substrate.
  • At least one embodiment of the present invention also provides a method of fabricating a conductive structure, comprising: fabricating a plurality of first metal layers on a substrate using aluminum, and using aluminum between each adjacent two first metal layers The metal is made of a second metal layer.
  • the substrate before the second metal layer is made of aluminum on the substrate, and the second metal layer is made of metal other than aluminum between each adjacent two first metal layers, the substrate is included:
  • the third metal layer is made of Ti or Mo;
  • the first metal layer is made of aluminum on the substrate, and the second metal layer is made of metal other than aluminum between each adjacent two first metal layers.
  • FIG. 1 is a schematic diagram of a conductive structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a conductive structure according to another embodiment of the present invention.
  • FIG. 3 is a partial schematic view of an array substrate according to an embodiment of the invention.
  • FIG. 4 is a partial plan view of an array substrate according to an embodiment of the invention.
  • At least one embodiment of the present invention provides a conductive structure including a plurality of first metal layers made of aluminum, and a second metal layer disposed between each adjacent two first metal layers.
  • the second metal layer is made of a metal other than aluminum.
  • At least one embodiment of the present invention provides a conductive structure by providing a plurality of first metal layers made of aluminum and providing a second metal layer between each adjacent two first metal layers for blocking, thereby reducing single
  • the continuous length of the grains in the first metal layer of the layer in turn, can reduce the small protrusion phenomenon of the conductive structure when heated without reducing the overall thickness of the conductive structure.
  • the first metal layer is an aluminum film made of pure aluminum
  • the material of the second metal layer may be Ag (silver), Cu (copper), MoTa (molybdenum-niobium alloy), One or more of MoNb (molybdenum-niobium alloy) and Ti (titanium).
  • the second metal layer may be Ag, or other layers such as Cu, MoTa, MoNb, Ti, etc. which are in good contact with Al may be selected, and for the convenience of process, the second metal The layer can be Ti.
  • the number of the first metal layer and the second metal layer may be set according to actual conditions.
  • the conductive structure may include 2 to 4 layers of the first metal layer (or 1 to 3 layers of the second metal layer), each of which The thickness of the first metal layer of the layer may range from 200 angstroms to 2800 angstroms.
  • the thickness of each first metal layer may be from 2000 angstroms to 2800 angstroms, for example, may be 2300 angstroms, 2600 angstroms, etc.; if the conductive structure includes four The first metal layer of the layer may have a thickness of 200 angstroms to 800 angstroms per layer of the first metal layer, for example, 300 angstroms, 600 angstroms, or the like.
  • the thickness of the second metal layer of each layer may be from 1 nm to 8 nm, thereby not only avoiding the adverse effect on the overall conductivity of the conductive structure, but also etching the pattern to form a pattern. Has a good etching effect.
  • the thickness of the second metal layer may be 3 nm, 5 nm, 7 nm, or the like.
  • the density of the first metal layers of the adjacent two layers may be different, so that the crystal grains in the first metal layer on both sides of the same second metal layer may be inconsistent, thereby further suppressing A small protrusion phenomenon that occurs when the conductive structure is heated.
  • the conductive structure further includes a third metal layer made of Ti or Mo and a fourth metal layer made of Ti or Mo, and each layer of the first metal layer and each layer of the second metal layer Both are located between the third metal layer and the fourth metal layer.
  • the third metal layer is formed on the conductive
  • the lowermost portion of the structure serves as a barrier layer for blocking the outward diffusion of aluminum atoms in the first metal layer.
  • a conductive structure (such as a gate or a source/drain) is formed over the semiconductor active layer, so that the third The metal layer is disposed between the first metal layer and the semiconductor amorphous silicon layer, so that the aluminum atoms in the first metal layer can be blocked from diffusing to the semiconductor active layer; and the fourth metal layer is disposed on the uppermost layer of the conductive structure, Since Mo and Ti do not easily cause small protrusions on the surface under high temperature conditions, and the hardness of both is higher than Al, the release of stress of the first metal layer can be suppressed, so that the surface of the first metal layer of the uppermost layer can be further suppressed. The production of small protrusions.
  • FIG. 1 is a schematic diagram of a conductive structure according to an embodiment of the present invention.
  • the conductive structure includes a third metal layer 30 made of Ti or Mo, and a fourth metal layer 40 made of Ti or Mo. Between the metal layer 30 and the fourth metal layer 40, two first metal layers 10 made of aluminum and a second metal layer 20 between the two first metal layers 10 are disposed.
  • the two first metal layers are aluminum films made of pure aluminum, and the deposition density of the two first metal layers is different.
  • the second metal layer is a metal film made of Ag, Cu, MoTa, MoNb or Ti, two layers.
  • the first metal layer and the second metal layer are disposed to overlap each other, and the second metal layer is disposed between the two first metal layers and is in close contact with the two first metal layers on both sides, and the second metal layer is The two first metal layers are isolated, so that the continuous length of the crystal grains in the first metal layer of each layer can be reduced, and the small protrusion phenomenon generated when the conductive structure is heated is effectively reduced.
  • FIG. 2 is a schematic diagram of a conductive structure according to another embodiment of the present invention.
  • the conductive structure includes a third metal layer 30 made of Ti or Mo, and a fourth metal layer 40 made of Ti or Mo.
  • a third metal layer 10 made of pure aluminum is further disposed between the three metal layers 30 and the fourth metal layer 40, and a second metal layer 20 is further disposed between each adjacent two first metal layers 10.
  • the layers are overlapped and the adjacent layers are in close contact.
  • the deposition density of the three first metal layers is different from each other.
  • the density of the three first metal layers may gradually increase from the third metal layer to the fourth metal layer, and the material of the second metal layer 20 may be adopted.
  • a metal film made of Ag, Cu, MoTa, MoNb or Ti The three first metal layers are separated from each other by the two second metal layers, so that the continuous length of the crystal grains in the first metal layer of each layer can be reduced, and the small protrusion phenomenon generated when the conductive structure is heated is effectively reduced.
  • At least one embodiment of the present invention further provides an array substrate including a gate line, a data line, a source, a drain, and a gate, wherein the gate line, the data line, and the source At least one of the pole, the drain, and the gate is the conductive structure described above.
  • FIG. 3 is a partial schematic view of an array substrate according to an embodiment of the present invention.
  • the array substrate includes a substrate substrate 1, and a buffer layer 2, a semiconductor active layer 3, and a gate sequentially disposed on the substrate substrate 1.
  • FIG. 4 is a partial schematic plan view of an array substrate according to an embodiment of the present invention. 4 shows only a portion corresponding to one pixel structure including gate lines 51 and data lines 71 crossing each other, wherein the gate lines 51 are connected to the gate 5, and the data lines 71 are connected to the source 7.
  • a pixel electrode 8 is further included, which is electrically connected to the drain 7 of the thin film transistor.
  • the gate electrode 5 and the source and drain electrodes 7 in the array substrate can adopt the above-mentioned conductive structure, taking the source and drain electrodes 7 as an example, wherein the third metal layer is located at the lowermost layer of the source and drain electrodes to be in contact with the substrate, and the multilayer layer A metal layer and a second metal layer are overlapped to form a surface of the third metal layer, and the fourth metal layer is located at the uppermost layer as a surface layer structure as a source and a drain, and when performing the hydrogenation process, the first metal of any two adjacent layers
  • the layer can be blocked by the second metal layer, thereby reducing the continuous length of the crystal grains in the first metal layer of each layer, effectively reducing the small protrusion phenomenon of the conductive structure when heated, and through the third metal layer,
  • the diffusion of aluminum atoms in the first metal layer in the source drain is blocked to the semiconductor active layer, preventing adverse effects on the semiconductor active layer.
  • the fourth metal layer the release of stress when the first metal layer is heated can be suppresse
  • the embodiment according to the present invention is not limited thereto, wherein the gate line, the data line, the source, the drain, and the gate are not limited thereto.
  • At least one of the poles may be fabricated from a conductive structure in accordance with an embodiment of the present invention.
  • the array substrate provided by at least one embodiment of the present invention is configured by disposing each electrode and signal line in the array substrate into a plurality of layers of a first metal layer made of aluminum, and in each adjacent two layers of the first metal layer.
  • a second metal layer is disposed between the barriers to further reduce the small protrusion phenomenon of the conductive structure when heated without affecting the electrical resistance of each conductive structure.
  • the respective conductive structures in the array substrate can be increased from the current 300-400 nm to 1000 nm or even thicker, and the signal is reduced in the case where the signal line width is small.
  • the resistance of the line has a good effect.
  • At least one embodiment of the present invention also provides a display device including the above array substrate.
  • the display device provided by the embodiment of the present invention may be any product or component having a display function, such as a notebook computer display screen, a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • At least one embodiment of the present invention further provides a method for fabricating a conductive structure, comprising: fabricating a plurality of first metal layers on a substrate using aluminum, and using aluminum between each adjacent two first metal layers The metal other than the metal is made of a second metal layer.
  • Each of the second metal layers may have a thickness of 1 nm to 8 nm, and each of the first metal layers may have a thickness of 200 angstroms to 2800 angstroms, and the second metal layer may be made of Ag or Cu. , MoTa, MoNb or Ti.
  • the first metal layer of 2 to 4 layers may be formed.
  • the density of the first metal layers of the adjacent two layers is different.
  • the method further includes: on the substrate A third metal layer is formed using Ti or Mo.
  • the method further includes: using Ti or Mo The fourth metal layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Electroluminescent Light Sources (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种导电结构及其制作方法、阵列基板、显示装置。该导电结构包括多层由铝制作的第一金属层(10)，且在每相邻的两层第一金属层(10)之间还设置有第二金属层(20)，所述第二金属层(20)由铝之外的金属制成。该导电结构可以在不减小导电结构整体厚度的情况下减少导电结构在受热时产生的小突起现象。

Description

导电结构及其制作方法、阵列基板、显示装置 技术领域
本发明的实施例涉及一种导电结构及其制作方法、阵列基板、显示装置。
背景技术
低温多晶硅(low temperature poly-silicon,简称为LTPS)薄膜晶体管显示器件有别于传统的非晶硅薄膜晶体管显示器件，其电子迁移率可以达到50～200cm2/vs，可以有效减小沟道面积从而减少薄膜晶体管器件的面积，达到提高开口率和集成度的目的，由此在提高显示器亮度的同时，也可以降低功率消耗。
在LTPS工艺中，为了降低线电阻，一般采用成本较低、导电性较高、金属离子扩散性非常小的金属铝(Al)制作各信号线。然而，在进行后续的Hydro(氢化)工艺时，由于纯铝本身的热膨胀性质，厚度较高的纯Al在晶粒方向比较一致的情况下非常容易发生表面上的小突起(hillock)现象，从而极大的影响信号线的接触情况以及后续的光学检查工作。
发明内容
本发明的实施例提供的导电结构及其制作方法、阵列基板、显示装置能够抑制阵列基板上的导电结构在受热时产生的小突起现象。
本发明至少一实施例提供了一种导电结构，包括多层由铝制作的第一金属层，且在每相邻的两层第一金属层之间还设置有第二金属层，所述第二金属层由铝之外的金属制成。
在一些示例中，相邻两层的第一金属层的密度不同。
在一些示例中，每一层所述第二金属层的厚度为1nm～8nm。
在一些示例中，每一层所述第一金属层的厚度为200埃米～2800埃米。
在一些示例中，所述导电结构包括2～4层的所述第一金属层。
在一些示例中，还包括由Ti或Mo制作的第三金属层以及由Ti或Mo制作的第四金属层，且每一层第一金属层和每一层第二金属层均位于所述第 三金属层与所述第四金属层之间。
在一些示例中，所述第二金属层的材料为以下的任意一种或多种：Ag、Cu、MoTa、MoNb、Ti。
本发明至少一实施例还提供了一种阵列基板，包括栅线、数据线、源极、漏极、栅极，所述栅线、所述数据线、所述源极、所述漏极、所述栅极中至少一者为上述的导电结构。
本发明至少一实施例还提供了一种显示装置，包括上述的阵列基板。
本发明至少一实施例还提供了一种导电结构的制作方法，包括：在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层。
在一些示例中，在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之前包括：在所述基板上采用Ti或Mo制作第三金属层；在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之后包括：采用Ti或Mo制作第四金属层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1是本发明一实施例提供的导电结构的示意图；
图2是本发明另一实施例提供的导电结构的示意图；
图3是本发明一实施例提供的阵列基板的局部示意图；
图4是本发明一实施例提供的阵列基板的局部平面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本发明保护的范围。
本发明至少一实施例提供了一种导电结构，该导电结构包括多层由铝制作的第一金属层，且在每相邻的两层第一金属层之间还设置有第二金属层，所述第二金属层由铝之外的金属制成。
本发明至少一实施例提供的导电结构，通过设置多层由铝制作的第一金属层，并在每相邻的两层第一金属层之间设置第二金属层进行阻隔，从而可以减少单层第一金属层中的晶粒的连续长度，进而可以在不减小导电结构整体厚度的情况下减少导电结构在受热时产生的小突起现象。
在本发明至少一实施例提供的导电结构，第一金属层为采用纯铝制作的铝膜，第二金属层的材料可以为Ag(银)、Cu(铜)、MoTa(钼钽合金)、MoNb(钼铌合金)、Ti(钛)中的一种或多种。例如，若为增强导电结构的导电性，第二金属层可以采用Ag，亦可以选择Cu、MoTa、MoNb、Ti等其他和Al接触较好的膜层，若为工艺便利性考量，第二金属层可以采用Ti。
此外，第一金属层以及第二金属层的数量可以根据实际情况进行设置，例如，导电结构可以包括2～4层的第一金属层(或者1～3层的第二金属层)，每一层第一金属层的厚度可以为200埃米～2800埃米。例如，若导电结构包括两层第一金属层，则每层第一金属层的厚度可以为2000埃米～2800埃米，例如，可以为2300埃米、2600埃米等；若导电结构包括四层第一金属层，则每层第一金属层的厚度可以为200埃米～800埃米，例如可以为300埃米、600埃米等。
在本发明至少一实施例中，每层第二金属层的厚度可以为1nm～8nm，从而不但可以避免对导电结构整体导电性造成不良影响，还能在对其的刻蚀以形成图案的过程中有良好的刻蚀效果。例如，第二金属层的厚度可以为3nm、5nm、7nm等。
在本发明至少一实施例中，可使相邻两层的第一金属层的密度不同，从而可以使同一第二金属层两侧的第一金属层中的晶粒不一致，从而可以进一步地抑制导电结构在受热时产生的小突起现象。
本发明至少一实施例中，导电结构还包括由Ti或Mo制作的第三金属层以及由Ti或Mo制作的第四金属层，且每一层第一金属层和每一层第二金属层均位于所述第三金属层与所述第四金属层之间。该第三金属层形成在导电 结构的最下方作为阻挡层，阻挡第一金属层中的铝原子向外扩散，例如在低温薄膜晶体管中，导电结构(如栅极或者源漏极)形成在半导体有源层上方，使得第三金属层设置在第一金属层与半导体非晶硅层之间，从而可以阻挡第一金属层中的铝原子扩散至半导体有源层；对于第四金属层，其设置在导电结构的最上层，由于Mo和Ti在高温条件下表面不容易产生小突起现象，且两者的硬度高于Al，从而可以抑制第一金属层应力的释放，从而可以进一步地抑制最上层的第一金属层的表面小突起的产生。
参见图1，图1是本发明一实施例提供的导电结构的示意图，该导电结构包括由Ti或Mo制作的第三金属层30、由Ti或Mo制作的第四金属层40，在第三金属层30与第四金属层40之间设置有两层由铝制作的第一金属层10以及位于两层第一金属层10之间的第二金属层20。两层第一金属层均为采用纯铝制作的铝膜，并且两层第一金属层的沉积密度不同，第二金属层为采用Ag、Cu、MoTa、MoNb或者Ti制作的金属薄膜，两层第一金属层、第二金属层之间相互重叠设置，第二金属层设置在两层第一金属层之间并分别在两侧与两层第一金属层紧密接触，通过第二金属层将两层第一金属层相隔离，从而可以减少每层第一金属层中的晶粒的连续长度，有效减少导电结构在受热时产生的小突起现象。
参见图2，图2是本发明另一实施例提供的导电结构的示意图，该导电结构包括由Ti或Mo制作的第三金属层30、由Ti或Mo制作的第四金属层40，在第三金属层30与第四金属层40之间还设置有三层由纯铝制作的第一金属层10，在每相邻的两层第一金属层10之间还设置有第二金属层20，各层结构之间重叠设置，且相邻层结构之间紧密接触。三层第一金属层的沉积密度互不相同，例如，该三层第一金属层的密度可以从第三金属层至第四金属层的方向逐渐增加，第二金属层20的材料可以为采用Ag、Cu、MoTa、MoNb或者Ti制作的金属薄膜。通过两层第二金属层将三层第一金属层相互隔离，从而可以减少每层第一金属层中的晶粒的连续长度，有效减少导电结构在受热时产生的小突起现象。
此外，本发明至少一实施例还提供了一种阵列基板，该阵列基板包括栅线、数据线、源极、漏极、栅极，其中，所述栅线、所述数据线、所述源极、所述漏极、所述栅极中至少一者为上述所述的导电结构。
参见图3，图3是本发明一实施例提供的阵列基板的局部示意图，该阵列基板包括衬底基板1，以及依次设置在衬底基板1上的缓冲层2、半导体有源层3、栅极绝缘层4、栅极5、层间绝缘层6以及源漏极7。参见图4，图4是本发明一实施例提供的阵列基板的局部示意平面图。图4仅示出了对应于一个像素结构的部分，其中包括彼此交叉的栅线51和数据线71，其中栅线51与栅极5相连，数据线71与源极7相连。在栅线和数据线限定的区域内，还包括像素电极8，该像素电极与薄膜晶体管的漏极7电连接。
阵列基板中的栅极5以及源漏极7均可以采用上述的导电结构，以源漏极7为例，其中的第三金属层位于源漏极的最下层从而与基板相接触，多层第一金属层以及第二金属层重叠形成在第三金属层的表面，第四金属层位于最上层为作为源漏极的表层结构，在进行氢化工艺时，由于任意相邻两层的第一金属层都能被第二金属层相阻隔，从而可以减少每层第一金属层中的晶粒的连续长度，有效减少导电结构在受热时产生的小突起现象，且通过第三金属层，可以以阻挡源漏极中的第一金属层中的铝原子扩散至半导体有源层，防止对半导体有源层产生不良影响。通过第四金属层，可以抑制第一金属层受热时应力的释放，从而可以进一步地抑制源漏极表面小突起的产生。
虽然上面以源漏极7由根据本发明实施例的导电结构制作为例进行了描述，然而根据本发明的实施例并不限制于此，其中栅线、数据线、源极、漏极、栅极中的至少之一可以由根据本发明实施例的导电结构制作。
本发明至少一实施例提供的阵列基板，通过将该阵列基板中的各电极及信号线设置为多层由铝制作的第一金属层的结构，并在每相邻的两层第一金属层之间设置第二金属层进行阻隔，进而可以在不影响各导电结构电阻的情况下减少导电结构在受热时产生的小突起现象。并且由于造成小突起(hillock)的主要原因及动力被抑制，阵列基板中的各导电结构可以由目前的300～400nm增加到1000nm甚至更厚，对于在信号线线宽较小的情况下减少信号线的电阻有很好的作用。
此外，本发明至少一实施例还提供了一种显示装置，包括上述所述的阵列基板。本发明实施例提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
此外，本发明至少一实施例还提供了一种导电结构的制作方法，包括：在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层。
每一层所述第二金属层的厚度可以为1nm～8nm，每一层所述第一金属层的厚度可以为200埃米～2800埃米，制作第二金属层的材料可以为Ag、Cu、MoTa、MoNb或者Ti。
在上述的导电结构的制作方法中，可以形成2～4层的所述第一金属层。
在上述的导电结构的制作方法中，相邻两层的第一金属层的密度不同。
在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之前，上述方法还包括：在所述基板上采用Ti或Mo制作第三金属层。
在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之后，上述方法还包括：采用Ti或Mo制作第四金属层。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年4月3日递交的中国专利申请第201510158811.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (11)

  1. 一种导电结构，包括至少两层由铝制作的第一金属层，且在每相邻的两层第一金属层之间还设置有第二金属层，所述第二金属层由铝之外的金属制成。
  2. 根据权利要求1所述的导电结构，其中，相邻两层的第一金属层的密度不同。
  3. 根据权利要求1或2所述的导电结构，其中，每一层所述第二金属层的厚度为1nm～8nm。
  4. 根据权利要求1-3任一项所述的导电结构，其中，每一层所述第一金属层的厚度为200埃米～2800埃米。
  5. 根据权利要求1-4任一项所述的导电结构，其中，所述导电结构包括2～4层的所述第一金属层。
  6. 根据权利要求1-5任一项所述的导电结构，还包括由Ti或Mo制作的第三金属层以及由Ti或Mo制作的第四金属层，且每一层第一金属层和每一层第二金属层均位于所述第三金属层与所述第四金属层之间。
  7. 根据权利要求1-6任一所述的导电结构，其中，所述第二金属层的材料为以下的任意一种或多种：Ag、Cu、MoTa、MoNb、Ti。
  8. 一种阵列基板，包括栅线、数据线、源极、漏极、栅极，所述栅线、所述数据线、所述源极、所述漏极、所述栅极中至少一者为权利要求1-7任一项所述的导电结构。
  9. 一种显示装置，包括如权利要求8所述的阵列基板。
  10. 一种导电结构的制作方法，包括：在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层。
  11. 根据权利要求10所述的导电结构的制作方法，还包括：在所述基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之前，在所述基板上采用Ti或Mo制作第三金属层；
    在基板上采用铝制作多层第一金属层，并在每相邻的两层第一金属层之间采用铝之外的金属制作第二金属层之后，采用Ti或Mo制作第四金属层。
PCT/CN2015/087879 2015-04-03 2015-08-24 导电结构及其制作方法、阵列基板、显示装置 WO2016155214A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/907,778 US9837502B2 (en) 2015-04-03 2015-08-24 Conductive structure and manufacturing method thereof, array substrate, display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510158811.9 2015-04-03
CN201510158811.9A CN104867904B (zh) 2015-04-03 2015-04-03 导电结构及其制作方法、阵列基板、显示装置

Publications (1)

Publication Number Publication Date
WO2016155214A1 true WO2016155214A1 (zh) 2016-10-06

Family

ID=53913637

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/087879 WO2016155214A1 (zh) 2015-04-03 2015-08-24 导电结构及其制作方法、阵列基板、显示装置

Country Status (3)

Country Link
US (1) US9837502B2 (zh)
CN (1) CN104867904B (zh)
WO (1) WO2016155214A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252357B (zh) * 2016-08-24 2019-05-21 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管阵列基板及其制作方法、液晶面板
CN106932956A (zh) * 2017-05-22 2017-07-07 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
US20230187343A1 (en) * 2021-12-09 2023-06-15 International Business Machines Corporation Top via interconnect structure with texture suppression layers

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297185A (ja) * 1994-04-20 1995-11-10 Matsushita Electric Ind Co Ltd 金属配線およびそれを用いた薄膜トランジスタとｔｆｔ液晶表示装置と金属配線の形成方法
JP2005044936A (ja) * 2003-07-25 2005-02-17 Seiko Epson Corp 薄膜トランジスタの製造方法、薄膜トランジスタ、電気光学装置、及び電子機器
CN101887893A (zh) * 2010-06-10 2010-11-17 深超光电（深圳）有限公司 一种薄膜晶体管阵列基板及其制造方法
CN102623461A (zh) * 2012-03-19 2012-08-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN103715171A (zh) * 2013-12-24 2014-04-09 京东方科技集团股份有限公司 导电金属互联线及其制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3878839B2 (ja) * 2001-05-31 2007-02-07 チ メイ オプトエレクトロニクス コーポレーション ヒロックのないアルミニウム配線層およびその形成方法
KR100626007B1 (ko) * 2004-06-30 2006-09-20 삼성에스디아이 주식회사 박막 트랜지스터, 상기 박막 트랜지스터의 제조방법, 이박막 트랜지스터를 구비한 평판표시장치, 및 이평판표시장치의 제조방법
KR101090252B1 (ko) * 2004-09-24 2011-12-06 삼성전자주식회사 박막 트랜지스터 표시판 및 그의 제조 방법
CN101226964A (zh) * 2008-02-14 2008-07-23 友达光电股份有限公司 薄膜晶体管、有源元件阵列基板以及液晶显示面板
US20130240995A1 (en) * 2012-03-19 2013-09-19 Shenzhen China Star Optoelectronics Technology Co., Ltd Thin-film transistor array substrate and manufacturing method thereof
CN102790062B (zh) * 2012-07-26 2016-01-27 北京京东方光电科技有限公司 一种传感器的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297185A (ja) * 1994-04-20 1995-11-10 Matsushita Electric Ind Co Ltd 金属配線およびそれを用いた薄膜トランジスタとｔｆｔ液晶表示装置と金属配線の形成方法
JP2005044936A (ja) * 2003-07-25 2005-02-17 Seiko Epson Corp 薄膜トランジスタの製造方法、薄膜トランジスタ、電気光学装置、及び電子機器
CN101887893A (zh) * 2010-06-10 2010-11-17 深超光电（深圳）有限公司 一种薄膜晶体管阵列基板及其制造方法
CN102623461A (zh) * 2012-03-19 2012-08-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制作方法
CN103715171A (zh) * 2013-12-24 2014-04-09 京东方科技集团股份有限公司 导电金属互联线及其制备方法

Also Published As

Publication number Publication date
CN104867904A (zh) 2015-08-26
CN104867904B (zh) 2018-05-04
US9837502B2 (en) 2017-12-05
US20170040430A1 (en) 2017-02-09

Similar Documents

Publication Publication Date Title
WO2015100935A1 (zh) 阵列基板及其制造方法、以及显示装置
US9911618B2 (en) Low temperature poly-silicon thin film transistor, fabricating method thereof, array substrate and display device
TWI519881B (zh) 陣列基板及其製造方法
WO2013149463A1 (zh) 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置
WO2016161863A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
TWI497182B (zh) 顯示裝置
WO2015043220A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
JP2017508275A (ja) 低温ポリシリコン薄膜トランジスタ及びその製造方法
WO2017202057A1 (zh) 电子器件、薄膜晶体管、以及阵列基板及其制作方法
TW200941106A (en) System for displaying images and fabrication method thereof
US11004980B2 (en) Thin film transistor having vertical channel and manufacturing method therefor, array substrate, display panel and display device
WO2016155214A1 (zh) 导电结构及其制作方法、阵列基板、显示装置
US9263467B2 (en) Thin film transistor array panel and manufacturing method thereof
US20160315158A1 (en) Thin-film transistor and method for fabricating the same, array substrate and method for fabricating the same, and display device
US20110228502A1 (en) Active device array substrate and fabricating method thereof
KR20180021958A (ko) 박막 트랜지스터, 박막 트랜지스터 제조 방법, 및 이를 포함하는 표시 장치
WO2015096369A1 (zh) 阵列基板及其制造方法、显示装置
US7923312B2 (en) Fabricating method of thin film transistor
WO2014172957A1 (zh) 电路板、其制作方法以及显示装置
WO2020244102A1 (zh) 阵列基板及制作方法
US9685463B2 (en) Array substrate, its manufacturing method, display panel and display device
TWI590426B (zh) 光感測陣列之光感測單元的製造方法及其結構
TWI440187B (zh) 畫素結構、陣列基板及其製作方法
CN114883346A (zh) 阵列基板及其制作方法、显示面板
WO2016192447A1 (zh) 一种阵列基板及其制备方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14907778

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15887171

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15887171

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 15887171

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17.04.2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15887171

Country of ref document: EP

Kind code of ref document: A1