WO2016155055A1 - 低温多晶硅tft基板结构及其制作方法 - Google Patents

低温多晶硅tft基板结构及其制作方法 Download PDF

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WO2016155055A1
WO2016155055A1 PCT/CN2015/077159 CN2015077159W WO2016155055A1 WO 2016155055 A1 WO2016155055 A1 WO 2016155055A1 CN 2015077159 W CN2015077159 W CN 2015077159W WO 2016155055 A1 WO2016155055 A1 WO 2016155055A1
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polysilicon
insulating layer
buffer layer
tft region
layer
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French (fr)
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张晓星
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a low temperature polysilicon TFT substrate structure and a method of fabricating the same.
  • Low Temperature Poly-silicon (LTPS) technology is the manufacturing technology of the new generation of TFT substrate.
  • a-Si amorphous silicon
  • Poly-Si has excellent electrical properties and has good driving ability for Active-Matrix Organic Light Emitting Diode (AMOLED). Therefore, AMOLED display backplanes based on low temperature polysilicon technology are currently widely used.
  • the manufacturing method of the existing low-temperature polysilicon TFT substrate structure mainly includes the following steps:
  • Step 1 as shown in FIG. 1, providing a substrate 100, the substrate 100 includes a driving TFT region and a display TFT region, and depositing a buffer layer 110 on the substrate 100;
  • Step 2 As shown in FIG. 2, an amorphous silicon layer is deposited on the buffer layer 110, and after excimer laser annealing, the amorphous silicon layer is subjected to excimer laser annealing treatment to make the non- The crystalline silicon layer is crystallized and converted into a polysilicon layer 130;
  • Step 6 Deposit an interlayer insulating layer 190 on the gate insulating layer 160, the first gate 170, and the second gate 180, and respectively on the interlayer insulating layer 190 and the gate insulating layer 160.
  • the first polysilicon segment 140 and the second polysilicon segment 150 forming a first via hole 200 and a second via hole 200';
  • Step 7 as shown in FIG. 4, depositing and patterning a second metal layer on the interlayer insulating layer 190, respectively forming a first source/drain 210 located in the driving TFT region, and located on the display a second source/drain 220 of the TFT region, the first source/drain 210 is in contact with the first polysilicon segment 140 via a first via 200, and the second source/drain 220 is via a first source/drain 220 The second via 200' is in contact with the second polysilicon segment 150.
  • Excimer Laser Annealing (ELA) technology uses a laser to instantaneously illuminate the surface of amorphous silicon to dissolve and recrystallize. Since the AMOLED driver needs to drive the TFT and the display TFT, the driving TFT requires a high electron mobility, so a relatively large crystal lattice is required, and the display TFT needs to have sufficient electron mobility and current uniformity, so that the OLED device can uniformly emit light.
  • ELA Excimer Laser Annealing
  • the current ELA crystallization technique cannot effectively control the uniformity of the crystal lattice and the crystallographic direction of the crystal lattice, so the crystallization condition is uneven in the distribution of the entire substrate, resulting in a non-uniform long-range display effect.
  • the present invention provides a method for fabricating a low temperature polysilicon TFT substrate structure, comprising the following steps:
  • Step 1 Providing a substrate, the substrate comprising a driving TFT region and a display TFT region, depositing a buffer layer on the substrate, and patterning the buffer layer, so that a thickness of the buffer layer of the driving TFT region is greater than a thickness of the buffer layer of the display TFT region;
  • Step 2 depositing an amorphous silicon layer on the buffer layer, and performing an excimer laser annealing treatment on the amorphous silicon layer after excimer laser annealing, to crystallize the amorphous silicon layer into a polysilicon layer, performing a patterning process on the polysilicon layer to obtain a first polysilicon segment located in the driving TFT region and a second polysilicon segment located in the display TFT region;
  • Step 3 depositing a gate insulating layer on the first polysilicon segment, the second polysilicon segment, and the buffer layer;
  • Step 4 depositing and patterning a first metal layer on the gate insulating layer, respectively forming a first gate and a second gate corresponding to the upper portion of the first polysilicon segment and the second polysilicon segment;
  • Step 5 depositing an interlayer insulating layer on the gate insulating layer, the first gate, and the second gate, and respectively corresponding to the first plurality on the interlayer insulating layer and the gate insulating layer Forming a first via and a second via above the crystalline silicon segment and the second polysilicon segment;
  • Step 6 Depositing and patterning a second metal layer on the interlayer insulating layer to form a first source/drain located in the driving TFT region and a second source/drain in the display TFT region
  • the first source/drain is in contact with the first polysilicon via a first via
  • the second source/drain is in contact with the second poly via via a second via.
  • the lattice size in the first polysilicon segment is larger than the lattice size in the second polysilicon segment; the fragmentation in the second polysilicon segment is more than the fragmentation in the first polysilicon segment .
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • a difference in thickness between the buffer layer of the driving TFT region and the buffer layer of the display TFT region is greater than 500A.
  • the present invention also provides a low-temperature polysilicon TFT substrate structure including a driving TFT region and a display TFT region, the driving TFT region including a substrate, a buffer layer disposed on the substrate, and a first layer disposed on the buffer layer a polysilicon segment, a gate insulating layer disposed on the buffer layer and the first polysilicon segment, and a first gate disposed on the gate insulating layer above the first polysilicon segment, An interlayer insulating layer disposed on the gate insulating layer and the first gate, and a first source/drain provided on the interlayer insulating layer;
  • the display TFT region includes a substrate, a buffer layer disposed on the substrate, a second polysilicon segment disposed on the buffer layer, and a gate disposed on the buffer layer and the second polysilicon segment An insulating layer, a second gate disposed on the gate insulating layer corresponding to the second polysilicon segment, an interlayer insulating layer disposed on the gate insulating layer and the second gate, and a second source/drain on the interlayer insulating layer;
  • the thickness of the buffer layer of the driving TFT region is greater than the thickness of the buffer layer of the display TFT region.
  • the lattice size in the first polysilicon segment is larger than the lattice size in the second polysilicon segment; the fragmentation in the second polysilicon segment is more than the fragmentation in the first polysilicon segment .
  • the substrate is a glass substrate, and the material of the buffer layer is silicon oxide, silicon nitride, or a combination of the two, and the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • a first via hole is formed on the interlayer insulating layer and the gate insulating layer of the driving TFT region corresponding to the first polysilicon segment, and the first source/drain passes through the first via hole and the The first polysilicon segments are in contact;
  • a second via hole is formed on the interlayer insulating layer and the gate insulating layer of the display TFT region corresponding to the second polysilicon segment, and the second source/drain is via the second via hole
  • the second polysilicon segments are in contact.
  • a difference in thickness between the buffer layer of the driving TFT region and the buffer layer of the display TFT region is greater than 500A.
  • the present invention also provides a low-temperature polysilicon TFT substrate structure including a driving TFT region and a display TFT region, the driving TFT region including a substrate, a buffer layer disposed on the substrate, and a first plurality disposed on the buffer layer a crystalline silicon segment, a gate insulating layer disposed on the buffer layer and the first polysilicon segment, and a first gate disposed on the gate insulating layer corresponding to the first polysilicon segment An interlayer insulating layer on the gate insulating layer and the first gate; and a first source/drain provided on the interlayer insulating layer;
  • the display TFT region includes a substrate, a buffer layer disposed on the substrate, a second polysilicon segment disposed on the buffer layer, and a gate disposed on the buffer layer and the second polysilicon segment An insulating layer, a second gate disposed on the gate insulating layer corresponding to the second polysilicon segment, an interlayer insulating layer disposed on the gate insulating layer and the second gate, and a second source/drain on the interlayer insulating layer;
  • the thickness of the buffer layer of the driving TFT region is greater than the thickness of the buffer layer of the display TFT region
  • the lattice size in the first polysilicon segment is larger than the lattice size in the second polysilicon segment; the crushed crystal in the second polysilicon segment is more than in the first polysilicon segment Crushed crystal
  • the substrate is a glass substrate
  • the material of the buffer layer is silicon oxide, silicon nitride, or a combination of the two
  • the material of the interlayer insulating layer is silicon oxide, silicon nitride, or a combination of the two.
  • the lattice size increases the electron mobility, so that the polysilicon layer in the TFT region is crystallized during the crystallization process, ensuring grain boundary uniformity and improving current uniformity, thereby satisfying the electrical requirements of different TFTs. Improve the uniformity of OLED illumination.
  • step 1 is a schematic diagram of step 1 of a method for fabricating a conventional low-temperature polysilicon TFT substrate structure
  • step 2 is a schematic diagram of step 2 of a method for fabricating a conventional low-temperature polysilicon TFT substrate structure
  • step 3 is a schematic diagram of step 3 of a method for fabricating a conventional low-temperature polysilicon TFT substrate structure
  • step 7 is a schematic diagram of step 7 of a method for fabricating a conventional low-temperature polysilicon TFT substrate structure
  • FIG. 5 is a flow chart of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • 6-7 is a schematic diagram of step 1 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 2 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention is a schematic diagram of step 2 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention.
  • step 3 is a schematic diagram of step 3 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention.
  • step 5 is a schematic diagram of step 5 of a method for fabricating a low temperature polysilicon TFT substrate structure according to the present invention
  • FIG. 13 is a schematic view showing the step 6 of the method for fabricating the low-temperature polysilicon TFT substrate structure of the present invention and a cross-sectional view showing the structure of the low-temperature polysilicon TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a low temperature polysilicon TFT substrate structure, including the following steps:
  • Step 1 as shown in FIG. 6-7, a substrate 1 is provided.
  • the substrate 1 includes a driving TFT region and a display TFT region, a buffer layer 11 is deposited on the substrate 1, and the buffer layer 11 is patterned.
  • the thickness of the buffer layer 11 of the driving TFT region is made larger than the thickness of the buffer layer 11 of the display TFT region;
  • the substrate 1 is a glass substrate, and the material of the buffer layer 11 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • the lattice size in the first polysilicon segment 14 is larger than the lattice size in the second polysilicon segment 15; Crushed crystals in the first polysilicon segment 14.
  • Step 3 As shown in FIG. 10, a gate insulating layer 16 is deposited on the first polysilicon segment 14, the second polysilicon segment 15, and the buffer layer 11.
  • Step 4 depositing and patterning a first metal layer on the gate insulating layer 16, respectively forming a first gate corresponding to the first polysilicon segment 14 and the second polysilicon segment 15
  • the pole 17 and the second grid 18 are provided.
  • the material of the interlayer insulating layer 19 is silicon oxide, silicon nitride, or a combination of the two.
  • Step 6 depositing and patterning a second metal layer on the interlayer insulating layer 19, respectively forming a first source/drain 21 in the driving TFT region, and located in the display TFT a second source/drain 22 of the region, the first source/drain 21 is in contact with the first polysilicon segment 14 via a first via 20, and the second source/drain 22 is via a second Via 20' and second polysilicon Segment 15 is in contact.
  • the present invention further provides a low temperature polysilicon TFT substrate structure including a driving TFT region and a display TFT region, the driving TFT region including a substrate 1 , a buffer layer 11 disposed on the substrate 1 , and a first polysilicon segment 14 on the buffer layer 11 , a gate insulating layer 16 disposed on the buffer layer 11 and the first polysilicon segment 14 , corresponding to the first polysilicon segment 14 a first gate electrode 17 on the gate insulating layer 16, an interlayer insulating layer 19 disposed on the gate insulating layer 16 and the first gate electrode 17, and an interlayer insulating layer 19 disposed on the interlayer insulating layer 19.
  • the display TFT region includes a substrate 1, a buffer layer 11 disposed on the substrate 1, a second polysilicon segment 15 disposed on the buffer layer 11, and a buffer layer 11 and a second poly layer. a gate insulating layer 16 on the silicon segment 15 , a second gate electrode 18 disposed on the gate insulating layer 16 corresponding to the second polysilicon segment 15 , and the gate insulating layer 16 and An interlayer insulating layer 19 on the second gate 18, and a second source/drain 22 disposed on the interlayer insulating layer 19;
  • the thickness of the buffer layer 11 of the driving TFT region is larger than the thickness of the buffer layer 11 of the display TFT region.
  • the lattice size in the first polysilicon segment 14 is greater than the lattice size in the second polysilicon segment 15; the fragmentation in the second polysilicon segment 15 is greater than the first polysilicon segment 14 Broken crystals in the middle.
  • a first via hole 20 is formed on the interlayer insulating layer 19 and the gate insulating layer 16 of the driving TFT region corresponding to the first polysilicon segment 14, and the first source/drain 21 is via the first via/drain 21
  • the first via 20 is in contact with the first polysilicon segment 14.
  • a second via hole 20 ′ is formed on the interlayer insulating layer 19 and the gate insulating layer 16 of the display TFT region corresponding to the second polysilicon segment 15 , and the second source/drain 22 is The second via 20' is in contact with the second polysilicon segment 15.
  • the substrate 1 is a glass substrate.
  • the material of the buffer layer 11 is silicon oxide, silicon nitride, or a combination of the two
  • the material of the interlayer insulating layer 19 is silicon oxide, silicon nitride, or a combination of the two.
  • the difference in thickness between the buffer layer 11 of the driving TFT region and the buffer layer 11 of the display TFT region is greater than 500A.
  • the driving TFT region and the buffer layer of the display TFT region have different thicknesses, the thickness of the buffer layer in the driving TFT region is large, and the thickness of the buffer layer in the display TFT region is small, and the polysilicon crystallization process can be performed.
  • Different temperature gradients are formed, and the polycrystalline silicon layer in the driving TFT region has a larger lattice size during crystallization, and has higher electron mobility, and the polycrystalline silicon layer in the TFT region exhibits better grain boundary uniformity during crystallization. It has high current uniformity, satisfies the electrical requirements of different TFTs, and improves the uniformity of OLED illumination.
  • the low-temperature polysilicon TFT substrate structure of the present invention and the method of fabricating the same by providing the buffer layer of the driving TFT region and the display TFT region to have different thicknesses, the thickness of the buffer layer in the driving TFT region is large, and the display TFT The thickness of the buffer layer in the region is small, and different temperature gradients are formed during the crystallization of the polycrystalline silicon, thereby realizing the control of the crystal grain size, so that the polysilicon layer of the driving TFT region forms a larger lattice size during the crystallization process.

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  • Recrystallisation Techniques (AREA)
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Abstract

提供一种低温多晶硅TFT基板结构及其制作方法，通过将驱动TFT区域与显示TFT区域的缓冲层（11）设置成不同的厚度，使驱动TFT区域的缓冲层（11）的厚度较大，显示TFT区域的缓冲层（11）的厚度较小，在多晶硅结晶过程中形成了不同的温度梯度，实现了对结晶颗粒大小的控制，使得驱动TFT 区域的多晶硅层在晶化过程中形成较大的晶格尺寸，提高了电子迁移率，使得显示TFT区域的多晶硅层在晶化过程中实现碎晶，保证了晶界均一性，提高了电流的均一性，从而满足不同TFT的电性要求，提高了OLED发光的均一性。

Description

低温多晶硅TFT基板结构及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板结构及其制作方法。
背景技术
低温多晶硅(Low Temperature Poly-silicon，LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。多晶硅(Poly-Si)具有优异的电学性能，对于主动式矩阵有机发光二极管(Active-Matrix Organic Light Emitting Diode，AMOLED)具有较好的驱动能力。因此，基于低温多晶硅技术的AMOLED显示背板目前被广泛使用。
现有低温多晶硅TFT基板结构的制作方法主要包括如下步骤：
步骤1、如图1所示，提供基板100，所述基板100包括驱动TFT区域与显示TFT区域，在所述基板100上沉积缓冲层110；
步骤2、如图2所示，在所述缓冲层110上沉积非晶硅层，并经过准分子激光退火前处理后，对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶、转变为多晶硅层130；
步骤3、如图3所示，对所述多晶硅层130进行图案化处理，得到间隔排列的位于所述驱动TFT区域的第一多晶硅段140、及位于所述显示TFT区域的第二多晶硅段150；
步骤4、在所述第一多晶硅段140、第二多晶硅段150及缓冲层110上沉积栅极绝缘层160；
步骤5、在所述栅极绝缘层160上沉积并图案化第一金属层，分别对应第一多晶硅段140与第二多晶硅段150的上方形成第一栅极170与第二栅极180；
步骤6、在所述栅极绝缘层160、第一栅极170、及第二栅极180上沉积层间绝缘层190，并在所述层间绝缘层190、及栅极绝缘层160上分别对应所述第一多晶硅段140、及第二多晶硅段150上方形成第一过孔200与第二过孔200’；
步骤7、如图4所示，在所述层间绝缘层190上沉积并图案化第二金属层，分别形成位于所述驱动TFT区域的第一源/漏极210、及位于所述显示 TFT区域的第二源/漏极220，所述第一源/漏极210经由第一过孔200与所述第一多晶硅段140相接触，所述第二源/漏极220经由第二过孔200’与第二多晶硅段150相接触。
其中，准分子激光退火处理(Excimer Laser Annealing，ELA)技术是利用激光的瞬间脉冲照射到非晶硅表面，使其溶化并重新结晶。因为AMOLED驱动需要驱动TFT和显示TFT，驱动TFT需要较高的电子迁移率，所以需要比较大的晶格，显示TFT需要有足够的电子迁移率和电流均一性，从而可以使OLED器件均匀发光。
然而目前的ELA结晶技术对于晶格的均一性和晶格结晶方向不能做到有效控制，所以结晶状况在整个基板的分布上很不均匀，造成显示效果的长程不均一。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板结构的制作方法，可对多晶硅的结晶过程进行控制，使驱动TFT区域的多晶硅层在晶化过程中形成较大的晶格尺寸，提高电子迁移率，使显示TFT区域的多晶硅层在晶化过程中实现碎晶，保证晶界的均一性，提高电流均一性，从而满足不同TFT的电性要求，提高OLED发光的均一性。
本发明的另一目的在于提供一种低温多晶硅TFT基板结构，驱动TFT区域的多晶硅层的晶格尺寸较大，具有较高的电子迁移率，显示TFT区域的多晶硅层的晶界均一性好，具有较高的电流均一性。
为实现上述目的，本发明提供一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
步骤1、提供基板，所述基板包括驱动TFT区域与显示TFT区域，在所述基板上沉积缓冲层，并对所述缓冲层进行图案化处理，使所述驱动TFT区域的缓冲层的厚度大于所述显示TFT区域的缓冲层的厚度；
步骤2、在所述缓冲层上沉积非晶硅层，并经过准分子激光退火前处理后，对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶，转变为多晶硅层，对所述多晶硅层进行图案化处理，得到位于所述驱动TFT区域的第一多晶硅段、及位于所述显示TFT区域的第二多晶硅段；
步骤3、在所述第一多晶硅段、第二多晶硅段及缓冲层上沉积栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积并图案化第一金属层，分别对应第一多晶硅段与第二多晶硅段的上方形成第一栅极与第二栅极；
步骤5、在所述栅极绝缘层、第一栅极、及第二栅极上沉积层间绝缘层，并在所述层间绝缘层、及栅极绝缘层上分别对应所述第一多晶硅段、及第二多晶硅段上方形成第一过孔与第二过孔；
步骤6、在所述层间绝缘层上沉积并图案化第二金属层，分别形成位于所述驱动TFT区域的第一源/漏极、及位于所述显示TFT区域的第二源/漏极，所述第一源/漏极经由第一过孔与所述第一多晶硅段相接触，所述第二源/漏极经由第二过孔与第二多晶硅段相接触。
所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述第二多晶硅段中的碎晶多于第一多晶硅段中的碎晶。
所述基板为玻璃基板，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述驱动TFT区域的缓冲层与所述显示TFT区域的缓冲层的厚度差大于500A。
本发明还提供一种低温多晶硅TFT基板结构，其包括驱动TFT区域与显示TFT区域，所述驱动TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层及第一多晶硅段上的栅极绝缘层、对应所述第一多晶硅段上方设于所述栅极绝缘层上的第一栅极、设于所述栅极绝缘层及第一栅极上的层间绝缘层、及设于所述层间绝缘层上的第一源/漏极；
所述显示TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层及第二多晶硅段上的栅极绝缘层、对应所述第二多晶硅段上方设于所述栅极绝缘层上的第二栅极、设于所述栅极绝缘层及第二栅极上的层间绝缘层、及设于所述层间绝缘层上的第二源/漏极；
其中，所述驱动TFT区域的缓冲层的厚度大于所述显示TFT区域的缓冲层的厚度。
所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述第二多晶硅段中的碎晶多于第一多晶硅段中的碎晶。
所述基板为玻璃基板，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
所述驱动TFT区域的层间绝缘层及栅极绝缘层上对应所述第一多晶硅段上方形成有第一过孔，所述第一源/漏极经由所述第一过孔与所述第一多晶硅段相接触；
所述显示TFT区域的层间绝缘层及栅极绝缘层上对应所述第二多晶硅段上方形成有第二过孔，所述第二源/漏极经由所述第二过孔与所述第二多晶硅段相接触。
所述驱动TFT区域的缓冲层与所述显示TFT区域的缓冲层的厚度差大于500A。
本发明还提供一种低温多晶硅TFT基板结构，包括驱动TFT区域与显示TFT区域，所述驱动TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层及第一多晶硅段上的栅极绝缘层、对应所述第一多晶硅段上方设于所述栅极绝缘层上的第一栅极、设于所述栅极绝缘层及第一栅极上的层间绝缘层、及设于所述层间绝缘层上的第一源/漏极；
所述显示TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层及第二多晶硅段上的栅极绝缘层、对应所述第二多晶硅段上方设于所述栅极绝缘层上的第二栅极、设于所述栅极绝缘层及第二栅极上的层间绝缘层、及设于所述层间绝缘层上的第二源/漏极；
其中，所述驱动TFT区域的缓冲层的厚度大于所述显示TFT区域的缓冲层的厚度；
其中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述第二多晶硅段中的碎晶多于第一多晶硅段中的碎晶；
其中，所述基板为玻璃基板，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
本发明的有益效果：本发明提供的一种低温多晶硅TFT基板结构及其制作方法，通过将驱动TFT区域与显示TFT区域的缓冲层设置成不同的厚度，使驱动TFT区域的缓冲层的厚度较大，显示TFT区域的缓冲层的厚度较小，在多晶硅结晶过程中形成了不同的温度梯度，实现了对结晶颗粒大小的控制，使得驱动TFT区域的多晶硅层在晶化过程中形成较大的晶格尺寸，提高了电子迁移率，使得显示TFT区域的多晶硅层在晶化过程中实现碎晶，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有低温多晶硅TFT基板结构的制作方法的步骤1的示意图；
图2为现有低温多晶硅TFT基板结构的制作方法的步骤2的示意图；
图3为现有低温多晶硅TFT基板结构的制作方法的步骤3的示意图；
图4为现有低温多晶硅TFT基板结构的制作方法的步骤7的示意图；
图5为本发明低温多晶硅TFT基板结构的制作方法的流程图；
图6-7为本发明低温多晶硅TFT基板结构的制作方法的步骤1的示意图；
图8-9为本发明低温多晶硅TFT基板结构的制作方法的步骤2的示意图；
图10为本发明低温多晶硅TFT基板结构的制作方法的步骤3的示意图；
图11为本发明低温多晶硅TFT基板结构的制作方法的步骤4的示意图；
图12为本发明低温多晶硅TFT基板结构的制作方法的步骤5的示意图；
图13为本发明低温多晶硅TFT基板结构的制作方法的步骤6的示意图暨本发明低温多晶硅TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5，本发明首先提供一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
步骤1、如图6-7所示，提供基板1，所述基板1包括驱动TFT区域与显示TFT区域，在所述基板1上沉积缓冲层11，并对所述缓冲层11进行图案化处理，使所述驱动TFT区域的缓冲层11的厚度大于所述显示TFT区域的缓冲层11的厚度；
具体地，所述基板1为玻璃基板，所述缓冲层11的材料为氧化硅(SiOx)、氮化硅(SiNx)、或二者的组合。
通过将驱动TFT区域与显示TFT区域的缓冲层11设置成不同的厚度， 可以在多晶硅结晶过程中形成不同的温度梯度，从而实现对结晶颗粒大小的控制。
优选的，所述驱动TFT区域的缓冲层11与所述显示TFT区域的缓冲层11的厚度差大于500A。
步骤2、如图8-9所示，在所述缓冲层11上沉积非晶硅层，并经过准分子激光退火前处理后，对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶，转变为多晶硅层12，对所述多晶硅层12进行图案化处理，得到位于所述驱动TFT区域的第一多晶硅段14、及位于所述显示TFT区域的第二多晶硅段15。
在准分子激光退火处理过程中，位于驱动TFT区域的较厚的缓冲层11可以形成较好保温层，多晶硅温度较高，融化完全，位于显示TFT区域的较薄的缓冲层11保温效果次之，多晶硅温度较底，融化不完全，从而形成不同的温度梯度，实现了对结晶颗粒大小的控制，使得驱动TFT区域的多晶硅层在晶化过程中形成较大的晶格尺寸，提高了电子迁移率，使得显示TFT区域的多晶硅层在晶化过程中实现碎晶，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。
因此在本实施例中，所述第一多晶硅段14中的晶格尺寸大于第二多晶硅段15中的晶格尺寸；所述第二多晶硅段15中的碎晶多于第一多晶硅段14中的碎晶。
步骤3、如图10所示，在所述第一多晶硅段14、第二多晶硅段15及缓冲层11上沉积栅极绝缘层16。
步骤4、如图11所示，在所述栅极绝缘层16上沉积并图案化第一金属层，分别对应第一多晶硅段14与第二多晶硅段15的上方形成第一栅极17与第二栅极18。
步骤5、如图12所示，在所述栅极绝缘层16、第一栅极17、及第二栅极18上沉积层间绝缘层19，并在所述层间绝缘层19、及栅极绝缘层16上分别对应所述第一多晶硅段14、及第二多晶硅段15上方形成第一过孔20与第二过孔20’。
具体地，所述层间绝缘层19的材料为氧化硅、氮化硅、或二者的组合。
步骤6、如图13所示，在所述层间绝缘层19上沉积并图案化第二金属层，分别形成位于所述驱动TFT区域的第一源/漏极21、及位于所述显示TFT区域的第二源/漏极22，所述第一源/漏极21经由第一过孔20与所述第一多晶硅段14相接触，所述第二源/漏极22经由第二过孔20’与第二多晶硅 段15相接触。
上述低温多晶硅TFT基板结构的制作方法，通过将驱动TFT区域与显示TFT区域的缓冲层设置成不同的厚度，使驱动TFT区域的缓冲层的厚度较大，显示TFT区域的缓冲层的厚度较小，从而在多晶硅结晶过程中形成了不同的温度梯度，实现了对结晶颗粒大小的控制，使得驱动TFT区域的多晶硅层在晶化过程中形成较大的晶格尺寸，提高了电子迁移率，使得显示TFT区域的多晶硅层在晶化过程中实现碎晶，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。
请参阅图13，本发明还提供一种低温多晶硅TFT基板结构，其包括驱动TFT区域与显示TFT区域，所述驱动TFT区域包括基板1、设于所述基板1上的缓冲层11、设于所述缓冲层11上的第一多晶硅段14、设于所述缓冲层11及第一多晶硅段14上的栅极绝缘层16、对应所述第一多晶硅段14上方设于所述栅极绝缘层16上的第一栅极17、设于所述栅极绝缘层16及第一栅极17上的层间绝缘层19、及设于所述层间绝缘层19上的第一源/漏极21；
所述显示TFT区域包括基板1、设于所述基板1上的缓冲层11、设于所述缓冲层11上的第二多晶硅段15、设于所述缓冲层11及第二多晶硅段15上的栅极绝缘层16、对应所述第二多晶硅段15上方设于所述栅极绝缘层16上的第二栅极18、设于所述栅极绝缘层16及第二栅极18上的层间绝缘层19、及设于所述层间绝缘层19上的第二源/漏极22；
其中，所述驱动TFT区域的缓冲层11的厚度大于所述显示TFT区域的缓冲层11的厚度。
所述第一多晶硅段14中的晶格尺寸大于第二多晶硅段15中的晶格尺寸；所述第二多晶硅段15中的碎晶多于第一多晶硅段14中的碎晶。
具体的，所述驱动TFT区域的层间绝缘层19及栅极绝缘层16上对应所述第一多晶硅段14上方形成有第一过孔20，所述第一源/漏极21经由所述第一过孔20与所述第一多晶硅段14相接触。
所述显示TFT区域的层间绝缘层19及栅极绝缘层16上对应所述第二多晶硅段15上方形成有第二过孔20’，所述第二源/漏极22经由所述第二过孔20’与所述第二多晶硅段15相接触。
具体地，所述基板1为玻璃基板。
具体地，所述缓冲层11的材料为氧化硅、氮化硅、或二者的组合，所述层间绝缘层19的材料为氧化硅、氮化硅、或二者的组合。
优选的，所述驱动TFT区域的缓冲层11与所述显示TFT区域的缓冲层11的厚度差大于500A。
上述低温多晶硅TFT基板结构，驱动TFT区域与显示TFT区域的缓冲层具有不同的厚度，驱动TFT区域的缓冲层的厚度较大，显示TFT区域的缓冲层的厚度较小，在多晶硅结晶过程中可形成不同的温度梯度，驱动TFT区域的多晶硅层在晶化过程中形成的晶格尺寸较大，具有较高的电子迁移率，显示TFT区域的多晶硅层在晶化过程中晶界均一性较好，具有较高的电流均一性，满足了不同TFT的电性要求，提高了OLED发光的均一性。
综上所述，本发明的低温多晶硅TFT基板结构及其制作方法，通过将驱动TFT区域与显示TFT区域的缓冲层设置成不同的厚度，使驱动TFT区域的缓冲层的厚度较大，显示TFT区域的缓冲层的厚度较小，在多晶硅结晶过程中形成了不同的温度梯度，实现了对结晶颗粒大小的控制，使得驱动TFT区域的多晶硅层在晶化过程中形成较大的晶格尺寸，提高了电子迁移率，使得显示TFT区域的多晶硅层在晶化过程中实现碎晶，保证了晶界均一性，提高了电流的均一性，从而满足了不同TFT的电性要求，提高了OLED发光的均一性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (13)

  1. 一种低温多晶硅TFT基板结构的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板包括驱动TFT区域与显示TFT区域，在所述基板上沉积缓冲层，并对所述缓冲层进行图案化处理，使所述驱动TFT区域的缓冲层的厚度大于所述显示TFT区域的缓冲层的厚度；
    步骤2、在所述缓冲层上沉积非晶硅层，并经过准分子激光退火前处理后，对所述非晶硅层进行准分子激光退火处理，使所述非晶硅层结晶，转变为多晶硅层，对所述多晶硅层进行图案化处理，得到位于所述驱动TFT区域的第一多晶硅段、及位于所述显示TFT区域的第二多晶硅段；
    步骤3、在所述第一多晶硅段、第二多晶硅段及缓冲层上沉积栅极绝缘层；
    步骤4、在所述栅极绝缘层上沉积并图案化第一金属层，分别对应第一多晶硅段与第二多晶硅段的上方形成第一栅极与第二栅极；
    步骤5、在所述栅极绝缘层、第一栅极、及第二栅极上沉积层间绝缘层，并在所述层间绝缘层、及栅极绝缘层上分别对应所述第一多晶硅段、及第二多晶硅段上方形成第一过孔与第二过孔；
    步骤6、在所述层间绝缘层上沉积并图案化第二金属层，分别形成位于所述驱动TFT区域的第一源/漏极、及位于所述显示TFT区域的第二源/漏极，所述第一源/漏极经由第一过孔与所述第一多晶硅段相接触，所述第二源/漏极经由第二过孔与第二多晶硅段相接触。
  2. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述步骤2中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述第二多晶硅段中的碎晶多于第一多晶硅段中的碎晶。
  3. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述基板为玻璃基板，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合。
  4. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  5. 如权利要求1所述的低温多晶硅TFT基板结构的制作方法，其中，所述驱动TFT区域的缓冲层与所述显示TFT区域的缓冲层的厚度差大于500A。
  6. 一种低温多晶硅TFT基板结构，包括驱动TFT区域与显示TFT区 域，所述驱动TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层及第一多晶硅段上的栅极绝缘层、对应所述第一多晶硅段上方设于所述栅极绝缘层上的第一栅极、设于所述栅极绝缘层及第一栅极上的层间绝缘层、及设于所述层间绝缘层上的第一源/漏极；
    所述显示TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层及第二多晶硅段上的栅极绝缘层、对应所述第二多晶硅段上方设于所述栅极绝缘层上的第二栅极、设于所述栅极绝缘层及第二栅极上的层间绝缘层、及设于所述层间绝缘层上的第二源/漏极；
    其中，所述驱动TFT区域的缓冲层的厚度大于所述显示TFT区域的缓冲层的厚度。
  7. 如权利要求6所述的低温多晶硅TFT基板结构，其中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述第二多晶硅段中的碎晶多于第一多晶硅段中的碎晶。
  8. 如权利要求6所述的低温多晶硅TFT基板结构，其中，所述基板为玻璃基板，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  9. 如权利要求6所述的低温多晶硅TFT基板结构，其中，所述驱动TFT区域的层间绝缘层及栅极绝缘层上对应所述第一多晶硅段上方形成有第一过孔，所述第一源/漏极经由所述第一过孔与所述第一多晶硅段相接触；
    所述显示TFT区域的层间绝缘层及栅极绝缘层上对应所述第二多晶硅段上方形成有第二过孔，所述第二源/漏极经由所述第二过孔与所述第二多晶硅段相接触。
  10. 如权利要求6所述的低温多晶硅TFT基板结构，其中，所述驱动TFT区域的缓冲层与所述显示TFT区域的缓冲层的厚度差大于500A。
  11. 一种低温多晶硅TFT基板结构，包括驱动TFT区域与显示TFT区域，所述驱动TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第一多晶硅段、设于所述缓冲层及第一多晶硅段上的栅极绝缘层、对应所述第一多晶硅段上方设于所述栅极绝缘层上的第一栅极、设于所述栅极绝缘层及第一栅极上的层间绝缘层、及设于所述层间绝缘层上的第一源/漏极；
    所述显示TFT区域包括基板、设于所述基板上的缓冲层、设于所述缓冲层上的第二多晶硅段、设于所述缓冲层及第二多晶硅段上的栅极绝缘层、 对应所述第二多晶硅段上方设于所述栅极绝缘层上的第二栅极、设于所述栅极绝缘层及第二栅极上的层间绝缘层、及设于所述层间绝缘层上的第二源/漏极；
    其中，所述驱动TFT区域的缓冲层的厚度大于所述显示TFT区域的缓冲层的厚度；
    其中，所述第一多晶硅段中的晶格尺寸大于第二多晶硅段中的晶格尺寸；所述第二多晶硅段中的碎晶多于第一多晶硅段中的碎晶；
    其中，所述基板为玻璃基板，所述缓冲层的材料为氧化硅、氮化硅、或二者的组合，所述层间绝缘层的材料为氧化硅、氮化硅、或二者的组合。
  12. 如权利要求11所述的低温多晶硅TFT基板结构，其中，所述驱动TFT区域的层间绝缘层及栅极绝缘层上对应所述第一多晶硅段上方形成有第一过孔，所述第一源/漏极经由所述第一过孔与所述第一多晶硅段相接触；
    所述显示TFT区域的层间绝缘层及栅极绝缘层上对应所述第二多晶硅段上方形成有第二过孔，所述第二源/漏极经由所述第二过孔与所述第二多晶硅段相接触。
  13. 如权利要求11所述的低温多晶硅TFT基板结构，其中，所述驱动TFT区域的缓冲层与所述显示TFT区域的缓冲层的厚度差大于500A。
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