WO2016145691A1 - Circuit d'attaque de grille et dispositif d'affichage - Google Patents

Circuit d'attaque de grille et dispositif d'affichage Download PDF

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Publication number
WO2016145691A1
WO2016145691A1 PCT/CN2015/075840 CN2015075840W WO2016145691A1 WO 2016145691 A1 WO2016145691 A1 WO 2016145691A1 CN 2015075840 W CN2015075840 W CN 2015075840W WO 2016145691 A1 WO2016145691 A1 WO 2016145691A1
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Prior art keywords
gate
signal line
source
circuit
outputs
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PCT/CN2015/075840
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English (en)
Chinese (zh)
Inventor
肖军城
赵莽
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Priority to US14/778,281 priority Critical patent/US9824621B2/en
Publication of WO2016145691A1 publication Critical patent/WO2016145691A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/021—Double addressing, i.e. scanning two or more lines, e.g. lines 2 and 3; 4 and 5, at a time in a first field, followed by scanning two or more lines in another combination, e.g. lines 1 and 2; 3 and 4, in a second field
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display technologies, and in particular to a gate driving circuit and a display device.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • the driving of the gate lines is mainly performed by a driving chip externally connected to the Array substrate, and the driving chip can control the stepwise charging and discharging of the respective gate lines.
  • the Gate Driver On Array (GOA) technology has been applied more and more.
  • the GOA technology realizes the progressive scanning of the gate lines by forming the gate driving circuit on the array substrate. Therefore, the gate driving circuit can be fabricated in the peripheral region of the array substrate by using the original process of the array substrate to replace the original one. External driver chip.
  • GOA technology can eliminate the bonding process of the driver chip, have the opportunity to increase the production capacity and reduce the product cost, and can reduce the frame width of the display device.
  • the present invention provides a gate driving circuit including a shift register, a first outputter, and a second outputter;
  • the shift register to the first outputter and the continuous scan cycle and the second scan cycle The second output device outputs a primary driving signal
  • the first output device In the first scanning period, the first output device outputs a gate driving signal to the first gate line under the driving of the primary driving signal;
  • the second outputter In the second scan period, the second outputter outputs a gate drive signal to the second gate line under the driving of the primary driving signal.
  • the shift register includes a latch and a NAND gate circuit
  • the latch receives the first trigger signal and outputs a second trigger signal before the first scan period and the second scan period;
  • the latch continuously outputs the second trigger signal, and the NAND circuit outputs the primary under the driving of the second trigger signal Drive signal.
  • the latch is connected to a first primary clock signal line, and the NAND gate circuit is connected to a second primary clock signal line;
  • the first primary clock signal line and the second primary clock signal line each output a pulse signal, and the phase difference between the two is 180°.
  • the latch comprises NMOS transistors T9, T10, T11, T12, T13, T14, and PMOS transistors T4, T5, T7, T8, T15, T16;
  • a gate of T7, T10, T13, T15 is connected to the first primary clock signal line, a gate of T4, T9 is connected to a first trigger signal end, and a gate of T8, T12 is connected to an output end of the latch;
  • the source of T13 is connected to a low-level signal line, the source of T15 is connected to a high-level signal line, and the drains of T13 and T15 are connected to the gates of T5 and T11;
  • the source of T4 and T8 is connected to the high-level signal line, the drain of T4 is connected to the source of T5, and the drain of T8 is connected to the source of T7;
  • the source of T9 and T12 is connected to the low-level signal line, the drain of T9 is connected to the source of T10, and the drain of T12 is connected to the source of T11;
  • T5, T7, T10, and T11 are connected to the gates of T14 and T16;
  • the source of T14 is connected to the low-level signal line
  • the source of T16 is connected to the high-level signal line
  • the drains of T14 and T16 are connected, and serve as the output end of the latch.
  • the NAND gate circuit includes NMOS transistors T41, T42, and PMOS transistors T39, T40;
  • a gate of T39, T41 is connected to the second primary clock signal line, and a gate of T40, T42 is connected to an output end of the latch;
  • the source of T42 is connected to the low-level signal line, the drain of T42 is connected to the source of T41, and the drain of T41 is used as the output end of the NAND circuit;
  • the sources of T39 and T40 are connected to the high-level signal line, and the drains of T39 and T40 are connected to the drain of T41.
  • the shift register further includes an inverter, the inverter includes an NMOS transistor T38 and a PMOS transistor T37;
  • T37 and T38 are connected to the output end of the NAND circuit, the source of T37 is connected to the high-level signal line, the source of T38 is connected to the low-level signal line, and the drains of T37 and T38 are connected, and The output of the shift register.
  • the shift register further includes a forward and reverse selection circuit.
  • the forward and reverse selection circuit includes NMOS transistors T1, T3, and PMOS transistors T0, T2:
  • T1 and T2 are connected to the forward scanning signal line, and the gates of T0 and T3 are connected to the reverse scanning signal line;
  • the source of T0 and T1 is connected to the output of the previous stage shift register or the forward trigger signal line, and the source of T2 and T3 is connected to the output of the first stage shift register or the reverse trigger signal line;
  • T0, T1, T2, and T3 are connected and serve as the output terminals of the forward and reverse selection circuits.
  • first output device is connected to the first secondary clock signal line
  • second output device is connected to the second secondary clock signal line
  • the first secondary clock signal line In the first scanning period, the first secondary clock signal line outputs a high level
  • the second secondary clock signal line outputs a high level.
  • the first output device includes a NAND gate circuit and a buffer
  • the NAND circuit performs a NAND operation on the high level outputted by the first secondary clock signal line and the primary driving signal, and outputs a low level;
  • the buffer receives the low level and outputs a gate drive signal to the first gate line.
  • the NAND gate circuit includes NMOS transistors T21 and T22, and a PMOS transistor T19. T20;
  • a gate of T19, T21 is connected to the first secondary clock signal line, and a gate of T20, T22 is connected to an output end of the shift register;
  • the source of T22 is connected to the low-level signal line, the drain of T22 is connected to the source of T21, and the drain of T21 is used as the output of the NAND circuit;
  • the sources of T19 and T20 are connected to a high-level signal line, and the drains of T19 and T20 are connected to the drain of T21;
  • the buffer includes NMOS transistors T18, T24, T26, and PMOS transistors T17, T23, T25;
  • T17 and T18 are connected to the output terminals of the NAND circuit, the drains of T17 and T18 are connected to the gates of T23 and T24, the drains of T23 and T24 are connected to the gates of T25 and T26, and the drains of T25 and T26 are leaked. Connecting the first gate line to the pole;
  • the sources of T17, T23, and T25 are connected to the high-level signal line, and the sources of T18, T24, and T26 are connected to the low-level signal line.
  • the second output device includes a NAND gate circuit and a buffer
  • the NAND gate circuit performs a NAND operation on the high level outputted by the second secondary clock signal line and the primary driving signal, and outputs a low level;
  • the buffer receives the low level and outputs a gate drive signal to the second gate line.
  • the NAND gate circuit includes NMOS transistors T29, T30, and PMOS transistors T27, T28;
  • a gate of T27, T29 is connected to the second secondary clock signal line, and a gate of T28, T30 is connected to an output end of the shift register;
  • the source of T30 is connected to the low-level signal line, the drain of T30 is connected to the source of T29, and the drain of T29 is used as the output end of the NAND circuit;
  • T27 and T28 are connected to a high-level signal line, and the drains of T27 and T28 are connected to the drain of T29;
  • the buffer includes NMOS transistors T32, T34, T36, and PMOS transistors T31, T33, T35;
  • T31 and T32 are connected to the output terminals of the NAND circuit, the drains of T31 and T32 are connected to the gates of T33 and T34, the drains of T33 and T34 are connected to the gates of T35 and T36, and the drains of T35 and T36 are leaked. Connecting the second gate line to the pole;
  • the sources of T31, T33, and T35 are connected to the high-level signal line, and the sources of T32, T34, and T36 are connected to the low-level signal line.
  • the gate driving circuit is a GOA gate driving circuit.
  • the present invention also provides a display device comprising a plurality of cascaded gate drive circuits, wherein the display device performs display in an interleaved driving manner.
  • the invention brings about the following beneficial effects: in the gate driving circuit provided by the invention, the shift register can output the primary driving signal in two consecutive scanning periods, and the first output device and the first driving unit are driven by the primary driving signal The two outputters are each capable of outputting a gate drive signal to a corresponding gate line. Therefore, the gate driving circuit provided by the present invention can drive two gate lines, and the invention significantly reduces the number of gate driving circuits compared to the prior art in which one gate driving circuit drives a gate line. Thereby, the width of the GOA circuit of the frame area of the array substrate can be reduced, thereby reducing the frame width of the display device.
  • FIG. 1 is a schematic diagram of a gate driving circuit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of a display device according to Embodiment 2 of the present invention.
  • FIG. 3 is a schematic diagram of a gate driving circuit on the left side of FIG. 2;
  • FIG. 4 is a schematic diagram of a gate driving circuit on the right side of FIG. 2;
  • Figure 5 is a schematic view of any of the gate drive circuits of Figure 3;
  • FIG. 6 is a schematic diagram of any of the gate driving circuits of FIG. 4;
  • FIG. 7 is a signal timing diagram of a display device according to Embodiment 2 of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • an embodiment of the present invention provides a gate driving circuit that can be fabricated in a peripheral region of an array substrate by using a GOA technique.
  • the gate drive circuit includes a shift register, a first outputter, and a second outputter.
  • the shift register outputs a primary drive signal to the first output and the second output during successive first scan periods and second scan periods.
  • the first output device In the first scan period, the first output device outputs a gate drive signal to the first gate line under the driving of the primary driving signal. In the second scan period, the second outputter outputs a gate drive signal to the second gate line under the driving of the primary drive signal.
  • the shift register can output the primary driving signal in two consecutive scanning periods, and the first output device and the second output device can respectively respond to the driving of the primary driving signal.
  • the gate line outputs a gate drive signal. Therefore, the gate driving circuit provided by the embodiment of the present invention can drive two gate lines. Compared with the prior art, a gate driving circuit drives a gate line, the embodiment of the present invention significantly reduces the gate. The number of driving circuits can reduce the width of the GOA circuit of the frame area of the array substrate, thereby reducing the frame width of the display device.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the embodiment of the present invention provides a display device, which may be an active display device such as a liquid crystal display or an OLED display.
  • a display device which may be an active display device such as a liquid crystal display or an OLED display.
  • This embodiment is described by taking a display screen of a mobile phone as an example.
  • the middle of the array substrate of the display screen is the display area 10
  • the two sides of the display area are the frame area 20, that is, the GOA area.
  • a plurality of cascaded gate driving circuits provided in the first embodiment are formed for driving the gate lines in the display region 10.
  • the display is performed by an interlace driving method, so that all the gate driving circuits are equally divided on both sides of the display region 10 to reduce the width of the one-sided bezel region 20.
  • the resolution of the display screen is 1920 ⁇ 1080
  • FIG. 3 and FIG. 4 are respectively a cascade diagram of the gate driving circuits in the left side frame area 20 and the right side frame area 20 in FIG. 2, which can be seen.
  • a total of 1920 grid lines are provided on the display.
  • FIG. 5 is a specific circuit diagram of any of the gate driving circuits of FIG. 3
  • FIG. 6 is a specific circuit diagram of any of the gate driving circuits of FIG.
  • the gate driving circuit in this embodiment is fabricated by a CMOS process, and the ultra-high carrier mobility characteristic of low temperature poly-silicon (LTPS) can be used in the fabrication including NMOS.
  • Gate drive circuits eg, transistors T1, T3
  • PMOS eg, transistors T0, T2).
  • the gate driving circuit is composed of a shift register, a first outputter, and a second outputter.
  • the shift register mainly includes a latch and a NAND gate circuit.
  • VGH is a high level signal line and VGL is a low level signal line.
  • the latch is connected to the first primary clock signal line, and the NAND gate circuit is connected to the second primary clock signal line.
  • the latch is connected to CK1_1, and the NAND gate is connected to CK1_3 (as shown in FIG. 5); for example, in the second gate driving circuit of FIG. , the latch is connected to CK1_3, and the NAND gate is connected to CK1_1.
  • Both CK1_1 and CK1_3 output a pulse signal (refer to FIG. 7), and the phase difference between the two is 180°.
  • the latch includes NMOS transistors T9, T10, T11, T12, T13, T14, and PMOS transistors T4, T5, T7, T8, T15, T16.
  • the gates of T7, T10, T13, and T15 are connected to CK1_1, the gates of T4 and T9 are connected to the first trigger signal terminal Q(N-1), and the gates of T8 and T12 are connected to the output terminals of the latches.
  • the source of T13 is connected to VGL
  • the source of T15 is connected to VGH
  • the drains of T13 and T15 are connected to the gates of T5 and T11.
  • the source of T4 and T8 is connected to VGH, the drain of T4 is connected to the source of T5, and the drain of T8 is connected to the source of T7.
  • the sources of T9 and T12 are connected to VGL, the drain of T9 is connected to the source of T10, and the drain of T12 is connected to the source of T11.
  • the drains of T5, T7, T10, and T11 are connected to the gates of T14 and T16 at point P.
  • the source of T14 is connected to VGL
  • the source of T16 is connected to VGH
  • the drains of T14 and T16 are connected, and serve as the output of the latch.
  • the latch further includes a PMOS transistor T6.
  • the gate of T6 is connected to the reset signal line Reset, the source of T6 is connected to VGH, and the drain of T6 is connected to the gate of T14 and T16, that is, point P.
  • the NAND gate circuit in the shift register includes NMOS transistors T41 and T42, and PMOS transistors T39 and T40.
  • the gates of T39 and T41 are connected to CK1_3, and the gates of T40 and T42 are connected to the output terminals of the latches.
  • the source of T42 is connected to VGL
  • the drain of T42 is connected to the source of T41
  • the drain of T41 is used as the output of NAND gate.
  • the sources of T39 and T40 are connected to VGH
  • the drains of T39 and T40 are connected to the drain of T41.
  • the shift register further includes an inverter disposed after the NAND gate circuit, and the inverter includes an NMOS transistor T38 and a PMOS transistor T37.
  • the gates of T37 and T38 are connected to the output of the NAND circuit.
  • the source of T37 is connected to VGH
  • the source of T38 is connected to VGL
  • the drains of T37 and T38 are connected, and it is used as the output of the shift register.
  • the shift register further includes a forward and reverse selection circuit.
  • the forward and reverse signal lines U2D and the reverse scan signal line D2U output different high and low levels, and the forward and reverse selection circuits can selectively receive the gate drive circuit from the upper stage or the gate drive circuit from the next stage.
  • the first trigger signal enables two scan modes from top to bottom (forward scan) and bottom to top (inverse scan).
  • the forward and reverse selection circuits include NMOS transistors T1 and T3, and PMOS transistors T0 and T2.
  • the gates of T1 and T2 are connected to U2D, and the gates of T0 and T3 are connected to D2U.
  • the source of T0 and T1 is connected to the output of the shift register of the previous stage (if it is the first stage shift register, it is connected to the forward trigger signal line STVF), and the output of the first stage shift register after the source of T2 and T3 is connected. End (if the last stage shift register is connected to the STVR reverse trigger signal line).
  • the drains of T0, T1, T2, and T3 are connected and serve as the output terminals of the forward and reverse selection circuits.
  • the first output device includes a NAND gate circuit and a buffer.
  • the NAND gate circuit in the first outputter includes NMOS transistors T21, T22, and PMOS transistors T19, T20.
  • the gates of T19 and T21 are connected to the first secondary clock signal line CK2_1, and the gates of T20 and T22 are connected to the output terminal of the shift register.
  • the source of T22 is connected to VGL
  • the drain of T22 is connected to the source of T21
  • the drain of T21 is used as the output of the NAND circuit.
  • the sources of T19 and T20 are connected to VGH
  • the drains of T19 and T20 are connected to the drain of T21.
  • the buffer in the first outputter includes NMOS transistors T18, T24, T26, and PMOS transistors T17, T23, T25.
  • the gates of T17 and T18 are connected to the output terminals of the NAND circuit, the drains of T17 and T18 are connected to the gates of T23 and T24, the drains of T23 and T24 are connected to the gates of T25 and T26, and the drains of T25 and T26 are connected.
  • Gate line gn The sources of T17, T23, and T25 are connected to VGH, and the sources of T18, T24, and T26 are connected to VGL.
  • the second output device also includes a NAND gate circuit and a buffer.
  • the NAND gate circuit in the second outputter includes NMOS transistors T29, T30, and PMOS transistors T27, T28.
  • the gates of T27 and T29 are connected to the second secondary clock signal line CK2_2, and the gates of T28 and T30 are connected to the output terminal of the shift register.
  • the source of T30 is connected to VGL
  • the drain of T30 is connected to the source of T29
  • the drain of T29 is used as the output of NAND gate.
  • the sources of T27 and T28 are connected to VGH
  • the drains of T27 and T28 are connected to the drain of T29.
  • the buffer in the second outputter includes NMOS transistors T32, T34, T36, and PMOS transistors T31, T33, T35.
  • the sources of T31, T33, and T35 are connected to VGH, and the sources of T32, T34, and T36 are connected to VGL.
  • the gate driving circuit is composed of a shift register, a first outputter, a second outputter, and a forward and reverse selection circuit, and the specific circuit is substantially the same as that in FIG. The difference is that the latch is connected to the third primary clock signal line, and the NAND gate circuit is connected to the fourth primary clock signal line.
  • the latch is connected to CK1_2, and the NAND gate is connected to CK1_4 (as shown in FIG. 6); for example, in the second gate driving circuit of FIG. , the latch is connected to CK1_4, and the NAND gate is connected to CK1_2.
  • CK1_2 and CK1_4 are both The pulse signal is output (refer to FIG.
  • the first output device and the second output device both include a NAND gate circuit and a buffer, and the specific device therein is also substantially the same as in FIG. The difference is that the first output is connected to the third secondary clock signal line CK2_3, and the second output is connected to the fourth secondary clock signal line CK2_4.
  • forward scanning is taken as an example.
  • U2D always outputs a high level
  • D2U always outputs a low level
  • T0 and T1 in each shift register are turned on
  • T2 and T3 are turned off.
  • Reset first outputs a low-level pulse, so that all T6 in each shift register is turned on, then P is high, and then the second trigger in each shift register after the inverter consisting of T14 and T16. Signal Q(N) is kept low.
  • the first trigger signal Q(0) is output from the STVF to the left (and right) first shift register, so that T9 in the latch is turned on.
  • T9 in the latch is turned on.
  • CK1_1 outputs a high level, T10 in the latch. It is also turned on, so that the P point is low, and after the inverter composed of T14 and T16, the second trigger signal Q(1) is output. If it is an inversion scan, the first trigger signal is output by the STVR.
  • CK1_1 outputs a low level
  • CK1_3 outputs a high level
  • T11 in the latch is turned on
  • Q(1) turns on T12 in the latch
  • the P point can be kept low.
  • Q (1) can continue to output.
  • T41 and T42 are turned on at the same time, that is, CK1_3 and Q(1) perform NAND operation, output low level, and then pass through the inverter consisting of T37 and T38. , the primary drive signal G(1) is output.
  • the output is high after the operation, so G(1) cannot be output.
  • Q(1) at this time is also input to the second shift register and serves as the first trigger signal of the second shift register.
  • CK2_1 outputs a high level.
  • T21 and T22 are simultaneously turned on, that is, CK2_1 and G(1) perform NAND operation and output low level.
  • the buffer receives the low level and outputs a high level gate drive signal to the first gate line g1.
  • CK2_2 outputs a high level.
  • T29 and T30 are simultaneously turned on, that is, CK2_2 and G(1) perform NAND operation and output low level.
  • the buffer receives the low level and goes to the second gate line G2 outputs a high level gate drive signal.
  • CK1_3 is at a low level, and the shift register no longer outputs G(1), and the gate drive circuit outputs a low level to g1 and g2.
  • the second gate driving circuit In the fifth scan period t5 and the sixth scan period t6, the second gate driving circuit outputs gate driving signals to the fifth gate line g5 and the sixth gate line g6, respectively. By analogy, all gate lines can be driven.
  • each gate driving circuit on the right side of the display area is the same as that on the left side, except that two scanning periods are delayed in timing, and therefore will not be described again.
  • the display device provided by the embodiment of the invention adopts the GOA technology, and the gate driving circuits of the respective stages can be fabricated in the frame region of the array substrate by using a CMOS process.
  • one gate driving circuit can drive two gate lines, and the gate driving circuit is equally divided on both sides of the display area in a manner of interleaving driving, so that one gate driving circuit is available in the length direction.
  • the size is equivalent to 4 grid lines.
  • a gate driving circuit drives a gate line.
  • the size of the gate driving circuit in the length direction is increased by 4 times, and the width direction can be reduced. It is 1/4 of the original, thereby significantly reducing the width of the GOA circuit of the frame area of the array substrate, thereby reducing the frame width of the display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

La présente invention concerne un circuit d'attaque de grille et un dispositif d'affichage. Le circuit d'attaque de grille peut être appliqué à des dispositifs d'affichage tels qu'un afficheur à cristaux liquides et un afficheur à OLED, et résout le problème technique lié à la largeur de cadre relativement grande des dispositifs d'affichage existants. Lorsque le circuit d'attaque de grille fonctionne à t1 et t2 consécutifs, un registre à décalage fournit en sortie un signal d'attaque primaire (G(1)) à une première unité de sortie et une seconde unité de sortie ; à t1, la première unité de sortie est attaquée par le signal d'attaque primaire (G(1)) pour fournir en sortie un signal d'attaque de grille à une première ligne de grille (g1) ; et à t2, la seconde unité de sortie est attaquée par le signal d'attaque primaire (G(1)) pour fournir en sortie un signal d'attaque de grille à une seconde ligne de grille (g2).
PCT/CN2015/075840 2015-03-17 2015-04-03 Circuit d'attaque de grille et dispositif d'affichage WO2016145691A1 (fr)

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CN105096853B (zh) * 2015-07-02 2017-04-19 武汉华星光电技术有限公司 一种扫描驱动电路
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KR102555084B1 (ko) * 2015-12-30 2023-07-13 엘지디스플레이 주식회사 게이트 구동 모듈 및 게이트 인 패널
CN106098001B (zh) 2016-08-04 2018-11-02 武汉华星光电技术有限公司 Goa电路及液晶显示面板
CN106128349B (zh) * 2016-08-29 2019-01-22 武汉华星光电技术有限公司 平面显示装置及其扫描驱动电路
CN106710548B (zh) * 2016-12-28 2018-06-01 武汉华星光电技术有限公司 Cmos goa电路
CN106782386A (zh) * 2016-12-30 2017-05-31 深圳市华星光电技术有限公司 栅极驱动电路
CN106887216B (zh) * 2017-03-09 2019-04-19 京东方科技集团股份有限公司 栅极驱动电路、显示面板及栅极驱动电路的驱动方法
CN106991955A (zh) * 2017-05-22 2017-07-28 厦门天马微电子有限公司 扫描驱动电路、显示面板以及驱动方法
CN108470545B (zh) * 2018-03-01 2020-02-21 昆山国显光电有限公司 一种像素驱动电路、amoled显示屏及电子设备
CN109559698B (zh) * 2018-12-26 2020-09-01 深圳市华星光电半导体显示技术有限公司 一种goa电路
CN111754916B (zh) * 2020-07-09 2021-07-23 武汉华星光电技术有限公司 Goa电路及显示面板
CN111883083B (zh) * 2020-07-30 2021-11-09 惠科股份有限公司 一种栅极驱动电路和显示装置
CN112447151A (zh) * 2020-10-28 2021-03-05 福建华佳彩有限公司 一种单级多输出gip驱动电路及驱动方法
CN114446248B (zh) * 2020-10-30 2023-06-27 华为技术有限公司 一种栅极驱动电路、显示面板及显示装置
CN113554970B (zh) * 2021-09-18 2022-01-14 惠科股份有限公司 Goa驱动电路、显示面板和显示装置

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