WO2016141737A1 - 一种采样时钟产生电路及模数转换器 - Google Patents

一种采样时钟产生电路及模数转换器 Download PDF

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Publication number
WO2016141737A1
WO2016141737A1 PCT/CN2015/095694 CN2015095694W WO2016141737A1 WO 2016141737 A1 WO2016141737 A1 WO 2016141737A1 CN 2015095694 W CN2015095694 W CN 2015095694W WO 2016141737 A1 WO2016141737 A1 WO 2016141737A1
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circuit
field effect
gate
effect transistor
level
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PCT/CN2015/095694
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English (en)
French (fr)
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杨金达
周立人
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华为技术有限公司
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Priority to EP15884415.9A priority Critical patent/EP3261257B1/en
Priority to EP20185869.3A priority patent/EP3790198A1/en
Publication of WO2016141737A1 publication Critical patent/WO2016141737A1/zh
Priority to US15/699,723 priority patent/US10320409B2/en
Priority to US16/434,593 priority patent/US10804922B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1071—Measuring or testing
    • H03M1/1076—Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Definitions

  • the present invention relates to the field of digital signal processing, and in particular, to a sampling clock generating circuit and an analog to digital converter.
  • sampling frequency of a single-chip analog-to-digital converter (ADC) chip cannot be made very high.
  • ADC analog-to-digital converter
  • multiple ADC chips can be used. Interleaved sampling is driven by sampling clocks of different phases.
  • sampling clocks of different phases are generally implemented by the following scheme: the logic circuit divides the clock source signal into n channels, and obtains n signals whose frequency is equal to the clock source signal frequency/n and the phases are different, n ⁇ 2 and n is an integer; A series of different inverters are connected in series in the transmission channel of the n signals to obtain an n-channel sampling clock. The sampling points alternately sampled by the n-channel sampling clock are the same as the sampling points driven by the clock source signal. .
  • the characteristics of each device in the logic circuit cannot reach the theoretical characteristics, resulting in a sampling time of the n-channel sampling clock obtained by the logic circuit and a timing deviation of the picosecond (ps) level from the sampling point of the clock source signal. . Since the delay of the series inverter in the transmission channel can only be as low as 20 ps, the sampling point timing deviation cannot be effectively adjusted, resulting in the interleaved sampling of the multi-chip ADC driven by n sampling clocks as non-uniform sampling, modulus Harmonics appear in the converted signal, reducing the conversion accuracy of the ADC.
  • the present invention provides a sampling clock generating circuit and an analog-to-digital converter.
  • the technical solution is as follows:
  • an embodiment of the present invention provides a sampling clock generating circuit, where the sampling clock generating circuit includes a resistance variable circuit, a non-gate circuit, and a capacitor, and the non-gate circuit includes an input end, an output end, and a power end. And the ground terminal, the input end of the non-gate circuit receives a pulse signal with a period T, the output end of the non-gate circuit is connected to one end of the capacitor, and the other end of the capacitor is grounded, the non-gate circuit The power supply terminates the power supply, the ground end of the non-gate circuit is connected to one end of the resistance variable circuit, and the other end of the resistance variable circuit is grounded;
  • the non-gate circuit is configured to output a low level when the pulse signal is at a high level, and output a high level when the pulse signal is at a low level;
  • the resistance variable circuit is configured to change the resistance value every time T, the change of the resistance value is in a period of n*T, and the resistance values after each change in each period are different, n ⁇ 2 and n is an integer.
  • the resistance variable circuit includes a field effect transistor Q1101 and n first gate switches K1102-K (1101+n), and each of the first gate switches is Including an input terminal, an output terminal, and a control terminal, a drain of the FET Q1101 is connected to a ground terminal of the non-gate circuit, a source of the FET Q1101 is grounded, and a gate of the FET Q1101 Connected to the output ends of the first gate switches respectively, the input ends of the first gate switches respectively receive a signal with a constant voltage value, and the signals received by the input ends of the first gate switches The voltage values of the first gate switches respectively receive a signal with a period of n*T.
  • the signal with the period of n*T is only one.
  • the time period of the time period T is the first level, and the remaining time periods are all the second level, and the signals received by the control ends of the respective strobe switches are not coincident for the time periods of the first level;
  • the input end of the first gating switch when the signal received by the control terminal of the first gating switch is the first level, the input end of the first gating switch is in communication with the output end of the first gating switch; When the signal received by the control terminal of the first gating switch is the second level, the input end of the first gating switch is disconnected from the output end of the first gating switch.
  • the field effect transistor Q1101 is a junction field effect transistor JFET, an enhancement metal-oxide semiconductor field effect transistor MOSFET, or a depletion mode MOSFET.
  • the resistance variable circuit further includes a field effect transistor Q (1102+n), a gate of the FET Q (1102+n) is connected to a power source, and the FET Q (1102+n) a drain connected to a drain of the field effect transistor Q1101, a source of the field effect transistor Q (1102+n) being connected to a source of the field effect transistor Q1101;
  • the field effect transistor Q (1102+n) and the field effect transistor Q1101 are both P-channel field effect transistors, or the field effect transistor Q (1102+n) and the field effect transistor Q1101 are both N-channel FET.
  • the field effect transistor Q (1102+n) is a JFET, an enhancement MOSFET, or a depletion MOSFET.
  • the resistance variable circuit further includes a resistor R (1103+n), one end of the resistor R (1103+n) is connected to a drain of the FET Q1101, and the resistor (1103+ The other end of n) is connected to the source of the field effect transistor Q1101.
  • the sampling clock generating circuit further includes a level adjusting circuit corresponding to the first strobe switch K1102-K (1101+n), and each of the level adjusting circuits and the corresponding one of the The input end of the first gating switch is connected;
  • Each of the level adjustment circuits is configured to provide a signal whose voltage value is constant and adjustable for the input ends of the corresponding first gate switches, and the voltage values of the signals provided by the level adjustment circuits are respectively Not the same.
  • each of the level adjustment circuits includes m resistors R41-R (40+m), m+1 second gate switches K(41+m)-K(41+2*m), and
  • the register IR, m ⁇ 2 and m is an integer
  • each of the second strobe switches includes an input end, an output end and a control end, and m of the resistors R41-R (41+m) are connected in series between the power source and the ground.
  • Each of the series connected contacts is connected to an input end of one of the second strobe switches, and the input ends of the second strobe switches to which the series connected contacts are connected are different, each of the second The output ends of the gate switches respectively correspond to the level adjustment circuit
  • the input ends of the first gating switches are connected, and the control ends of the second gating switches are respectively connected to the register IR.
  • the NOT gate circuit is an inverter, a NAND gate circuit or a NOR gate circuit.
  • the inverter includes a FET Q211 and a FET Q212, and a gate of the FET Q211 and a gate of the FET Q212 are inputs of the non-gate circuit.
  • the drain of the FET Q211 and the drain of the FET Q212 are both outputs of the non-gate circuit, and the source of the FET Q211 is the power terminal of the non-gate circuit, The source of the FET Q212 is the ground of the non-gate circuit;
  • the field effect transistor Q211 is a P-channel enhancement type metal-oxide semiconductor field effect transistor MOSFET, and the field effect transistor Q212 is an N-channel MOSFET; or the field effect transistor Q211 is an N-channel MOSFET.
  • the FET Q212 is a P-channel MOSFET.
  • a level of the pulse signal and a resistance value of the resistance variable circuit do not change at the same time.
  • an embodiment of the present invention provides an analog-to-digital converter ADC, the ADC includes an n-chip ADC chip, the ADC further includes a sampling clock generating circuit and a mixer, and the sampling clock generating circuit is mixed with the Connected to the n-chip ADC chip;
  • the sampling clock generating circuit includes a resistance variable circuit, a non-gate circuit, and a capacitor
  • the non-gate circuit includes an input end, an output end, a power end, and a ground end, and an input end of the non-gate circuit receives a period T a pulse signal, an output end of the non-gate circuit is connected to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the non-gate circuit is connected to a power source, and a ground end of the non-gate circuit is One end of the resistance variable circuit is connected, and the other end of the resistance variable circuit is grounded;
  • the non-gate circuit is configured to output a low level when the pulse signal is at a high level, and output a high level when the pulse signal is at a low level;
  • the resistance variable circuit is configured to change the resistance value once every time period T, and the resistance value is changed by n*T is a period, and the resistance values after each change in each period are different, n ⁇ 2 and n is an integer;
  • the mixer is configured to generate a sampling signal with n cycles of n*T.
  • the level of the i-th sampling signal is in the (i-1)th time period of T
  • the output signal is the same as the output signal of the sampling clock generating circuit, and is low in the remaining time period, and the i-th ADC chip uses the i-th sampling signal as the sampling clock.
  • the RC circuit is formed by a resistance variable circuit, a non-gate circuit and a capacitor.
  • the capacitor is discharged through the RC circuit, so that the resistance variable circuit, the non-gate circuit and the capacitor are composed.
  • the level of the output signal of the sampling clock generating circuit does not immediately change from a high level to a low level due to the level change of the pulse signal, but remains high after a period of time. If the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment.
  • the duration of the high level is related to the resistance value of the variable resistance circuit, the relationship between the duration of the high level and the resistance of the variable resistance circuit is maintained, even if the resistance of the variable resistance circuit is
  • the adjustment precision of the value size only reaches the general level, and the adjustment precision of the high-level time is also high.
  • the adjustment precision of the sampling point timing deviation can reach the hundred femtosecond level, thereby effectively correcting the sampling point timing deviation and avoiding the modulus. Harmonics appear in the converted signal to improve the spurious free dynamic range (SFF, the ratio of the rms value of the carrier frequency to the rms value of the sub-maximum noise component or harmonic distortion component), Improve the conversion accuracy of the ADC.
  • SFF spurious free dynamic range
  • FIG. 1 is a schematic structural diagram of a multi-chip ADC chip parallel sampling circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of waveforms of parallel sampling of a plurality of ADC chips according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a sampling clock generating circuit according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram showing waveforms of input signals and output signals of a non-gate type circuit according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic diagram of resistance value change of a variable value variable circuit according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic waveform diagram of a working process of a sampling clock generating circuit according to Embodiment 1 of the present invention.
  • FIG. 7a-7b are schematic structural diagrams of a sampling clock generating circuit according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic diagram of waveforms of respective end points of each first strobe switch according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic structural diagram of a level adjustment circuit according to Embodiment 2 of the present invention.
  • 10a-10f are schematic structural diagrams of a non-gate circuit according to Embodiment 2 of the present invention.
  • FIG. 11 is a schematic diagram showing changes in resistance values of a pulse signal and a resistance variable circuit according to Embodiment 2 of the present invention.
  • FIG. 12 is a schematic structural diagram of a sampling clock generating circuit according to Embodiment 3 of the present invention.
  • FIG. 13 is a schematic structural diagram of a sampling clock generating circuit according to Embodiment 4 of the present invention.
  • FIG. 14 is a schematic structural diagram of an analog-to-digital converter according to Embodiment 5 of the present invention.
  • Figure 15 is a waveform diagram showing the input signal of the mixer and the output signals of the theoretical and actual cases provided by the fifth embodiment of the present invention.
  • FIG. 1 and FIG. 2 are respectively a schematic diagram of a circuit structure and a waveform diagram of parallel sampling of multiple ADC chips, which can be seen from FIG. 1 . It can be seen that the sampling clock generation circuit is respectively connected to ADC1 and ADC2.
  • the ADC3 and ADC4 are connected by four ADC chips to provide sampling clocks for the four ADC chips of ADC1, ADC2, ADC3 and ADC4.
  • the four ADC chips of ADC1, ADC2, ADC3 and ADC4 respectively sample the input signal under the driving of the sampling clock.
  • the signals obtained by sampling the four ADC chips of ADC1, ADC2, ADC3 and ADC4 constitute the output signal.
  • the sampling clock generation circuit provides the same sampling clocks for the four ADC chips of ADC1, ADC2, ADC3, and ADC4 at the same frequency and different phases, so that ADC1, ADC2, ADC3, and ADC4 are periodically in timing.
  • the input signal is sequentially sampled, and the effect of sampling with a sampling frequency of the sampling clock frequency of 4 times is obtained.
  • the number of the foregoing ADC chips, the circuit for parallel sampling of the plurality of ADC chips, and the waveforms thereof are merely examples, and the present invention is not limited thereto.
  • the sampling clock generating circuit includes a resistance variable circuit 1, a non-gate circuit 2, and a capacitor C.
  • the non-gate circuit 2 includes an input end and an output end. The power terminal and the ground terminal, the input terminal of the non-gate circuit 2 receives the pulse signal of the period T, the output end of the non-gate circuit 2 is the output end of the sampling clock generation circuit, and the output end of the non-gate circuit 2 is connected with one end of the capacitor C.
  • the other end of the capacitor C is grounded, the power supply terminal of the non-gate circuit 2 is connected to the power supply, the ground terminal of the non-gate circuit 2 is connected to one end of the resistance variable circuit 1, and the other end of the resistance variable circuit 1 is grounded.
  • the non-gate circuit 2 is used to output a low level when the pulse signal is at a high level (ie, the input signal of the non-gate circuit is high) (ie, the output signal of the non-gate circuit is low) Flat); When the pulse signal is low (ie, the input signal of the non-gate circuit is low), the output is high (ie, the output signal of the non-gate circuit is high).
  • the resistance variable circuit 1 is used for the resistance value to change every time T, the change of the resistance value is in the period of n*T, and the resistance values after each change in each period are different, n ⁇ 2 and n is Integer.
  • the resistance changes from R1 to R2, and then a period of time T reaches the end of one cycle and another cycle.
  • the resistance value changes from R2 to R1, that is, the resistance values after each change in each cycle are different.
  • n is equal to the number of slices of ADC chips that are sampled in parallel.
  • the high level and the low level are an electrical engineering statement, and the high level is a high voltage opposite to the low level.
  • the high level is the input (or output) level allowed when the input (or output) of the logic gate is 1.
  • the low level is allowed when the input (or output) of the logic gate is 0.
  • Input (or output) level For example, for a signal whose voltage value varies from 0 to 5V, when the voltage value is 0-0.25V, the logic gate is 1 and the level is high. When the voltage value is 3.5-5V, the logic gate is 0. Flat is low.
  • sampling clock generating circuit The working principle of the sampling clock generating circuit provided by the embodiment of the present invention is briefly described below with reference to FIG. 6:
  • the output signal of the non-gate circuit 2 is at a high level, and the output signal (high level) of the non-gate circuit 2 is divided into two paths, one for the capacitor C. Charging, the other is the output signal output of the sampling clock generating circuit, that is, the output signal of the sampling clock generating circuit is at a high level.
  • the output signal of the sampling clock generating circuit corresponding to the pulse signal is at a high level.
  • the capacitor C, the non-gate circuit 2, the resistance variable circuit 1 constitute an RC discharge circuit, and before the capacitor C (
  • the pulse signal is low, the charged amount is released by the resistance variable circuit 1, and the output signal of the sampling clock generating circuit (the output of the non-gate circuit 2 is the output of the sampling clock generating circuit) does not immediately become low.
  • the level is first maintained at a high level for a period of time.
  • the power of the capacitor C is released to a certain level, it is turned to a low level.
  • the output signal of the sampling clock generating circuit corresponding to the pulse signal being high level is maintained at a high level for a period of time and then changed to a low level.
  • the duration of the output signal of the sampling clock generating circuit being kept at a high level is related to the speed at which the capacitor C discharges the power, and it is easy to know that the larger the resistance value of the resistance variable circuit 1 is, the slower the speed at which the capacitor C discharges the power, the sampling clock The longer the output signal of the generating circuit remains high. Since the resistance value of the resistance variable circuit 1 changes once every time T, the change of the resistance value is cycled by n*T, and the resistance values after each change in each cycle are different, so the output of the sampling clock generation circuit The signal is a signal with a period of n*T.
  • each pulse signal (period T) changes from a low level to a high level
  • the output signal of the sampling clock generating circuit remains at a high level.
  • the output signal of the circuit is kept at a high level for T2, T1 ⁇ T2, that is, in each cycle, after each pulse signal (period T) changes from a low level to a high level, the sampling clock generating circuit The duration of the output signal staying high is different.
  • the RC circuit is formed by the resistance variable circuit, the non-gate circuit and the capacitor.
  • the capacitor is discharged through the RC circuit, so that the resistance variable circuit and the non-gate circuit
  • the level of the output signal of the sampling clock generating circuit composed of the capacitor and the capacitor does not change from the high level to the low level immediately after the level change of the pulse signal, but remains high for a period of time and then becomes Low level. If the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment. Because it stays high The duration is related to the resistance value of the variable resistance circuit.
  • the accuracy of the high-level time is also high, and the adjustment accuracy of the timing deviation of the sampling point can reach the hundred femtosecond level, thereby effectively correcting the timing deviation of the sampling point, and avoiding the occurrence of the signal after the analog-to-digital conversion.
  • Harmonics improve the spurious free dynamic range (SFF, the ratio of the rms value of the carrier frequency to the rms value of the sub-maximum noise component or harmonic distortion component), improve the conversion accuracy of the ADC .
  • the embodiment of the present invention provides a sampling clock generating circuit.
  • the variable value variable circuit of the embodiment is specifically implemented by using a field effect transistor and a gate switch.
  • the sampling clock generating circuit includes a variable resistance value.
  • the circuit 1, the non-gate circuit 2, and the capacitor C, the non-gate circuit 2 includes an input terminal, an output terminal, a power terminal, and a ground terminal.
  • the input terminal of the non-gate circuit 2 receives a pulse signal of a period T, and the output of the non-gate circuit 2
  • the end is the output end of the sampling clock generating circuit
  • the output end of the non-gate type circuit 2 is connected to one end of the capacitor C
  • the other end of the capacitor C is grounded
  • the power end of the non-gate type circuit 2 is connected to the power supply
  • the ground end of the non-gate type circuit 2 is blocked.
  • One end of the value variable circuit 1 is connected, and the other end of the resistance variable circuit 1 is grounded.
  • the non-gate circuit 2 is used to output a low level when the pulse signal is at a high level, and a high level when the pulse signal is at a low level (as shown in FIG. 4).
  • the resistance variable circuit 1 is used for the resistance value to change every time T, the change of the resistance value is in the period of n*T, and the resistance values after each change in each period are different, n ⁇ 2 and n is Integer (as shown in Figure 5).
  • the resistance variable circuit 1 may include a field effect transistor Q1101 and n first gate switches K1102-K (1101+n), each of the first gate switches including an input end, an output end, and Control terminal.
  • the drain of the FET Q1101 is connected to the ground of the NAND circuit 2, the source of the FET Q1101 is grounded, and the gate of the FET Q1101 is connected to the output of each of the first strobe switches.
  • the control ends of the respective first strobe switches respectively receive a signal with a period of n*T.
  • the signal with a period of n*T is only the first period in a period of time T.
  • the control terminal of the first strobe switch K1102 receives a period of 2T and is at a high level during a period of time T of each period of the first period (first)
  • the control terminal of the second strobe switch K1103 receives a signal having a period of 2T and a high level (first level) during a period of time T of the second period of each period.
  • the input end of the first gating switch when the signal received by the control end of the first gating switch is at the first level, the input end of the first gating switch is in communication with the output end of the first gating switch; when the control end of the first gating switch receives When the signal is at the second level, the input of the first gating switch is disconnected from the output of the first gating switch.
  • the first level is a high level
  • the second level is a low level
  • the first level is a low level
  • the second level is a high level. 8 is only an example in which the first level is at a high level and the second level is at a low level, and is not intended to limit the present invention.
  • the signal received by the gate of the FET Q1101 is a signal whose voltage value changes once every time T and has a period of n*T, and the voltage values after each change in each period are different.
  • n 2
  • the signal voltage value received by the gate of the field effect transistor Q1101 is V1 in the period of the first duration T, and the period of the second duration is T.
  • the inner is V2, and is V1 in the time period when the third duration is T, and V2 in the time period in which the fourth duration is T, that is, the signal that each time length T changes once and the period is 2T, each The voltage values after each change in the cycle are different.
  • the field effect transistor Q1101 may be an N-channel FET or a P-channel FET.
  • Figure 7a and Figure 7b only take the FET Q1101 as an N-channel FET, not as a pair. Limitations of the invention.
  • the field effect transistor Q1101 may be a Junction Field-Effect Transistor (JFET) or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Or a depletion MOSFET.
  • JFET Junction Field-Effect Transistor
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the resistance variable circuit 1 may further include a field effect transistor Q (1102+n), and the gate of the field effect transistor Q (1102+n) is connected to the power supply.
  • the drain of the FET Q (1102+n) is connected to the drain of the FET Q1101, and the source of the FET Q (1102+n) is connected to the source of the FET Q1101.
  • the field effect transistor Q (1102+n) and the field effect transistor Q1101 are both P-channel field effect transistors, or the field effect transistor Q (1102+n) and the field effect transistor Q1101 are both N-channel field effect transistors.
  • Fig. 7a is exemplified by the fact that the field effect transistor Q (1102+n) and the field effect transistor Q1101 are both N-channel field effect transistors, and are not intended to limit the invention.
  • the FET Q (1102+n) may be a JFET, an enhancement MOSFET, or a depletion MOSFET.
  • the resistance variable circuit 1 may further include a resistor R (1103+n), one end of the resistor R (1103+n) and the field effect transistor Q1101. The drain is connected, and the other end of the resistor (1103+n) is connected to the source of the field effect transistor Q1101.
  • the sampling clock generating circuit may further include a level adjusting circuit 4 corresponding to the first strobe switch K1102-K (1101+n). Each level adjusting circuit is connected to an input end of a corresponding first gate switch;
  • Each level adjusting circuit 4 is configured to provide a signal whose voltage value is constant and adjustable for the input ends of the respective first gate switches, and the voltage values of the signals provided by the respective level adjusting circuits 4 are different.
  • the constant voltage value and adjustable means that the voltage value of the signal usually remains at a constant value, but the value that remains unchanged can be adjusted.
  • the signal voltage value is adjusted from being held at V1 to being held at V2, V1 ⁇ V2.
  • the level adjustment circuit 4 adjusts the voltage value of the signal received by the input terminal of the corresponding first gate switch, the voltage value of the signal received by the gate of the field effect transistor Q1101 changes accordingly.
  • the FET Q1101 operates in the linear region, the voltage and drain current between the drain and the source of the FET Q1101 change and the rate of change is different. Between the drain and the source of the FET Q1101 The equivalent resistance changes, and the resistance value of the resistance variable circuit 1 changes.
  • the discharge rate of the capacitance C through the resistance variable circuit 1 is slower, and the output signal of the sampling clock generation circuit remains high. The longer the level of the level, the more the resistance value of the resistance variable circuit 1 changes, and the discharge rate of the capacitor C and the duration of the high level are sequentially changed.
  • the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment and correction. Since the duration of the high level is related to the resistance value of the resistance variable circuit, the relationship between the duration of the high level and the resistance of the variable resistance circuit is used (this is a prior art, here) No longer listed), even if the resistance of the resistance variable circuit is adjusted to a normal level, the adjustment accuracy of the high-level time is high, and the timing of the sampling point is high. The adjustment accuracy of the deviation can reach at least 100 femtoseconds.
  • the resistance value of the resistance variable circuit 1 is adjusted, and the resistance variable circuit 1 is adjusted.
  • the accuracy of the resistance adjustment is improved, so the adjustment precision of the sampling point timing deviation can further reach the femtosecond level, further improving the conversion precision of the ADC.
  • each level adjusting circuit 4 may include m resistors R41-R (40+m), m+1 second gate switches K(41+m)-K (41). +2*m), and the register IR, m ⁇ 2 and m is an integer.
  • Each of the second gating switches includes an input end, an output end, and a control end.
  • m resistors R41-R (41+m) are connected in series between the power source and the ground, each series contact is connected to the input end of a second gate switch, and the second gate switch to which each series contact is connected The inputs are different.
  • the output ends of the respective second strobe switches are respectively connected to the input ends of the first strobe switches corresponding to the level adjusting circuit 4, and the control terminals of the respective second strobe switches are respectively connected to the register IR.
  • the resistor R41-R (40+m) connected in series between the power source and the ground divides the power supply voltage into m+1 levels, and the voltages of the respective levels are different.
  • Each series of contacts is connected to an input of a second strobe switch, and the input terminals of the second strobe switches to which the respective series of contacts are connected are different, so each second strobe switch receives a signal of a different voltage .
  • the register IR to output different control signals
  • one of the second strobe switches K(41+m)-K(41+2*m) can be controlled to be turned on, and the contacts of the second strobe switch connected to be connected can be controlled.
  • the voltage is the voltage of the signal received at the input of the first gating switch, and the voltage value of the signal received at the input end of the first gating switch is changed by turning on the different second on switch.
  • the NOT circuit 2 can be an inverter, a NAND gate, or a NOR gate.
  • the non-gate circuit 2 is any one of an inverter, a NAND gate circuit, and a NOT gate circuit, its specific implementation circuit can have several implementation manners.
  • the non-gate circuit 2 is an inverter, There are at least the following implementations:
  • the inverter may include a field effect transistor Q211 and a field effect transistor Q212.
  • the gate of the FET Q211 and the gate of the FET Q212 are inputs of the non-gate circuit 2.
  • the drain of the FET Q211 and the drain of the FET Q212 are the output terminals of the non-gate circuit 2.
  • the source of the FET Q211 is the power supply terminal of the gate circuit 2, and the source of the FET Q212 is extremely non- The ground terminal of the gate circuit 2.
  • the field effect transistor Q211 is a P-channel enhancement type MOSFET, and the field effect transistor Q212 is an N-channel MOSFET; or, the field effect transistor Q211 is an N-channel MOSFET, and the field effect transistor Q212 is a P-channel MOSFET.
  • FIG. 10a is only an example in which the field effect transistor Q211 is a P-channel enhancement type MOSFET and the field effect transistor Q212 is an N-channel MOSFET, and is not intended to limit the present invention.
  • the inverter may include a bipolar transistor Q221 and a bipolar transistor Q222.
  • the base of the bipolar transistor Q221 and the base of the bipolar transistor Q222 are non-gate types.
  • the input terminal of the circuit 2, the emitter of the bipolar transistor Q221 and the emitter of the bipolar transistor Q222 are the output terminals of the non-gate circuit 2, and the collector of the bipolar transistor Q221 is the power terminal of the non-gate circuit 2, bipolar
  • the collector of the transistor Q222 is the ground of the non-gate circuit 2.
  • the bipolar transistor Q221 is an NPN bipolar transistor, and the bipolar transistor Q222 is a PNP bipolar transistor; or the bipolar transistor Q221 is a PNP bipolar transistor, and the bipolar transistor Q222 It is an NPN type bipolar transistor.
  • 10b is only an example in which the bipolar transistor Q221 is an NPN bipolar transistor and the bipolar transistor Q222 is a PNP bipolar transistor, and is not intended to limit the present invention.
  • the inverter may include a field effect transistor Q231 and a resistor R232.
  • the gate of the field effect transistor Q231 is an input terminal of the non-gate circuit 2, and the drain of the field effect transistor Q231 is non-
  • the output of the gate circuit 2 the source of the FET Q231 is the ground terminal of the gate circuit 2, the drain of the FET Q231 is connected to one end of the resistor R232, and the other end of the resistor R232 is the power terminal of the non-gate circuit 2.
  • the field effect transistor Q231 is an enhancement type MOSFET.
  • the field effect transistor Q231 may be an N-channel field effect transistor or a P-channel field effect transistor.
  • Fig. 10c is only an example of the field effect transistor Q231 being an N-channel field effect transistor, and is not intended to limit the invention.
  • the inverter may include a field effect transistor Q241 and a resistor R242.
  • the gate of the field effect transistor Q241 is an input terminal of the non-gate circuit 2, and the source of the field effect transistor Q241 is extremely non-
  • the output terminal of the gate circuit 2 the drain of the field effect transistor Q241 is the power supply terminal of the non-gate circuit 2
  • the source of the field effect transistor Q241 is connected to one end of the resistor R242, and the other end of the resistor R242 is the ground terminal of the non-gate circuit 2.
  • the field effect transistor Q241 is an enhancement type MOSFET.
  • the field effect transistor Q241 may be a P-channel field effect transistor or an N-channel field effect transistor.
  • Fig. 10d is exemplified by the fact that the field effect transistor Q241 is a P-channel field effect transistor, and is not intended to limit the invention.
  • the NAND gate circuit can adopt the following implementation manner:
  • the NAND gate circuit may include a field effect transistor Q251, a field effect transistor Q252, a field effect transistor Q253, and a field effect transistor Q254, a gate of the field effect transistor Q251, a gate of the field effect transistor Q252, and a field effect transistor Q253.
  • the gate of the gate and FET Q254 is the input terminal of the non-gate circuit 2.
  • the drain of the FET Q251, the drain of the FET Q252, and the drain of the FET Q253 are all non-gate circuits 2
  • the output terminal, the source of the FET Q251 and the source of the FET Q252 are the power terminals of the non-gate circuit 2
  • the source of the FET Q253 is connected to the drain of the FET Q254, and the field effect transistor Q254 The source is very far from the ground of the gate circuit 2.
  • the field effect transistor Q251 and the field effect transistor Q252 are both P channel field effect transistors, and the field effect transistor Q253 and the field effect transistor Q254 are both N channel field effect transistors; or, the field effect transistor Q251 and the field effect transistor Q252 are both N-channel FET, and FET Q253 and FET Q254 are P-channel FETs.
  • Figure 10e is only a P-channel field with FET Q251 and FET Q252
  • the effect tube, the field effect transistor Q253, and the field effect transistor Q254 are all examples of an N-channel field effect transistor, and are not intended to limit the present invention.
  • the non-gate circuit 2 is a NOR circuit
  • the NOR circuit can adopt the following implementation manner:
  • the NOR circuit may include a FET Q261, a FET Q262, and a resistor R263.
  • the gate of the FET Q261 and the gate of the FET Q262 are inputs of the non-gate circuit 2
  • the drain of the effect transistor Q261 and the drain of the FET Q262 are the output terminals of the non-gate circuit 2
  • the source of the FET Q261 and the source of the FET Q262 are the power terminals of the non-gate circuit 2
  • the resistor One end of the R263 is the ground terminal of the non-gate circuit 2, and the other end of the resistor R263 is connected to the drain of the field effect transistor Q261 and the drain of the field effect transistor Q262, respectively.
  • the field effect transistor Q261 and the field effect transistor Q262 are both N-channel field effect transistors; or, the field effect transistor Q261 and the field effect transistor Q262 are both P-channel field effect transistors.
  • FIG. 10f is exemplified by the fact that both the field effect transistor Q261 and the field effect transistor Q262 are N-channel field effect transistors, and are not intended to limit the present invention.
  • the non-gate circuit 2 uses an inverter, which requires less devices, occupies less space, and lowers cost than a NAND gate circuit or a NAND gate circuit.
  • the device implements the non-gate circuit 2.
  • the first implementation is compared with the other three implementations, and since only the FET is used, no resistance is involved, so integration and stability are achieved. Both are better and are the best implementation.
  • the level of the pulse signal and the resistance value of the resistance variable circuit 1 do not change at the same time.
  • the timing of the pulse signal and the resistance timing of the variable resistance circuit 1 can be adjusted to achieve non-simultaneous changes of the two, such as direct control of the pulse signal output by the pulse signal generator at a desired timing. Or use an inverter or other device to delay the pulse signal.
  • the level of the pulse signal and the resistance value of the resistance change circuit do not change at the same time, so when the pulse signal changes from low level to high level, the resistance value of the resistance change circuit is fixed, and the resistance value changes.
  • the voltage across the circuit is stable, improving the stability of the sampling clock generation circuit.
  • the voltage of the power source is positive or negative, and the type of each field effect transistor or bipolar transistor (such as N-channel or P-channel, JFET or enhanced MOSFET or depletion MOSFET, PNP type or NPN type) needs to cooperate with each other as long as the desired effect is achieved.
  • the type of each field effect transistor or bipolar transistor such as N-channel or P-channel, JFET or enhanced MOSFET or depletion MOSFET, PNP type or NPN type
  • the RC circuit is formed by the resistance variable circuit, the non-gate circuit and the capacitor.
  • the capacitor is discharged through the RC circuit, so that the resistance variable circuit and the non-gate circuit
  • the level of the output signal of the sampling clock generating circuit composed of the capacitor and the capacitor does not change from the high level to the low level immediately after the level change of the pulse signal, but remains high for a period of time and then becomes Low level. If the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment.
  • the duration of the high level is related to the resistance value of the variable resistance circuit, the relationship between the duration of the high level and the resistance of the variable resistance circuit is maintained, even if the resistance of the variable resistance circuit is
  • the adjustment precision of the value size only reaches the general level, and the adjustment precision of the high-level time is also high.
  • the adjustment precision of the sampling point timing deviation can reach the hundred femtosecond level, thereby effectively correcting the sampling point timing deviation and avoiding the modulus. Harmonics appear in the converted signal to improve SFDR and improve the conversion accuracy of the ADC.
  • the embodiment of the present invention provides a sampling clock generating circuit, which is different from the second embodiment in that the resistance variable circuit of the embodiment is implemented by using a corresponding resistance and a gate switch, and each resistor corresponds to each other.
  • the branches of the strobe switches in series are connected in parallel.
  • the resistance variable circuit 1 may include n resistors R1201-R (1200+n) and n third selections corresponding to the one resistor R1201-R(1200+n).
  • the switch K (1201+n)-K (1200+2*n) has different resistance values, and each of the third gate switches includes an input end, an output end and a control end.
  • Each of the resistors is connected in parallel with a branch of the respective third gate switch in parallel between the ground terminal of the non-gate circuit 2 and the ground.
  • each of the third gating switches respectively receive a signal with a period of n*T, and in each period n*T, the period is n*T
  • the signal is only the first level in a period of time T, and the second level in the remaining time period, and the time period of the signal received by the control end of each third strobe switch is the first level does not coincide. .
  • the input end of the third gating switch when the signal received by the control terminal of the third gating switch is at the first level, the input end of the third gating switch is in communication with the output end of the third gating switch; when the control end of the third gating switch receives When the signal is at the second level, the input of the third strobe switch is disconnected from the output of the third strobe switch.
  • the first level is a high level
  • the second level is a low level
  • the first level is a low level
  • the second level is a high level
  • the RC circuit is formed by the resistance variable circuit, the non-gate circuit and the capacitor.
  • the capacitor is discharged through the RC circuit, so that the resistance variable circuit and the non-gate circuit
  • the level of the output signal of the sampling clock generating circuit composed of the capacitor and the capacitor does not change from the high level to the low level immediately after the level change of the pulse signal, but remains high for a period of time and then becomes Low level. If the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment.
  • the duration of the high level is related to the resistance value of the variable resistance circuit, the relationship between the duration of the high level and the resistance of the variable resistance circuit is maintained, even if the resistance of the variable resistance circuit is
  • the adjustment precision of the value size only reaches the general level, and the adjustment precision of the high-level time is also high.
  • the adjustment precision of the sampling point timing deviation can reach the hundred femtosecond level, thereby effectively correcting the sampling point timing deviation and avoiding the modulus. Harmonics appear in the converted signal to improve SFDR and improve the conversion accuracy of the ADC.
  • the embodiment of the present invention provides a sampling clock generating circuit, which is different from the second embodiment in that the resistance variable circuit of the embodiment is implemented by using a corresponding resistance and a gate switch, and each resistor corresponds to each other.
  • the branches of the strobe switches in parallel are connected in series.
  • the resistance variable circuit 1 may include n resistors R1301-R (1300+n) and n fourth selections one-to-one corresponding to the n resistors R1301-R(1300+n) Switch K(1301+n)-K(1300+2*n), the resistance values of the respective resistors are different, and each of the fourth gate switches includes an input end, an output end, and a control end.
  • a branch formed by each resistor in parallel with a corresponding fourth gate switch is connected in series between the ground terminal of the non-gate circuit 2 and the ground.
  • the control ends of the fourth strobe switches respectively receive a signal with a period of n*T.
  • each period n*T the signal with the period of n*T is only in the second period of time T.
  • the level is the first level in the remaining time period, and the time period in which the signal received by the control end of each fourth gate switch is the second level does not coincide.
  • the input end of the fourth gating switch when the signal received by the control terminal of the fourth gating switch is at the first level, the input end of the fourth gating switch is in communication with the output end of the fourth gating switch; when the control end of the fourth gating switch receives When the signal is at the second level, the input of the fourth strobe switch is disconnected from the output of the fourth strobe switch.
  • the first level is a high level
  • the second level is a low level
  • the first level is a low level
  • the second level is a high level
  • the RC circuit is formed by the resistance variable circuit, the non-gate circuit and the capacitor.
  • the capacitor is discharged through the RC circuit, so that the resistance variable circuit and the non-gate circuit
  • the level of the output signal of the sampling clock generating circuit composed of the capacitor and the capacitor does not change from the high level to the low level immediately after the level change of the pulse signal, but remains high for a period of time and then becomes Low level. If the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment.
  • the duration of the high level is related to the resistance value of the variable resistance circuit, the relationship between the duration of the high level and the resistance of the variable resistance circuit is maintained, even if the resistance of the variable resistance circuit is
  • the adjustment precision of the value size only reaches the general level, and the adjustment precision of the high-level time is also high.
  • the adjustment precision of the sampling point timing deviation can reach the hundred femtosecond level, thereby effectively correcting the sampling point timing deviation and avoiding the modulus. Harmonics appear in the converted signal to improve SFDR and improve the conversion accuracy of the ADC.
  • An embodiment of the present invention provides an ADC.
  • the ADC includes an n-chip ADC chip. IC100-IC (n*100), sampling clock generation circuit (n+1)*100 and mixer (n+2)*100, sampling clock generation circuit (n+1)*100 and mixer (n+2) *100 connection, mixer (n+2)*100 is connected to n chip ADC chip IC100-IC (n*100).
  • sampling clock generating circuit (n+1)*100 may be the same as the sampling clock generating circuit provided in any one of Embodiments 1 to 4.
  • the mixer (n+2)*100 is used to generate a sampling signal with an n-channel period of n*T.
  • the level of the i-th sampling signal is at the (i-1)th duration. It is the same as the output signal of the sampling clock generation circuit (n+1)*100 for the time period of T, and is low for the rest of the time period, and the i-th ADC chip uses the i-th sampling signal as the sampling clock.
  • the mixer generates two sampling signals with a period of 2T.
  • the level of the first sampling signal is the first in each period of 2T.
  • the output signal of the sampling clock generation circuit (n+1)*100 (the input signal of the mixer (n+2)*100) is the same as the period of time T, and the low level in the remaining time period, the second way
  • the level of the sampling clock signal is the same as the output signal of the sampling clock generating circuit (n+1)*100 (the input signal of the mixer (n+2)*100) during the second period of time T, and the rest of the time The segment is low.
  • the RC circuit is formed by the resistance variable circuit, the non-gate circuit and the capacitor.
  • the capacitor is discharged through the RC circuit, so that the resistance variable circuit and the non-gate circuit.
  • the level of the output signal of the sampling clock generating circuit composed of the capacitor and the level of the pulse signal does not change from the high level to the low level immediately, but remains high. After a while, it goes low again. If the sampling point timing offset canceling logic circuit or other circuit caused by the duration of the high level is divided into the sampling point timing deviation generated by the sampling path generating circuit, the sampling point timing deviation can be performed. Adjustment.
  • the duration of the high level is related to the resistance value of the variable resistance circuit, the relationship between the duration of the high level and the resistance of the variable resistance circuit is maintained, even if the resistance of the variable resistance circuit is
  • the adjustment precision of the value size only reaches the general level, and the adjustment precision of the high-level time is also high.
  • the adjustment precision of the sampling point timing deviation can reach the hundred femtosecond level, thereby effectively correcting the sampling point timing deviation and avoiding the modulus. Harmonics appear in the converted signal to improve SFDR and improve the conversion accuracy of the ADC.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

本发明公开了一种采样时钟产生电路及模数转换器，属于数字信号处理领域。所述采样时钟产生电路包括阻值可变电路、非门类电路、以及电容，非门类电路的输入端接收周期为T的脉冲信号，非门类电路的输出端与电容的一端连接，电容的另一端接地，非门类电路的电源端接电源，非门类电路的接地端与阻值可变电路的一端连接，阻值可变电路的另一端接地；非门类电路，用于当脉冲信号为高电平时，输出低电平；当脉冲信号为低电平时，输出高电平；阻值可变电路，用于阻值每隔时长T变化一次，阻值的变化以n*T为周期，每个周期内各次变化后的阻值各不相同，n≥2且n为整数。本发明提高了ADC的转换精度。

Description

一种采样时钟产生电路及模数转换器 技术领域
本发明涉及数字信号处理领域，特别涉及一种采样时钟产生电路及模数转换器。
背景技术
由于工艺和器件发展的限制，单片模数转换器(Analog to Digital Converter，简称ADC)芯片的采样频率还不能做的非常高，若要达到更高的采样频率，可以利用多片ADC芯片在不同相位的采样时钟驱动下交错采样实现。
其中，不同相位的采样时钟通常采用如下方案实现：逻辑电路将时钟源信号分成n路，得到n路频率等于时钟源信号频率/n且相位各不相同的信号，n≥2且n为整数；分别在n路信号的传输信道中串联不同数量的反相器进行延时，得到n路采样时钟，在n路采样时钟驱动下交错采样的采样点与在时钟源信号驱动下采样的采样点相同。
在实现本发明的过程中，发明人发现现有技术至少存在以下问题：
基于工艺的限制，逻辑电路中各个器件的特性不能达到理论特性，导致通过逻辑电路得到的n路采样时钟的采样点，与时钟源信号的采样点之间存在皮秒(ps)级的时序偏差。由于在传输信道中串联反相器进行的延时只能低至20ps，无法对采样点时序偏差进行有效调整，导致多片ADC在n路采样时钟驱动下的交错采样为非均匀采样，模数转换后的信号中出现谐波，降低了ADC的转换精度。
发明内容
为了解决现有技术无法对采样点时序偏差进行有效调整、降低了ADC的 转换精度的问题，本发明实施例提供了一种采样时钟产生电路及模数转换器。所述技术方案如下：
一方面，本发明实施例提供了一种采样时钟产生电路，所述采样时钟产生电路包括阻值可变电路、非门类电路、以及电容，所述非门类电路包括输入端、输出端、电源端和接地端，所述非门类电路的输入端接收周期为T的脉冲信号，所述非门类电路的输出端与所述电容的一端连接，所述电容的另一端接地，所述非门类电路的电源端接电源，所述非门类电路的接地端与所述阻值可变电路的一端连接，所述阻值可变电路的另一端接地；
所述非门类电路，用于当所述脉冲信号为高电平时，输出低电平；当所述脉冲信号为低电平时，输出高电平；
所述阻值可变电路，用于阻值每隔时长T变化一次，所述阻值的变化以n*T为周期，每个周期内各次变化后的所述阻值各不相同，n≥2且n为整数。
在本发明一种可能的实现方式中，所述阻值可变电路包括场效应管Q1101和n个第一选通开关K1102-K(1101+n)，每个所述第一选通开关均包括输入端、输出端和控制端，所述场效应管Q1101的漏极与所述非门类电路的接地端连接，所述场效应管Q1101的源极接地，所述场效应管Q1101的栅极分别与各个所述第一选通开关的输出端连接，各个所述第一选通开关的输入端分别接收一个电压值恒定的信号，且各个所述第一选通开关的输入端接收的信号的电压值各不相同，各个所述第一选通开关的控制端分别接收一个周期为n*T的信号，在每个周期n*T内，所述周期为n*T的信号只在一个时长为T的时间段内为第一电平，其余时间段内均为第二电平，且各个所述选通开关的控制端接收的信号为所述第一电平的时间段不重合；
其中，当所述第一选通开关的控制端接收的信号为所述第一电平时，所述第一选通开关的输入端与所述第一选通开关的输出端连通；当所述第一选通开关的控制端接收的信号为所述第二电平时，所述第一选通开关的输入端与所述第一选通开关的输出端断开。
可选地，所述场效应管Q1101为结型场效应晶体管JFET、增强型金属-氧化物半导体场效应晶体管MOSFET、或者耗尽型MOSFET。
可选地，所述阻值可变电路还包括场效应管Q(1102+n)，所述场效应管Q(1102+n)的栅极接电源，所述场效应管Q(1102+n)的漏极与所述场效应管Q1101的漏极连接，所述场效应管Q(1102+n)的源极与所述场效应管Q1101的源极连接；
其中，所述场效应管Q(1102+n)和所述场效应管Q1101均为P沟道场效应管，或者，所述场效应管Q(1102+n)和所述场效应管Q1101均为N沟道场效应管。
具体地，所述场效应管Q(1102+n)为JFET、增强型MOSFET或者耗尽型MOSFET。
可选地，所述阻值可变电路还包括电阻R(1103+n)，所述电阻R(1103+n)的一端与所述场效应管Q1101的漏极连接，所述电阻(1103+n)的另一端与所述场效应管Q1101的源极连接。
可选地，所述采样时钟产生电路还包括与所述第一选通开关K1102-K(1101+n)一一对应的电平调整电路，各个所述电平调整电路与各自对应的所述第一选通开关的输入端连接；
各个所述电平调整电路，用于为各自对应的所述第一选通开关的输入端提供一个电压值恒定且可调的信号，且各个所述电平调整电路提供的信号的电压值各不相同。
具体地，各个所述电平调整电路均包括m个电阻R41-R(40+m)、m+1个第二选通开关K(41+m)-K(41+2*m)、以及寄存器IR，m≥2且m为整数，每个所述第二选通开关均包括输入端、输出端和控制端，m个所述电阻R41-R(41+m)串联在电源与地之间，每个串联的接点与一个所述第二选通开关的输入端连接，且各个所述串联的接点所连接的所述第二选通开关的输入端各不相同，各个所述第二选通开关的输出端分别与所述电平调整电路对应的 所述第一选通开关的输入端连接，各个所述第二选通开关的控制端分别与所述寄存器IR连接。
在本发明另一种可能的实现方式中，所述非门类电路为反相器、与非门电路或者或非门电路。
可选地，所述反相器包括场效应管Q211和场效应管Q212，所述场效应管Q211的栅极与所述场效应管Q212的栅极均为所述非门类电路的输入端，所述场效应管Q211的漏极和所述场效应管Q212的漏极均为所述非门类电路的输出端，所述场效应管Q211的源极为所述非门类电路的电源端，所述场效应管Q212的源极为所述非门类电路的接地端；
其中，所述场效应管Q211为P沟道增强型金属-氧化物半导体场效应晶体管MOSFET，且所述场效应管Q212为N沟道MOSFET；或者，所述场效应管Q211为N沟道MOSFET，且所述场效应管Q212为P沟道MOSFET。
在本发明又一种可能的实现方式中，所述脉冲信号的电平与所述阻值可变电路的阻值非同时变化。
另一方面，本发明实施例提供了一种模数转换器ADC，所述ADC包括n片ADC芯片，所述ADC还包括采样时钟产生电路和混合器，所述采样时钟产生电路与所述混合器连接，所述混合器分别与所述n片ADC芯片连接；
所述采样时钟产生电路包括阻值可变电路、非门类电路、以及电容，所述非门类电路包括输入端、输出端、电源端和接地端，所述非门类电路的输入端接收周期为T的脉冲信号，所述非门类电路的输出端与所述电容的一端连接，所述电容的另一端接地，所述非门类电路的电源端接电源，所述非门类电路的接地端与所述阻值可变电路的一端连接，所述阻值可变电路的另一端接地；
所述非门类电路，用于当所述脉冲信号为高电平时，输出低电平；当所述脉冲信号为低电平时，输出高电平；
所述阻值可变电路，用于阻值每隔时长T变化一次，所述阻值的变化以 n*T为周期，每个周期内各次变化后的所述阻值各不相同，n≥2且n为整数；
所述混合器，用于产生n路周期为n*T的采样信号，在每个周期n*T内，第i路采样信号的电平在第(i-1)个时长为T的时间段内与所述采样时钟产生电路的输出信号相同，其余时间段内为低电平，第i片ADC芯片采用第i路采样信号作为采样时钟。
本发明实施例提供的技术方案带来的有益效果是：
通过阻值可变电路、非门类电路和电容形成RC电路，当脉冲信号从低电平变为高电平时，电容通过该RC电路放电，使得阻值可变电路、非门类电路和电容组成的采样时钟产生电路的输出信号的电平由于放电作用，没有随脉冲信号的电平变化立即从高电平变为低电平，而是保持为高电平一段时间后再变为低电平。若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整。由于保持为高电平的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序偏差的调整精度可以达到百飞秒级，从而对采样点时序偏差进行有效校正，避免模数转换后的信号中出现谐波，提升无杂散动态范围(Spurious Free Dynamic Range，简称SFDR，载波频率的均方根值与次最大噪声成分或谐波失真成分的均方根值之比)，提高了ADC的转换精度。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的多片ADC芯片并行采样电路的结构示意图；
图2是本发明实施例提供的多片ADC芯片并行采样的波形示意图；
图3是本发明实施例一提供的一种采样时钟产生电路的结构示意图；
图4是本发明实施例一提供的非门类电路输入信号与输出信号的波形示意图；
图5是本发明实施例一提供的阻值可变电路阻值变化的示意图；
图6是本发明实施例一提供的采样时钟产生电路工作过程的波形示意图；
图7a-图7b是本发明实施例二提供的一种采样时钟产生电路的结构示意图；
图8是本发明实施例二提供的各个第一选通开关各端点的波形示意图；
图9是本发明实施例二提供的电平调整电路的结构示意图；
图10a-图10f是本发明实施例二提供的非门类电路的结构示意图；
图11是本发明实施例二提供的脉冲信号与阻值可变电路阻值的变化示意图；
图12是本发明实施例三提供的一种采样时钟产生电路的结构示意图；
图13是本发明实施例四提供的一种采样时钟产生电路的结构示意图；
图14是本发明实施例五提供的一种模数转换器的结构示意图；
图15是本发明实施例五提供的混合器的输入信号、及理论和实际两种情况下的输出信号的波形示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
下面先结合图1和图2简单介绍一下本发明实施例提供的采样时钟产生电路的应用场景，图1和图2分别为多片ADC芯片并行采样的电路结构示意图和波形示意图，从图1可以看出，采样时钟产生电路分别与ADC1、ADC2、 ADC3、ADC4四片ADC芯片连接，以分别为ADC1、ADC2、ADC3、ADC4四片ADC芯片提供采样时钟，ADC1、ADC2、ADC3、ADC4四片ADC芯片分别在采样时钟的驱动下对输入信号进行采样，ADC1、ADC2、ADC3、ADC4四片ADC芯片采样得到的信号组成了输出信号。如图2所示，采样时钟产生电路为ADC1、ADC2、ADC3、ADC4四片ADC芯片提供的采样时钟的频率相同且相位各不相同，从而使得ADC1、ADC2、ADC3、ADC4在时序上周期性地依次对输入信号采样，得到与采样时钟的频率*4倍的采样频率进行采样的效果。
需要说明的是，上述ADC芯片的数量、多片ADC芯片并行采样的电路及其呈现的波形仅为举例，本发明并不限制于此。
实施例一
本发明实施例提供了一种采样时钟产生电路，参见图3，该采样时钟产生电路包括阻值可变电路1、非门类电路2、以及电容C，非门类电路2包括输入端、输出端、电源端和接地端，非门类电路2的输入端接收周期为T的脉冲信号，非门类电路2的输出端为采样时钟产生电路的输出端，非门类电路2的输出端与电容C的一端连接，电容C的另一端接地，非门类电路2的电源端接电源，非门类电路2的接地端与阻值可变电路1的一端连接，阻值可变电路1的另一端接地。
其中，参见图4，非门类电路2用于，当脉冲信号为高电平(即非门类电路的输入信号为高电平)时，输出低电平(即非门类电路的输出信号为低电平)；当脉冲信号为低电平(即非门类电路的输入信号为低电平)时，输出高电平(即非门类电路的输出信号为高电平)。
阻值可变电路1用于，阻值每隔时长T变化一次，阻值的变化以n*T为周期，每个周期内各次变化后的阻值各不相同，n≥2且n为整数。例如，当n＝2时，如图5所示，阻值可变电路的阻值在第一个时长T内为R1，在第二 个时长T内为R2，在第三个时长T内又为R1，在第四个时长T内又为R2，R1≠R2，也就是说，阻值每隔时长T变化一次，阻值的变化以2T为周期，在每个周期的开始，阻值是从R2变为的R1，经过一个时长T，阻值从R1变为R2，再经过一个时长T，达到一个周期的结束和另一个周期的开始，阻值又从R2变为R1，即每个周期内各次变化后的阻值各不相同。
具体地，n等于并行采样的ADC芯片的片数。以图1来说，并行采样的ADC芯片有ADC1、ADC2、ADC3、ADC4四片，此时n＝4。
需要说明的是，高电平和低电平是电工程上的一种说法，高电平是与低电平相对的高电压。具体来说，高电平为保证逻辑门的输入(或输出)为1时所允许的输入(或输出)电平，低电平为保证逻辑门的输入(或输出)为0时所允许的输入(或输出)电平。例如，对于电压值的变化范围为0-5V的信号，电压值为0-0.25V时，逻辑门为1，电平为高电平，电压值为3.5-5V时，逻辑门为0，电平为低电平。
下面结合图6简单介绍一下本发明实施例提供的采样时钟产生电路的工作原理：
参见图3，当脉冲信号从高电平变为低电平时，非门类电路2的输出信号为高电平，非门类电路2的输出信号(高电平)分为两路，一路为电容C充电，另一路作为采样时钟产生电路的输出信号输出，即采样时钟产生电路的输出信号为高电平。例如，如图6所示(图6对应n＝2的情况)，对应脉冲信号为低电平的采样时钟产生电路的输出信号为高电平。
当脉冲信号从低电平变为高电平时，非门类电路2的输出信号为低电平，此时电容C、非门类电路2、阻值可变电路1组成RC放电电路，电容C之前(脉冲信号为低电平时)充入的电量通过阻值可变电路1释放，采样时钟产生电路的输出信号(非门类电路2的输出端为采样时钟产生电路的输出端)不会立即变为低电平，而是先保持一段时间的高电平，当电容C的电量释放到一定程度时，再变为低电平。例如，如图6所示(图6对应n＝2的情况)， 对应脉冲信号为高电平的采样时钟产生电路的输出信号是先保持一段时间的高电平再变为低电平。
当脉冲信号再次从高电平变为低电平时，非门类电路2的输出信号又变为高电平，此时电容C充电，采样时钟产生电路的输出信号(非门类电路2的输出端为采样时钟产生电路的输出端)为高电平，如此循环，如图6所示。
其中，采样时钟产生电路的输出信号保持高电平的时长与电容C释放电量的快慢有关，容易知道，阻值可变电路1的阻值越大，电容C释放电量的速度越慢，采样时钟产生电路的输出信号保持高电平的时长越长。由于阻值可变电路1的阻值每隔时长T变化一次，阻值的变化以n*T为周期，每个周期内各次变化后的阻值各不相同，因此采样时钟产生电路的输出信号为周期为n*T的信号，在每个周期内，在各次脉冲信号(周期为T)从低电平变为高电平之后，采样时钟产生电路的输出信号保持为高电平的时长各不相同。例如，当n＝2时，如图6所示，采样时钟产生电路的输出信号为周期为2T的信号，在一个周期2T的第一个时长T内，在脉冲信号从低电平变为高电平之后，采样时钟产生电路的输出信号保持为高电平的时长为T1，在一个周期2T的第二个时长T内，在脉冲信号从低电平变为高电平之后，采样时钟产生电路的输出信号保持为高电平的时长为T2，T1≠T2，即在每个周期内，在各次脉冲信号(周期为T)从低电平变为高电平之后，采样时钟产生电路的输出信号保持为高电平的时长各不相同。
本发明实施例通过阻值可变电路、非门类电路和电容形成RC电路，当脉冲信号从低电平变为高电平时，电容通过该RC电路放电，使得阻值可变电路、非门类电路和电容组成的采样时钟产生电路的输出信号的电平由于放电作用，没有随脉冲信号的电平变化立即从高电平变为低电平，而是保持为高电平一段时间后再变为低电平。若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整。由于保持为高电平 的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序偏差的调整精度可以达到百飞秒级，从而对采样点时序偏差进行有效校正，避免模数转换后的信号中出现谐波，提升无杂散动态范围(Spurious Free Dynamic Range，简称SFDR，载波频率的均方根值与次最大噪声成分或谐波失真成分的均方根值之比)，提高了ADC的转换精度。
实施例二
本发明实施例提供了一种采样时钟产生电路，本实施例的阻值可变电路具体采用场效应管和选通开关实现，参见图7a或图7b，该采样时钟产生电路包括阻值可变电路1、非门类电路2、以及电容C，非门类电路2包括输入端、输出端、电源端和接地端，非门类电路2的输入端接收周期为T的脉冲信号，非门类电路2的输出端为采样时钟产生电路的输出端，非门类电路2的输出端与电容C的一端连接，电容C的另一端接地，非门类电路2的电源端接电源，非门类电路2的接地端与阻值可变电路1的一端连接，阻值可变电路1的另一端接地。
其中，非门类电路2用于，当脉冲信号为高电平时，输出低电平；当脉冲信号为低电平时，输出高电平(如图4所示)。
阻值可变电路1用于，阻值每隔时长T变化一次，阻值的变化以n*T为周期，每个周期内各次变化后的阻值各不相同，n≥2且n为整数(如图5所示)。
在本实施例中，阻值可变电路1可以包括场效应管Q1101和n个第一选通开关K1102-K(1101+n)，每个第一选通开关均包括输入端、输出端和控制端。
场效应管Q1101的漏极与非门类电路2的接地端连接，场效应管Q1101的源极接地，场效应管Q1101的栅极分别与各个第一选通开关的输出端连接。
各个第一选通开关的输入端分别接收一个电压值恒定的信号，且各个第一选通开关的输入端接收的信号的电压值各不相同。例如，当n＝2时，如图8所示，第一选通开关K1102的输入端接收一个电压值恒为V1的信号，第一选通开关K1103的输入端接收一个电压值恒为V2的信号，V1≠V2。
各个第一选通开关的控制端分别接收一个周期为n*T的信号，在每个周期n*T内，周期为n*T的信号只在一个时长为T的时间段内为第一电平，其余时间段内均为第二电平，且各个第一选通开关的控制端接收的信号为第一电平的时间段不重合。例如，当n＝2时，如图8所示，第一选通开关K1102的控制端接收一个周期为2T且在每个周期的第一个时长为T的时间段内为高电平(第一电平)的信号，第二选通开关K1103的控制端接收一个周期为2T且在每个周期的第二个时长为T的时间段内为高电平(第一电平)的信号。
其中，当第一选通开关的控制端接收的信号为第一电平时，第一选通开关的输入端与第一选通开关的输出端连通；当第一选通开关的控制端接收的信号为第二电平时，第一选通开关的输入端与第一选通开关的输出端断开。
具体地，第一电平为高电平，第二电平为低电平；或者，第一电平为低电平，第二电平为高电平。图8仅以第一电平为高电平、第二电平为低电平为例进行说明，并不作为对本发明的限制。
可以理解地，场效应管Q1101的栅极接收到的信号为一个电压值每隔时长T变化一次且周期为n*T的信号，每个周期内各次变化后的电压值各不相同。例如，当n＝2时，以图8为例，场效应管Q1101的栅极接收到的信号电压值在第一个时长为T的时间段内为V1，在第二时长为T的时间段内为V2，在第三个时长为T的时间段内又为V1，在第四个时长为T的时间段内又为V2，即每个时长T变化一次且周期为2T的信号，每个周期内各次变化后的电压值各不相同。
具体地，场效应管Q1101可以为N沟道场效应管，也可以P沟道场效应管。图7a和图7b仅以场效应管Q1101为N沟道场效应管为例，并不作为对 本发明的限制。
可选地，场效应管Q1101可以为结型场效应晶体管(Junction Field-Effect Transistor，简称JFET)、增强型金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)、或者耗尽型MOSFET。
在本实施例的一种实现方式中，如图7a所示，阻值可变电路1还可以包括场效应管Q(1102+n)，场效应管Q(1102+n)的栅极接电源，场效应管Q(1102+n)的漏极与场效应管Q1101的漏极连接，场效应管Q(1102+n)的源极与场效应管Q1101的源极连接。
其中，场效应管Q(1102+n)和场效应管Q1101均为P沟道场效应管，或者，场效应管Q(1102+n)和场效应管Q1101均为N沟道场效应管。图7a仅以场效应管Q(1102+n)和场效应管Q1101均为N沟道场效应管为例，并不作为对本发明的限制。
可选地，场效应管Q(1102+n)可以为JFET、增强型MOSFET或者耗尽型MOSFET。
在本实施例的另一种实现方式中，如图7b所示，阻值可变电路1还可以包括电阻R(1103+n)，电阻R(1103+n)的一端与场效应管Q1101的漏极连接，电阻(1103+n)的另一端与场效应管Q1101的源极连接。
容易知道，无论是场效应管Q(1102+n)，还是电阻R(1103+n)，都是或相当于是在场效应管Q1101的漏极与源极之间并联了一个电阻，可以减小场效应管Q1101的漏极与源极之间的等效电阻的变化幅度，从而减小阻值可变电路1的阻值变化幅度。例如，在并联电阻之前，场效应管Q1101的漏极与源极之间的等效电阻阻值从r增大为2*r时，阻值可变电路1的阻值变化幅度为2*r-r＝r；在并联阻值为r的电阻之后，场效应管Q1101的漏极与源极之间的等效电阻阻值从r增大为2*r时，阻值可变电路1的阻值变化幅度为1/(1/(2*r)+1/r)-1/(1/r+1/r)＝2*r/3-r/2＝r/6，r/6明显小于r，因此采用上述两种实现方 式中的任意一种，都可以减小阻值可变电路1的阻值变化幅度，实现更精细地调整。
在本实施例的又一种实现方式中，参见图7a或图7b，该采样时钟产生电路还可以包括与第一选通开关K1102-K(1101+n)一一对应的电平调整电路4，各个电平调整电路与各自对应的第一选通开关的输入端连接；
各个电平调整电路4，用于为各自对应的第一选通开关的输入端提供一个电压值恒定且可调的信号，且各个电平调整电路4提供的信号的电压值各不相同。
其中，电压值恒定且可调是指信号的电压值通常保持为一个值不变，但这个保持不变的值是可以调整的。例如，将信号电压值从保持为V1调整为保持为V2，V1≠V2。
可以理解地，当电平调整电路4调整对应的第一选通开关的输入端接收的信号的电压值时，场效应管Q1101的栅极接收到的信号的电压值随之发生改变。当场效应管Q1101工作在线性区时，场效应管Q1101的漏极和源极之间的电压和漏极电流均随之改变且改变速率不一样，场效应管Q1101的漏极和源极之间的等效电阻发生变化，阻值可变电路1的阻值发生变化。
由于阻值可变电路1的阻值越大，当脉冲信号从高电平变为低电平时，电容C通过阻值可变电路1放电速率越慢，采样时钟产生电路的输出信号保持为高电平的时长越长，因此当阻值可变电路1的阻值发生变化时，电容C的放电速率、保持为高电平的时长依次随之变化。
若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整和校正。由于保持为高电平的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式(此为现有技术，在此不再列举)，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序 偏差的调整精度至少可以达到百飞秒级。
同时由于直接利用对第一选通开关K1102-K(1101+n)的输入端接收的信号的电压值进行调整，对阻值可变电路1的阻值进行调整，对阻值可变电路1的阻值调整精度提高了，因此采样点时序偏差的调整精度可以进一步达到飞秒级，进一步提高了ADC的转换精度。
可选地，如图9所示，各个电平调整电路4均可以包括m个电阻R41-R(40+m)、m+1个第二选通开关K(41+m)-K(41+2*m)、以及寄存器IR，m≥2且m为整数。每个第二选通开关均包括输入端、输出端和控制端。m个电阻R41-R(41+m)串联在电源与地之间，每个串联的接点与一个第二选通开关的输入端连接，且各个串联的接点所连接的第二选通开关的输入端各不相同。各个第二选通开关的输出端分别与电平调整电路4对应的第一选通开关的输入端连接，各个第二选通开关的控制端分别与寄存器IR连接。
可以理解地，串联在电源与地之间的电阻R41-R(40+m)将电源电压分为m+1个等级，各个等级的电压各不相同。每个串联的接点与一个第二选通开关的输入端连接，且各个串联的接点所连接的第二选通开关的输入端各不相同，因此各个第二选通开关接收一个不同电压的信号。利用寄存器IR输出不同的控制信号，可以控制第二选通开关K(41+m)-K(41+2*m)中的一个接通，接通的第二选通开关所连接的接点的电压即为第一选通开关的输入端接收的信号的电压，通过接通不同的第二接通开关，改变第一选通开关的输入端接收的信号的电压值。
具体地，m的取值取决于对第一选通开关的输入端接收的信号的电压值的调整精度，如电源电压为5V，调整精度为1V，则电源电压分为5V、4V、3V、2V、1V、0V六个等级，即m＝5。
在具体实现中，非门类电路2可以为反相器、与非门电路或者或非门电路。当非门类电路2为反相器、与非门电路、非门电路中的任意一个时，其具体的实现电路都可以有几种实现方式。例如，当非门类电路2为反相器时， 可以至少有以下几种实现方式：
在第一种实现方式中，参见图10a，反相器可以包括场效应管Q211和场效应管Q212，场效应管Q211的栅极与场效应管Q212的栅极均为非门类电路2的输入端，场效应管Q211的漏极和场效应管Q212的漏极均为非门类电路2的输出端，场效应管Q211的源极为非门类电路2的电源端，场效应管Q212的源极为非门类电路2的接地端。
其中，场效应管Q211为P沟道增强型MOSFET，且场效应管Q212为N沟道MOSFET；或者，场效应管Q211为N沟道MOSFET，且场效应管Q212为P沟道MOSFET。图10a仅以场效应管Q211为P沟道增强型MOSFET、场效应管Q212为N沟道MOSFET为例，并不作为对本发明的限制。
在第二种实现方式中，参见图10b，反相器可以包括双极型晶体管Q221和双极型晶体管Q222，双极型晶体管Q221的基极和双极型晶体管Q222的基极均为非门类电路2的输入端，双极性晶体管Q221的发射极和双极型晶体管Q222的发射极为非门类电路2的输出端，双极型晶体管Q221的集电极为非门类电路2的电源端，双极型晶体管Q222的集电极为非门类电路2的接地端。
其中，双极型晶体管Q221为NPN型双极型晶体管，且双极型晶体管Q222为PNP型双极型晶体管；或者，双极性晶体管Q221为PNP型双极型晶体管，且双极型晶体管Q222为NPN型双极型晶体管。图10b仅以双极型晶体管Q221为NPN型双极型晶体管、双极型晶体管Q222为PNP型双极型晶体管为例，并不作为对本发明的限制。
在第三种实现方式中，如图10c所示，反相器可以包括场效应管Q231和电阻R232，场效应管Q231的栅极为非门类电路2的输入端，场效应管Q231的漏极为非门类电路2的输出端，场效应管Q231的源极为非门类电路2的接地端，场效应管Q231的漏极与电阻R232的一端连接，电阻R232的另一端为非门类电路2的电源端。
其中，场效应管Q231为增强型MOSFET。
具体地，场效应管Q231可以为N沟道场效应管，也可以为P沟道场效应管。图10c仅以场效应管Q231为N沟道场效应管为例，并不作为对本发明的限制。
在第四种实现方式中，如图10d所示，反相器可以包括场效应管Q241和电阻R242，场效应管Q241的栅极为非门类电路2的输入端，场效应管Q241的源极为非门类电路2的输出端，场效应管Q241的漏极为非门类电路2的电源端，场效应管Q241的源极与电阻R242的一端连接，电阻R242的另一端为非门类电路2的接地端。
其中，场效应管Q241为增强型MOSFET。
具体地，场效应管Q241可以为P沟道场效应管，也可以为N沟道场效应管。图10d仅以场效应管Q241为P沟道场效应管为例，并不作为对本发明的限制。
又如，当非门类电路2为与非门电路时，与非门电路可以采用如下实现方式：
参见图10e，与非门电路可以包括场效应管Q251、场效应管Q252、场效应管Q253和场效应管Q254，场效应管Q251的栅极、场效应管Q252的栅极、场效应管Q253的栅极和场效应管Q254的栅极均为非门类电路2的输入端，场效应管Q251的漏极、场效应管Q252的漏极和场效应管Q253的漏极均为非门类电路2的输出端，场效应管Q251的源极和场效应管Q252的源极均为非门类电路2的电源端，场效应管Q253的源极与场效应管Q254的漏极连接，场效应管Q254的源极为非门类电路2的接地端。
其中，场效应管Q251和场效应管Q252均为P沟道场效应管，且场效应管Q253和场效应管Q254均为N沟道场效应管；或者，场效应管Q251和场效应管Q252均为N沟道场效应管，且场效应管Q253和场效应管Q254均为P沟道场效应管。图10e仅以场效应管Q251和场效应管Q252均为P沟道场 效应管、场效应管Q253和场效应管Q254均为N沟道场效应管为例，并不作为对本发明的限制。
又如，当非门类电路2为或非门电路时，或非门电路可以采用如下实现方式：
参见图10f，或非门电路可以包括场效应管Q261、场效应管Q262、以及电阻R263，场效应管Q261的栅极和场效应管Q262的栅极均为非门类电路2的输入端，场效应管Q261的漏极和场效应管Q262的漏极均为非门类电路2的输出端，场效应管Q261的源极和场效应管Q262的源极均为非门类电路2的电源端，电阻R263的一端为非门类电路2的接地端，电阻R263的另一端分别与场效应管Q261的漏极、场效应管Q262的漏极连接。
其中，场效应管Q261和场效应管Q262均为N沟道场效应管；或者，场效应管Q261和场效应管Q262均为P沟道场效应管。图10f仅以场效应管Q261和场效应管Q262均为N沟道场效应管为例，并不作为对本发明的限制。
综合上述实现方式，非门类电路2采用反相器，比采用与非门电路或者或非门电路，所需的器件较少，占用的空间较少，成本也较低，因此通常优选采用反相器实现非门类电路2。具体地，在上述提供的四种实现反相器的电路中，第一种实现方式与其它三种实现方式相比，由于只采用了场效应管，不涉及到电阻，因此集成度和稳定度都较好，为最优的实现方式。
在本实施例的又一种实现方式中，参见图11，脉冲信号的电平与阻值可变电路1的阻值非同时变化。
在具体实现中，可以通过对脉冲信号的电平时序与阻值可变电路1的阻值时序进行调整实现两者的非同时变化，如直接控制脉冲信号发生器输出所需时序的脉冲信号，或者采用反相器或其它器件对脉冲信号进行延时。
容易知道，脉冲信号的电平与阻值变化电路的阻值非同时变化，如此在脉冲信号从低电平变为高电平时，阻值变化电路的阻值是固定不变的，阻值变化电路两端的电压是稳定的，提高了采样时钟产生电路的稳定性。
需要说明的是，本实施例中电源的电压正负、各个场效应管或双极型晶体管的型号(如N沟道或者P沟道、JFET或者增强型MOSFET或者耗尽型MOSFET、PNP型或者NPN型)需要相互配合，只要达到所需效果即可。
本发明实施例通过阻值可变电路、非门类电路和电容形成RC电路，当脉冲信号从低电平变为高电平时，电容通过该RC电路放电，使得阻值可变电路、非门类电路和电容组成的采样时钟产生电路的输出信号的电平由于放电作用，没有随脉冲信号的电平变化立即从高电平变为低电平，而是保持为高电平一段时间后再变为低电平。若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整。由于保持为高电平的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序偏差的调整精度可以达到百飞秒级，从而对采样点时序偏差进行有效校正，避免模数转换后的信号中出现谐波，提升SFDR，提高了ADC的转换精度。
实施例三
本发明实施例提供了一种采样时钟产生电路，与实施例二的不同之处在于，本实施例的阻值可变电路采用一一对应的电阻和选通开关实现，且各个电阻与各自对应的选通开关串联后的支路并联。
具体地，如图12所示，阻值可变电路1可以包括n个电阻R1201-R(1200+n)和与n个电阻R1201-R(1200+n)一一对应的n个第三选通开关K(1201+n)-K(1200+2*n)，各个电阻的阻值各不相同，每个第三选通开关均包括输入端、输出端和控制端。各个电阻分别与各自对应的第三选通开关串联组成的支路并联在非门类电路2的接地端与地之间。各个第三选通开关的控制端分别接收一个周期为n*T的信号，在每个周期n*T内，该周期为n*T的 信号只在一个时长为T的时间段内为第一电平，其余时间段内为第二电平，且各个第三选通开关的控制端接收的信号为第一电平的时间段不重合。
其中，当第三选通开关的控制端接收的信号为第一电平时，第三选通开关的输入端与第三选通开关的输出端连通；当第三选通开关的控制端接收的信号为第二电平时，第三选通开关的输入端与第三选通开关的输出端断开。
具体地，第一电平为高电平，第二电平为低电平；或者，第一电平为低电平，第二电平为高电平。
本发明实施例通过阻值可变电路、非门类电路和电容形成RC电路，当脉冲信号从低电平变为高电平时，电容通过该RC电路放电，使得阻值可变电路、非门类电路和电容组成的采样时钟产生电路的输出信号的电平由于放电作用，没有随脉冲信号的电平变化立即从高电平变为低电平，而是保持为高电平一段时间后再变为低电平。若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整。由于保持为高电平的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序偏差的调整精度可以达到百飞秒级，从而对采样点时序偏差进行有效校正，避免模数转换后的信号中出现谐波，提升SFDR，提高了ADC的转换精度。
实施例四
本发明实施例提供了一种采样时钟产生电路，与实施例二的不同之处在于，本实施例的阻值可变电路采用一一对应的电阻和选通开关实现，且各个电阻与各自对应的选通开关并联后的支路串联。
具体地，如图13所示，阻值可变电路1可以包括n个电阻R1301-R(1300+n)和与n个电阻R1301-R(1300+n)一一对应的n个第四选通开关 K(1301+n)-K(1300+2*n)，各个电阻的阻值各不相同，每个第四选通开关均包括输入端、输出端和控制端。各个电阻分别与各自对应的第四选通开关并联组成的支路串联在非门类电路2的接地端与地之间。各个第四选通开关的控制端分别接收一个周期为n*T的信号，在每个周期n*T内，该周期为n*T的信号只在一个时长为T的时间段内为第二电平，其余时间段内为第一电平，且各个第四选通开关的控制端接收的信号为第二电平的时间段不重合。
其中，当第四选通开关的控制端接收的信号为第一电平时，第四选通开关的输入端与第四选通开关的输出端连通；当第四选通开关的控制端接收的信号为第二电平时，第四选通开关的输入端与第四选通开关的输出端断开。
具体地，第一电平为高电平，第二电平为低电平；或者，第一电平为低电平，第二电平为高电平。
本发明实施例通过阻值可变电路、非门类电路和电容形成RC电路，当脉冲信号从低电平变为高电平时，电容通过该RC电路放电，使得阻值可变电路、非门类电路和电容组成的采样时钟产生电路的输出信号的电平由于放电作用，没有随脉冲信号的电平变化立即从高电平变为低电平，而是保持为高电平一段时间后再变为低电平。若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整。由于保持为高电平的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序偏差的调整精度可以达到百飞秒级，从而对采样点时序偏差进行有效校正，避免模数转换后的信号中出现谐波，提升SFDR，提高了ADC的转换精度。
实施例五
本发明实施例提供了一种ADC，参见图14，该ADC包括n片ADC芯片 IC100-IC(n*100)、采样时钟产生电路(n+1)*100和混合器(n+2)*100，采样时钟产生电路(n+1)*100与混合器(n+2)*100连接，混合器(n+2)*100分别与n片ADC芯片IC100-IC(n*100)连接。
其中，采样时钟产生电路(n+1)*100可以与实施例一至实施例四任一实施例提供的采样时钟产生电路相同。
混合器(n+2)*100用于，产生n路周期为n*T的采样信号，在每个周期n*T内，第i路采样信号的电平在第(i-1)个时长为T的时间段内与采样时钟产生电路(n+1)*100的输出信号相同，其余时间段内为低电平，第i片ADC芯片采用第i路采样信号作为采样时钟。例如，当n＝2时，如图15所示，混合器产生两路周期为2T的采样信号，在理论情况下，在每个周期2T内，第1路采样信号的电平在第1个时长为T的时间段内与采样时钟产生电路(n+1)*100的输出信号(混合器(n+2)*100的输入信号)相同，其余时间段内为低电平，第2路采样时钟信号的电平在第2个时长为T的时间段内与采样时钟产生电路(n+1)*100的输出信号(混合器(n+2)*100的输入信号)相同，其余时间段内为低电平。
可以理解地，在实际应用中，由于混合器(n+2)*100中各个器件的特性不能达到理论特性，导致混合器(n+2)*100产生的n路信号的采样点与采样时钟产生电路(n+1)*100的输出信号的采样点之间存在时序偏差，只要对采样时钟产生电路(n+1)*100的输出信号的采样点时序偏差进行适当调整，就可以抵消混合器(n+2)*100中与由于器件特性而产生的采样点时序偏差，使得混合器(n+2)*100的产生n路周期为n*T且同频不同相的采样信号，n路采样信号的采样点与脉冲信号的采样点相同，如图15所示。
本发明实施例通过阻值可变电路、非门类电路和电容形成RC电路，当脉冲信号从低电平变为高电平时，电容通过该RC电路放电，使得阻值可变电路、非门类电路和电容组成的采样时钟产生电路的输出信号的电平由于放电作用，没有随脉冲信号的电平变化立即从高电平变为低电平，而是保持为高电 平一段时间后再变为低电平。若利用保持为高电平的时长导致的采样点时序偏移抵消逻辑电路或其它电路将采样时钟产生电路的输出信号分为n路所产生的采样点时序偏差，即可对采样点时序偏差进行调整。由于保持为高电平的时长与阻值可变电路的阻值大小有关，按照保持为高电平的时长与阻值可变电路的电阻之间的关系式，即使阻值可变电路的阻值大小的调整精度只达到一般水平，高电平的时长的调整精度也较高，对采样点时序偏差的调整精度可以达到百飞秒级，从而对采样点时序偏差进行有效校正，避免模数转换后的信号中出现谐波，提升SFDR，提高了ADC的转换精度。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种采样时钟产生电路，其特征在于，所述采样时钟产生电路包括阻值可变电路、非门类电路、以及电容，所述非门类电路包括输入端、输出端、电源端和接地端，所述非门类电路的输入端接收周期为T的脉冲信号，所述非门类电路的输出端与所述电容的一端连接，所述电容的另一端接地，所述非门类电路的电源端接电源，所述非门类电路的接地端与所述阻值可变电路的一端连接，所述阻值可变电路的另一端接地；
    所述非门类电路，用于当所述脉冲信号为高电平时，输出低电平；当所述脉冲信号为低电平时，输出高电平；
    所述阻值可变电路，用于阻值每隔时长T变化一次，所述阻值的变化以n*T为周期，每个周期内各次变化后的所述阻值各不相同，n≥2且n为整数。
  2. 根据权利要求1所述的采样时钟产生电路，其特征在于，所述阻值可变电路包括场效应管Q1101和n个第一选通开关K1102-K(1101+n)，每个所述第一选通开关均包括输入端、输出端和控制端，所述场效应管Q1101的漏极与所述非门类电路的接地端连接，所述场效应管Q1101的源极接地，所述场效应管Q1101的栅极分别与各个所述第一选通开关的输出端连接，各个所述第一选通开关的输入端分别接收一个电压值恒定的信号，且各个所述第一选通开关的输入端接收的信号的电压值各不相同，各个所述第一选通开关的控制端分别接收一个周期为n*T的信号，在每个周期n*T内，所述周期为n*T的信号只在一个时长为T的时间段内为第一电平，其余时间段内均为第二电平，且各个所述选通开关的控制端接收的信号为所述第一电平的时间段不重合；
    其中，当所述第一选通开关的控制端接收的信号为所述第一电平时，所述第一选通开关的输入端与所述第一选通开关的输出端连通；当所述第一选通开关的控制端接收的信号为所述第二电平时，所述第一选通开关的输入端与所述第一选通开关的输出端断开。
  3. 根据权利要求2所述的采样时钟产生电路，其特征在于，所述场效应管Q1101为结型场效应晶体管JFET、增强型金属-氧化物半导体场效应晶体管MOSFET、或者耗尽型MOSFET。
  4. 根据权利要求2所述的采样时钟产生电路，其特征在于，所述阻值可变电路还包括场效应管Q(1102+n)，所述场效应管Q(1102+n)的栅极接电源，所述场效应管Q(1102+n)的漏极与所述场效应管Q1101的漏极连接，所述场效应管Q(1102+n)的源极与所述场效应管Q1101的源极连接；
    其中，所述场效应管Q(1102+n)和所述场效应管Q1101均为P沟道场效应管，或者，所述场效应管Q(1102+n)和所述场效应管Q1101均为N沟道场效应管。
  5. 根据权利要求4所述的采样时钟产生电路，其特征在于，所述场效应管Q(1102+n)为JFET、增强型MOSFET或者耗尽型MOSFET。
  6. 根据权利要求2所述的采样时钟产生电路，其特征在于，所述阻值可变电路还包括电阻R(1103+n)，所述电阻R(1103+n)的一端与所述场效应管Q1101的漏极连接，所述电阻(1103+n)的另一端与所述场效应管Q1101的源极连接。
  7. 根据权利要求2所述的采样时钟产生电路，其特征在于，所述采样时钟产生电路还包括与所述第一选通开关K1102-K(1101+n)一一对应的电平调整电路，各个所述电平调整电路与各自对应的所述第一选通开关的输入端连接；
    各个所述电平调整电路，用于为各自对应的所述第一选通开关的输入端提供一个电压值恒定且可调的信号，且各个所述电平调整电路提供的信号的电压值各不相同。
  8. 根据权利要求7所述的采样时钟产生电路，其特征在于，各个所述电平 调整电路均包括m个电阻R41-R(40+m)、m+1个第二选通开关K(41+m)-K(41+2*m)、以及寄存器IR，m≥2且m为整数，每个所述第二选通开关均包括输入端、输出端和控制端，m个所述电阻R41-R(41+m)串联在电源与地之间，每个串联的接点与一个所述第二选通开关的输入端连接，且各个所述串联的接点所连接的所述第二选通开关的输入端各不相同，各个所述第二选通开关的输出端分别与所述电平调整电路对应的所述第一选通开关的输入端连接，各个所述第二选通开关的控制端分别与所述寄存器IR连接。
  9. 根据权利要求1所述的采样时钟产生电路，其特征在于，所述非门类电路为反相器、与非门电路或者或非门电路。
  10. 根据权利要求9所述的采样时钟产生电路，其特征在于，所述反相器包括场效应管Q211和场效应管Q212，所述场效应管Q211的栅极与所述场效应管Q212的栅极均为所述非门类电路的输入端，所述场效应管Q211的漏极和所述场效应管Q212的漏极均为所述非门类电路的输出端，所述场效应管Q211的源极为所述非门类电路的电源端，所述场效应管Q212的源极为所述非门类电路的接地端；
    其中，所述场效应管Q211为P沟道增强型金属-氧化物半导体场效应晶体管MOSFET，且所述场效应管Q212为N沟道MOSFET；或者，所述场效应管Q211为N沟道MOSFET，且所述场效应管Q212为P沟道MOSFET。
  11. 根据权利要求1-10任一项所述的采样时钟产生电路，其特征在于，所述脉冲信号的电平与所述阻值可变电路的阻值非同时变化。
  12. 一种模数转换器ADC，所述ADC包括n片ADC芯片，其特征在于，所述ADC还包括采样时钟产生电路和混合器，所述采样时钟产生电路与所述混 合器连接，所述混合器分别与所述n片ADC芯片连接；
    所述采样时钟产生电路包括阻值可变电路、非门类电路、以及电容，所述非门类电路包括输入端、输出端、电源端和接地端，所述非门类电路的输入端接收周期为T的脉冲信号，所述非门类电路的输出端与所述电容的一端连接，所述电容的另一端接地，所述非门类电路的电源端接电源，所述非门类电路的接地端与所述阻值可变电路的一端连接，所述阻值可变电路的另一端接地；
    所述非门类电路，用于当所述脉冲信号为高电平时，输出低电平；当所述脉冲信号为低电平时，输出高电平；
    所述阻值可变电路，用于阻值每隔时长T变化一次，所述阻值的变化以n*T为周期，每个周期内各次变化后的所述阻值各不相同，n≥2且n为整数；
    所述混合器，用于产生n路周期为n*T的采样信号，在每个周期n*T内，第i路采样信号的电平在第(i-1)个时长为T的时间段内与所述采样时钟产生电路的输出信号相同，其余时间段内为低电平，第i片ADC芯片采用第i路采样信号作为采样时钟。
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US20190363726A1 (en) 2019-11-28
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