WO2016127824A1 - 应用于单端sar adc的二进制电容阵列及其冗余校准方法 - Google Patents

应用于单端sar adc的二进制电容阵列及其冗余校准方法 Download PDF

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Publication number
WO2016127824A1
WO2016127824A1 PCT/CN2016/072559 CN2016072559W WO2016127824A1 WO 2016127824 A1 WO2016127824 A1 WO 2016127824A1 CN 2016072559 W CN2016072559 W CN 2016072559W WO 2016127824 A1 WO2016127824 A1 WO 2016127824A1
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Prior art keywords
capacitor
redundancy
cir
calibration
binary
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PCT/CN2016/072559
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English (en)
French (fr)
Chinese (zh)
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吴建辉
林志伦
杜媛
陈超
黄成�
李红
张萌
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东南大学
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing

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  • the invention relates to a binary capacitor array redundancy calibration method applied to a single-ended SAR ADC, belonging to a SAR ADC calibration technique.
  • High-precision SAR ADCs Serial Approximation Register Type Analog-to-Digital Converters
  • the establishment time is thus limited and difficult to improve.
  • the comparator is misjudged to generate dynamic error, which affects the overall linearity of the SAR ADC.
  • non-binary capacitor arrays can achieve redundant calibration, allowing the establishment of dynamic errors caused by incompleteness, increasing the speed of SAR ADCs, but requiring an additional number of conversion cycles, and non-binary capacitor arrays require ROM to record each bit.
  • the weight, and the complex calculation of the final output code greatly increases the complexity of the system, and the non-binary capacitor array is difficult to achieve matching design on the layout.
  • a binary-capacitor array redundancy algorithm with fully differential structure has been proposed, but its operation cannot be applied to a single-ended SAR ADC.
  • the present invention provides a single-ended SAR ADC binary capacitor array and a redundancy calibration method thereof, which combines the small complexity and small area advantages of SAR ADC single-ended operation, and Redundant calibration improves its accuracy and linearity performance.
  • the technical solution adopted by the present invention is: a binary capacitor array applied to a single-ended SAR ADC, including an addition redundancy calibration capacitor and a subtraction redundancy calibration capacitor; the addition redundancy calibration capacitor and subtraction redundancy The remaining calibration capacitor is inserted after a certain bit Ci of the binary capacitor array, and the capacitance values of the two are the same as the Ci capacitor value, and the calibration range is the same as the voltage weight represented by Ci, which is:
  • Vref is the reference power supply voltage
  • N is the total number of bits of the binary capacitor array
  • the number of bits of Ci is the number of bits when the addition redundancy calibration capacitor and the subtraction redundancy calibration capacitor are not considered;
  • the addition redundant calibration capacitor reference level reset state is connected in the same manner as the Ci reference level reset state, and the subtraction redundancy calibration capacitor reference level reset state connection mode and the addition redundancy calibration capacitance reference level reset
  • the connection mode of the state is reversed, that is, the gnd of the subtractive redundancy calibration capacitor corresponds to the Vref of the addition redundancy calibration capacitor, and the subtraction method
  • the Vref of the redundant calibration capacitor corresponds to the gnd of the additive redundancy calibration capacitor, and the subtraction operation is implemented by the opposite reference level operation.
  • the invention also provides a redundancy calibration method implemented by a binary capacitor array applied to a single-ended SAR ADC, and the specific steps are as follows:
  • Step 1 resetting the addition redundancy capacitor and the subtraction redundancy capacitor, that is, the lower plate of the addition redundancy capacitor is connected to the switch of the gnd, and the lower plate of the subtraction redundancy capacitor is connected to the switch of the Vref; Sampling of binary capacitors other than redundant capacitors and subtractive redundant capacitors;
  • Step 2 Convert the capacitance of the binary capacitor array in order from the high level to the low level.
  • Ci the output result of the Ci bit comparator
  • the next conversion is switched to the addition redundancy calibration capacitor.
  • the Ci lower plate is connected to gnd, the next conversion is switched to the subtractive redundant calibration capacitor, and no operation is performed on the subtractive redundant calibration capacitor, and the redundancy calibration is directly obtained.
  • Step 3 Converting the capacitors at the i-1th position and after;
  • Step 4 After all the conversion processes are finished, input the output of the comparator to the output code calculation module, perform calculation, and finally output the digital code of the ADC, where:
  • Di is the total output result of the i-th Ci input to the output code calculation module
  • bi is the comparator output of the i-th Ci
  • biR is the comparison of the addition redundant calibration capacitor and the subtractive redundancy calibration capacitor inserted after Ci
  • J is the compensation coefficient of the Ci bit.
  • the binary capacitors other than the addition redundant capacitor and the subtractive redundant capacitor are sampled as described in the first step, as follows: the switch of the capacitor upper board is closed, that is, the reference level Vcm connected to the comparator, which needs to be sampled.
  • the lower plate of the capacitor is connected to the input signal Vin for sampling; after the sampling is finished, the upper plate switch connected to the capacitor of Vcm is turned off, and all the switches of the lower plate of the sampling capacitor are switched from the input signal Vin to gnd.
  • the conversion method of the binary capacitor Ck other than the additive redundant capacitor and the subtractive redundant capacitor in the binary capacitor array is as follows:
  • the binary capacitor array redundancy calibration method applied to the single-ended SAR ADC provided by the present invention has the following advantages over the prior art:
  • the redundant calibration algorithm enables digital calibration of the capacitance mismatch without the need to introduce additional capacitance mismatch calibration capacitors.
  • Redundant calibration of capacitors using binary capacitor arrays saves conversions compared to traditional non-binary redundancy calibrations, and binary capacitor arrays are easy to match on the layout.
  • the single-ended binary capacitor array redundancy calibration algorithm proposed by the present invention combines the small complexity and small area advantages of SAR ADC single-ended operation, and improves the accuracy and linearity performance through redundant calibration.
  • the calibration algorithm is also compatible.
  • FIG. 1 is a block diagram of a single-ended SAR ADC
  • FIG. 2 is a structural diagram of a 4-bit DAC redundant capacitor array applied to a single-ended SAR ADC according to the present invention
  • Figure 3 is a 4-bit schematic diagram of a single-ended SAR ADC with no redundant calibration conversion process.
  • FIG. 4 is a schematic diagram of a 4 bit diagram of a binary capacitor array redundancy calibration conversion process applied to a single-ended SAR ADC according to the present invention.
  • FIG. 5 is a flow chart of the binary capacitor array redundancy calibration operation applied to the single-ended SAR ADC of the present invention.
  • FIG. 6 is a calculation diagram of a binary capacitor array redundancy calibration digital output applied to a single-ended SAR ADC according to the present invention.
  • FIG. 7 is a schematic diagram of a binary capacitor array redundancy calibration structure applied to a single-ended SAR ADC according to the present invention.
  • FIG. 1 Block diagram of a single-ended SAR ADC, including sample-and-hold circuits, comparators, SAR logic, and DAC capacitor arrays. This structure is easy to understand and the following operating instructions will explain this structure. Where DAC is a binary capacitor array, its high and low reference The levels are Vref and Gnd.
  • FIG. 2 is a structural diagram of a 4-bit DAC redundant capacitor array applied to a single-ended SAR ADC of the present invention, after adding a complementary redundancy calibration capacitor C1R+ and a subtractive redundancy calibration capacitor C1R- after a capacitor C1 of a 4-bit binary capacitor array.
  • Figure 3 is a 4-bit schematic diagram of a single-ended SAR ADC with no redundant calibration conversion process.
  • the ordinate indicates the input analog signal of the comparator
  • the line corresponding to Vi is the input signal, that is, the positive input of the comparator
  • the bent connecting line indicates the output signal of the DAC, that is, the negative end signal of the comparator.
  • the abscissa represents the conversion process, the timeline.
  • the bar represents the operation of the DAC capacitor for each conversion process.
  • the black number below the abscissa indicates the output code of the comparator.
  • the top of the ordinate represents the last digital output code.
  • (a) and (b) are the non-redundant calibration normal conversion when the highest bit ⁇ 0 and the highest bit>0, respectively.
  • (c) and (d) indicate an error conversion in which the highest-order comparator output is misjudged as 0, and an error conversion in which the highest-order comparator output is misjudged as 0.
  • the conversion process of (a) to (d) is the same. Taking (a) as an example, the input signal is sampled and held at the beginning of the conversion process, and the DAC capacitor is reset.
  • the highest-order capacitor C3 is connected to Vref, so the DAC output is Vref/2 at this time, compared with the input signal, since Vi ⁇ Vdac(Vref/2), the comparator output is 0 at this time, the control is the highest.
  • Bit capacitor C3 is connected back to Gnd, and the C2 capacitor is connected to Vref. At this time, the DAC output is Vref/4.
  • the comparator output is 1, keeping the C2 capacitor state, and C1
  • the capacitor is connected to Vref
  • the DAC output is Vref/4+Vref/8
  • the comparator output is 1, the C1 capacitor state is maintained, and the C0 capacitor is connected to Vref.
  • the digital output code is 0111. As can be seen from the figure, once the misjudgment is caused by the incomplete DAC establishment, the error will continue until the wrong digital code is output.
  • FIG. 7 is a schematic diagram of a binary capacitor array redundancy calibration structure applied to a single-ended SAR ADC according to the present invention, which is a schematic diagram of an algorithm for practical application.
  • a redundant capacitor array, a comparator, a SAR logic control module, an output code calculation module wherein the redundantly calibrated binary capacitor array includes an addition redundancy calibration capacitor CiR+ and a subtraction redundancy calibration capacitor CiR-;
  • the remaining calibration capacitor CiR+ and the subtractive redundancy calibration capacitor CiR- are inserted after a certain bit Ci of the binary capacitor array, and the capacitance values of the two are the same as the Ci capacitance value, and the calibration range is the same as the voltage weight represented by Ci, which is:
  • Vref is the reference power supply voltage
  • N is the total number of bits of the binary capacitor array
  • the number of bits of Ci is the number of bits when the addition redundancy calibration capacitor and the subtraction redundancy calibration capacitor are not considered;
  • connection redundancy reset capacitor CiR+ reference level reset state is connected in the same manner as the Ci reference level reset state, and the subtraction redundancy calibration capacitor CiR-reference level reset state connection mode and the addition redundancy calibration capacitor CiR+
  • the reference level reset state is connected in the opposite way, that is, the gnd of the subtractive redundancy calibration capacitor CiR- corresponds to the Vref of the addition redundancy calibration capacitor CiR+, and the Vref of the subtraction redundancy calibration capacitor CiR- corresponds to the addition redundancy calibration capacitor CiR+ Gnd, through the opposite reference level operation to achieve the subtraction operation.
  • the redundancy calibration method implemented by the binary capacitor array applied to the single-ended SAR ADC is as follows:
  • Step 1 Reset the addition redundancy capacitor CiR+ and the subtraction redundancy capacitor CiR-, that is, the lower plate of the addition redundancy capacitor CiR+ is connected to the switch of gnd, and the lower plate of the subtraction redundancy capacitor CiR- is connected to the switch of Vref.
  • Step 2 As shown in FIG. 5, the capacitance of the binary capacitor array is sequentially converted from the high level to the low level.
  • the Ci lower plate is connected to gnd, the next conversion is switched to the subtractive redundant calibration capacitor CiR-, and the subtractive redundant calibration capacitor CiR- is not operated directly.
  • Step 3 Converting the capacitors at the i-1th position and after;
  • Step 4 After all the conversion processes are finished, input the output of the comparator to the output code calculation module, perform calculation, and finally output the digital code of the ADC, where:
  • Di is the total output result of the i-th Ci input to the output code calculation module
  • bi is the comparator output of the i-th Ci
  • biR is the addition redundancy calibration capacitor CiR+ and the subtractive redundancy calibration capacitor CiR inserted after Ci - Comparator output
  • J is the compensation coefficient of the Ci bit.
  • FIG. 5 is a flow chart showing the operation of the present invention for redundant calibration of a binary capacitor array of a single-ended SAR ADC. Wherein: for this embodiment, i takes 1.
  • the operation of the ordinary single-ended SAR ADC does not meet the requirements, so an additional detection phase needs to be introduced to judge whether the error occurs.
  • the error in which the addition or subtraction is cancelled can be easily distinguished by the comparator output code bi of the Ci bit.

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PCT/CN2016/072559 2015-02-10 2016-01-28 应用于单端sar adc的二进制电容阵列及其冗余校准方法 WO2016127824A1 (zh)

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CN110266312A (zh) * 2019-05-30 2019-09-20 福建工程学院 一种应用于sar adc的dac开关方法
CN110572158A (zh) * 2019-10-16 2019-12-13 合肥工业大学 逐次逼近型adc的电容阵列电路及其电容开关控制方法
CN110868216A (zh) * 2019-11-29 2020-03-06 湖南国科微电子股份有限公司 一种sar adc的数据转换方法、装置、设备及介质
CN112290945A (zh) * 2020-09-30 2021-01-29 西安电子科技大学 单通道高速高精度sar adc的数字后台自校准电路结构及方法
CN113922819A (zh) * 2021-12-14 2022-01-11 之江实验室 基于后台校准的一步两位逐次逼近型模数转换器
CN114389609A (zh) * 2021-12-14 2022-04-22 中国科学院微电子研究所 一种补偿电路及补偿方法
CN115021749A (zh) * 2022-06-30 2022-09-06 天津大学合肥创新发展研究院 适用于一阶误差反馈式失配误差整形的动态范围补偿方法
CN116707527A (zh) * 2023-05-30 2023-09-05 南京铭芯半导体科技有限公司 一种saradc电容阵列校准方法和电路
CN118337216A (zh) * 2024-04-25 2024-07-12 成都士模微电子有限责任公司 模数转换器中电容翻转方法及逐次逼近型模数转换器

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CN104639164B (zh) * 2015-02-10 2017-09-29 东南大学 应用于单端sar adc的二进制电容阵列及其冗余校准方法
CN104917527B (zh) * 2015-06-30 2017-12-05 东南大学 应用于单端sar adc的电容失配校准电路及其校准方法
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WO2023173973A1 (zh) * 2022-03-17 2023-09-21 上海美仁半导体有限公司 冗余校准的sar-adc电路和模数转换器
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CN110266312A (zh) * 2019-05-30 2019-09-20 福建工程学院 一种应用于sar adc的dac开关方法
CN110266312B (zh) * 2019-05-30 2022-09-13 福建工程学院 一种应用于sar adc的dac开关方法
CN110572158B (zh) * 2019-10-16 2022-08-30 合肥工业大学 逐次逼近型adc的电容阵列电路及其电容开关控制方法
CN110572158A (zh) * 2019-10-16 2019-12-13 合肥工业大学 逐次逼近型adc的电容阵列电路及其电容开关控制方法
CN110868216A (zh) * 2019-11-29 2020-03-06 湖南国科微电子股份有限公司 一种sar adc的数据转换方法、装置、设备及介质
CN110868216B (zh) * 2019-11-29 2024-05-07 湖南国科微电子股份有限公司 一种sar adc的数据转换方法、装置、设备及介质
CN112290945A (zh) * 2020-09-30 2021-01-29 西安电子科技大学 单通道高速高精度sar adc的数字后台自校准电路结构及方法
CN112290945B (zh) * 2020-09-30 2023-03-28 西安电子科技大学 单通道高速高精度sar adc的数字后台自校准电路结构及方法
CN114389609A (zh) * 2021-12-14 2022-04-22 中国科学院微电子研究所 一种补偿电路及补偿方法
CN114389609B (zh) * 2021-12-14 2022-11-11 中国科学院微电子研究所 一种补偿电路及补偿方法
CN113922819A (zh) * 2021-12-14 2022-01-11 之江实验室 基于后台校准的一步两位逐次逼近型模数转换器
CN115021749A (zh) * 2022-06-30 2022-09-06 天津大学合肥创新发展研究院 适用于一阶误差反馈式失配误差整形的动态范围补偿方法
CN116707527A (zh) * 2023-05-30 2023-09-05 南京铭芯半导体科技有限公司 一种saradc电容阵列校准方法和电路
CN118337216A (zh) * 2024-04-25 2024-07-12 成都士模微电子有限责任公司 模数转换器中电容翻转方法及逐次逼近型模数转换器

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