WO2016125881A1 - 半導体装置の製造方法、及びアンダーフィルフィルム - Google Patents

半導体装置の製造方法、及びアンダーフィルフィルム Download PDF

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Publication number
WO2016125881A1
WO2016125881A1 PCT/JP2016/053462 JP2016053462W WO2016125881A1 WO 2016125881 A1 WO2016125881 A1 WO 2016125881A1 JP 2016053462 W JP2016053462 W JP 2016053462W WO 2016125881 A1 WO2016125881 A1 WO 2016125881A1
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Prior art keywords
underfill film
melt viscosity
temperature
underfill
epoxy resin
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PCT/JP2016/053462
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English (en)
French (fr)
Inventor
健二 久保田
崇之 齋藤
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デクセリアルズ株式会社
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Application filed by デクセリアルズ株式会社 filed Critical デクセリアルズ株式会社
Priority to CN201680006768.7A priority Critical patent/CN107112254B/zh
Priority to US15/532,931 priority patent/US10280347B2/en
Priority to KR1020177010337A priority patent/KR101947293B1/ko
Priority to EP16746712.5A priority patent/EP3255658B1/en
Publication of WO2016125881A1 publication Critical patent/WO2016125881A1/ja

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    • C09J7/00—Adhesives in the form of films or foils
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    • C08G—MACROMOLECULAR COMPOUNDS OBTAINED OTHERWISE THAN BY REACTIONS ONLY INVOLVING UNSATURATED CARBON-TO-CARBON BONDS
    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/40—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the curing agents used
    • C08G59/42—Polycarboxylic acids; Anhydrides, halides or low molecular weight esters thereof
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Definitions

  • the present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is mounted on a substrate or a wafer, and an underfill film used therefor.
  • the conventional general liquid underfill material makes it difficult to mount a thinned semiconductor chip or 3D.
  • the "Pre-applied Underfill Film (PUF)” which attaches an underfill film on a substrate before metal bonding or pressure welding of a semiconductor IC (Integrated Circuit) electrode and a substrate electrode, Use is under consideration.
  • the mounting method using this pre-feed type underfill film is performed, for example, as follows (see, for example, Patent Document 1).
  • Step A An underfill film is attached to a wafer and diced to obtain a semiconductor chip.
  • Step B The semiconductor chip is aligned on the substrate.
  • Process C The semiconductor chip and the substrate are pressure-bonded at a high temperature and a high pressure, the conduction is ensured by metal bonding of the solder bumps, and the semiconductor chip and the substrate are bonded by curing the underfill film.
  • the present invention has been proposed in view of such a conventional situation, and even when a plurality of semiconductor chips are collectively pressure-bonded, a method for manufacturing a semiconductor device and an underfill capable of obtaining voidless mounting and good solderability. Provide film.
  • the inventor has collectively pressed a plurality of semiconductor chips by using an underfill film having a predetermined minimum melt viscosity and a predetermined melt viscosity gradient at a temperature higher than the minimum melt viscosity attainment temperature. It has been found that even in this case, it is possible to obtain voidless mounting and good solderability.
  • a plurality of semiconductor chips on which soldered electrodes are formed are mounted on an electronic component on which an opposing electrode facing the soldered electrode is formed via an underfill film.
  • an organic peroxide having a minimum melt viscosity of 1000 Pa ⁇ s to 2000 Pa ⁇ s, and a melt viscosity from a temperature 10 ° C. higher than the lowest melt viscosity attainment temperature to a temperature 10 ° C. higher than the temperature.
  • the inclination is 900 Pa ⁇ s / ° C. or more and 3100 Pa ⁇ s / ° C. or less.
  • the present invention is an underfill film for press-bonding a plurality of semiconductor chips and electronic components at once, containing an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide,
  • the minimum melt viscosity is 1000 Pa ⁇ s or more and 2000 Pa ⁇ s or less
  • the slope of the melt viscosity from a temperature 10 ° C. higher than the minimum melt viscosity attainment temperature to a temperature 10 ° C. higher than the temperature is 900 Pa ⁇ s / ° C. or more and 3100 Pa ⁇ s. It is characterized by being s / ° C. or less.
  • the present invention even when a plurality of semiconductor chips are collectively pressure-bonded by using an underfill film having a predetermined minimum melt viscosity and a predetermined melt viscosity gradient at a temperature higher than the minimum melt viscosity attainment temperature, Therefore, the influence of the temperature rise temperature difference due to the above can be reduced, and voidless mounting and good solderability can be obtained.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor chip and a circuit board before mounting in the first example.
  • FIG. 2 is a cross-sectional view schematically showing the semiconductor chip and the circuit board before mounting in the second example.
  • FIG. 3 is a cross-sectional view schematically showing a semiconductor chip and a circuit board when mounted.
  • FIG. 4 is a cross-sectional view schematically showing the semiconductor chip and the circuit board after thermocompression bonding.
  • FIG. 5 is a graph showing an example of bonding conditions.
  • FIG. 6 is a graph showing a melt viscosity curve of an underfill film adapted to the bonding conditions shown in FIG.
  • FIG. 7 is a flowchart showing a method for manufacturing a semiconductor device in the present embodiment.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor chip and a circuit board before mounting in the first example.
  • FIG. 2 is a cross-sectional view schematically showing the semiconductor chip and the circuit board before mounting in the
  • FIG. 8 is a perspective view schematically showing a process of attaching an underfill film on the wafer.
  • FIG. 9 is a perspective view schematically showing a process of dicing the wafer.
  • FIG. 10 is a perspective view schematically showing a process of picking up a semiconductor chip.
  • FIG. 11 is a cross-sectional view schematically showing a process of collectively crimping a plurality of semiconductor chips.
  • FIG. 12 is a perspective view schematically showing a step of collectively crimping a plurality of semiconductor chips.
  • FIG. 13 is a graph showing a melt viscosity curve of a sample of an underfill film.
  • the underfill film in the present embodiment is for collectively crimping a plurality of semiconductor chips and electronic components, and contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide.
  • the minimum melt viscosity is 1000 Pa ⁇ s or more and 2000 Pa ⁇ s or less, and the slope of the melt viscosity from a temperature 10 ° C. higher than the minimum melt viscosity attainment temperature to a temperature 10 ° C. higher than the temperature is 900 Pa ⁇ s / ° C. or more. 3100 Pa ⁇ s / ° C. or less.
  • the electronic component include a bottom chip on which a plurality of semiconductor chips are mounted, a circuit board, and the like.
  • FIG. 1 and 2 are cross-sectional views schematically showing a semiconductor chip and a circuit board before mounting in the first example and the second example, respectively.
  • 3 is a cross-sectional view schematically showing the semiconductor chip and the circuit board when mounted
  • FIG. 4 is a cross-sectional view schematically showing the semiconductor chip and the circuit board after thermocompression bonding.
  • the underfill film 20 is used by being bonded in advance to the electrode surface of the semiconductor chip 10 on which the soldered electrode 13 is formed.
  • the underfill film 20 may be used by being bonded in advance to the electrode surface of the circuit board 30 on which the counter electrode 32 facing the soldered electrode 13 is formed.
  • the plurality of semiconductor chips 10 are bonded to the circuit board 30 by the adhesive layer 21 in which the underfill film 20 is cured.
  • the semiconductor chip 10 has an integrated circuit formed on the surface of a semiconductor 11 such as silicon, and has soldered electrodes for connection called bumps.
  • the soldered electrode is obtained by joining the solder 13 on the electrode 12 made of copper or the like, and has a total thickness of the electrode 12 and the solder 13.
  • solder As the solder, Sn-37Pb eutectic solder (melting point 183 ° C), Sn-Bi solder (melting point 139 ° C), Sn-3.5Ag (melting point 221 ° C), Sn-3.0Ag-0.5Cu (melting point 217 ° C) ), Sn-5.0Sb (melting point: 240 ° C.), etc. can be used.
  • the circuit board 30 has a circuit formed on a base material 31 such as a rigid board or a flexible board.
  • a counter electrode 32 having a predetermined thickness is formed at a position facing the soldered electrode of the semiconductor chip 10 in the mounting portion where the semiconductor chip 10 is mounted.
  • the underfill film 20 contains a film-forming resin, an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide.
  • the film-forming resin corresponds to a high-molecular weight resin having a weight average molecular weight of 10 ⁇ 10 4 or more, and preferably has a weight average molecular weight of 10 ⁇ 10 4 to 100 ⁇ 10 4 from the viewpoint of film formation.
  • various resins such as an acrylic rubber polymer, a phenoxy resin, an epoxy resin, a modified epoxy resin, and a urethane resin can be used. These film forming resins may be used alone or in combination of two or more.
  • an acrylic rubber polymer having a glycidyl group is suitably used from the viewpoint of film strength and adhesiveness.
  • Examples of commercially available acrylic rubber polymers having a glycidyl group include the trade name “Taisan Resin SG-P3” (Nagase Chemtech Co., Ltd.).
  • epoxy resin examples include glycidyl such as tetrakis (glycidyloxyphenyl) ethane, tetrakis (glycidyloxymethylphenyl) ethane, tetrakis (glycidyloxyphenyl) methane, trikis (glycidyloxyphenyl) ethane, and trikis (glycidyloxyphenyl) methane.
  • glycidyl such as tetrakis (glycidyloxyphenyl) ethane, tetrakis (glycidyloxymethylphenyl) ethane, tetrakis (glycidyloxyphenyl) methane, trikis (glycidyloxyphenyl) ethane, and trikis (glycidyloxyphenyl) methane.
  • Ether type epoxy resin dicyclopentadiene type epoxy resin, glycidylamine type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, spiro ring type epoxy resin, naphthalene type epoxy resin, biphenyl type epoxy Resin, terpene epoxy resin, tetrabromobisphenol A epoxy resin, cresol novolac epoxy resin, phenol novolac epoxy Carboxymethyl resins, alpha-naphthol novolak type epoxy resin, and the like brominated phenol novolak type epoxy resin. These epoxy resins may be used alone or in combination of two or more.
  • a glycidyl ether type epoxy resin from the point of high adhesiveness and heat resistance.
  • a commercial item of a glycidyl ether type epoxy resin a brand name "JER1031S” (Mitsubishi Chemical Corporation) etc. are mentioned, for example.
  • Acid anhydrides include, for example, alicyclic acid anhydrides such as hexahydrophthalic anhydride and methyltetrahydrophthalic anhydride, aliphatic acid anhydrides such as tetrapropenyl succinic anhydride and dodecenyl succinic anhydride, phthalic anhydride, anhydrous Examples thereof include aromatic acid anhydrides such as trimellitic acid and pyromellitic anhydride. These epoxy curing agents may be used alone or in combination of two or more.
  • alicyclic acid anhydrides from the viewpoint of solder connectivity.
  • Commercially available products of alicyclic acid anhydrides include, for example, trade name “Licacid HNA-100” (Shin Nihon Rika Co., Ltd.).
  • a curing accelerator examples include 1,8-diazabicyclo (5,4,0) undecene-7 salt (DBU salt), 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, etc.
  • DBU salt 1,8-diazabicyclo (5,4,0) undecene-7 salt
  • 2-methylimidazole 2-ethylimidazole
  • 2-ethyl-4-methylimidazole examples thereof include imidazoles, tertiary amines such as 2- (dimethylaminomethyl) phenol, phosphines such as triphenylphosphine, and metal compounds such as tin octylate.
  • monofunctional (meth) acrylate As the acrylic resin, monofunctional (meth) acrylate, bifunctional or higher (meth) acrylate can be used.
  • the monofunctional (meth) acrylate include methyl (meth) acrylate, ethyl (meth) acrylate, n-propyl (meth) acrylate, i-propyl (meth) acrylate, and n-butyl (meth) acrylate.
  • Bifunctional or higher (meth) acrylates include fluorene acrylate, bisphenol F-EO modified di (meth) acrylate, bisphenol A-EO modified di (meth) acrylate, trimethylolpropane PO modified (meth) acrylate, polyfunctional urethane A (meth) acrylate etc.
  • acrylic resins may be used alone or in combination of two or more.
  • fluorene acrylate is preferably used. Examples of commercially available products of fluorene acrylate include “Oxol EA-0200” (Osaka Organic Chemical Co., Ltd.).
  • organic peroxides examples include peroxyketals, peroxyesters, hydroperoxides, dialkyl peroxides, diacyl peroxides, and peroxydicarbonates. These organic peroxides may be used alone or in combination of two or more. Among these, peroxyketal is preferably used in the present embodiment. As a commercial product of peroxyketal, for example, trade name “Perhexa V” (NOF Corporation) and the like can be mentioned.
  • an inorganic filler as another additive composition.
  • the fluidity of the resin layer at the time of pressure bonding can be adjusted.
  • the inorganic filler silica, talc, titanium oxide, calcium carbonate, magnesium oxide, or the like can be used.
  • silane coupling agents such as epoxy, amino, mercapto / sulfide, and ureido may be added.
  • FIG. 5 is a graph showing an example of bonding conditions. This bonding condition is to raise the temperature from the temperature T1 to 250 ° C. at a temperature rising rate of 50 ° C./sec or more and 150 ° C./sec or less.
  • the temperature T1 is preferably substantially the same as the minimum melt viscosity of the underfill film, and is preferably 50 ° C. or higher and 150 ° C. or lower.
  • FIG. 6 is a graph showing the melt viscosity curve of the underfill film that meets the bonding conditions shown in FIG. This melt viscosity curve is obtained by measuring an underfill film using a rheometer under conditions of 5 ° C./min and 1 Hz.
  • the minimum melt viscosity ⁇ of the underfill film that meets this bonding condition is 1000 Pa ⁇ s or more and 2000 Pa ⁇ s or less. Thereby, generation
  • the minimum melt viscosity attainment temperature of an underfill film is 125 degrees C or less.
  • the elasticity modulus of an underfill film is 1 GPa or more and 10 GPa or less.
  • the slope of the melt viscosity from a temperature 10 ° C. higher than the lowest melt viscosity attainment temperature of the underfill film to a temperature 10 ° C. higher than the temperature is 900 Pa ⁇ s / ° C. to 3100 Pa ⁇ s / ° C.
  • the underfill film can suppress the formation of fillets on the side surfaces of the chips, it is possible to reduce the interval between adjacent chips.
  • the filletless prevents adhesion to the tool and eliminates the need for a cushioning material.
  • the lowest melt viscosity reaching temperature is substantially the same as the temperature T1 of the bonding condition.
  • the ratio of the total mass of acrylic resin and organic peroxide to the total mass of epoxy resin and acid anhydride is preferably 7: 3 to 4: 6, more preferably 7: 3 to 5 : 5. This increases the margin of the heating rate under the bonding conditions, so even when multiple semiconductor chips are bonded together, the influence of the difference in the heating rate depending on the chip position can be reduced. And good solderability can be realized.
  • an adhesive composition containing a film-forming resin, an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide is dissolved in a solvent.
  • a solvent toluene, ethyl acetate or the like, or a mixed solvent thereof can be used.
  • the resin composition After preparing the resin composition, it is applied onto the release substrate using a bar coater, a coating device or the like.
  • the release substrate has, for example, a laminated structure in which a release agent such as silicone is applied to PET (PolyPoEthylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), etc. While preventing drying of a composition, the shape of a composition is maintained.
  • a release agent such as silicone is applied to PET (PolyPoEthylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), etc. While preventing drying of a composition, the shape of a composition is maintained.
  • the resin composition applied on the release substrate is dried by a heat oven, a heat drying apparatus or the like. Thereby, a pre-feed type underfill film having a predetermined thickness can be obtained.
  • the manufacturing method of the semiconductor device in the present embodiment is a mounting process in which a plurality of semiconductor chips on which soldered electrodes are formed are mounted on an electronic component on which counter electrodes facing the soldered electrodes are formed via an underfill film. And a crimping step of collectively crimping a plurality of semiconductor chips and electronic components via an underfill film.
  • the underfill film used in this method contains an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide, and has a minimum melt viscosity of 1000 Pa ⁇ s to 2000 Pa ⁇ s.
  • the slope of the melt viscosity from a temperature 10 ° C. higher than the lowest melt viscosity attainment temperature to a temperature 10 ° C. higher than the temperature is 900 Pa ⁇ s / ° C. or more and 3100 Pa ⁇ s / ° C. or less.
  • FIG. 7 is a flowchart showing a method for manufacturing a semiconductor device.
  • the manufacturing method of the semiconductor device in the present embodiment includes an underfill film sticking step S1, a dicing step S2, a semiconductor chip mounting step S3, and a thermocompression bonding step S4.
  • FIG. 8 is a perspective view schematically showing a process of attaching an underfill film on a wafer.
  • the wafer 1 is fixed by a jig 3 having a ring-shaped or frame-shaped frame having a diameter larger than the diameter of the wafer 1, and the underfill is formed on the wafer 1.
  • the underfill film 2 functions as a dicing tape that protects and fixes the wafer 1 when the wafer 1 is diced and holds the wafer 1 during pick-up.
  • a large number of integrated circuits (ICs) are formed on the wafer 1, and soldered electrodes are provided on the bonding surface of the wafer 1 for each semiconductor chip 10 divided by scribe lines.
  • ICs integrated circuits
  • FIG. 9 is a perspective view schematically showing a process of dicing the wafer. As shown in FIG. 9, in the dicing step S2, the blade 4 is pressed along the scribe line to cut the wafer 1 and divide it into individual semiconductor chips.
  • FIG. 10 is a perspective view schematically showing a process of picking up a semiconductor chip. As shown in FIG. 10, each semiconductor chip 10 with an underfill film is held and picked up by the underfill film.
  • the semiconductor chip 10 with the underfill film and the circuit board 30 are arranged via the underfill film. Further, the semiconductor chip 10 with the underfill film is aligned and disposed so that the soldered electrode and the counter electrode 32 face each other. Then, by the heat bonder, fluidity is generated in the underfill film, but the film is heated and pressed under conditions of a predetermined temperature, pressure, and time that do not cause main curing.
  • the temperature condition at the time of mounting is preferably 30 ° C. or higher and 155 ° C. or lower.
  • the pressure condition is preferably 60 N or less, more preferably 50 N or less.
  • time conditions are 0.5 second or more and 10 seconds or less, More preferably, they are 0.1 second or more and 3.0 seconds or less.
  • thermocompression bonding step S4 using a gang bonding apparatus, the solder of the soldered electrodes of the plurality of semiconductor chips 10 is melted to form a metal bond, and the underfill film is completely cured and collectively bonded.
  • FIG. 11 and FIG. 12 are a cross-sectional view and a perspective view, respectively, schematically showing a process of collectively crimping a plurality of semiconductor chips.
  • the bottom chip 41 is arranged 3 ⁇ 3 as an electronic component on the stage 50.
  • each of the semiconductor chips 10 is mounted on the bottom chip 41, and the 3 ⁇ 3 semiconductor chips are collectively pressure-bonded by the heat tool 60, so that the plurality of semiconductor chips 10 are bottomed by the adhesive layer 21 in which the underfill film 20 is cured. Bonded to the chip 41.
  • the temperature condition at the time of batch pressing is preferably 150 ° C. or higher and 300 ° C. or lower, more preferably 230 ° C. or higher and 280 ° C. or lower.
  • the pressure condition is preferably 60 N or less, more preferably 50 N or less.
  • time conditions are 0.1 second or more and 60 seconds or less, More preferably, they are 5 seconds or more and 20 seconds or less.
  • the underfill film is allowed to function as a dicing tape.
  • the present invention is not limited to this, and dicing tape is used separately, and flip chip mounting is performed using the underfill film after dicing. You may go.
  • the present technology can also be applied to a TSV (Through Silicon Via) technology in which a plurality of chip substrates stacked in a sandwich shape are electrically connected by filling a small hole provided in a semiconductor chip with metal.
  • TSV Three Silicon Via
  • a semiconductor device in which a plurality of chip substrates having a first surface on which a soldered electrode is formed and a second surface on which a counter electrode facing the soldered electrode is formed on the opposite side of the first surface are stacked. This method can also be applied.
  • the first chip substrate is mounted on the second surface of the second chip substrate with the underfill film attached to the first surface side. Thereafter, a semiconductor in which a plurality of chip substrates are stacked by thermocompression bonding the first surface of the first chip substrate and the second surface of the second chip substrate at a temperature equal to or higher than the melting point of the solder of the soldered electrode. A device can be obtained.
  • Example> Examples of the present invention will be described below.
  • a pre-feed type underfill film is produced, and then a plurality of upper chips having soldered electrodes using the underfill film and lower chips having electrodes opposed thereto are shown in FIGS.
  • a gang bonding apparatus as shown in FIG. 12 was used to produce a mounting body by collectively pressing, and evaluation of voids, solder joint state, and fillet was performed.
  • an IC chip having a soldered electrode using an underfill film and an IC substrate having an electrode opposite to this are connected to each head one chip at a time. What was produced and evaluated for the void and solder joint state will be described.
  • an underfill film was used to connect one chip at a time to one chip to produce a mounting body, and the void and solder bonding state were evaluated.
  • the measurement of the minimum melt viscosity of the underfill film and the gradient of the melt viscosity, the fabrication of the mounting body, the evaluation of voids, and the evaluation of solder bonding were performed as follows.
  • the underfill film was bonded onto the wafer with a press machine at 50 ° C. to 0.5 MPa, and dancing was performed to obtain an IC chip having a soldered electrode.
  • the IC chip has a size of 7 mm ⁇ and a thickness of 200 ⁇ m, and a peripherally arranged bump (16 ⁇ m thick solder (Sn-3.5Ag, melting point 221 ° C.) formed on the tip of an electrode made of Cu having a thickness of 20 ⁇ m. ⁇ 30 ⁇ m, 85 ⁇ m pitch, 280 pins).
  • a peripherally arranged bump (16 ⁇ m thick solder (Sn-3.5Ag, melting point 221 ° C.) formed on the tip of an electrode made of Cu having a thickness of 20 ⁇ m. ⁇ 30 ⁇ m, 85 ⁇ m pitch, 280 pins).
  • the IC substrate opposite to this has a size of 7 mm ⁇ , a thickness of 200 ⁇ m, and a peripheral arrangement bump ( ⁇ 30 ⁇ m, 85 ⁇ m pitch, 280 pins) on which an electrode made of Cu of 20 ⁇ m is formed. I had it.
  • an IC chip was mounted on the IC substrate using a flip chip bonder under the conditions of 60 ° C. ⁇ 0.5 seconds ⁇ 30N.
  • thermocompression bonding was performed at a temperature increase rate of 50 ° C./sec from the lowest melt viscosity attainment temperature of the underfill film to 250 ° C.
  • the bonder head was lowered to the lowest point within the time to raise the temperature from the lowest melt viscosity attainment temperature to 250 ° C. (30 N).
  • curing was performed at 150 ° C. for 2 hours to obtain a first mounting body.
  • thermocompression bonding was performed at a temperature increase rate of 150 ° C./sec from the lowest melt viscosity attainment temperature of the underfill film to 250 ° C.
  • the bonder head was lowered to the lowest point within the time to raise the temperature from the lowest melt viscosity attainment temperature to 250 ° C. (30 N). Furthermore, it was cured at 150 ° C. for 2 hours to obtain a second mounting body.
  • the temperature at the time of using the flip chip bonder is obtained by measuring the actual temperature of the sample with a thermocouple.
  • peeled PET Polyethylene terephthalate
  • bar coater This was applied to peeled PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce a 50 ⁇ m thick underfill film (cover peeled PET (25 ⁇ m) / underfill). Film (50 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 13 shows the melt viscosity curve of the underfill film of Reference Example 1.
  • Table 1 shows the evaluation results of the underfill film of Reference Example 1.
  • the minimum melt viscosity of the underfill film was 1490 Pa ⁇ s, and the minimum melt viscosity attainment temperature was 113 ° C.
  • the gradient ⁇ of the melt viscosity at 123 ° C. to 133 ° C. was 3100 Pa ⁇ s / ° C.
  • the evaluation of the void of the mounting body produced using the underfill film was “good”, and the solder joint evaluation was “good”.
  • peeled PET Polyethylene terephthalate
  • bar coater This was applied to peeled PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce a 50 ⁇ m thick underfill film (cover peeled PET (25 ⁇ m) / underfill). Film (50 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 13 shows the melt viscosity curve of the underfill film of Reference Example 2.
  • Table 1 shows the evaluation results of the underfill film of Reference Example 2.
  • the minimum melt viscosity of the underfill film was 1330 Pa ⁇ s, and the minimum melt viscosity attainment temperature was 112 ° C.
  • the gradient ⁇ of the melt viscosity at 122 ° C. to 132 ° C. was 1700 Pa ⁇ s / ° C.
  • the evaluation of the void of the mounting body produced using the underfill film was “good”, and the solder joint evaluation was “good”.
  • peeled PET Polyethylene terephthalate
  • bar coater This was applied to peeled PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce a 50 ⁇ m thick underfill film (cover peeled PET (25 ⁇ m) / underfill). Film (50 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 13 shows the melt viscosity curve of the underfill film of Reference Example 3.
  • Table 1 shows the evaluation results of the underfill film of Reference Example 3.
  • the minimum melt viscosity of the underfill film was 1390 Pa ⁇ s, and the minimum melt viscosity attainment temperature was 113 ° C.
  • the slope ⁇ of the melt viscosity at 123 ° C. to 133 ° C. was 900 Pa ⁇ s / ° C.
  • the evaluation of the void of the mounting body produced using the underfill film was “good”, and the solder joint evaluation was “good”.
  • peeled PET Polyethylene terephthalate
  • bar coater This was applied to peeled PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce a 50 ⁇ m thick underfill film (cover peeled PET (25 ⁇ m) / underfill). Film (50 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 13 shows the melt viscosity curve of the underfill film of Reference Example 4.
  • Table 1 shows the evaluation results of the underfill film of Reference Example 4.
  • the minimum melt viscosity of the underfill film was 1950 Pa ⁇ s, and the minimum melt viscosity attainment temperature was 113 ° C.
  • the slope ⁇ of the melt viscosity at 123 ° C. to 133 ° C. was 4000 Pa ⁇ s / ° C.
  • the evaluation of the void of the mounting body produced using the underfill film was “good”, and the evaluation of solder joint was “poor”.
  • peeled PET Polyethylene terephthalate
  • bar coater This was applied to peeled PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce a 50 ⁇ m thick underfill film (cover peeled PET (25 ⁇ m) / underfill). Film (50 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 13 shows the melt viscosity curve of the underfill film of Reference Example 5.
  • Table 1 shows the evaluation results of the underfill film of Reference Example 5.
  • the minimum melt viscosity of the underfill film was 1300 Pa ⁇ s, and the minimum melt viscosity attainment temperature was 115 ° C.
  • the gradient ⁇ of the melt viscosity at 125 ° C. to 135 ° C. was 400 Pa ⁇ s / ° C.
  • the evaluation of the void of the mounting body produced using the underfill film was x, and the solder joint evaluation was o.
  • melt viscosity slope ⁇ exceeds 3100 Pa ⁇ s / ° C. as in Reference Example 4, it is possible to perform voidless mounting, but the first mounting body thermocompression-bonded at a temperature rising rate of 50 ° C./sec, and 150 A defect occurred in the solder joint of the second mounting body thermocompression-bonded at a temperature increase rate of ° C./sec. Further, as in Reference Example 5, when the melt viscosity slope ⁇ was less than 900 Pa ⁇ s / ° C., the solder bonding was good, but in the second mounting body thermocompression bonded at a temperature rising rate of 150 ° C./sec. A void was inherent.
  • a pre-feed type underfill film is manufactured, and then a plurality of upper chips having soldered electrodes using the underfill film, and lower chips having electrodes opposed thereto.
  • a mounting body was produced by collectively pressing, and evaluation of voids, solder joints, and fillets was performed.
  • the elastic modulus of the underfill film, the measurement of the minimum melt viscosity and the gradient of the melt viscosity, the production of the mounting body, chip misalignment at the time of mounting, void, solder bonding, and evaluation of the fillet were performed as follows.
  • the upper chip was a cap type with a size of 5 mm ⁇ 5 mm, a thickness of 200 ⁇ m, and bumps of Cu / SnAg.
  • the bumps had a diameter of 50 ⁇ m, a height of 20 ⁇ m (SnAg 5 ⁇ m), a pitch of 150 ⁇ m, and a number of bumps of 592.
  • the lower chip was a pad type having a size of 10 mm ⁇ 10 mm (divided block type 30 ⁇ m ⁇ 30 ⁇ m), a thickness of 200 ⁇ m, and bumps of Ni / Au.
  • the bumps had a diameter of 50 ⁇ m, a height of 3 ⁇ m, a pitch of 150 ⁇ m, and a number of bumps of 592.
  • the temperature of the underfill film from the lowest melt viscosity reaching temperature to 250 ° C. is increased at a rate of 50 ° C./sec. Crimped. Further, the heat tool of the gang bonding apparatus was lowered to the lowest point within the time required to reach 250 ° C. from the lowest melt viscosity temperature (40 N-10 seconds). Further, it was cured at 150 ° C. for 2 hours to obtain a mounting body shown in FIG.
  • Example 1 A composition similar to the resin composition described in Reference Example 1 was prepared. This composition was applied to release-treated PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce an underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • release-treated PET Polyethylene terephthalate
  • underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 12 shows the melt viscosity curve of the underfill film of Example 1.
  • Table 2 shows the evaluation results of the underfill film of Example 1.
  • the underfill film had an elastic modulus of 2.5 GPa, a minimum melt viscosity of 1490 Pa ⁇ s, and a minimum melt viscosity attainment temperature of 113 ° C.
  • the gradient ⁇ of the melt viscosity at 123 ° C. to 133 ° C. was 3100 Pa ⁇ s / ° C.
  • Example 2 A resin composition similar to the resin composition described in Reference Example 2 was prepared. This composition was applied to release-treated PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce an underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • release-treated PET Polyethylene terephthalate
  • underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 12 shows the melt viscosity curve of the underfill film of Example 2.
  • Table 2 shows the evaluation results of the underfill film of Example 2.
  • the underfill film had an elastic modulus of 2.5 GPa, a minimum melt viscosity of 1330 Pa ⁇ s, and a minimum melt viscosity attainment temperature of 112 ° C.
  • the gradient ⁇ of the melt viscosity at 122 ° C. to 132 ° C. was 1700 Pa ⁇ s / ° C.
  • Example 3 A resin composition similar to the resin composition described in Reference Example 3 was prepared. This composition was applied to release-treated PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce an underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • release-treated PET Polyethylene terephthalate
  • underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 12 shows the melt viscosity curve of the underfill film of Example 3.
  • Table 2 shows the evaluation results of the underfill film of Example 3.
  • the underfill film had an elastic modulus of 2.5 GPa, a minimum melt viscosity of 1390 Pa ⁇ s, and a minimum melt viscosity attainment temperature of 113 ° C.
  • the slope ⁇ of the melt viscosity at 123 ° C. to 133 ° C. was 900 Pa ⁇ s / ° C.
  • the evaluation of chip misalignment when the chip was mounted was ⁇ .
  • the evaluation of the void of the mounting body produced using the underfill film was “good”, the evaluation of the solder joint was “good”, and the evaluation of the fillet was “poor”.
  • composition similar to the resin composition of Reference Example 4 was prepared. This composition was applied to release-treated PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce an underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • release-treated PET Polyethylene terephthalate
  • underfill film having a thickness of 18 ⁇ m (cover release PET (25 ⁇ m) / Underfill film (18 ⁇ m) / base release PET (50 ⁇ m)).
  • FIG. 12 shows the melt viscosity curve of the underfill film of Comparative Example 1.
  • Table 1 shows the evaluation results of the underfill film of Comparative Example 1.
  • the underfill film had an elastic modulus of 2.5 GPa, a minimum melt viscosity of 1950 Pa ⁇ s, and a minimum melt viscosity attainment temperature of 113 ° C.
  • the slope ⁇ of the melt viscosity at 123 ° C. to 133 ° C. was 4000 Pa ⁇ s / ° C.
  • Comparative Example 2 A similar resin composition of the resin composition described in Comparative Example 5 was prepared. This resin composition was applied to peeled PET (Polyethylene terephthalate) using a bar coater and dried in an oven at 80 ° C. for 3 minutes to produce an underfill film having a thickness of 18 ⁇ m (cover peeled PET (25 ⁇ m)). / Underfill film (18 ⁇ m) / Base peeled PET (50 ⁇ m)).
  • FIG. 12 shows the melt viscosity curve of the underfill film of Comparative Example 2.
  • Table 2 shows the evaluation results of the underfill film of Comparative Example 2.
  • the underfill film had an elastic modulus of 2.5 GPa, a minimum melt viscosity of 1300 Pa ⁇ s, and a minimum melt viscosity attainment temperature of 115 ° C.
  • the gradient ⁇ of the melt viscosity at 125 ° C. to 135 ° C. was 400 Pa ⁇ s / ° C.

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Abstract

　複数の半導体チップを一括圧着した場合でも、ボイドレス実装及び良好なハンダ接合性が得られる半導体装置の製造方法及びアンダーフィルフィルムを提供する。　ハンダ付き電極が形成された複数の半導体チップを、アンダーフィルフィルムを介してハンダ付き電極と対向する対向電極が形成された電子部品に搭載する搭載工程と、複数の半導体チップと電子部品とを、アンダーフィルフィルムを介して一括圧着する圧着工程とを有する。アンダーフィルフィルムは、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下である。

Description

半導体装置の製造方法、及びアンダーフィルフィルム
　本発明は、基板又はウエハに半導体チップを搭載する半導体装置の製造方法、及びこれに用いられるアンダーフィルフィルムに関する。本出願は、日本国において２０１５年２月６日に出願された日本特許出願番号特願２０１５－０２２６７２を基礎として優先権を主張するものであり、この出願は参照されることにより、本出願に援用される。
　従来の一般的な液状のアンダーフィル材では、薄膜化した半導体チップの実装や３Ｄ実装などが困難となっている。このため、半導体ＩＣ（Integrated Circuit）電極と基板電極とを金属接合又は圧接接合する前にアンダーフィルフィルムを基板上に貼り付ける「先供給型アンダーフィルフィルム（ＰＵＦ：Pre-applied Underfill Film）」の使用が検討されている。
　この先供給型アンダーフィルフィルムを使用した搭載方法は、例えば、以下のように行われる（例えば、特許文献１参照。）。
　工程Ａ：ウエハにアンダーフィルフィルムを貼り付け、ダイシングして半導体チップを得る。
　工程Ｂ：基板上で半導体チップの位置合わせを行う。
　工程Ｃ：高温・高圧により半導体チップと基板を圧着し、ハンダバンプの金属結合による導通確保、及びアンダーフィルフィルムの硬化による半導体チップと基板の接着を行う。
　このような実装方法を用いて１チップ当たりの生産タクトを向上させる方法として、マルチヘッド、一括圧着などが挙げられる。しかしながら、マルチヘッドの装置は価格が高額であり、１チップ当たりのコストが増加してしまう。また、一括圧着では、ボンダー（ヒートツール）による温度コントロールが困難であるため、チップの位置によって昇温速度に差が生じてしまい、バンプ間の樹脂噛み込みなどの接合不良やボイドが発生することがあった。
特開２００５－２８７３４号公報
　本発明は、このような従来の実情に鑑みて提案されたものであり、複数の半導体チップを一括圧着した場合でも、ボイドレス実装及び良好なハンダ接合性が得られる半導体装置の製造方法及びアンダーフィルフィルムを提供する。
　本発明者は、鋭意検討を行った結果、所定の最低溶融粘度及び最低溶融粘度到達温度より高い温度において所定の溶融粘度の傾きを有するアンダーフィルフィルムを用いることにより、複数の半導体チップを一括圧着した場合でも、ボイドレス実装及び良好なハンダ接合性が得られることを見出した。
　すなわち、本発明に係る半導体装置の製造方法は、ハンダ付き電極が形成された複数の半導体チップを、アンダーフィルフィルムを介して前記ハンダ付き電極と対向する対向電極が形成された電子部品に搭載する搭載工程と、前記複数の半導体チップと前記電子部品とを、前記アンダーフィルフィルムを介して一括圧着する圧着工程とを有し、前記アンダーフィルフィルムが、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下であることを特徴とする。
　また、本発明は、複数の半導体チップと電子部品とを、一括圧着するためのアンダーフィルフィルムであって、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下であることを特徴とする。
　本発明によれば、所定の最低溶融粘度及び最低溶融粘度到達温度より高い温度において所定の溶融粘度の傾きを有するアンダーフィルフィルムを用いることにより、複数の半導体チップを一括圧着した場合でも、チップ位置による昇温温度差の影響を低減することができ、ボイドレス実装及び良好なハンダ接合性が得られる。
図１は、第１例の搭載前の半導体チップと回路基板とを模式的に示す断面図である。 図２は、第２例の搭載前の半導体チップと回路基板とを模式的に示す断面図である。 図３は、搭載時の半導体チップと回路基板とを模式的に示す断面図である。 図４は、熱圧着後の半導体チップと回路基板とを模式的に示す断面図である。 図５は、ボンディング条件の一例を示すグラフである。 図６は、図４に示すボンディング条件に適合したアンダーフィルフィルムの溶融粘度カーブを示すグラフである。 図７は、本実施の形態における半導体装置の製造方法を示すフローチャートである。 図８は、ウエハ上にアンダーフィルフィルムを貼り付ける工程を模式的に示す斜視図である。 図９は、ウエハをダイシングする工程を模式的に示す斜視図である。 図１０は、半導体チップをピックアップする工程を模式的に示す斜視図である。 図１１は、複数の半導体チップを一括圧着する工程を模式的に示す断面図である。 図１２は、複数の半導体チップを一括圧着する工程を模式的に示す斜視図である。 図１３は、アンダーフィルフィルムのサンプルの溶融粘度カーブを示すグラフである。
　以下、本発明の実施の形態について、下記順序にて詳細に説明する。
１．アンダーフィルフィルム
２．半導体装置の製造方法
３．実施例
　＜１．アンダーフィルフィルム＞
　本実施の形態におけるアンダーフィルフィルムは、複数の半導体チップと電子部品とを、一括圧着するためのものであって、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下である。ここで、電子部品としては、複数の半導体チップを搭載するボトムチップ、回路基板などが挙げられる。
　図１及び図２は、夫々第１例及び第２例の搭載前の半導体チップと回路基板とを模式的に示す断面図である。また、図３は、搭載時の半導体チップと回路基板とを模式的に示す断面図、及び、図４は、熱圧着後の半導体チップと回路基板とを模式的に示す断面図である。
　図１に示すように、アンダーフィルフィルム２０は、ハンダ付き電極１３が形成された半導体チップ１０の電極面に予め貼り合わされて使用される。又は、図２に示すように、アンダーフィルフィルム２０は、ハンダ付き電極１３と対向する対向電極３２が形成された回路基板３０の電極面に予め貼り合わされて使用されても良い。そして、図３及び図４に示すように、アンダーフィルフィルム２０が硬化した接着層２１により複数の半導体チップ１０が回路基板３０に接合される。
　半導体チップ１０は、シリコンなどの半導体１１表面に集積回路が形成され、バンプと呼ばれる接続用のハンダ付き電極を有する。ハンダ付き電極は、銅などからなる電極１２上にハンダ１３を接合したものであり、電極１２の厚みとハンダ１３の厚みとを合計した厚みを有する。
　ハンダとしては、Ｓｎ－３７Ｐｂ共晶ハンダ（融点１８３℃）、Ｓｎ－Ｂｉハンダ（融点１３９℃）、Ｓｎ－３．５Ａｇ（融点２２１℃）、Ｓｎ－３．０Ａｇ－０．５Ｃｕ（融点２１７℃）、Ｓｎ－５．０Ｓｂ（融点２４０℃）などを用いることができる。
　回路基板３０は、例えばリジット基板、フレキシブル基板などの基材３１に回路が形成されている。また、半導体チップ１０が搭載される実装部には、半導体チップ１０のハンダ付き電極と対向する位置に所定の厚みを有する対向電極３２が形成されている。
　アンダーフィルフィルム２０は、膜形成樹脂と、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有する。
　膜形成樹脂は、重量平均分子量が１０×１０４以上の高分子量樹脂に相当し、フィルム形成性の観点から、１０×１０４～１００×１０４の重量平均分子量であることが好ましい。膜形成樹脂としては、アクリルゴムポリマー、フェノキシ樹脂、エポキシ樹脂、変性エポキシ樹脂、ウレタン樹脂等の種々の樹脂を用いることができる。これらの膜形成樹脂は、１種を単独で用いても、２種類以上を組み合わせて用いても良い。これらの中でも、本実施の形態では、膜強度及び接着性の観点から、グリシジル基を有するアクリルゴムポリマーが好適に用いられる。グリシジル基を有するアクリルゴムポリマーの市販品としては、例えば商品名「テイサンレジンＳＧ－Ｐ３」(ナガセケムテック（株))などが挙げられる。
　エポキシ樹脂としては、例えば、テトラキス(グリシジルオキシフェニル)エタン、テトラキス（グリシジルオキシメチルフェニル）エタン、テトラキス（グリシジルオキシフェニル）メタン、トリキス（グリシジルオキシフェニル）エタン、トリキス（グリシジルオキシフェニル）メタン等のグリシジルエーテル型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂、グリシジルアミン型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂、スピロ環型エポキシ樹脂、ナフタレン型エポキシ樹脂、ビフェニル型エポキシ樹脂、テルペン型エポキシ樹脂、テトラブロムビスフェノールＡ型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、α－ナフトールノボラック型エポキシ樹脂、臭素化フェノールノボラック型エポキシ樹脂などを挙げることができる。これらのエポキシ樹脂は、１種を単独で用いても、２種類以上を組み合わせて用いても良い。これらの中でも、本実施の形態では、高接着性、耐熱性の点から、グリシジルエーテル型エポキシ樹脂を用いることが好ましい。グリシジルエーテル型エポキシ樹脂の市販品としては、例えば商品名「ＪＥＲ１０３１Ｓ」(三菱化学（株))などが挙げられる。
　酸無水物は、ハンダ表面の酸化膜を除去するフラックス機能を有するため、優れた接続信頼性を得ることができる。酸無水物としては、例えばヘキサヒドロ無水フタル酸、メチルテトラヒドロ無水フタル酸などの脂環式酸無水物、テトラプロペニル無水コハク酸、ドデセニル無水コハク酸、などの脂肪族酸無水物、無水フタル酸、無水トリメリット酸、無水ピロメリット酸などの芳香族酸無水物などを挙げることができる。これらのエポキシ硬化剤は、１種を単独で用いても、２種類以上を組み合わせて用いても良い。これらのエポキシ硬化剤の中でもこれらのうちハンダ接続性の点から、脂環式酸無水物を用いることが好ましい。脂環式酸無水物の市販品としては、例えば商品名「リカシッドＨＮＡ－１００」(新日本理化（株))などが挙げられる。
　また、硬化促進剤を添加することが好ましい。硬化促進剤の具体例としては、１，８－ジアザビシクロ（５，４，０）ウンデセン－７塩（ＤＢＵ塩）、２－メチルイミダゾール、２－エチルイミダゾール、２－エチル－４－メチルイミダゾールなどのイミダゾ－ル類、２－（ジメチルアミノメチル）フェノールなどの第３級アミン類、トリフェニルホスフィンなどのホスフィン類、オクチル酸スズなどの金属化合物などが挙げられる。
　アクリル樹脂としては、単官能（メタ）アクリレート、２官能以上の（メタ）アクリレートを使用可能である。単官能（メタ）アクリレートとしては、メチル（メタ）アクリレート、エチル（メタ）アクリレート、ｎ－プロピル（メタ）アクリレート、ｉ－プロピル（メタ）アクリレート、ｎ－ブチル（メタ）アクリレート等が挙げられる。２官能以上の（メタ）アクリレートとしては、フルオレン系アクリレート、ビスフェノールＦ―ＥＯ変性ジ（メタ）アクリレート、ビスフェノールＡ―ＥＯ変性ジ（メタ）アクリレート、トリメチロールプロパンＰＯ変性（メタ）アクリレート、多官能ウレタン（メタ）アクリレート等を挙げることができる。これらのアクリル樹脂は、単独で用いてもよいし、２種以上を組み合わせて用いてもよい。これらの中でも、本実施の形態では、フルオレン系アクリレートが好適に用いられる。フルオレン系アクリレートの市販品としては、例えば商品名「オクゾールＥＡ－０２００」(大阪有機化学（株))などが挙げられる。
　有機過酸化物としては、例えば、パーオキシケタール、パーオキシエステル、ハイドロパーオキサイド、ジアルキルパーオキサイド、ジアシルパーオキサイド、パーオキシジカーボネート等を挙げることができる。これらの有機過酸化物は、単独で用いてもよいし、２種以上を組み合わせて用いてもよい。これらの中でも、本実施の形態では、パーオキシケタールが好適に用いられる。パーオキシケタールの市販品としては、例えば商品名「パーヘキサＶ」(日油（株))などが挙げられる。
　また、その他の添加組成物として、無機フィラーを含有することが好ましい。無機フィラーを含有することにより、圧着時における樹脂層の流動性を調整することができる。無機フィラーとしては、シリカ、タルク、酸化チタン、炭酸カルシウム、酸化マグネシウム等を用いることができる。
　さらに、必要に応じて、エポキシ系、アミノ系、メルカプト・スルフィド系、ウレイド系などのシランカップリング剤を添加してもよい。
　このように硬化反応の比較的遅いエポキシ系と、硬化反応の比較的速いアクリル系とを併用することにより、ボンディング条件における昇温速度のマージンが大きくなるため、複数の半導体チップを一括圧着させた場合であっても、チップ位置による昇温速度の差の影響を軽減し、ボイドレス実装及び良好なハンダ接合性を実現することが可能となる。
　図５は、ボンディング条件の一例を示すグラフである。このボンディング条件は、温度Ｔ１から２５０℃まで５０℃／ｓｅｃ以上１５０℃／ｓｅｃ以下の昇温速度で昇温させるものである。ここで、温度Ｔ１は、アンダーフィルフィルムの最低溶融粘度と略同一であることが好ましく、５０℃以上１５０℃以下であることが好ましい。
　また、図６は、図５に示すボンディング条件に適合したアンダーフィルフィルムの溶融粘度カーブを示すグラフである。この溶融粘度カーブは、レオメータを用いて、５℃／ｍｉｎ、１Ｈｚの条件でアンダーフィルフィルムを測定したものである。
　このボンディング条件に適合したアンダーフィルフィルムの最低溶融粘度ηは、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下である。これにより、加熱圧着時のボイドの発生を抑制することができる。また、アンダーフィルフィルムの最低溶融粘度到達温度は、１２５℃以下であることが好ましい。また、アンダーフィルフィルムの弾性率は１ＧＰａ以上１０ＧＰａ以下であることが好ましい。
　また、アンダーフィルフィルムの最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きは、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下である。これにより、５０℃／ｓｅｃ以上１５０℃／ｓｅｃ以下の昇温速度で昇温させるボンディング条件でも、ボイドレス実装及び良好なハンダ接合性を実現することができる。すなわち、アンダーフィルフィルムは、昇温速度のマージンが大きく、複数の半導体チップを一括圧着させた場合であっても、チップ位置による昇温速度の差の影響を軽減することができる。また、アンダーフィルフィルムは、チップ側面のフィレットの形成を抑制することができるため、隣接するチップ間隔を小さくすることが可能となる。また、フィレットレスにより、ツールへの付着を防止し、緩衝材を不要とすることができる。
　また、最低溶融粘度到達温度は、ボンディング条件の温度Ｔ１と略同一であることが好ましい。これによりボンディング条件に合致した硬化挙動となるアンダーフィルフィルムを得ることができる。
　また、アクリル樹脂と有機過酸化物との合計質量と、エポキシ樹脂と酸無水物との合計質量との比は、好ましくは７：３～４：６であり、より好ましくは７：３～５：５である。これにより、ボンディング条件における昇温速度のマージンが大きくなるため、複数の半導体チップを一括圧着させた場合であっても、チップ位置による昇温速度の差の影響を軽減することができ、ボイドレス実装及び良好なハンダ接合性を実現することができる。
　次に、前述したアンダーフィルフィルムの製造方法について説明する。先ず、膜形成樹脂と、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有する接着剤組成物を溶剤に溶解させる。溶剤としては、トルエン、酢酸エチルなど、又はこれらの混合溶剤を用いることができる。樹脂組成物を調整後、バーコーター、塗布装置などを用いて剥離基材上に塗布する。
　剥離基材は、例えば、シリコーンなどの剥離剤をＰＥＴ（Poly Ethylene Terephthalate）、ＯＰＰ（Oriented Polypropylene）、ＰＭＰ（Poly-4-methylpentene-1）、ＰＴＦＥ（Polytetrafluoroethylene）などに塗布した積層構造からなり、組成物の乾燥を防ぐとともに、組成物の形状を維持するものである。
　次に、剥離基材上に塗布された樹脂組成物を熱オーブン、加熱乾燥装置などにより乾燥させる。これにより、所定の厚さの先供給型アンダーフィルフィルムを得ることができる。
　＜２．半導体装置の製造方法＞
　次に、前述したアンダーフィルフィルムを用いた半導体装置の製造方法について説明する。本実施の形態における半導体装置の製造方法は、ハンダ付き電極が形成された複数の半導体チップを、アンダーフィルフィルムを介してハンダ付き電極と対向する対向電極が形成された電子部品に搭載する搭載工程と、複数の半導体チップと電子部品とを、アンダーフィルフィルムを介して一括圧着する圧着工程とを有する。本法で使用するアンダーフィルフィルムは、前述のように、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下であるものである。
　図７は、半導体装置の製造方法を示すフローチャートである。図７に示すように、本実施の形態における半導体装置の製造方法は、アンダーフィルフィルム貼付工程Ｓ１と、ダイシング工程Ｓ２と、半導体チップ搭載工程Ｓ３と、熱圧着工程Ｓ４とを有する。
　図８は、ウエハ上にアンダーフィルフィルムを貼り付ける工程を模式的に示す斜視図である。図８に示すように、アンダーフィルフィルム貼付工程Ｓ１では、ウエハ１の直径よりも大きな直径を有するリング状又は枠状のフレームを有する治具３によりウエハ１を固定し、ウエハ１上にアンダーフィルフィルム２を貼り付ける。アンダーフィルフィルム２は、ウエハ１のダイシング時にウエハ１を保護・固定し、ピックアップ時に保持するダイシングテープとして機能する。なお、ウエハ１には多数のＩＣ（Integrated Circuit）が作り込まれ、ウエハ１の接着面には、スクライブラインによって区分される半導体チップ１０毎にハンダ付き電極が設けられている。
　図９は、ウエハをダイシングする工程を模式的に示す斜視図である。図９に示すように、ダイシング工程Ｓ２では、ブレード４をスクライブラインに沿って押圧してウエハ１を切削し、個々の半導体チップに分割する。
　図１０は、半導体チップをピックアップする工程を模式的に示す斜視図である。図１０に示すように、各アンダーフィルフィルム付き半導体チップ１０は、アンダーフィルフィルムに保持されてピックアップされる。
　半導体チップ搭載工程Ｓ３では、図３に示すように、アンダーフィルフィルム付き半導体チップ１０と回路基板３０とをアンダーフィルフィルムを介して配置する。また、アンダーフィルフィルム付き半導体チップ１０をハンダ付き電極と対向電極３２とが対向するように位置合わせして配置する。そして、加熱ボンダーによって、アンダーフィルフィルムに流動性は生じるが、本硬化は生じない程度の所定の温度、圧力、時間の条件で加熱押圧し、搭載する。
　搭載時の温度条件は、３０℃以上１５５℃以下であることが好ましい。また、圧力条件は６０Ｎ以下であることが好ましく、より好ましくは５０Ｎ以下である。また、時間条件は０．５秒以上１０秒以下であることが好ましく、より好ましくは０．１秒以上３．０秒以下である。これにより、ハンダ付き電極が溶融せずに回路基板３０側の電極と接している状態とすることができ、アンダーフィルフィルムが完全硬化していない状態とすることができる。また、低い温度で固定するため、ボイドの発生を抑制し、半導体チップ１０へのダメージを低減することができる。
　次の熱圧着工程Ｓ４では、ギャングボンディング装置を用いて、複数の半導体チップ１０のハンダ付き電極のハンダを溶融させて金属結合を形成させるとともに、アンダーフィルフィルムを完全硬化させ、一括圧着する。
　図１１及び図１２は、それぞれ複数の半導体チップを一括圧着する工程を模式的に示す断面図及び斜視図である。図１１及び図１２では、ステージ５０上に電子部品としてボトムチップ４１が３×３配列されている。そして、半導体チップ１０をそれぞれボトムチップ４１上に搭載し、３×３の半導体チップをヒートツール６０で一括圧着することにより、アンダーフィルフィルム２０が硬化した接着層２１により複数の半導体チップ１０がボトムチップ４１に接合される。
　一括圧着時の温度条件は、１５０℃以上３００℃以下であることが好まし、より好ましくは２３０℃以上２８０℃以下である。また、圧力条件は６０Ｎ以下であることが好ましく、より好ましくは５０Ｎ以下である。また、時間条件は０．１秒以上６０秒以下であることが好ましく、より好ましくは５秒以上２０秒以下である。これにより、ハンダ付き電極と基板電極とを金属結合させるとともに、アンダーフィルフィルムを完全硬化させ、複数の半導体チップ１０の電極と回路基板３０の電極とを電気的、機械的に一括圧着させることができる。
　このように所定の最低溶融粘度及び最低溶融粘度到達温度より高い温度において所定の溶融粘度の傾きを有するアンダーフィルフィルムを用いることにより、複数の半導体チップを一括圧着した場合でも、ボイドレス実装及び良好なハンダ接合性を実現することができる。
　なお、前述の実施の形態では、アンダーフィルフィルムをダイシングテープとして機能させることとしたが、これに限られるものではなく、ダイシングテープを別に用い、ダイシング後にアンダーフィルフィルムを使用してフリップチップ実装を行ってもよい。
　［他の実施の形態］
　また、本技術は、半導体チップに設けた小さな孔に金属を充填することによって、サンドイッチ状に積み重ねた複数のチップ基板を電気的に接続するＴＳＶ（Through Silicon Via）技術にも適用可能である。
　すなわち、ハンダ付き電極が形成された第１の面と、第１の面の反対側にハンダ付き電極と対向する対向電極が形成された第２の面を有する複数のチップ基板を積層する半導体装置の製造方法にも適用可能である。
　この場合、第１のチップ基板の第１の面側にアンダーフィルフィルムを貼り付けた状態で、第２のチップ基板の第２の面に搭載する。その後、第１のチップ基板の第１の面と第２のチップ基板の第２の面とをハンダ付き電極のハンダの融点以上の温度で熱圧着することにより、複数のチップ基板を積層した半導体装置を得ることができる。
　＜３．実施例＞
　以下、本発明の実施例について説明する。本実施例では、先供給型のアンダーフィルフィルムを作製し、次いで、アンダーフィルフィルムを用いてハンダ付き電極を有する複数の上チップと、これに対向する電極を有する下チップとを図１１及び図１２に示すようなギャングボンディング装置を使って、一括圧着させて実装体を作製し、ボイド、ハンダ接合状態、及びフィレットについて評価した。
　なお、その前に、参考例として、アンダーフィルフィルムを用いてハンダ付き電極を有するＩＣチップと、これに対向する電極を有するＩＣ基板とを１ヘッドに対して１チップずつ接続させて実装体を作製し、ボイド及びハンダ接合状態を評価したものを説明する。
　＜３．１　参考例＞
　まず、参考例として、アンダーフィルフィルムを用いて１ヘッドに対して１チップずつ接続させて実装体を作製し、ボイド及びハンダ接合状態を評価した。アンダーフィルフィルムの最低溶融粘度及び溶融粘度の傾きの測定、実装体の作製、ボイドの評価、ハンダ接合の評価は、次のように行った。
　［最低溶融粘度の測定、及び溶融粘度の傾きの算出］
　３．１の実施例と同様、各アンダーフィルフィルムについて、レオメータ（ＴＡ社製ＡＲＥＳ）を用いて、５℃／ｍｉｎ、１Ｈｚの条件でサンプルの最低溶融粘度及び最低溶融粘度到達温度を測定した。そして、最低溶融粘度到達温度＋１０℃～最低溶融粘度到達温度＋２０℃の温度範囲における溶融粘度の傾きを算出した。
　［実装体の作製］
　アンダーフィルフィルムをウエハ上にプレス機にて、５０℃－０．５ＭＰａの条件で貼り合わせ、ダンシングしてハンダ付き電極を有するＩＣチップを得た。
　ＩＣチップは、その大きさが７ｍｍ□、厚み２００μｍであり、厚み２０μｍのＣｕからなる電極の先端に厚み１６μｍのハンダ（Ｓｎ－３．５Ａｇ、融点２２１℃）が形成されたペリフェラル配置のバンプ（φ３０μｍ、８５μｍピッチ、２８０ピン）を有するものであった。
　また、これに対向するＩＣ基板は、同様に、その大きさは７ｍｍ□、厚み２００μｍであり、厚み２０μｍのＣｕからなる電極が形成されたペリフェラル配置のバンプ（φ３０μｍ、８５μｍピッチ、２８０ピン）を有するものであった。
　次に、フリップチップボンダーを用いて、６０℃－０．５秒－３０Ｎの条件でＩＣ基板上にＩＣチップを搭載した。
　その後、図５に示すボンディング条件のように、フリップチップボンダーを用いて、アンダーフィルフィルムの最低溶融粘度到達温度から２５０℃まで５０℃／ｓｅｃの昇温速度で熱圧着した。なお、最低溶融粘度到達温度から２５０℃に昇温する時間内にボンダーヘッドを最下点まで下降させた（３０Ｎ）。さらに、１５０℃－２時間の条件でキュアし、第１の実装体を得た。また、同様に、フリップチップボンダーを用いて、アンダーフィルフィルムの最低溶融粘度到達温度から２５０℃まで１５０℃／ｓｅｃの昇温速度で熱圧着した。なお、最低溶融粘度到達温度から２５０℃に昇温する時間内にボンダーヘッドを最下点まで下降させた（３０Ｎ）。さらに、１５０℃－２時間の条件でキュアし、第２の実装体を得た。なお、フリップチップボンダー使用時における温度は、熱電対によりサンプルの実温を測定したものである。
　［ボイドの評価］
　５０℃／ｓｅｃの昇温速度で熱圧着した第１の実装体、及び１５０℃／ｓｅｃの昇温速度で熱圧着した第２の実装体をＳＡＴ（Scanning Acoustic Tomograph, 超音波映像装置）を用いて観察した。第１の実装体及び第２の実装体の両者ともボイドが発生していない場合を「○」と評価し、いずれかの実装体にボイドが発生している場合を「×」と評価した。一般的に、ボイドが生じると、長期信頼性に悪影響を及ぼす可能性が高くなる。
　［ハンダ接合の評価］
　５０℃／ｓｅｃの昇温速度で熱圧着した第１の実装体、及び１５０℃／ｓｅｃの昇温速度で熱圧着した第２の実装体のサンプルを切断し、断面研磨を行い、ＩＣチップの電極とＩＣ基板の電極との間のハンダの状態をＳＥＭ（Scanning Electron Microscope）観察した。第１の実装体及び第２の実装体の両者ともハンダ接続、ハンダ濡れ共に良好な状態を「○」と評価し、いずれかの実装体のハンダ接続、又はハンダ濡れが不十分な状態を「×」と評価した。
　［参考例１］
　膜形成樹脂としてのアクリルゴムポリマー（品名：テイサンレジンＳＧ－Ｐ３、ナガセケムテックス社製）を４０質量部、エポキシ樹脂（品名：ＪＥＲ１０３１Ｓ、三菱化学社製）を２０質量部、酸無水物（品名：リカシッドＨＮＡ－１００、新日本理化社製)を１０質量部、硬化促進剤としてのイミダゾール（品名：Ｕ－ＣＡＴ－５００２、サンアプロ社製）を１質量部、アクリル樹脂（品名：オクゾールＥＡ－０２００、大阪有機化学社製）を６８質量部、有機過酸化物（品名：パーヘキサＶ、日油社製）を２質量部、フィラー（品名：アエロジルＲ２０２、日本アエロジル社製）を１５質量部配合し、アクリル／エポキシが７０／３０の樹脂組成物を調製した。これを、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み５０μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（５０μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１３に、参考例１のアンダーフィルフィルムの溶融粘度カーブを示す。また、表１に、参考例１のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの最低溶融粘度は１４９０Ｐａ・ｓであり、最低溶融粘度到達温度は１１３℃であった。また、１２３℃～１３３℃における溶融粘度の傾きφは３１００Ｐａ・ｓ／℃であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は○であった。
　［参考例２］
　膜形成樹脂としてのアクリルゴムポリマー（品名：テイサンレジンＳＧ－Ｐ３、ナガセケムテックス社製）を４０質量部、エポキシ樹脂（品名：ＪＥＲ１０３１Ｓ、三菱化学社製）を３０質量部、酸無水物（品名：リカシッドＨＮＡ－１００、新日本理化社製)を２０質量部、硬化促進剤としてのイミダゾール（品名：Ｕ－ＣＡＴ－５００２、サンアプロ社製）を１質量部、アクリル樹脂（品名：オクゾールＥＡ－０２００、大阪有機化学社製）を４９質量部、有機過酸化物（品名：パーヘキサＶ、日油社製）を１質量部、フィラー（品名：アエロジルＲ２０２、日本アエロジル社製）を１５質量部配合し、アクリル／エポキシが５０／５０の樹脂組成物を調製した。これを、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み５０μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（５０μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１３に、参考例２のアンダーフィルフィルムの溶融粘度カーブを示す。また、表１に、参考例２のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの最低溶融粘度は１３３０Ｐａ・ｓであり、最低溶融粘度到達温度は１１２℃であった。また、１２２℃～１３２℃における溶融粘度の傾きφは１７００Ｐａ・ｓ／℃であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は○であった。
　［参考例３］
　膜形成樹脂としてのアクリルゴムポリマー（品名：テイサンレジンＳＧ－Ｐ３、ナガセケムテックス社製）を４０質量部、エポキシ樹脂（品名：ＪＥＲ１０３１Ｓ、三菱化学社製）を４５質量部、酸無水物（品名：リカシッドＨＮＡ－１００、新日本理化社製)を１５質量部、硬化促進剤としてのイミダゾール（品名：Ｕ－ＣＡＴ－５００２、サンアプロ社製）を１質量部、アクリル樹脂（品名：オクゾールＥＡ－０２００、大阪有機化学社製）を３９質量部、有機過酸化物（品名：パーヘキサＶ、日油社製）を１質量部、フィラー（品名：アエロジルＲ２０２、日本アエロジル社製）を１５質量部配合し、アクリル／エポキシが５０／５０の樹脂組成物を調製した。これを、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み５０μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（５０μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１３に、参考例３のアンダーフィルフィルムの溶融粘度カーブを示す。また、表１に、参考例３のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの最低溶融粘度は１３９０Ｐａ・ｓであり、最低溶融粘度到達温度は１１３℃であった。また、１２３℃～１３３℃における溶融粘度の傾きφは９００Ｐａ・ｓ／℃であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は○であった。
　［参考例４］
　膜形成樹脂としてのアクリルゴムポリマー（品名：テイサンレジンＳＧ－Ｐ３、ナガセケムテックス社製）を４０質量部、エポキシ樹脂（品名：ＪＥＲ１０３１Ｓ、三菱化学社製）を１３質量部、酸無水物（品名：リカシッドＨＮＡ－１００、新日本理化社製)を７質量部、硬化促進剤としてのイミダゾール（品名：Ｕ－ＣＡＴ－５００２、サンアプロ社製）を１質量部、アクリル樹脂（品名：オクゾールＥＡ－０２００、大阪有機化学社製）を７６質量部、有機過酸化物（品名：パーヘキサＶ、日油社製）を４質量部、フィラー（品名：アエロジルＲ２０２、日本アエロジル社製）を１５質量部配合し、アクリル／エポキシが８０／２０の樹脂組成物を調製した。これを、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み５０μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（５０μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１３に、参考例４のアンダーフィルフィルムの溶融粘度カーブを示す。また、表１に、参考例４のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの最低溶融粘度は１９５０Ｐａ・ｓであり、最低溶融粘度到達温度は１１３℃であった。また、１２３℃～１３３℃における溶融粘度の傾きφは４０００Ｐａ・ｓ／℃であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は×であった。
　［参考例５］
　膜形成樹脂としてのアクリルゴムポリマー（品名：テイサンレジンＳＧ－Ｐ３、ナガセケムテックス社製）を４０質量部、エポキシ樹脂（品名：ＪＥＲ１０３１Ｓ、三菱化学社製）を４０質量部、酸無水物（品名：リカシッドＨＮＡ－１００、新日本理化社製)を３０質量部、硬化促進剤としてのイミダゾール（品名：Ｕ－ＣＡＴ－５００２、サンアプロ社製）を１質量部、アクリル樹脂（品名：オクゾールＥＡ－０２００、大阪有機化学社製）を２９質量部、有機過酸化物（品名：パーヘキサＶ、日油社製）を１質量部、フィラー（品名：アエロジルＲ２０２、日本アエロジル社製）を１５質量部配合し、アクリル／エポキシが３０／７０の樹脂組成物を調製した。これを、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み５０μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（５０μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１３に、参考例５のアンダーフィルフィルムの溶融粘度カーブを示す。また、表１に、参考例５のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの最低溶融粘度は１３００Ｐａ・ｓであり、最低溶融粘度到達温度は１１５℃であった。また、１２５℃～１３５℃における溶融粘度の傾きφは４００Ｐａ・ｓ／℃であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は×であり、ハンダ接合評価は○であった。
Figure JPOXMLDOC01-appb-T000001
　参考例４のように溶融粘度の傾きφが３１００Ｐａ・ｓ／℃を超えた場合、ボイドレス実装は可能であるが、５０℃／ｓｅｃの昇温速度で熱圧着した第１の実装体、及び１５０℃／ｓｅｃの昇温速度で熱圧着した第２の実装体の両者のハンダ接合に不良が発生した。また、参考例５のように溶融粘度の傾きφが９００Ｐａ・ｓ／℃未満の場合、ハンダ接合は良好であったが、１５０℃／ｓｅｃの昇温速度で熱圧着した第２の実装体においてボイドが内在した。
　一方、参考例１～３のように溶融粘度の傾きφが９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下の場合、５０℃／ｓｅｃ以上１５０℃／ｓｅｃ以下の昇温速度のボンディング条件でも、ボイドレス及び良好なハンダ接合を実現できた。
　＜３．２　実施例（一括圧着）＞
　上述したとおり、本実施例では、先供給型のアンダーフィルフィルムを作製し、次いで、アンダーフィルフィルムを用いてハンダ付き電極を有する複数の上チップと、これに対向する電極を有する下チップとを図１１及び図１２に示すようなギャングボンディング装置を用い、一括圧着させて実装体を作製し、ボイド、ハンダ接合状態、及びフィレットについて評価した。その際のアンダーフィルフィルムの弾性率、最低溶融粘度及び溶融粘度の傾きの測定、実装体の作製、搭載時のチップズレ、ボイド、ハンダ接合、及びフィレットの評価は、次のように行った。
　［弾性率、最低溶融粘度の測定、及び溶融粘度の傾きの算出］
　各アンダーフィルフィルムについて、レオメータ（ＴＡ社製ＡＲＥＳ）を用いて、５℃／ｍｉｎ、１Ｈｚの条件でサンプルの弾性率、最低溶融粘度及び最低溶融粘度到達温度を測定した。そして、最低溶融粘度到達温度＋１０℃～最低溶融粘度到達温度＋２０℃の温度範囲における溶融粘度の傾きを算出した。
　［実装体の作製］
　まず、アンダーフィルフィルムをウエハ上にプレス機にて、５０℃－０．５ＭＰａの条件で貼り合わせ、ダンシングしてハンダ付き電極を有する上チップを得た。
　上チップは、サイズが５ｍｍ×５ｍｍ、厚みが２００μｍ、バンプがＣｕ／ＳｎＡｇのキャップタイプのものを使用した。バンプは、直径が５０μｍ、高さが２０μｍ（ＳｎＡｇ５μｍ）、ピッチが１５０μｍ、バンプ数が５９２であった。
　また、下チップは、サイズが１０ｍｍ×１０ｍｍ（分割ブロックタイプ３０μｍ×３０μｍ）、厚みが２００μｍ、バンプがＮｉ／Ａｕのパッドタイプのものを使用した。バンプは、直径が５０μｍ、高さが３μｍ、ピッチが１５０μｍ、バンプ数が５９２であった。
　次に、フリップチップボンダーを用いて、８０℃－２秒－４０Ｎの条件で下チップ上に９個の上チップを搭載した。
　その後、図１１及び図１２に示すようなギャングボンディング装置を用い、図５に示すボンディング条件のように、アンダーフィルフィルムの最低溶融粘度到達温度から２５０℃まで５０℃／ｓｅｃの昇温速度で一括圧着した。また、最低溶融粘度到達温度から２５０℃に到達する時間内に、ギャングボンディング装置のヒートツールを最下点まで下降させた（４０Ｎ－１０秒）。更に、１５０℃－２時間の条件でキュアし、図３に示す実装体を得た。
　［チップズレの評価］
　下チップ上に９個の上チップを一括圧着した際のチップズレを、Ｘ線装置にて目視し、チップズレが５μｍ以下で実質的に確認できない場合を「○」と評価し、他方、それ以上チップズレが確認できた場合を「×」と評価した。
　［ボイドの評価］
　実装体をＳＡＴ（Scanning Acoustic Tomograph, 超音波映像装置）を用いて観察した。実装体のボイド面積を確認し、ボイドが発生していないか、又は発生してもボイドの直径が１００μｍ以下の場合を「○」と評価し、それ以上のボイドが確認できた場合を「×」と評価した。一般的に、１００μｍを超えたボイドが生じると、経験上、長期信頼性に悪影響を及ぼす可能性が高くなる。
　［接合の評価］
　実装体のサンプルを切断し、断面研磨を行い、上チップと下チップとのバンプ間のハンダの状態をＳＥＭ（Scanning Electron Microscope）観察した。下チップ側のバンプの９０％以上にハンダ濡れ広がりがある場合の良好な状態を「○」と評価し、それ以外のハンダ濡れが不十分な状態を「×」と評価した。
　［フィレットの評価］
　実装体のチップ間及びチップ端部を目視にて観察し、フィレットが形成されている場合を「×」と評価し、フィレットが形成されていない場合を「○」と評価した。
　［実施例１］
　参考例１に記載の樹脂組成物と同様の組成物を調整した。この組成物を、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み１８μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（１８μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１２に、実施例１のアンダーフィルフィルムの溶融粘度カーブを示す。また、表２に、実施例１のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの弾性率は２．５ＧＰａであり、最低溶融粘度は１４９０Ｐａ・ｓであり、最低溶融粘度到達温度は１１３℃であった。また、１２３℃～１３３℃における溶融粘度の傾きφは３１００Ｐａ・ｓ／℃であった。この実施例１のアンダーフィルフィルムを使った実装体について各評価を行うと、まずチップを搭載した際のチップズレの評価は○であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は○であり、フィレットの評価は○であった。
　［実施例２］
　参考例２に記載された樹脂組成物と同様な樹脂組成物を作成した。この組成物を、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み１８μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（１８μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１２に、実施例２のアンダーフィルフィルムの溶融粘度カーブを示す。また、表２に、実施例２のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの弾性率は２．５ＧＰａであり、最低溶融粘度は１３３０Ｐａ・ｓであり、最低溶融粘度到達温度は１１２℃であった。また、１２２℃～１３２℃における溶融粘度の傾きφは１７００Ｐａ・ｓ／℃であった。この実施例２のアンダーフィルフィルムを使った実装体について各評価を行うと、まずチップを搭載した際のチップズレの評価は○であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は○であり、フィレットの評価は○であった。
　［実施例３］
　参考例３に記載の樹脂組成物と同様な樹脂組成物を調整した。この組成物を、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み１８μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（１８μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１２に、実施例３のアンダーフィルフィルムの溶融粘度カーブを示す。また、表２に、実施例３のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの弾性率は２．５ＧＰａであり、最低溶融粘度は１３９０Ｐａ・ｓであり、最低溶融粘度到達温度は１１３℃であった。また、１２３℃～１３３℃における溶融粘度の傾きφは９００Ｐａ・ｓ／℃であった。この実施例３のアンダーフィルフィルムを使った実装体について各評価を行うと、まず、チップを搭載した際のチップズレの評価は○であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は○であり、フィレットの評価は×であった。
　［比較例１］
　参考例４の樹脂組成物と同様の組成物を調整した。この組成物を、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み１８μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（１８μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１２に、比較例１のアンダーフィルフィルムの溶融粘度カーブを示す。また、表１に、比較例１のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの弾性率は２．５ＧＰａであり、最低溶融粘度は１９５０Ｐａ・ｓであり、最低溶融粘度到達温度は１１３℃であった。また、１２３℃～１３３℃における溶融粘度の傾きφは４０００Ｐａ・ｓ／℃であった。この比較例１のアンダーフィルフィルムを使った実装体について各評価を行うと、まず、チップを搭載した際のチップズレの評価は○であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は○であり、ハンダ接合評価は×であり、フィレットの評価は×であった。
　［比較例２］
　比較例５に記載の樹脂組成物の同様な樹脂組成物を調整した。この樹脂組成物を、剥離処理されたＰＥＴ（Polyethylene terephthalate）にバーコーターを用いて塗布し、８０℃のオーブンで３分間乾燥させ、厚み１８μｍのアンダーフィルフィルムを作製した（カバー剥離ＰＥＴ（２５μｍ）／アンダーフィルフィルム（１８μｍ）／ベース剥離ＰＥＴ（５０μｍ））。
　図１２に、比較例２のアンダーフィルフィルムの溶融粘度カーブを示す。また、表２に、比較例２のアンダーフィルフィルムの評価結果を示す。アンダーフィルフィルムの弾性率は２．５ＧＰａであり、最低溶融粘度は１３００Ｐａ・ｓであり、最低溶融粘度到達温度は１１５℃であった。また、１２５℃～１３５℃における溶融粘度の傾きφは４００Ｐａ・ｓ／℃であった。この比較例２のアンダーフィルムフィルムを使った実装体について各評価を行うと、まず、チップを搭載した際のチップズレの評価は○であった。また、アンダーフィルフィルムを用いて作製した実装体のボイドの評価は×であり、ハンダ接合評価は○であり、フィレットの評価は×であった。
Figure JPOXMLDOC01-appb-T000002
　比較例１のように溶融粘度の傾きφが３１００Ｐａ・ｓ／℃を超えるアンダーフィルフィルムを用いた場合、ボイドレス実装は可能であるが、ハンダ接合に不良が発生した。また、比較例２のように溶融粘度の傾きφが９００Ｐａ・ｓ／℃未満のアンダーフィルフィルムを用いた場合、ハンダ接合は良好であったが、ボイドが発生した。
　一方、実施例１～３のように溶融粘度の傾きφが９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下のアンダーフィルフィルムを用いた場合、複数のチップを一括圧着しても、ボイドレス及び良好なハンダ接合を実現できた。これは、チップ位置による昇温温度差の影響を低減できたためであると考えられる。また、実施例１，２のように溶融粘度の傾きφが１７００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下のアンダーフィルフィルムを用いた場合、フィレットの形成を抑制することができた。
　１　ウエハ、　２　アンダーフィルフィルム、　３　治具、　４　ブレード、　１０　半導体チップ、１１　半導体、１２　電極、１３　ハンダ、２０　アンダーフィルフィルム、２１　接着層、　３０　回路基板、３１　基材、３２　対向電極、４１　ボトムチップ、４２　対向電極、５０　ステージ、６０　ヒートツール

Claims (10)

  1. 　ハンダ付き電極が形成された複数の半導体チップを、アンダーフィルフィルムを介して前記ハンダ付き電極と対向する対向電極が形成された電子部品に搭載する搭載工程と、
    　前記複数の半導体チップと前記電子部品とを、前記アンダーフィルフィルムを介して一括圧着する圧着工程とを有し、
    　前記アンダーフィルフィルムが、エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下である半導体装置の製造方法。
  2. 　前前記溶融粘度の傾きが、１７００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下である請求項１記載の半導体装置の製造方法。
  3. 　前記アクリル樹脂と前記有機過酸化物との合計質量と、前記エポキシ樹脂と前記酸無水物との合計質量との比が、７：３～５：５である請求項２記載の半導体装置の製造方法。
  4. 　前記エポキシ樹脂が、グリシジルエーテル型エポキシ樹脂であり、
    　前記酸無水物が、脂環式酸無水物である請求項１乃至３のいずれか１項に記載の半導体装置の製造方法。
  5. 　前記アクリル樹脂が、フルオレン系アクリレートであり、
    　前記有機過酸化物が、パーオキシケタールである請求項１乃至４のいずれか１項に記載の半導体装置の製造方法。
  6. 　複数の半導体チップと電子部品とを、一括圧着するためのアンダーフィルフィルムであって、
    　エポキシ樹脂と、酸無水物と、アクリル樹脂と、有機過酸化物とを含有し、最低溶融粘度が、１０００Ｐａ・ｓ以上２０００Ｐａ・ｓ以下であり、最低溶融粘度到達温度より１０℃高い温度から該温度より１０℃高い温度までの溶融粘度の傾きが、９００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下であるアンダーフィルフィルム。
  7. 　前前記溶融粘度の傾きが、１７００Ｐａ・ｓ／℃以上３１００Ｐａ・ｓ／℃以下である請求項６記載のアンダーフィルフィルム。
  8. 　前記アクリル樹脂と前記有機過酸化物との合計質量と、前記エポキシ樹脂と前記酸無水物との合計質量との比が、７：３～５：５である請求項７記載のアンダーフィルフィルム。
  9. 　前記エポキシ樹脂が、グリシジルエーテル型エポキシ樹脂であり、
    　前記酸無水物が、脂環式酸無水物である請求項６乃至８のいずれか１項に記載のアンダーフィルフィルム。
  10. 　前記アクリル樹脂が、フルオレン系アクリレートであり、
    　前記有機過酸化物が、パーオキシケタールである請求項６乃至９のいずれか１項に記載のアンダーフィルフィルム。
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Families Citing this family (10)

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KR101837511B1 (ko) * 2016-04-04 2018-03-14 주식회사 네패스 반도체 패키지 및 그 제조방법
JP2018160566A (ja) * 2017-03-23 2018-10-11 三井化学東セロ株式会社 ギャングボンディングプロセス用アンダーフィル絶縁フィルム
CN110582841B (zh) 2017-05-16 2023-08-22 迪睿合株式会社 底部填充材料、底部填充薄膜及使用其的半导体装置的制备方法
US10693432B2 (en) * 2018-05-17 2020-06-23 Qualcommm Incorporated Solenoid structure with conductive pillar technology
US10923365B2 (en) * 2018-10-28 2021-02-16 Richwave Technology Corp. Connection structure and method for forming the same
WO2021152934A1 (ja) * 2020-01-29 2021-08-05 株式会社村田製作所 電極付き受動部品及び電極付き受動部品の集合体
KR102485700B1 (ko) * 2020-12-23 2023-01-06 주식회사 두산 반도체 패키지용 언더필 필름 및 이를 이용하는 반도체 패키지의 제조방법
US11355361B1 (en) * 2021-04-28 2022-06-07 Coretech System Co., Ltd. Method of measuring underfill profile of underfill cavity having solder bumps
TWI773360B (zh) * 2021-06-03 2022-08-01 矽品精密工業股份有限公司 電子封裝件及其承載結構與製法
JP7524839B2 (ja) 2021-06-22 2024-07-30 味の素株式会社 半導体チップ接着用樹脂シート

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252254A (ja) * 2001-02-26 2002-09-06 Sony Chem Corp 電気装置製造方法
WO2013080708A1 (ja) * 2011-11-29 2013-06-06 東レ株式会社 樹脂組成物、樹脂組成物シート、半導体装置およびその製造方法
JP2013211352A (ja) * 2012-03-30 2013-10-10 Dexerials Corp 回路接続材料、及びこれを用いた半導体装置の製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965663A (en) * 1995-06-06 1999-10-12 Kabushiki Kaisha Toshiba Resin composition and resin-molded type semiconductor device
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
JP4170839B2 (ja) 2003-07-11 2008-10-22 日東電工株式会社 積層シート
JP2008074928A (ja) * 2006-09-20 2008-04-03 Hitachi Chem Co Ltd 半導体用接着フィルム及びこれを用いた半導体装置
JP2012234804A (ja) * 2011-04-21 2012-11-29 Sumitomo Electric Ind Ltd フィルム状異方導電性接着剤
JP2013175546A (ja) * 2012-02-24 2013-09-05 Dexerials Corp アンダーフィル材、及びそれを用いた半導体装置の製造方法
US9287204B2 (en) * 2012-12-20 2016-03-15 Stats Chippac, Ltd. Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
CN115216150A (zh) * 2014-02-24 2022-10-21 汉高知识产权控股有限责任公司 导热性预涂底部填充配制物及其用途

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252254A (ja) * 2001-02-26 2002-09-06 Sony Chem Corp 電気装置製造方法
WO2013080708A1 (ja) * 2011-11-29 2013-06-06 東レ株式会社 樹脂組成物、樹脂組成物シート、半導体装置およびその製造方法
JP2013211352A (ja) * 2012-03-30 2013-10-10 Dexerials Corp 回路接続材料、及びこれを用いた半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3255658A4 *

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