CN107112254A - 半导体装置的制造方法及底部填充膜 - Google Patents

半导体装置的制造方法及底部填充膜 Download PDF

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CN107112254A
CN107112254A CN201680006768.7A CN201680006768A CN107112254A CN 107112254 A CN107112254 A CN 107112254A CN 201680006768 A CN201680006768 A CN 201680006768A CN 107112254 A CN107112254 A CN 107112254A
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underfill film
melt viscosity
temperature
chip
epoxy resin
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CN201680006768.7A
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CN107112254B (zh
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久保田健二
斋藤崇之
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Dexerials Corp
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Dexerials Corp
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    • C08G59/00—Polycondensates containing more than one epoxy group per molecule; Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups
    • C08G59/18—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing
    • C08G59/40—Macromolecules obtained by polymerising compounds containing more than one epoxy group per molecule using curing agents or catalysts which react with the epoxy groups ; e.g. general methods of curing characterised by the curing agents used
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Abstract

提供在成批压接多个半导体芯片的情况下，也能得到无空隙安装及良好的焊接性的半导体装置的制造方法及底部填充膜。具有：搭载工序，隔着底部填充膜而将形成有带焊锡电极的多个半导体芯片搭载到形成有与带焊锡电极对置的对置电极的电子部件；以及压接工序，将多个半导体芯片和电子部件，隔着底部填充膜成批压接。底部填充膜含有环氧树脂、酸酐、丙烯树脂、和有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。

Description

半导体装置的制造方法及底部填充膜
技术领域
本发明涉及向基板或晶圆搭载半导体芯片的半导体装置的制造方法、及用于该方法的底部填充膜（Underfill Film）。本申请以在日本于2015年2月6日申请的日本专利申请号特愿2015－022672为基础主张优先权，该申请通过参照而被引入本申请。
背景技术
现有的一般的液状的底部填充材料中，难以进行薄膜化的半导体芯片的安装或3D安装等。因此，研究在将半导体IC（Integrated Circuit）电极与基板电极金属接合或压接接合之前将底部填充膜粘贴到基板上的“先供给型底部填充膜（PUF：Pre－appliedUnderfill Film）”的使用。
使用该先供给型底部填充膜的搭载方法，例如，如以下那样进行（例如，参照专利文献1。）。
工序A：向晶圆粘贴底部填充膜，并切片而得到半导体芯片。
工序B：在基板上进行半导体芯片的对位。
工序C：通过高温/高压来压接半导体芯片和基板，进行通过焊锡凸点的金属结合进行的导通确保，和通过底部填充膜的固化进行的半导体芯片与基板的粘接。
作为利用这样的安装方法提高每个芯片的生产节拍（tact）的方法，能举出多头（multi head）、成批压接等。然而，多头的装置价格高昂，会增加每个芯片的成本。另外，成批压接中，难以进行利用接合器（bonder）（热工具：heat tool）的温度控制，因此，根据芯片的位置在升温速度上会出现差异，有时会发生凸点间的树脂咬入等的接合不良或空隙（void）。
现有技术文献
专利文献
专利文献1：日本特开2005－28734号公报。
发明内容
发明要解决的课题
本发明鉴于这样的现有实情而提出，提供在成批压接多个半导体芯片的情况下，也能得到无空隙安装及良好的焊接性的半导体装置的制造方法及底部填充膜。
用于解决课题的方案
本发明人专心研究的结果，发现了通过使用在既定的最低熔化粘度及比到达最低熔化粘度温度高的温度具有既定的熔化粘度梯度的底部填充膜，在成批压接多个半导体芯片的情况下，也能得到无空隙安装及良好的焊接性。
即，本发明所涉及的半导体装置的制造方法，其特征在于具有：搭载工序，隔着底部填充膜而将形成有带焊锡电极的多个半导体芯片搭载到形成有与所述带焊锡电极对置的对置电极的电子部件；以及压接工序，将所述多个半导体芯片和所述电子部件，隔着所述底部填充膜成批压接，所述底部填充膜含有环氧树脂、酸酐、丙烯树脂、和有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。
另外，本发明为用于成批压接多个半导体芯片和电子部件的底部填充膜，其特征在于，该底部填充膜含有环氧树脂、酸酐、丙烯树脂以及有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。
发明效果
依据本发明，通过使用在既定的最低熔化粘度及比到达最低熔化粘度温度高的温度具有既定的熔化粘度梯度的底部填充膜，在成批压接多个半导体芯片的情况下，也能减少芯片位置对升温温度差异的影响，能得到无空隙安装及良好的焊接性。
附图说明
[图1]图1是示意性地示出第1例的搭载前的半导体芯片和电路基板的截面图。
[图2]图2是示意性地示出第2例的搭载前的半导体芯片和电路基板的截面图。
[图3]图3是示意性地示出搭载时的半导体芯片和电路基板的截面图。
[图4]图4是示意性地示出热压接后的半导体芯片和电路基板的截面图。
[图5]图5是示出接合条件的一个例子的图表。
[图6]图6是示出适合图4所示的接合条件的底部填充膜的熔化粘度曲线的图表。
[图7]图7是示出本实施方式中的半导体装置的制造方法的流程图。
[图8]图8是示意性地示出晶圆上粘贴底部填充膜的工序的立体图。
[图9]图9是示意性地示出将晶圆切片的工序的立体图。
[图10]图10是示意性地示出拾取半导体芯片的工序的立体图。
[图11]图11是示意性地示出成批压接多个半导体芯片的工序的截面图。
[图12]图12是示意性地示出成批压接多个半导体芯片的工序的立体图。
[图13]图13是示出底部填充膜的样品的熔化粘度曲线的图表。
具体实施方式
以下，按照下述顺序，对本发明的实施方式详细地进行说明。
1.底部填充膜
2.半导体装置的制造方法
3.实施例
＜1.底部填充膜＞
本实施方式中的底部填充膜，用来成批压接多个半导体芯片和电子部件，含有环氧树脂、酸酐、丙烯树脂、和有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。在此，作为电子部件，能举出搭载多个半导体芯片的底部芯片（bottom chip）、电路基板等。
图1及图2分别是示意性地示出第1例及第2例的搭载前的半导体芯片和电路基板的截面图。另外，图3是示意性地示出搭载时的半导体芯片和电路基板的截面图，以及图4是示意性地示出热压接后的半导体芯片和电路基板的截面图。
如图1所示，底部填充膜20预先粘合到形成有带焊锡电极13的半导体芯片10的电极面而使用。或者，如图2所示，底部填充膜20也可以预先粘合到形成有与带焊锡电极13对置的对置电极32的电路基板30的电极面而使用。而且，如图3及图4所示，多个半导体芯片10通过底部填充膜20固化的粘接层21接合到电路基板30。
半导体芯片10在硅等的半导体11表面形成有集成电路，具有称为凸点的连接用的带焊锡电极。带焊锡电极在由铜等构成的电极12上接合了焊锡13，具有对电极12的厚度和焊锡13的厚度进行合计的厚度。
作为焊锡，能够使用Sn－37Pb共晶焊锡（熔点183℃）、Sn－Bi焊锡（熔点139℃）、Sn－3.5Ag（熔点221℃）、Sn－3.0Ag－0.5Cu（熔点217℃）、Sn－5.0Sb（熔点240℃）等。
电路基板30在例如刚性基板、柔性基板等的基体材料31形成有电路。另外，在搭载半导体芯片10的安装部中，在与半导体芯片10的带焊锡电极对置的位置形成有具有既定厚度的对置电极32。
底部填充膜20含有膜形成树脂、环氧树脂、酸酐、丙烯树脂、和有机过氧化物。
膜形成树脂相当于重量平均分子量为10×104以上的高分子量树脂，从膜形成性的观点来看，优选为10×104～100×104的重量平均分子量。作为膜形成树脂，能够使用丙烯酸酯橡胶聚合物、苯氧基树脂、环氧树脂、改性环氧树脂、尿烷树脂等的各种树脂。这些膜形成树脂可以单独使用1种，也可以组合使用2种以上。这些之中，从膜强度及粘接性的观点来看，在本实施方式中适合使用具有缩水甘油基的丙烯酸酯橡胶聚合物。作为具有缩水甘油基的丙烯酸酯橡胶聚合物的市售品，能够举出例如商品名“特森树脂（テイサンレジン）SG－P3”（Nagase ChemteX （株））等。
作为环氧树脂，能够举出例如4-（氧化缩水甘油苯基）乙烷（テトラキス(グリシジルオキシフェニル)エタン）、4-（氧化缩水甘油甲基苯基）乙烷、4-（氧化缩水甘油苯基）甲烷、3-（氧化缩水甘油苯基）乙烷（トリキス（グリシジルオキシフェニル）エタン）、3-（氧化缩水甘油苯基）甲烷等的缩水甘油醚型环氧树脂；双环戊二烯型环氧树脂；缩水甘油胺型环氧树脂；双酚A型环氧树脂；双酚F型环氧树脂；双酚S型环氧树脂；螺环型环氧树脂；萘型环氧树脂；联苯型环氧树脂；萜烯型环氧树脂；四溴双酚A型环氧树脂；邻甲酚醛型环氧树脂；苯酚酚醛型环氧树脂；α－萘酚酚醛型环氧树脂；溴化苯酚酚醛型环氧树脂等。这些环氧树脂可以单独使用1种，也可以组合使用2种以上。这些之中，从高粘接性、耐热性的观点来看，在本实施方式中优选使用缩水甘油醚型环氧树脂。作为缩水甘油醚型环氧树脂的市售品，能举出例如商品名“JER 1031S”（三菱化学（株））等。
酸酐具有除去焊锡表面的氧化膜的焊剂功能，因此能够得到优异的连接可靠性。作为酸酐，能够举出例如六氢邻苯二甲酸酐、甲基四氢苯酐等的脂环式酸酐；十二烯基丁二酸酐（テトラプロペニル無水コハク酸）、十二碳烯基丁二酸酐（ドデセニル無水コハク酸）等的脂肪族酸酐；邻苯二甲酸酐、偏苯三酸酐、均苯四酸二酐等的芳香族酸酐等。这些环氧固化剂可以单独使用1种，也可以组合使用2种以上。从焊锡连接性的观点来看，在这些环氧固化剂之中优选使用脂环式酸酐。作为脂环式酸酐的市售品，能举出例如商品名“RIKACIDHNA－100”（新日本理化（株））等。
另外，优选添加固化促进剂。作为固化促进剂的具体例，能举出1, 8－二氮杂环（5, 4, 0）十一烯－7盐（DBU盐）；2－甲基咪唑、2－乙基咪唑、2－乙基－4－甲基咪唑等的咪唑类；2－（二甲胺基甲基）苯酚等的叔胺类；三苯基膦等的膦类、辛酸锡等的金属化合物等。
作为丙烯树脂，能够使用单官能（甲基）丙烯酸酯、2官能以上的（甲基）丙烯酸酯。作为单官能（甲基）丙烯酸酯，能举出二甲基丙烯酸酯（メチル（メタ）アクリレート）、乙基（甲基）丙烯酸酯、n－丙基（甲基）丙烯酸酯、i－丙基（甲基）丙烯酸酯、n－丁基（甲基）丙烯酸酯等。作为2官能以上的（甲基）丙烯酸酯，能够举出芴类丙烯酸酯、双酚F－EO改性二（甲基）丙烯酸酯、双酚A－EO改性二（甲基）丙烯酸酯、三羟基丙烷PO改性（甲基）丙烯酸酯、多官能尿烷（甲基）丙烯酸酯等。这些丙烯树脂可以单独使用，也可以组合2种以上使用。即便这些之中，在本实施方式也适合使用芴类丙烯酸酯。作为芴类丙烯酸酯的市售品，能举出例如商品名“OGSOL EA－0200（オクゾールＥＡ－０２００）”（大阪有机化学（株））等。
作为有机过氧化物，能够举出例如过氧缩酮、过氧酯、氢过氧化物、二烷基过氧化物、二酰基过氧化物、过氧化二碳酸酯等。这些有机过氧化物可以单独使用，也可以组合使用2种以上。即便这些之中，在本实施方式也适合使用过氧缩酮。作为过氧缩酮的市售品，能举出例如商品名“PERHEXA V”（日油（株））等。
另外，作为其他的添加组合物，优选含有无机填充剂。通过含有无机填充剂，能够调整压接时的树脂层的流动性。作为无机填充剂，能够使用硅石、滑石、氧化钛、碳酸钙、氧化镁等。
进而，根据需要，也可以添加环氧类、胺类、巯基/硫化物类、酰脲类等的硅烷偶联剂。
通过这样一并使用固化反应比较慢的环氧类和固化反应比较快的丙烯类，使得接合条件中的升温速度的容限变大，因此在成批压接多个半导体芯片的情况下，也能减轻芯片位置对升温速度差异的影响，能够实现无空隙安装及良好的焊接性。
图5是示出接合条件的一个例子的图表。该接合条件是以50℃/sec以上且150℃/sec以下的升温速度从温度T1升温到250℃。在此，温度T1优选与底部填充膜的最低熔化粘度大致相同，且优选为50℃以上且150℃以下。
另外，图6是示出适合于图5所示的接合条件的底部填充膜的熔化粘度曲线的图表。关于该熔化粘度曲线，利用流变仪，在5℃/min、1Hz的条件下测定了底部填充膜。
适合于该接合条件的底部填充膜的最低熔化粘度η为1000Pa·s以上且2000Pa·s以下。由此，能够抑制加热压接时的空隙发生。另外，底部填充膜的到达最低熔化粘度温度优选为125℃以下。另外，底部填充膜的弹性率优选为1GPa以上且10GPa以下。
另外，从比底部填充膜的到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度为900Pa·s/℃以上且3100Pa·s/℃以下。由此，在以50℃/sec以上且150℃/sec以下的升温速度升温的接合条件下，也能实现无空隙安装及良好的焊接性。即，底部填充膜的升温速度的容限大，在成批压接多个半导体芯片的情况下，也能减轻芯片位置对升温速度差异的影响。另外，底部填充膜能够抑制芯片侧面的圆角（fillet）形成，因此能够减小邻接的芯片间隔。另外，通过无圆角而防止对工具的附着，可以不需要缓冲材料。
另外，到达最低熔化粘度温度优选与接合条件的温度T1大致相同。由此能够得到成为符合接合条件的固化行动的底部填充膜。
另外，丙烯树脂和有机过氧化物的合计质量、与环氧树脂和酸酐的合计质量之比，优选为7:3～4:6，更优选为7:3～5:5。由此，接合条件中的升温速度的容限变大，因此在成批压接多个半导体芯片的情况下，也能减轻芯片位置对升温速度差异的影响，能够实现无空隙安装及良好的焊接性。
接着，对前述的底部填充膜的制造方法进行说明。首先，使含有膜形成树脂、环氧树脂、酸酐、丙烯树脂、和有机过氧化物的粘接剂组合物溶解到溶剂中。作为溶剂，能够使用甲苯、醋酸乙酯等，或者它们的混合溶剂。在调整树脂组合物后，利用棒涂机、涂敷装置等来涂敷到剥离基体材料上。
剥离基体材料例如由将硅酮等的剥离剂涂敷在PET（聚对苯二甲酸乙二醇酯：PolyEthylene Terephthalate）、OPP（定向聚丙烯：Oriented Polypropylene）、PMP（聚4－甲基戊烯－1：Poly－4－methylpentene－1）、PTFE（聚四氟乙烯：Polytetrafluoroethylene）等的层叠构造构成，防止组合物的干燥，并且维持组合物的形状。
接着，利用热烤箱、加热干燥装置等，使涂敷在剥离基体材料上的树脂组合物干燥。由此，能够得到既定厚度的先供给型底部填充膜。
＜2.半导体装置的制造方法＞
接着，对使用前述的底部填充膜的半导体装置的制造方法进行说明。本实施方式中的半导体装置的制造方法具有：搭载工序，隔着底部填充膜而将形成有带焊锡电极的多个半导体芯片搭载到形成有与带焊锡电极对置的对置电极的电子部件；以及压接工序，将多个半导体芯片和电子部件，隔着底部填充膜成批压接。本法中使用的底部填充膜，如前所述，含有环氧树脂、酸酐、丙烯树脂、和有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。
图7是示出半导体装置的制造方法的流程图。如图7所示，本实施方式中的半导体装置的制造方法具有：底部填充膜粘贴工序S1；切片工序S2；半导体芯片搭载工序S3；以及热压接工序S4。
图8是示意性地示出在晶圆上粘贴底部填充膜的工序的立体图。如图8所示，在底部填充膜粘贴工序S1中，利用具有直径比晶圆1的直径大的环状或框状的框架的夹具3来固定晶圆1，在晶圆1上粘贴底部填充膜2。底部填充膜2在将晶圆1切片时保护并固定晶圆1，作为在拾取时保持的切片带而发挥功能。此外，对晶圆1制作多个IC（Integrated Circuit），在晶圆1的粘接面，按照由划线区分的每个半导体芯片10设有带焊锡电极。
图9是示意性地示出将晶圆切片的工序的立体图。如图9所示，在切片工序S2中，沿着划线按压切刀4而切削晶圆1，分割为各个半导体芯片。
图10是示意性地示出拾取半导体芯片的工序的立体图。如图10所示，各带底部填充膜的半导体芯片10被保持在底部填充膜从而被拾取。
在半导体芯片搭载工序S3中，如图3所示，隔着底部填充膜配置带底部填充膜的半导体芯片10和电路基板30。另外，将带底部填充膜的半导体芯片10以使带焊锡电极和对置电极32对置的方式对位并配置。而且，通过加热接合器，在底部填充膜出现流动性，但是以不发生正式固化的程度的既定温度、压力、时间的条件进行加热按压并搭载。
搭载时的温度条件，优选为30℃以上且155℃以下。另外，压力条件优选为60N以下，更优选为50N以下。另外，时间条件优选为0.5秒以上且10秒以下，更优选为0.1秒以上且3.0秒以下。由此，能够使带焊锡电极不熔化而处于与电路基板30侧的电极相接的状态，并能使底部填充膜处于不完全固化的状态。另外，由于在低的温度下固定，所以抑制空隙的发生，能够减少对半导体芯片10的损伤。
在接着的热压接工序S4中，利用多端子接合（gang bonding）装置，使多个半导体芯片10的带焊锡电极的焊锡熔化而形成金属结合，并且使底部填充膜完全固化，并成批压接。
图11及图12分别示意性地示出成批压接多个半导体芯片的工序的截面图及立体图。在图11及图12中，作为电子部件，在载物台50上以3×3排列有底部芯片41。而且，将半导体芯片10分别搭载到底部芯片41上，以热工具60成批压接3×3的半导体芯片，从而多个半导体芯片10利用底部填充膜20固化的粘接层21来接合到底部芯片41。
成批压接时的温度条件优选为150℃以上且300℃以下，更优选为230℃以上且280℃以下。另外，压力条件优选为60N以下，更优选为50N以下。另外，时间条件优选为0.1秒以上且60秒以下，更优选为5秒以上且20秒以下。由此，使带焊锡电极和基板电极金属结合，并且使底部填充膜完全固化，能够使多个半导体芯片10的电极与电路基板30的电极电气、机械地成批压接。
通过使用这样在既定的最低熔化粘度及比到达最低熔化粘度温度高的温度具有既定的熔化粘度梯度的底部填充膜，在成批压接多个半导体芯片的情况下，也能实现无空隙安装及良好的焊接性。
此外，在前述的实施方式中，使底部填充膜作为切片带发挥功能，但并不限于此，也可以另外使用切片带，在切片后使用底部填充膜进行倒装芯片安装。
[其他实施方式]
另外，本技术也可以适用在通过向设置在半导体芯片的小孔填充金属来电连接以三明治状叠置的多个芯片基板的TSV（穿透硅通孔：Through Silicon Via）技术。
即，也可以适用在层叠具有形成带焊锡电极的第1面和在第1面的相反侧形成与带焊锡电极对置的对置电极的第2面的多个芯片基板的半导体装置的制造方法。
在该情况下，以在第1芯片基板的第1面侧粘贴底部填充膜的状态，搭载于第2芯片基板的第2面。然后，在带焊锡电极的焊锡的熔点以上的温度下将第1芯片基板的第1面和第2芯片基板的第2面进行热压接，从而能够得到层叠多个芯片基板的半导体装置。
实施例
＜3.实施例＞
以下，对本发明的实施例进行说明。在本实施例中，制作先供给型的底部填充膜，接着，使用如图11及图12所示的多端子接合装置，利用底部填充膜来使具有带焊锡电极的多个上芯片和具有与它对置的电极的下芯片成批压接，从而制作安装体，对空隙、焊接状态、及圆角进行了评价。
此外，在此之前，作为参考例，利用底部填充膜，对于1个头各1个芯片地连接具有带焊锡电极的IC芯片和具有与它对置的电极的IC基板而制作安装体，并说明对空隙及焊接状态的评价。
＜3.1参考例＞
首先，作为参考例，利用底部填充膜，对于1个头各1个芯片地连接而制作安装体，并评价了空隙及焊接状态。关于底部填充膜的最低熔化粘度及熔化粘度梯度的测定、安装体的制作、空隙的评价、焊接的评价，则如下进行。
[最低熔化粘度的测定及熔化粘度梯度的算出]
与3.1的实施例同样，对于各底部填充膜，利用流变仪（TA公司制ARES），在5℃/min、1Hz的条件下测定了样品的最低熔化粘度及到达最低熔化粘度温度。然后，算出了到达最低熔化粘度温度＋10℃～到达最低熔化粘度温度＋20℃的温度范围中的熔化粘度梯度。
[安装体的制作]
用压力机，在50℃－0.5MPa的条件下将底部填充膜粘合到晶圆上，经调松紧（dancing）而得到具有带焊锡电极的IC芯片。
关于IC芯片，其大小为7mm□、厚度为200μm，具有在厚度20μm的由Cu构成的电极的前端形成有厚度16μm的焊锡（Sn－3.5Ag、熔点221℃）的外围（peripheral）配置的凸点（φ30μm、85μm间距、280端子（pin））。
另外，与之对置的IC基板，同样地，其大小为7mm□、厚度为200μm，具有形成有厚度20μm的由Cu构成的电极的外围配置的凸点（φ30μm、85μm间距、280端子）。
接着，利用倒装接合器，在60℃－0.5秒－30N的条件下将IC芯片搭载到IC基板上。
然后，如图5所示的接合条件那样，利用倒装接合器，以50℃/sec的升温速度从底部填充膜的到达最低熔化粘度温度热压接到250℃。此外，在从到达最低熔化粘度温度升温至250℃的时间内使接合器头下降到最下点（30N）。进而，在150℃－2小时的条件下固化（cure），从而得到了第1安装体。另外，同样地，利用倒装接合器，以150℃/sec的升温速度从底部填充膜的到达最低熔化粘度温度热压接到250℃。此外，在从到达最低熔化粘度温度升温至250℃的时间内使接合器头下降到最下点（30N）。进而，在150℃－2小时的条件下固化，得到了第2安装体。此外，在使用倒装接合器时的温度是通过热电对来测定的样品的实际温度。
[空隙的评价]
利用SAT（Scanning Acoustic Tomograph、超声波影像装置），观察了以50℃/sec的升温速度热压接的第1安装体及以150℃/sec的升温速度热压接的第2安装体。将第1安装体及第2安装体两者都未发生空隙的情况评价为“○”，将在任一安装体发生空隙的情况评价为“×”。一般来说，如果发生空隙，则对长期可靠性产生负面影响的可能性变高。
[焊接的评价]
切断以50℃/sec的升温速度热压接的第1安装体及以150℃/sec的升温速度热压接的第2安装体的样品，并进行截面研磨，SEM（扫描电子显微镜：Scanning ElectronMicroscope）观察了IC芯片的电极与IC基板的电极之间的焊锡的状态。将第1安装体及第2安装体两者都焊锡连接、焊锡润湿都良好的状态评价为“○”，将任一安装体的焊锡连接、或焊锡润湿不充分的状态评价为“×”。
[参考例1]
混合作为膜形成树脂的丙烯酸酯橡胶聚合物（品名：特森树脂SG－P3、Nagase ChemteX公司制）40质量份、环氧树脂（品名：JER 1031S、三菱化学公司制）20质量份、酸酐（品名：RIKACID HNA－100、新日本理化公司制）10质量份、作为固化促进剂的咪唑（品名：U－CAT－5002、SAN－APRO 公司制）1质量份、丙烯树脂（品名：OGSOL EA－0200、大阪有机化学公司制）68质量份、有机过氧化物（品名：PERHEXA V、日油公司制）2质量份、填充剂（品名：AEROSIL R202、日本AEROSIL 公司制）15质量份，调制了丙烯/环氧为70/30的树脂组合物。利用棒涂机来将它涂敷到剥离处理的PET（Polyethylene terephthalate），在80℃的烤箱干燥3分钟，制作了厚度50μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（50μm）/基底剥离PET（50μm））。
图13中示出参考例1的底部填充膜的熔化粘度曲线。另外，表1中示出参考例1的底部填充膜的评价结果。底部填充膜的最低熔化粘度为1490Pa·s，到达最低熔化粘度温度为113℃。另外，在123℃～133℃中的熔化粘度梯度φ为3100Pa·s/℃。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“○”。
[参考例2]
混合作为膜形成树脂的丙烯酸酯橡胶聚合物（品名：特森树脂SG－P3、Nagase ChemteX公司制）40质量份、环氧树脂（品名：JER 1031S、三菱化学公司制）30质量份、酸酐（品名：RIKACID HNA－100、新日本理化公司制）20质量份、作为固化促进剂的咪唑（品名：U－CAT－5002、SAN－APRO 公司制）1质量份、丙烯树脂（品名：OGSOL EA－0200、大阪有机化学公司制）49质量份、有机过氧化物（品名：PERHEXA V、日油公司制）1质量份、填充剂（品名：AEROSIL R202、日本AEROSIL 公司制）15质量份，调制了丙烯/环氧为50/50的树脂组合物。利用棒涂机来将它涂敷到剥离处理的PET（Polyethylene terephthalate），在80℃的烤箱干燥3分钟，制作了厚度50μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（50μm）/基底剥离PET（50μm））。
图13中示出参考例2的底部填充膜的熔化粘度曲线。另外，表1中示出参考例2的底部填充膜的评价结果。底部填充膜的最低熔化粘度为1330Pa·s，到达最低熔化粘度温度为112℃。另外，在122℃～132℃中的熔化粘度梯度φ为1700Pa·s/℃。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“○”。
[参考例3]
混合作为膜形成树脂的丙烯酸酯橡胶聚合物（品名：特森树脂SG－P3、Nagase ChemteX公司制）40质量份、环氧树脂（品名：JER 1031S、三菱化学公司制）45质量份、酸酐（品名：RIKACID HNA－100、新日本理化公司制）15质量份、作为固化促进剂的咪唑（品名：U－CAT－5002、SAN－APRO 公司制）1质量份、丙烯树脂（品名：OGSOL EA－0200、大阪有机化学公司制）39质量份、有机过氧化物（品名：PERHEXA V、日油公司制）1质量份、填充剂（品名：AEROSIL R202、日本AEROSIL 公司制）15质量份，调制了丙烯/环氧为50/50的树脂组合物。利用棒涂机来将它涂敷到剥离处理的PET（Polyethylene terephthalate），在80℃的烤箱干燥3分钟，制作了厚度50μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（50μm）/基底剥离PET（50μm））。
图13中示出参考例3的底部填充膜的熔化粘度曲线。另外，表1中示出参考例3的底部填充膜的评价结果。底部填充膜的最低熔化粘度为1390Pa·s，到达最低熔化粘度温度为113℃。另外，在123℃～133℃中的熔化粘度梯度φ为900Pa·s/℃。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“○”。
[参考例4]
混合作为膜形成树脂的丙烯酸酯橡胶聚合物（品名：特森树脂SG－P3、Nagase ChemteX公司制）40质量份、环氧树脂（品名：JER 1031S、三菱化学公司制）13质量份、酸酐（品名：RIKACID HNA－100、新日本理化公司制）7质量份、作为固化促进剂的咪唑（品名：U－CAT－5002、SAN－APRO 公司制）1质量份、丙烯树脂（品名：OGSOL EA－0200、大阪有机化学公司制）76质量份、有机过氧化物（品名：PERHEXA V、日油公司制）4质量份、填充剂（品名：AEROSIL R202、日本AEROSIL 公司制）15质量份，调制了丙烯/环氧为80/20的树脂组合物。利用棒涂机来将它涂敷到剥离处理的PET（Polyethylene terephthalate），在80℃的烤箱干燥3分钟，制作了厚度50μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（50μm）/基底剥离PET（50μm））。
图13中示出参考例4的底部填充膜的熔化粘度曲线。另外，表1中示出参考例4的底部填充膜的评价结果。底部填充膜的最低熔化粘度为1950Pa·s，到达最低熔化粘度温度为113℃。另外，在123℃～133℃中的熔化粘度梯度φ为4000Pa·s/℃。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“×”。
[参考例5]
混合作为膜形成树脂的丙烯酸酯橡胶聚合物（品名：特森树脂SG－P3、Nagase ChemteX公司制）40质量份、环氧树脂（品名：JER 1031S、三菱化学公司制）40质量份、酸酐（品名：RIKACID HNA－100、新日本理化公司制）30质量份、作为固化促进剂的咪唑（品名：U－CAT－5002、SAN－APRO 公司制）1质量份、丙烯树脂（品名：OGSOL EA－0200、大阪有机化学公司制）29质量份、有机过氧化物（品名：PERHEXA V、日油公司制）1质量份、填充剂（品名：AEROSIL R202、日本AEROSIL 公司制）15质量份，调制了丙烯/环氧为30/70的树脂组合物。利用棒涂机来将它涂敷到剥离处理的PET（Polyethylene terephthalate），在80℃的烤箱干燥3分钟，制作了厚度50μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（50μm）/基底剥离PET（50μm））。
图13中示出参考例5的底部填充膜的熔化粘度曲线。另外，表1中示出参考例5的底部填充膜的评价结果。底部填充膜的最低熔化粘度为1300Pa·s，到达最低熔化粘度温度为115℃。另外，125℃～135℃中的熔化粘度梯度φ为400Pa·s/℃。另外，利用底部填充膜制作的安装体的空隙的评价为“×”，且焊接评价为“○”。
[表1]
如参考例4那样在熔化粘度梯度φ超过3100Pa·s/℃的情况下，可以进行无空隙安装，但是在以50℃/sec的升温速度热压接的第1安装体及以150℃/sec的升温速度热压接的第2安装体两者的焊接上发生了不良。另外，如参考例5那样在熔化粘度梯度φ小于900Pa·s/℃的情况下，焊接为良好，但是在以150℃/sec的升温速度热压接的第2安装体内存在空隙。
另一方面，如参考例1～3那样在熔化粘度梯度φ为900Pa·s/℃以上且3100Pa·s/℃以下的情况下，在50℃/sec以上且150℃/sec以下的升温速度的接合条件下，也能实现无空隙及良好的焊接。
＜3.2实施例（成批压接）＞
如上所述，在本实施例中，制作先供给型的底部填充膜，接着，使用如图11及图12所示的多端子接合装置，利用底部填充膜来使具有带焊锡电极的多个上芯片和具有与它对置的电极的下芯片成批压接而制作安装体，并对空隙、焊接状态及圆角进行了评价。关于此时的底部填充膜的弹性率、最低熔化粘度及熔化粘度梯度的测定、安装体的制作、搭载时的芯片偏离、空隙、焊接、及圆角的评价，则如下进行。
[弹性率、最低熔化粘度的测定、及熔化粘度梯度的算出]
对于各底部填充膜，利用流变仪（TA公司制ARES），在5℃/min、1Hz的条件下测定了样品的弹性率、最低熔化粘度及到达最低熔化粘度温度。然后，算出了到达最低熔化粘度温度＋10℃～到达最低熔化粘度温度＋20℃的温度范围中的熔化粘度梯度。
[安装体的制作]
首先，用压力机，在50℃－0.5MPa的条件下将底部填充膜粘合到晶圆上，经调松紧而得到具有带焊锡电极的上芯片。
上芯片使用尺寸为5mm×5mm、厚度为200μm、凸点为Cu/SnAg的盖（cap）类型的芯片。凸点直径为50μm、高度为20μm（SnAg5μm）、间距为150μm、凸点数为592个。
另外，下芯片使用尺寸为10mm×10mm（分割块类型30μm×30μm）、厚度为200μm、凸点为Ni/Au的焊盘类型的芯片。凸点直径为50μm、高度为3μm、间距为150μm、凸点数为592个。
接着，利用倒装接合器，在80℃－2秒－40N的条件下将9个上芯片搭载到下芯片上。
然后，使用如图11及图12所示的多端子接合装置，如图5所示的接合条件那样，以50℃/sec的升温速度从底部填充膜的到达最低熔化粘度温度成批压接到250℃。另外，在从到达最低熔化粘度温度到达250℃的时间内，使多端子接合装置的热工具下降到最下点（40N－10秒）。进而，在150℃－2小时的条件下固化，得到了图3所示的安装体。
[芯片偏离的评价]
关于在下芯片上成批压接9个上芯片时的芯片偏离，以X射线装置进行目视，将芯片偏离为5μm以下且实质上无法确认的情况评价为“○”，另一方面，能够确认到其以上芯片偏离的情况评价为“×”。
[空隙的评价]
利用SAT（Scanning Acoustic Tomograph、超声波影像装置）观察了安装体。确认安装体的空隙面积，将没有发生空隙、或即便发生空隙的直径也为100μm以下的情况评价为“○”，将能够确认其以上的空隙的情况评价为“×”。一般来说，如果发生超过100μm的空隙，则从经验上来看对长期可靠性产生负面影响的可能性变高。
[接合的评价]
切断安装体的样品，并进行截面研磨，SEM（Scanning Electron Microscope）观察了上芯片与下芯片的凸点间的焊锡的状态。将下芯片侧的凸点的90％以上具有焊锡润湿开的情况的良好的状态评价为“○”，将除此以外的焊锡润湿不充分的状态评价为“×”。
[圆角的评价]
以目视观察安装体的芯片间及芯片端部，将形成有圆角的情况评价为“×”，将没有形成圆角的情况评价为“○”。
[实施例1]
调整了与在参考例1记载的树脂组合物同样的组合物。利用棒涂机来将该组合物涂敷到剥离处理的PET（Polyethylene terephthalate），并在80℃的烤箱干燥3分钟，从而制作了厚度18μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（18μm）/基底剥离PET（50μm））。
图12中示出实施例1的底部填充膜的熔化粘度曲线。另外，表2中示出实施例1的底部填充膜的评价结果。底部填充膜的弹性率为2.5GPa，最低熔化粘度为1490Pa·s，到达最低熔化粘度温度为113℃。另外，在123℃～133℃中的熔化粘度梯度φ为3100Pa·s/℃。若对于使用该实施例1的底部填充膜的安装体进行各评价，则首先搭载芯片时的芯片偏离的评价为“○”。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“○”、圆角的评价为“○”。
[实施例2]
制作了与在参考例2记载的树脂组合物同样的树脂组合物。利用棒涂机来将该组合物涂敷到剥离处理的PET（Polyethylene terephthalate），并在80℃的烤箱干燥3分钟，从而制作了厚度18μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（18μm）/基底剥离PET（50μm））。
图12中示出实施例2的底部填充膜的熔化粘度曲线。另外，表2中示出实施例2的底部填充膜的评价结果。底部填充膜的弹性率为2.5GPa，最低熔化粘度为1330Pa·s，到达最低熔化粘度温度为112℃。另外，在122℃～132℃中的熔化粘度梯度φ为1700Pa·s/℃。若对于使用该实施例2的底部填充膜的安装体进行各评价，则首先搭载芯片时的芯片偏离的评价为“○”。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“○”、圆角的评价为“○”。
[实施例3]
调整了与在参考例3记载的树脂组合物同样的树脂组合物。利用棒涂机来将该组合物涂敷到剥离处理的PET（Polyethylene terephthalate），并在80℃的烤箱干燥3分钟，从而制作了厚度18μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（18μm）/基底剥离PET（50μm））。
图12中示出实施例3的底部填充膜的熔化粘度曲线。另外，表2中示出实施例3的底部填充膜的评价结果。底部填充膜的弹性率为2.5GPa，最低熔化粘度为1390Pa·s，到达最低熔化粘度温度为113℃。另外，在123℃～133℃中的熔化粘度梯度φ为900Pa·s/℃。若对于使用该实施例3的底部填充膜的安装体进行各评价，则首先搭载芯片时的芯片偏离的评价为“○”。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，且焊接评价为“○”，而圆角的评价为“×”。
[比较例1]
调整了与参考例4的树脂组合物同样的组合物。利用棒涂机来将该组合物涂敷到剥离处理的PET（Polyethylene terephthalate），并在80℃的烤箱干燥3分钟，从而制作了厚度18μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（18μm）/基底剥离PET（50μm））。
图12中示出比较例1的底部填充膜的熔化粘度曲线。另外，表1中示出比较例1的底部填充膜的评价结果。底部填充膜的弹性率为2.5GPa，最低熔化粘度为1950Pa·s，到达最低熔化粘度温度为113℃。另外，在123℃～133℃中的熔化粘度梯度φ为4000Pa·s/℃。若对于使用该比较例1的底部填充膜的安装体进行各评价，则首先搭载芯片时的芯片偏离的评价为“○”。另外，利用底部填充膜来制作的安装体的空隙的评价为“○”，而焊接评价为“×”、圆角的评价为“×”。
[比较例2]
调整了与在比较例5记载的树脂组合物同样的树脂组合物。利用棒涂机来将该树脂组合物涂敷到剥离处理的PET（Polyethylene terephthalate），并在80℃的烤箱干燥3分钟，从而制作了厚度18μm的底部填充膜（盖剥离PET（25μm）/底部填充膜（18μm）/基底剥离PET（50μm））。
图12中示出比较例2的底部填充膜的熔化粘度曲线。另外，表2中示出比较例2的底部填充膜的评价结果。底部填充膜的弹性率为2.5GPa，最低熔化粘度为1300Pa·s，到达最低熔化粘度温度为115℃。另外，在125℃～135℃中的熔化粘度梯度φ为400Pa·s/℃。若对于使用该比较例2的底部填充膜的安装体进行各评价，则首先搭载芯片时的芯片偏离的评价为“○”。另外，利用底部填充膜来制作的安装体的空隙的评价为“×”，而焊接评价为“○”，且圆角的评价为“×”。
[表2]
如比较例1那样在使用熔化粘度梯度φ超过3100Pa·s/℃的底部填充膜的情况下，可以进行无空隙安装，但是在焊接上会发生不良。另外，如比较例2那样在使用熔化粘度梯度φ小于900Pa·s/℃的底部填充膜的情况下，焊接为良好，但发生空隙。
另一方面，如实施例1～3那样在使用熔化粘度梯度φ为900Pa·s/℃以上且3100Pa·s/℃以下的底部填充膜的情况下，成批压接多个芯片也能实现无空隙及良好的焊接。这被认为是因为能够减少芯片位置对升温温度差的影响。另外，如实施例1、2那样在使用熔化粘度梯度φ为1700Pa·s/℃以上且3100Pa·s/℃以下的底部填充膜的情况下，能够抑制圆角的形成。
标号说明
1 晶圆；2 底部填充膜；3 夹具；4 切刀；10 半导体芯片；11 半导体；12 电极；13 焊锡；20 底部填充膜；21 粘接层；30 电路基板；31 基体材料；32 对置电极；41 底部芯片；42对置电极；50 载物台；60 热工具。

Claims (10)

1.一种半导体装置的制造方法，具有：
搭载工序，隔着底部填充膜而将形成有带焊锡电极的多个半导体芯片搭载到形成有与所述带焊锡电极对置的对置电极的电子部件；以及
压接工序，将所述多个半导体芯片和所述电子部件，隔着所述底部填充膜成批压接，
所述底部填充膜含有环氧树脂、酸酐、丙烯树脂、和有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。
2.如权利要求1所述的半导体装置的制造方法，其中，所述熔化粘度梯度为1700Pa·s/℃以上且3100Pa·s/℃以下。
3.如权利要求2所述的半导体装置的制造方法，其中，所述丙烯树脂和所述有机过氧化物的合计质量、与所述环氧树脂和所述酸酐的合计质量之比为7:3～5:5。
4.如权利要求1至3的任一项所述的半导体装置的制造方法，其中，
所述环氧树脂为缩水甘油醚型环氧树脂，
所述酸酐为脂环式酸酐。
5.如权利要求1至4的任一项所述的半导体装置的制造方法，其中，
所述丙烯树脂为芴类丙烯酸酯，
所述有机过氧化物为过氧缩酮。
6.一种底部填充膜，用于成批压接多个半导体芯片和电子部件，其中，
含有环氧树脂、酸酐、丙烯树脂、及有机过氧化物，最低熔化粘度为1000Pa·s以上且2000Pa·s以下，从比到达最低熔化粘度温度高10℃的温度到比该温度高10℃的温度的熔化粘度梯度，为900Pa·s/℃以上且3100Pa·s/℃以下。
7.如权利要求6所述的底部填充膜，其中，所述熔化粘度梯度为1700Pa·s/℃以上且3100Pa·s/℃以下。
8.如权利要求7所述的底部填充膜，其中，所述丙烯树脂和所述有机过氧化物的合计质量、与所述环氧树脂和所述酸酐的合计质量之比为7:3～5:5。
9.如权利要求6至8的任一项所述的底部填充膜，其中，
所述环氧树脂为缩水甘油醚型环氧树脂，
所述酸酐为脂环式酸酐。
10.如权利要求6至9的任一项所述的底部填充膜，其中，
所述丙烯树脂为芴类丙烯酸酯，
所述有机过氧化物为过氧缩酮。
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